src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "dev/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_INT8:
  48       return BRW_REGISTER_TYPE_B;
  49    case GLSL_TYPE_UINT:
  50       return BRW_REGISTER_TYPE_UD;
  51    case GLSL_TYPE_UINT16:
  52       return BRW_REGISTER_TYPE_UW;
  53    case GLSL_TYPE_UINT8:
  54       return BRW_REGISTER_TYPE_UB;
  55    case GLSL_TYPE_ARRAY:
  56       return brw_type_for_base_type(type->fields.array);
  57    case GLSL_TYPE_STRUCT:
  58    case GLSL_TYPE_INTERFACE:
  59    case GLSL_TYPE_SAMPLER:
  60    case GLSL_TYPE_ATOMIC_UINT:
  61       /* These should be overridden with the type of the member when
  62        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  63        * way to trip up if we don't.
  64        */
  65       return BRW_REGISTER_TYPE_UD;
  66    case GLSL_TYPE_IMAGE:
  67       return BRW_REGISTER_TYPE_UD;
  68    case GLSL_TYPE_DOUBLE:
  69       return BRW_REGISTER_TYPE_DF;
  70    case GLSL_TYPE_UINT64:
  71       return BRW_REGISTER_TYPE_UQ;
  72    case GLSL_TYPE_INT64:
  73       return BRW_REGISTER_TYPE_Q;
  74    case GLSL_TYPE_VOID:
  75    case GLSL_TYPE_ERROR:
  76    case GLSL_TYPE_FUNCTION:
  77       unreachable("not reached");
  78    }
  79
  80    return BRW_REGISTER_TYPE_F;
  81 }
  82
  83 enum brw_conditional_mod
  84 brw_conditional_for_comparison(unsigned int op)
  85 {
  86    switch (op) {
  87    case ir_binop_less:
  88       return BRW_CONDITIONAL_L;
  89    case ir_binop_gequal:
  90       return BRW_CONDITIONAL_GE;
  91    case ir_binop_equal:
  92    case ir_binop_all_equal: /* same as equal for scalars */
  93       return BRW_CONDITIONAL_Z;
  94    case ir_binop_nequal:
  95    case ir_binop_any_nequal: /* same as nequal for scalars */
  96       return BRW_CONDITIONAL_NZ;
  97    default:
  98       unreachable("not reached: bad operation for comparison");
  99    }
 100 }
 101
 102 uint32_t
 103 brw_math_function(enum opcode op)
 104 {
 105    switch (op) {
 106    case SHADER_OPCODE_RCP:
 107       return BRW_MATH_FUNCTION_INV;
 108    case SHADER_OPCODE_RSQ:
 109       return BRW_MATH_FUNCTION_RSQ;
 110    case SHADER_OPCODE_SQRT:
 111       return BRW_MATH_FUNCTION_SQRT;
 112    case SHADER_OPCODE_EXP2:
 113       return BRW_MATH_FUNCTION_EXP;
 114    case SHADER_OPCODE_LOG2:
 115       return BRW_MATH_FUNCTION_LOG;
 116    case SHADER_OPCODE_POW:
 117       return BRW_MATH_FUNCTION_POW;
 118    case SHADER_OPCODE_SIN:
 119       return BRW_MATH_FUNCTION_SIN;
 120    case SHADER_OPCODE_COS:
 121       return BRW_MATH_FUNCTION_COS;
 122    case SHADER_OPCODE_INT_QUOTIENT:
 123       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 124    case SHADER_OPCODE_INT_REMAINDER:
 125       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 126    default:
 127       unreachable("not reached: unknown math function");
 128    }
 129 }
 130
 131 bool
 132 brw_texture_offset(const nir_tex_instr *tex, unsigned src,
 133                    uint32_t *offset_bits_out)
 134 {
 135    if (!nir_src_is_const(tex->src[src].src))
 136       return false;
 137
 138    const unsigned num_components = nir_tex_instr_src_size(tex, src);
 139
 140    /* Combine all three offsets into a single unsigned dword:
 141     *
 142     *    bits 11:8 - U Offset (X component)
 143     *    bits  7:4 - V Offset (Y component)
 144     *    bits  3:0 - R Offset (Z component)
 145     */
 146    uint32_t offset_bits = 0;
 147    for (unsigned i = 0; i < num_components; i++) {
 148       int offset = nir_src_comp_as_int(tex->src[src].src, i);
 149
 150       /* offset out of bounds; caller will handle it. */
 151       if (offset > 7 || offset < -8)
 152          return false;
 153
 154       const unsigned shift = 4 * (2 - i);
 155       offset_bits |= (offset << shift) & (0xF << shift);
 156    }
 157
 158    *offset_bits_out = offset_bits;
 159
 160    return true;
 161 }
 162
 163 const char *
 164 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 165 {
 166    switch (op) {
 167    case 0 ... NUM_BRW_OPCODES - 1:
 168       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 169        * start of a loop in the IR.
 170        */
 171       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 172          return "do";
 173
 174       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 175        * then to mark that we want to do the conversion.
 176        */
 177       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 178          return "f32to16";
 179
 180       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 181          return "f16to32";
 182
 183       assert(brw_opcode_desc(devinfo, op)->name);
 184       return brw_opcode_desc(devinfo, op)->name;
 185    case FS_OPCODE_FB_WRITE:
 186       return "fb_write";
 187    case FS_OPCODE_FB_WRITE_LOGICAL:
 188       return "fb_write_logical";
 189    case FS_OPCODE_REP_FB_WRITE:
 190       return "rep_fb_write";
 191    case FS_OPCODE_FB_READ:
 192       return "fb_read";
 193    case FS_OPCODE_FB_READ_LOGICAL:
 194       return "fb_read_logical";
 195
 196    case SHADER_OPCODE_RCP:
 197       return "rcp";
 198    case SHADER_OPCODE_RSQ:
 199       return "rsq";
 200    case SHADER_OPCODE_SQRT:
 201       return "sqrt";
 202    case SHADER_OPCODE_EXP2:
 203       return "exp2";
 204    case SHADER_OPCODE_LOG2:
 205       return "log2";
 206    case SHADER_OPCODE_POW:
 207       return "pow";
 208    case SHADER_OPCODE_INT_QUOTIENT:
 209       return "int_quot";
 210    case SHADER_OPCODE_INT_REMAINDER:
 211       return "int_rem";
 212    case SHADER_OPCODE_SIN:
 213       return "sin";
 214    case SHADER_OPCODE_COS:
 215       return "cos";
 216
 217    case SHADER_OPCODE_SEND:
 218       return "send";
 219
 220    case SHADER_OPCODE_UNDEF:
 221       return "undef";
 222
 223    case SHADER_OPCODE_TEX:
 224       return "tex";
 225    case SHADER_OPCODE_TEX_LOGICAL:
 226       return "tex_logical";
 227    case SHADER_OPCODE_TXD:
 228       return "txd";
 229    case SHADER_OPCODE_TXD_LOGICAL:
 230       return "txd_logical";
 231    case SHADER_OPCODE_TXF:
 232       return "txf";
 233    case SHADER_OPCODE_TXF_LOGICAL:
 234       return "txf_logical";
 235    case SHADER_OPCODE_TXF_LZ:
 236       return "txf_lz";
 237    case SHADER_OPCODE_TXL:
 238       return "txl";
 239    case SHADER_OPCODE_TXL_LOGICAL:
 240       return "txl_logical";
 241    case SHADER_OPCODE_TXL_LZ:
 242       return "txl_lz";
 243    case SHADER_OPCODE_TXS:
 244       return "txs";
 245    case SHADER_OPCODE_TXS_LOGICAL:
 246       return "txs_logical";
 247    case FS_OPCODE_TXB:
 248       return "txb";
 249    case FS_OPCODE_TXB_LOGICAL:
 250       return "txb_logical";
 251    case SHADER_OPCODE_TXF_CMS:
 252       return "txf_cms";
 253    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 254       return "txf_cms_logical";
 255    case SHADER_OPCODE_TXF_CMS_W:
 256       return "txf_cms_w";
 257    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 258       return "txf_cms_w_logical";
 259    case SHADER_OPCODE_TXF_UMS:
 260       return "txf_ums";
 261    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 262       return "txf_ums_logical";
 263    case SHADER_OPCODE_TXF_MCS:
 264       return "txf_mcs";
 265    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 266       return "txf_mcs_logical";
 267    case SHADER_OPCODE_LOD:
 268       return "lod";
 269    case SHADER_OPCODE_LOD_LOGICAL:
 270       return "lod_logical";
 271    case SHADER_OPCODE_TG4:
 272       return "tg4";
 273    case SHADER_OPCODE_TG4_LOGICAL:
 274       return "tg4_logical";
 275    case SHADER_OPCODE_TG4_OFFSET:
 276       return "tg4_offset";
 277    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 278       return "tg4_offset_logical";
 279    case SHADER_OPCODE_SAMPLEINFO:
 280       return "sampleinfo";
 281    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 282       return "sampleinfo_logical";
 283
 284    case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
 285       return "image_size_logical";
 286
 287    case SHADER_OPCODE_SHADER_TIME_ADD:
 288       return "shader_time_add";
 289
 290    case VEC4_OPCODE_UNTYPED_ATOMIC:
 291       return "untyped_atomic";
 292    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 293       return "untyped_atomic_logical";
 294    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 295       return "untyped_atomic_float_logical";
 296    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
 297       return "untyped_surface_read";
 298    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 299       return "untyped_surface_read_logical";
 300    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
 301       return "untyped_surface_write";
 302    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 303       return "untyped_surface_write_logical";
 304    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
 305       return "a64_untyped_read_logical";
 306    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
 307       return "a64_untyped_write_logical";
 308    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
 309       return "a64_byte_scattered_read_logical";
 310    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
 311       return "a64_byte_scattered_write_logical";
 312    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
 313       return "a64_untyped_atomic_logical";
 314    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
 315       return "a64_untyped_atomic_int64_logical";
 316    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 317       return "a64_untyped_atomic_float_logical";
 318    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 319       return "typed_atomic_logical";
 320    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 321       return "typed_surface_read_logical";
 322    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 323       return "typed_surface_write_logical";
 324    case SHADER_OPCODE_MEMORY_FENCE:
 325       return "memory_fence";
 326    case FS_OPCODE_SCHEDULING_FENCE:
 327       return "scheduling_fence";
 328    case SHADER_OPCODE_INTERLOCK:
 329       /* For an interlock we actually issue a memory fence via sendc. */
 330       return "interlock";
 331
 332    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 333       return "byte_scattered_read_logical";
 334    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 335       return "byte_scattered_write_logical";
 336    case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
 337       return "dword_scattered_read_logical";
 338    case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
 339       return "dword_scattered_write_logical";
 340
 341    case SHADER_OPCODE_LOAD_PAYLOAD:
 342       return "load_payload";
 343    case FS_OPCODE_PACK:
 344       return "pack";
 345
 346    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 347       return "gen4_scratch_read";
 348    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 349       return "gen4_scratch_write";
 350    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 351       return "gen7_scratch_read";
 352    case SHADER_OPCODE_URB_WRITE_SIMD8:
 353       return "gen8_urb_write_simd8";
 354    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 355       return "gen8_urb_write_simd8_per_slot";
 356    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 357       return "gen8_urb_write_simd8_masked";
 358    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 359       return "gen8_urb_write_simd8_masked_per_slot";
 360    case SHADER_OPCODE_URB_READ_SIMD8:
 361       return "urb_read_simd8";
 362    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 363       return "urb_read_simd8_per_slot";
 364
 365    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 366       return "find_live_channel";
 367    case SHADER_OPCODE_BROADCAST:
 368       return "broadcast";
 369    case SHADER_OPCODE_SHUFFLE:
 370       return "shuffle";
 371    case SHADER_OPCODE_SEL_EXEC:
 372       return "sel_exec";
 373    case SHADER_OPCODE_QUAD_SWIZZLE:
 374       return "quad_swizzle";
 375    case SHADER_OPCODE_CLUSTER_BROADCAST:
 376       return "cluster_broadcast";
 377
 378    case SHADER_OPCODE_GET_BUFFER_SIZE:
 379       return "get_buffer_size";
 380
 381    case VEC4_OPCODE_MOV_BYTES:
 382       return "mov_bytes";
 383    case VEC4_OPCODE_PACK_BYTES:
 384       return "pack_bytes";
 385    case VEC4_OPCODE_UNPACK_UNIFORM:
 386       return "unpack_uniform";
 387    case VEC4_OPCODE_DOUBLE_TO_F32:
 388       return "double_to_f32";
 389    case VEC4_OPCODE_DOUBLE_TO_D32:
 390       return "double_to_d32";
 391    case VEC4_OPCODE_DOUBLE_TO_U32:
 392       return "double_to_u32";
 393    case VEC4_OPCODE_TO_DOUBLE:
 394       return "single_to_double";
 395    case VEC4_OPCODE_PICK_LOW_32BIT:
 396       return "pick_low_32bit";
 397    case VEC4_OPCODE_PICK_HIGH_32BIT:
 398       return "pick_high_32bit";
 399    case VEC4_OPCODE_SET_LOW_32BIT:
 400       return "set_low_32bit";
 401    case VEC4_OPCODE_SET_HIGH_32BIT:
 402       return "set_high_32bit";
 403
 404    case FS_OPCODE_DDX_COARSE:
 405       return "ddx_coarse";
 406    case FS_OPCODE_DDX_FINE:
 407       return "ddx_fine";
 408    case FS_OPCODE_DDY_COARSE:
 409       return "ddy_coarse";
 410    case FS_OPCODE_DDY_FINE:
 411       return "ddy_fine";
 412
 413    case FS_OPCODE_LINTERP:
 414       return "linterp";
 415
 416    case FS_OPCODE_PIXEL_X:
 417       return "pixel_x";
 418    case FS_OPCODE_PIXEL_Y:
 419       return "pixel_y";
 420
 421    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 422       return "uniform_pull_const";
 423    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 424       return "uniform_pull_const_gen7";
 425    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 426       return "varying_pull_const_gen4";
 427    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 428       return "varying_pull_const_logical";
 429
 430    case FS_OPCODE_DISCARD_JUMP:
 431       return "discard_jump";
 432
 433    case FS_OPCODE_SET_SAMPLE_ID:
 434       return "set_sample_id";
 435
 436    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 437       return "pack_half_2x16_split";
 438
 439    case FS_OPCODE_PLACEHOLDER_HALT:
 440       return "placeholder_halt";
 441
 442    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 443       return "interp_sample";
 444    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 445       return "interp_shared_offset";
 446    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 447       return "interp_per_slot_offset";
 448
 449    case VS_OPCODE_URB_WRITE:
 450       return "vs_urb_write";
 451    case VS_OPCODE_PULL_CONSTANT_LOAD:
 452       return "pull_constant_load";
 453    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 454       return "pull_constant_load_gen7";
 455
 456    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 457       return "set_simd4x2_header_gen9";
 458
 459    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 460       return "unpack_flags_simd4x2";
 461
 462    case GS_OPCODE_URB_WRITE:
 463       return "gs_urb_write";
 464    case GS_OPCODE_URB_WRITE_ALLOCATE:
 465       return "gs_urb_write_allocate";
 466    case GS_OPCODE_THREAD_END:
 467       return "gs_thread_end";
 468    case GS_OPCODE_SET_WRITE_OFFSET:
 469       return "set_write_offset";
 470    case GS_OPCODE_SET_VERTEX_COUNT:
 471       return "set_vertex_count";
 472    case GS_OPCODE_SET_DWORD_2:
 473       return "set_dword_2";
 474    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 475       return "prepare_channel_masks";
 476    case GS_OPCODE_SET_CHANNEL_MASKS:
 477       return "set_channel_masks";
 478    case GS_OPCODE_GET_INSTANCE_ID:
 479       return "get_instance_id";
 480    case GS_OPCODE_FF_SYNC:
 481       return "ff_sync";
 482    case GS_OPCODE_SET_PRIMITIVE_ID:
 483       return "set_primitive_id";
 484    case GS_OPCODE_SVB_WRITE:
 485       return "gs_svb_write";
 486    case GS_OPCODE_SVB_SET_DST_INDEX:
 487       return "gs_svb_set_dst_index";
 488    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 489       return "gs_ff_sync_set_primitives";
 490    case CS_OPCODE_CS_TERMINATE:
 491       return "cs_terminate";
 492    case SHADER_OPCODE_BARRIER:
 493       return "barrier";
 494    case SHADER_OPCODE_MULH:
 495       return "mulh";
 496    case SHADER_OPCODE_ISUB_SAT:
 497       return "isub_sat";
 498    case SHADER_OPCODE_USUB_SAT:
 499       return "usub_sat";
 500    case SHADER_OPCODE_MOV_INDIRECT:
 501       return "mov_indirect";
 502
 503    case VEC4_OPCODE_URB_READ:
 504       return "urb_read";
 505    case TCS_OPCODE_GET_INSTANCE_ID:
 506       return "tcs_get_instance_id";
 507    case TCS_OPCODE_URB_WRITE:
 508       return "tcs_urb_write";
 509    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 510       return "tcs_set_input_urb_offsets";
 511    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 512       return "tcs_set_output_urb_offsets";
 513    case TCS_OPCODE_GET_PRIMITIVE_ID:
 514       return "tcs_get_primitive_id";
 515    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 516       return "tcs_create_barrier_header";
 517    case TCS_OPCODE_SRC0_010_IS_ZERO:
 518       return "tcs_src0<0,1,0>_is_zero";
 519    case TCS_OPCODE_RELEASE_INPUT:
 520       return "tcs_release_input";
 521    case TCS_OPCODE_THREAD_END:
 522       return "tcs_thread_end";
 523    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 524       return "tes_create_input_read_header";
 525    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 526       return "tes_add_indirect_urb_offset";
 527    case TES_OPCODE_GET_PRIMITIVE_ID:
 528       return "tes_get_primitive_id";
 529
 530    case SHADER_OPCODE_RND_MODE:
 531       return "rnd_mode";
 532    case SHADER_OPCODE_FLOAT_CONTROL_MODE:
 533       return "float_control_mode";
 534    }
 535
 536    unreachable("not reached");
 537 }
 538
 539 bool
 540 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 541 {
 542    union {
 543       unsigned ud;
 544       int d;
 545       float f;
 546       double df;
 547    } imm, sat_imm = { 0 };
 548
 549    const unsigned size = type_sz(type);
 550
 551    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 552     * irrelevant, so just check the size of the type and copy from/to an
 553     * appropriately sized field.
 554     */
 555    if (size < 8)
 556       imm.ud = reg->ud;
 557    else
 558       imm.df = reg->df;
 559
 560    switch (type) {
 561    case BRW_REGISTER_TYPE_UD:
 562    case BRW_REGISTER_TYPE_D:
 563    case BRW_REGISTER_TYPE_UW:
 564    case BRW_REGISTER_TYPE_W:
 565    case BRW_REGISTER_TYPE_UQ:
 566    case BRW_REGISTER_TYPE_Q:
 567       /* Nothing to do. */
 568       return false;
 569    case BRW_REGISTER_TYPE_F:
 570       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 571       break;
 572    case BRW_REGISTER_TYPE_DF:
 573       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 574       break;
 575    case BRW_REGISTER_TYPE_UB:
 576    case BRW_REGISTER_TYPE_B:
 577       unreachable("no UB/B immediates");
 578    case BRW_REGISTER_TYPE_V:
 579    case BRW_REGISTER_TYPE_UV:
 580    case BRW_REGISTER_TYPE_VF:
 581       unreachable("unimplemented: saturate vector immediate");
 582    case BRW_REGISTER_TYPE_HF:
 583       unreachable("unimplemented: saturate HF immediate");
 584    case BRW_REGISTER_TYPE_NF:
 585       unreachable("no NF immediates");
 586    }
 587
 588    if (size < 8) {
 589       if (imm.ud != sat_imm.ud) {
 590          reg->ud = sat_imm.ud;
 591          return true;
 592       }
 593    } else {
 594       if (imm.df != sat_imm.df) {
 595          reg->df = sat_imm.df;
 596          return true;
 597       }
 598    }
 599    return false;
 600 }
 601
 602 bool
 603 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 604 {
 605    switch (type) {
 606    case BRW_REGISTER_TYPE_D:
 607    case BRW_REGISTER_TYPE_UD:
 608       reg->d = -reg->d;
 609       return true;
 610    case BRW_REGISTER_TYPE_W:
 611    case BRW_REGISTER_TYPE_UW: {
 612       uint16_t value = -(int16_t)reg->ud;
 613       reg->ud = value | (uint32_t)value << 16;
 614       return true;
 615    }
 616    case BRW_REGISTER_TYPE_F:
 617       reg->f = -reg->f;
 618       return true;
 619    case BRW_REGISTER_TYPE_VF:
 620       reg->ud ^= 0x80808080;
 621       return true;
 622    case BRW_REGISTER_TYPE_DF:
 623       reg->df = -reg->df;
 624       return true;
 625    case BRW_REGISTER_TYPE_UQ:
 626    case BRW_REGISTER_TYPE_Q:
 627       reg->d64 = -reg->d64;
 628       return true;
 629    case BRW_REGISTER_TYPE_UB:
 630    case BRW_REGISTER_TYPE_B:
 631       unreachable("no UB/B immediates");
 632    case BRW_REGISTER_TYPE_UV:
 633    case BRW_REGISTER_TYPE_V:
 634       assert(!"unimplemented: negate UV/V immediate");
 635    case BRW_REGISTER_TYPE_HF:
 636       reg->ud ^= 0x80008000;
 637       return true;
 638    case BRW_REGISTER_TYPE_NF:
 639       unreachable("no NF immediates");
 640    }
 641
 642    return false;
 643 }
 644
 645 bool
 646 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 647 {
 648    switch (type) {
 649    case BRW_REGISTER_TYPE_D:
 650       reg->d = abs(reg->d);
 651       return true;
 652    case BRW_REGISTER_TYPE_W: {
 653       uint16_t value = abs((int16_t)reg->ud);
 654       reg->ud = value | (uint32_t)value << 16;
 655       return true;
 656    }
 657    case BRW_REGISTER_TYPE_F:
 658       reg->f = fabsf(reg->f);
 659       return true;
 660    case BRW_REGISTER_TYPE_DF:
 661       reg->df = fabs(reg->df);
 662       return true;
 663    case BRW_REGISTER_TYPE_VF:
 664       reg->ud &= ~0x80808080;
 665       return true;
 666    case BRW_REGISTER_TYPE_Q:
 667       reg->d64 = imaxabs(reg->d64);
 668       return true;
 669    case BRW_REGISTER_TYPE_UB:
 670    case BRW_REGISTER_TYPE_B:
 671       unreachable("no UB/B immediates");
 672    case BRW_REGISTER_TYPE_UQ:
 673    case BRW_REGISTER_TYPE_UD:
 674    case BRW_REGISTER_TYPE_UW:
 675    case BRW_REGISTER_TYPE_UV:
 676       /* Presumably the absolute value modifier on an unsigned source is a
 677        * nop, but it would be nice to confirm.
 678        */
 679       assert(!"unimplemented: abs unsigned immediate");
 680    case BRW_REGISTER_TYPE_V:
 681       assert(!"unimplemented: abs V immediate");
 682    case BRW_REGISTER_TYPE_HF:
 683       reg->ud &= ~0x80008000;
 684       return true;
 685    case BRW_REGISTER_TYPE_NF:
 686       unreachable("no NF immediates");
 687    }
 688
 689    return false;
 690 }
 691
 692 backend_shader::backend_shader(const struct brw_compiler *compiler,
 693                                void *log_data,
 694                                void *mem_ctx,
 695                                const nir_shader *shader,
 696                                struct brw_stage_prog_data *stage_prog_data)
 697    : compiler(compiler),
 698      log_data(log_data),
 699      devinfo(compiler->devinfo),
 700      nir(shader),
 701      stage_prog_data(stage_prog_data),
 702      mem_ctx(mem_ctx),
 703      cfg(NULL),
 704      stage(shader->info.stage)
 705 {
 706    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 707    stage_name = _mesa_shader_stage_to_string(stage);
 708    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 709 }
 710
 711 backend_shader::~backend_shader()
 712 {
 713 }
 714
 715 bool
 716 backend_reg::equals(const backend_reg &r) const
 717 {
 718    return brw_regs_equal(this, &r) && offset == r.offset;
 719 }
 720
 721 bool
 722 backend_reg::negative_equals(const backend_reg &r) const
 723 {
 724    return brw_regs_negative_equal(this, &r) && offset == r.offset;
 725 }
 726
 727 bool
 728 backend_reg::is_zero() const
 729 {
 730    if (file != IMM)
 731       return false;
 732
 733    assert(type_sz(type) > 1);
 734
 735    switch (type) {
 736    case BRW_REGISTER_TYPE_HF:
 737       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 738       return (d & 0xffff) == 0 || (d & 0xffff) == 0x8000;
 739    case BRW_REGISTER_TYPE_F:
 740       return f == 0;
 741    case BRW_REGISTER_TYPE_DF:
 742       return df == 0;
 743    case BRW_REGISTER_TYPE_W:
 744    case BRW_REGISTER_TYPE_UW:
 745       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 746       return (d & 0xffff) == 0;
 747    case BRW_REGISTER_TYPE_D:
 748    case BRW_REGISTER_TYPE_UD:
 749       return d == 0;
 750    case BRW_REGISTER_TYPE_UQ:
 751    case BRW_REGISTER_TYPE_Q:
 752       return u64 == 0;
 753    default:
 754       return false;
 755    }
 756 }
 757
 758 bool
 759 backend_reg::is_one() const
 760 {
 761    if (file != IMM)
 762       return false;
 763
 764    assert(type_sz(type) > 1);
 765
 766    switch (type) {
 767    case BRW_REGISTER_TYPE_HF:
 768       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 769       return (d & 0xffff) == 0x3c00;
 770    case BRW_REGISTER_TYPE_F:
 771       return f == 1.0f;
 772    case BRW_REGISTER_TYPE_DF:
 773       return df == 1.0;
 774    case BRW_REGISTER_TYPE_W:
 775    case BRW_REGISTER_TYPE_UW:
 776       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 777       return (d & 0xffff) == 1;
 778    case BRW_REGISTER_TYPE_D:
 779    case BRW_REGISTER_TYPE_UD:
 780       return d == 1;
 781    case BRW_REGISTER_TYPE_UQ:
 782    case BRW_REGISTER_TYPE_Q:
 783       return u64 == 1;
 784    default:
 785       return false;
 786    }
 787 }
 788
 789 bool
 790 backend_reg::is_negative_one() const
 791 {
 792    if (file != IMM)
 793       return false;
 794
 795    assert(type_sz(type) > 1);
 796
 797    switch (type) {
 798    case BRW_REGISTER_TYPE_HF:
 799       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 800       return (d & 0xffff) == 0xbc00;
 801    case BRW_REGISTER_TYPE_F:
 802       return f == -1.0;
 803    case BRW_REGISTER_TYPE_DF:
 804       return df == -1.0;
 805    case BRW_REGISTER_TYPE_W:
 806       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 807       return (d & 0xffff) == 0xffff;
 808    case BRW_REGISTER_TYPE_D:
 809       return d == -1;
 810    case BRW_REGISTER_TYPE_Q:
 811       return d64 == -1;
 812    default:
 813       return false;
 814    }
 815 }
 816
 817 bool
 818 backend_reg::is_null() const
 819 {
 820    return file == ARF && nr == BRW_ARF_NULL;
 821 }
 822
 823
 824 bool
 825 backend_reg::is_accumulator() const
 826 {
 827    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 828 }
 829
 830 bool
 831 backend_instruction::is_commutative() const
 832 {
 833    switch (opcode) {
 834    case BRW_OPCODE_AND:
 835    case BRW_OPCODE_OR:
 836    case BRW_OPCODE_XOR:
 837    case BRW_OPCODE_ADD:
 838    case BRW_OPCODE_MUL:
 839    case SHADER_OPCODE_MULH:
 840       return true;
 841    case BRW_OPCODE_SEL:
 842       /* MIN and MAX are commutative. */
 843       if (conditional_mod == BRW_CONDITIONAL_GE ||
 844           conditional_mod == BRW_CONDITIONAL_L) {
 845          return true;
 846       }
 847       /* fallthrough */
 848    default:
 849       return false;
 850    }
 851 }
 852
 853 bool
 854 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 855 {
 856    return ::is_3src(devinfo, opcode);
 857 }
 858
 859 bool
 860 backend_instruction::is_tex() const
 861 {
 862    return (opcode == SHADER_OPCODE_TEX ||
 863            opcode == FS_OPCODE_TXB ||
 864            opcode == SHADER_OPCODE_TXD ||
 865            opcode == SHADER_OPCODE_TXF ||
 866            opcode == SHADER_OPCODE_TXF_LZ ||
 867            opcode == SHADER_OPCODE_TXF_CMS ||
 868            opcode == SHADER_OPCODE_TXF_CMS_W ||
 869            opcode == SHADER_OPCODE_TXF_UMS ||
 870            opcode == SHADER_OPCODE_TXF_MCS ||
 871            opcode == SHADER_OPCODE_TXL ||
 872            opcode == SHADER_OPCODE_TXL_LZ ||
 873            opcode == SHADER_OPCODE_TXS ||
 874            opcode == SHADER_OPCODE_LOD ||
 875            opcode == SHADER_OPCODE_TG4 ||
 876            opcode == SHADER_OPCODE_TG4_OFFSET ||
 877            opcode == SHADER_OPCODE_SAMPLEINFO);
 878 }
 879
 880 bool
 881 backend_instruction::is_math() const
 882 {
 883    return (opcode == SHADER_OPCODE_RCP ||
 884            opcode == SHADER_OPCODE_RSQ ||
 885            opcode == SHADER_OPCODE_SQRT ||
 886            opcode == SHADER_OPCODE_EXP2 ||
 887            opcode == SHADER_OPCODE_LOG2 ||
 888            opcode == SHADER_OPCODE_SIN ||
 889            opcode == SHADER_OPCODE_COS ||
 890            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 891            opcode == SHADER_OPCODE_INT_REMAINDER ||
 892            opcode == SHADER_OPCODE_POW);
 893 }
 894
 895 bool
 896 backend_instruction::is_control_flow() const
 897 {
 898    switch (opcode) {
 899    case BRW_OPCODE_DO:
 900    case BRW_OPCODE_WHILE:
 901    case BRW_OPCODE_IF:
 902    case BRW_OPCODE_ELSE:
 903    case BRW_OPCODE_ENDIF:
 904    case BRW_OPCODE_BREAK:
 905    case BRW_OPCODE_CONTINUE:
 906       return true;
 907    default:
 908       return false;
 909    }
 910 }
 911
 912 bool
 913 backend_instruction::can_do_source_mods() const
 914 {
 915    switch (opcode) {
 916    case BRW_OPCODE_ADDC:
 917    case BRW_OPCODE_BFE:
 918    case BRW_OPCODE_BFI1:
 919    case BRW_OPCODE_BFI2:
 920    case BRW_OPCODE_BFREV:
 921    case BRW_OPCODE_CBIT:
 922    case BRW_OPCODE_FBH:
 923    case BRW_OPCODE_FBL:
 924    case BRW_OPCODE_SUBB:
 925    case SHADER_OPCODE_BROADCAST:
 926    case SHADER_OPCODE_CLUSTER_BROADCAST:
 927    case SHADER_OPCODE_MOV_INDIRECT:
 928       return false;
 929    default:
 930       return true;
 931    }
 932 }
 933
 934 bool
 935 backend_instruction::can_do_saturate() const
 936 {
 937    switch (opcode) {
 938    case BRW_OPCODE_ADD:
 939    case BRW_OPCODE_ASR:
 940    case BRW_OPCODE_AVG:
 941    case BRW_OPCODE_DP2:
 942    case BRW_OPCODE_DP3:
 943    case BRW_OPCODE_DP4:
 944    case BRW_OPCODE_DPH:
 945    case BRW_OPCODE_F16TO32:
 946    case BRW_OPCODE_F32TO16:
 947    case BRW_OPCODE_LINE:
 948    case BRW_OPCODE_LRP:
 949    case BRW_OPCODE_MAC:
 950    case BRW_OPCODE_MAD:
 951    case BRW_OPCODE_MATH:
 952    case BRW_OPCODE_MOV:
 953    case BRW_OPCODE_MUL:
 954    case SHADER_OPCODE_MULH:
 955    case BRW_OPCODE_PLN:
 956    case BRW_OPCODE_RNDD:
 957    case BRW_OPCODE_RNDE:
 958    case BRW_OPCODE_RNDU:
 959    case BRW_OPCODE_RNDZ:
 960    case BRW_OPCODE_SEL:
 961    case BRW_OPCODE_SHL:
 962    case BRW_OPCODE_SHR:
 963    case FS_OPCODE_LINTERP:
 964    case SHADER_OPCODE_COS:
 965    case SHADER_OPCODE_EXP2:
 966    case SHADER_OPCODE_LOG2:
 967    case SHADER_OPCODE_POW:
 968    case SHADER_OPCODE_RCP:
 969    case SHADER_OPCODE_RSQ:
 970    case SHADER_OPCODE_SIN:
 971    case SHADER_OPCODE_SQRT:
 972       return true;
 973    default:
 974       return false;
 975    }
 976 }
 977
 978 bool
 979 backend_instruction::can_do_cmod() const
 980 {
 981    switch (opcode) {
 982    case BRW_OPCODE_ADD:
 983    case BRW_OPCODE_ADDC:
 984    case BRW_OPCODE_AND:
 985    case BRW_OPCODE_ASR:
 986    case BRW_OPCODE_AVG:
 987    case BRW_OPCODE_CMP:
 988    case BRW_OPCODE_CMPN:
 989    case BRW_OPCODE_DP2:
 990    case BRW_OPCODE_DP3:
 991    case BRW_OPCODE_DP4:
 992    case BRW_OPCODE_DPH:
 993    case BRW_OPCODE_F16TO32:
 994    case BRW_OPCODE_F32TO16:
 995    case BRW_OPCODE_FRC:
 996    case BRW_OPCODE_LINE:
 997    case BRW_OPCODE_LRP:
 998    case BRW_OPCODE_LZD:
 999    case BRW_OPCODE_MAC:
1000    case BRW_OPCODE_MACH:
1001    case BRW_OPCODE_MAD:
1002    case BRW_OPCODE_MOV:
1003    case BRW_OPCODE_MUL:
1004    case BRW_OPCODE_NOT:
1005    case BRW_OPCODE_OR:
1006    case BRW_OPCODE_PLN:
1007    case BRW_OPCODE_RNDD:
1008    case BRW_OPCODE_RNDE:
1009    case BRW_OPCODE_RNDU:
1010    case BRW_OPCODE_RNDZ:
1011    case BRW_OPCODE_SAD2:
1012    case BRW_OPCODE_SADA2:
1013    case BRW_OPCODE_SHL:
1014    case BRW_OPCODE_SHR:
1015    case BRW_OPCODE_SUBB:
1016    case BRW_OPCODE_XOR:
1017    case FS_OPCODE_LINTERP:
1018       return true;
1019    default:
1020       return false;
1021    }
1022 }
1023
1024 bool
1025 backend_instruction::reads_accumulator_implicitly() const
1026 {
1027    switch (opcode) {
1028    case BRW_OPCODE_MAC:
1029    case BRW_OPCODE_MACH:
1030    case BRW_OPCODE_SADA2:
1031       return true;
1032    default:
1033       return false;
1034    }
1035 }
1036
1037 bool
1038 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
1039 {
1040    return writes_accumulator ||
1041           (devinfo->gen < 6 &&
1042            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1043             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
1044           (opcode == FS_OPCODE_LINTERP &&
1045            (!devinfo->has_pln || devinfo->gen <= 6));
1046 }
1047
1048 bool
1049 backend_instruction::has_side_effects() const
1050 {
1051    switch (opcode) {
1052    case SHADER_OPCODE_SEND:
1053       return send_has_side_effects;
1054
1055    case BRW_OPCODE_SYNC:
1056    case VEC4_OPCODE_UNTYPED_ATOMIC:
1057    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1058    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1059    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1060    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
1061    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1062    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
1063    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
1064    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
1065    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
1066    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1067    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1068    case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
1069    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1070    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1071    case SHADER_OPCODE_MEMORY_FENCE:
1072    case SHADER_OPCODE_INTERLOCK:
1073    case SHADER_OPCODE_URB_WRITE_SIMD8:
1074    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1075    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1076    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1077    case FS_OPCODE_FB_WRITE:
1078    case FS_OPCODE_FB_WRITE_LOGICAL:
1079    case FS_OPCODE_REP_FB_WRITE:
1080    case SHADER_OPCODE_BARRIER:
1081    case TCS_OPCODE_URB_WRITE:
1082    case TCS_OPCODE_RELEASE_INPUT:
1083    case SHADER_OPCODE_RND_MODE:
1084    case SHADER_OPCODE_FLOAT_CONTROL_MODE:
1085    case FS_OPCODE_SCHEDULING_FENCE:
1086       return true;
1087    default:
1088       return eot;
1089    }
1090 }
1091
1092 bool
1093 backend_instruction::is_volatile() const
1094 {
1095    switch (opcode) {
1096    case SHADER_OPCODE_SEND:
1097       return send_is_volatile;
1098
1099    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
1100    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1101    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1102    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1103    case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
1104    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
1105    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
1106    case SHADER_OPCODE_URB_READ_SIMD8:
1107    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1108    case VEC4_OPCODE_URB_READ:
1109       return true;
1110    default:
1111       return false;
1112    }
1113 }
1114
1115 #ifndef NDEBUG
1116 static bool
1117 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1118 {
1119    bool found = false;
1120    foreach_inst_in_block (backend_instruction, i, block) {
1121       if (inst == i) {
1122          found = true;
1123       }
1124    }
1125    return found;
1126 }
1127 #endif
1128
1129 static void
1130 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1131 {
1132    for (bblock_t *block_iter = start_block->next();
1133         block_iter;
1134         block_iter = block_iter->next()) {
1135       block_iter->start_ip += ip_adjustment;
1136       block_iter->end_ip += ip_adjustment;
1137    }
1138 }
1139
1140 void
1141 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1142 {
1143    assert(this != inst);
1144
1145    if (!this->is_head_sentinel())
1146       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1147
1148    block->end_ip++;
1149
1150    adjust_later_block_ips(block, 1);
1151
1152    exec_node::insert_after(inst);
1153 }
1154
1155 void
1156 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1157 {
1158    assert(this != inst);
1159
1160    if (!this->is_tail_sentinel())
1161       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1162
1163    block->end_ip++;
1164
1165    adjust_later_block_ips(block, 1);
1166
1167    exec_node::insert_before(inst);
1168 }
1169
1170 void
1171 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1172 {
1173    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1174
1175    unsigned num_inst = list->length();
1176
1177    block->end_ip += num_inst;
1178
1179    adjust_later_block_ips(block, num_inst);
1180
1181    exec_node::insert_before(list);
1182 }
1183
1184 void
1185 backend_instruction::remove(bblock_t *block)
1186 {
1187    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1188
1189    adjust_later_block_ips(block, -1);
1190
1191    if (block->start_ip == block->end_ip) {
1192       block->cfg->remove_block(block);
1193    } else {
1194       block->end_ip--;
1195    }
1196
1197    exec_node::remove();
1198 }
1199
1200 void
1201 backend_shader::dump_instructions()
1202 {
1203    dump_instructions(NULL);
1204 }
1205
1206 void
1207 backend_shader::dump_instructions(const char *name)
1208 {
1209    FILE *file = stderr;
1210    if (name && geteuid() != 0) {
1211       file = fopen(name, "w");
1212       if (!file)
1213          file = stderr;
1214    }
1215
1216    if (cfg) {
1217       int ip = 0;
1218       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1219          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1220             fprintf(file, "%4d: ", ip++);
1221          dump_instruction(inst, file);
1222       }
1223    } else {
1224       int ip = 0;
1225       foreach_in_list(backend_instruction, inst, &instructions) {
1226          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1227             fprintf(file, "%4d: ", ip++);
1228          dump_instruction(inst, file);
1229       }
1230    }
1231
1232    if (file != stderr) {
1233       fclose(file);
1234    }
1235 }
1236
1237 void
1238 backend_shader::calculate_cfg()
1239 {
1240    if (this->cfg)
1241       return;
1242    cfg = new(mem_ctx) cfg_t(&this->instructions);
1243 }
1244
1245 extern "C" const unsigned *
1246 brw_compile_tes(const struct brw_compiler *compiler,
1247                 void *log_data,
1248                 void *mem_ctx,
1249                 const struct brw_tes_prog_key *key,
1250                 const struct brw_vue_map *input_vue_map,
1251                 struct brw_tes_prog_data *prog_data,
1252                 nir_shader *nir,
1253                 int shader_time_index,
1254                 struct brw_compile_stats *stats,
1255                 char **error_str)
1256 {
1257    const struct gen_device_info *devinfo = compiler->devinfo;
1258    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1259    const unsigned *assembly;
1260
1261    nir->info.inputs_read = key->inputs_read;
1262    nir->info.patch_inputs_read = key->patch_inputs_read;
1263
1264    brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
1265    brw_nir_lower_tes_inputs(nir, input_vue_map);
1266    brw_nir_lower_vue_outputs(nir);
1267    brw_postprocess_nir(nir, compiler, is_scalar);
1268
1269    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1270                        nir->info.outputs_written,
1271                        nir->info.separate_shader);
1272
1273    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1274
1275    assert(output_size_bytes >= 1);
1276    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1277       if (error_str)
1278          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1279       return NULL;
1280    }
1281
1282    prog_data->base.clip_distance_mask =
1283       ((1 << nir->info.clip_distance_array_size) - 1);
1284    prog_data->base.cull_distance_mask =
1285       ((1 << nir->info.cull_distance_array_size) - 1) <<
1286       nir->info.clip_distance_array_size;
1287
1288    /* URB entry sizes are stored as a multiple of 64 bytes. */
1289    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1290
1291    /* On Cannonlake software shall not program an allocation size that
1292     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1293     */
1294    if (devinfo->gen == 10 &&
1295        prog_data->base.urb_entry_size % 3 == 0)
1296       prog_data->base.urb_entry_size++;
1297
1298    prog_data->base.urb_read_length = 0;
1299
1300    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1301    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1302                  TESS_SPACING_FRACTIONAL_ODD - 1);
1303    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1304                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1305
1306    prog_data->partitioning =
1307       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1308
1309    switch (nir->info.tess.primitive_mode) {
1310    case GL_QUADS:
1311       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1312       break;
1313    case GL_TRIANGLES:
1314       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1315       break;
1316    case GL_ISOLINES:
1317       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1318       break;
1319    default:
1320       unreachable("invalid domain shader primitive mode");
1321    }
1322
1323    if (nir->info.tess.point_mode) {
1324       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1325    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1326       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1327    } else {
1328       /* Hardware winding order is backwards from OpenGL */
1329       prog_data->output_topology =
1330          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1331                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1332    }
1333
1334    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1335       fprintf(stderr, "TES Input ");
1336       brw_print_vue_map(stderr, input_vue_map);
1337       fprintf(stderr, "TES Output ");
1338       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1339    }
1340
1341    if (is_scalar) {
1342       fs_visitor v(compiler, log_data, mem_ctx, &key->base,
1343                    &prog_data->base.base, nir, 8,
1344                    shader_time_index, input_vue_map);
1345       if (!v.run_tes()) {
1346          if (error_str)
1347             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1348          return NULL;
1349       }
1350
1351       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1352       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1353
1354       fs_generator g(compiler, log_data, mem_ctx,
1355                      &prog_data->base.base, v.shader_stats, false,
1356                      MESA_SHADER_TESS_EVAL);
1357       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1358          g.enable_debug(ralloc_asprintf(mem_ctx,
1359                                         "%s tessellation evaluation shader %s",
1360                                         nir->info.label ? nir->info.label
1361                                                         : "unnamed",
1362                                         nir->info.name));
1363       }
1364
1365       g.generate_code(v.cfg, 8, stats);
1366
1367       assembly = g.get_assembly();
1368    } else {
1369       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1370                               nir, mem_ctx, shader_time_index);
1371       if (!v.run()) {
1372          if (error_str)
1373             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1374          return NULL;
1375       }
1376
1377       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1378          v.dump_instructions();
1379
1380       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1381                                             &prog_data->base, v.cfg, stats);
1382    }
1383
1384    return assembly;
1385 }