src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "common/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_UINT:
  48       return BRW_REGISTER_TYPE_UD;
  49    case GLSL_TYPE_UINT16:
  50       return BRW_REGISTER_TYPE_UW;
  51    case GLSL_TYPE_ARRAY:
  52       return brw_type_for_base_type(type->fields.array);
  53    case GLSL_TYPE_STRUCT:
  54    case GLSL_TYPE_SAMPLER:
  55    case GLSL_TYPE_ATOMIC_UINT:
  56       /* These should be overridden with the type of the member when
  57        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  58        * way to trip up if we don't.
  59        */
  60       return BRW_REGISTER_TYPE_UD;
  61    case GLSL_TYPE_IMAGE:
  62       return BRW_REGISTER_TYPE_UD;
  63    case GLSL_TYPE_DOUBLE:
  64       return BRW_REGISTER_TYPE_DF;
  65    case GLSL_TYPE_UINT64:
  66       return BRW_REGISTER_TYPE_UQ;
  67    case GLSL_TYPE_INT64:
  68       return BRW_REGISTER_TYPE_Q;
  69    case GLSL_TYPE_VOID:
  70    case GLSL_TYPE_ERROR:
  71    case GLSL_TYPE_INTERFACE:
  72    case GLSL_TYPE_FUNCTION:
  73       unreachable("not reached");
  74    }
  75
  76    return BRW_REGISTER_TYPE_F;
  77 }
  78
  79 enum brw_conditional_mod
  80 brw_conditional_for_comparison(unsigned int op)
  81 {
  82    switch (op) {
  83    case ir_binop_less:
  84       return BRW_CONDITIONAL_L;
  85    case ir_binop_gequal:
  86       return BRW_CONDITIONAL_GE;
  87    case ir_binop_equal:
  88    case ir_binop_all_equal: /* same as equal for scalars */
  89       return BRW_CONDITIONAL_Z;
  90    case ir_binop_nequal:
  91    case ir_binop_any_nequal: /* same as nequal for scalars */
  92       return BRW_CONDITIONAL_NZ;
  93    default:
  94       unreachable("not reached: bad operation for comparison");
  95    }
  96 }
  97
  98 uint32_t
  99 brw_math_function(enum opcode op)
 100 {
 101    switch (op) {
 102    case SHADER_OPCODE_RCP:
 103       return BRW_MATH_FUNCTION_INV;
 104    case SHADER_OPCODE_RSQ:
 105       return BRW_MATH_FUNCTION_RSQ;
 106    case SHADER_OPCODE_SQRT:
 107       return BRW_MATH_FUNCTION_SQRT;
 108    case SHADER_OPCODE_EXP2:
 109       return BRW_MATH_FUNCTION_EXP;
 110    case SHADER_OPCODE_LOG2:
 111       return BRW_MATH_FUNCTION_LOG;
 112    case SHADER_OPCODE_POW:
 113       return BRW_MATH_FUNCTION_POW;
 114    case SHADER_OPCODE_SIN:
 115       return BRW_MATH_FUNCTION_SIN;
 116    case SHADER_OPCODE_COS:
 117       return BRW_MATH_FUNCTION_COS;
 118    case SHADER_OPCODE_INT_QUOTIENT:
 119       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 120    case SHADER_OPCODE_INT_REMAINDER:
 121       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 122    default:
 123       unreachable("not reached: unknown math function");
 124    }
 125 }
 126
 127 bool
 128 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 129 {
 130    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 131
 132    /* offset out of bounds; caller will handle it. */
 133    for (unsigned i = 0; i < num_components; i++)
 134       if (offsets[i] > 7 || offsets[i] < -8)
 135          return false;
 136
 137    /* Combine all three offsets into a single unsigned dword:
 138     *
 139     *    bits 11:8 - U Offset (X component)
 140     *    bits  7:4 - V Offset (Y component)
 141     *    bits  3:0 - R Offset (Z component)
 142     */
 143    *offset_bits = 0;
 144    for (unsigned i = 0; i < num_components; i++) {
 145       const unsigned shift = 4 * (2 - i);
 146       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 147    }
 148    return true;
 149 }
 150
 151 const char *
 152 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 153 {
 154    switch (op) {
 155    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 156       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 157        * start of a loop in the IR.
 158        */
 159       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 160          return "do";
 161
 162       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 163        * then to mark that we want to do the conversion.
 164        */
 165       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 166          return "f32to16";
 167
 168       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 169          return "f16to32";
 170
 171       assert(brw_opcode_desc(devinfo, op)->name);
 172       return brw_opcode_desc(devinfo, op)->name;
 173    case FS_OPCODE_FB_WRITE:
 174       return "fb_write";
 175    case FS_OPCODE_FB_WRITE_LOGICAL:
 176       return "fb_write_logical";
 177    case FS_OPCODE_REP_FB_WRITE:
 178       return "rep_fb_write";
 179    case FS_OPCODE_FB_READ:
 180       return "fb_read";
 181    case FS_OPCODE_FB_READ_LOGICAL:
 182       return "fb_read_logical";
 183
 184    case SHADER_OPCODE_RCP:
 185       return "rcp";
 186    case SHADER_OPCODE_RSQ:
 187       return "rsq";
 188    case SHADER_OPCODE_SQRT:
 189       return "sqrt";
 190    case SHADER_OPCODE_EXP2:
 191       return "exp2";
 192    case SHADER_OPCODE_LOG2:
 193       return "log2";
 194    case SHADER_OPCODE_POW:
 195       return "pow";
 196    case SHADER_OPCODE_INT_QUOTIENT:
 197       return "int_quot";
 198    case SHADER_OPCODE_INT_REMAINDER:
 199       return "int_rem";
 200    case SHADER_OPCODE_SIN:
 201       return "sin";
 202    case SHADER_OPCODE_COS:
 203       return "cos";
 204
 205    case SHADER_OPCODE_TEX:
 206       return "tex";
 207    case SHADER_OPCODE_TEX_LOGICAL:
 208       return "tex_logical";
 209    case SHADER_OPCODE_TXD:
 210       return "txd";
 211    case SHADER_OPCODE_TXD_LOGICAL:
 212       return "txd_logical";
 213    case SHADER_OPCODE_TXF:
 214       return "txf";
 215    case SHADER_OPCODE_TXF_LOGICAL:
 216       return "txf_logical";
 217    case SHADER_OPCODE_TXF_LZ:
 218       return "txf_lz";
 219    case SHADER_OPCODE_TXL:
 220       return "txl";
 221    case SHADER_OPCODE_TXL_LOGICAL:
 222       return "txl_logical";
 223    case SHADER_OPCODE_TXL_LZ:
 224       return "txl_lz";
 225    case SHADER_OPCODE_TXS:
 226       return "txs";
 227    case SHADER_OPCODE_TXS_LOGICAL:
 228       return "txs_logical";
 229    case FS_OPCODE_TXB:
 230       return "txb";
 231    case FS_OPCODE_TXB_LOGICAL:
 232       return "txb_logical";
 233    case SHADER_OPCODE_TXF_CMS:
 234       return "txf_cms";
 235    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 236       return "txf_cms_logical";
 237    case SHADER_OPCODE_TXF_CMS_W:
 238       return "txf_cms_w";
 239    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 240       return "txf_cms_w_logical";
 241    case SHADER_OPCODE_TXF_UMS:
 242       return "txf_ums";
 243    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 244       return "txf_ums_logical";
 245    case SHADER_OPCODE_TXF_MCS:
 246       return "txf_mcs";
 247    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 248       return "txf_mcs_logical";
 249    case SHADER_OPCODE_LOD:
 250       return "lod";
 251    case SHADER_OPCODE_LOD_LOGICAL:
 252       return "lod_logical";
 253    case SHADER_OPCODE_TG4:
 254       return "tg4";
 255    case SHADER_OPCODE_TG4_LOGICAL:
 256       return "tg4_logical";
 257    case SHADER_OPCODE_TG4_OFFSET:
 258       return "tg4_offset";
 259    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 260       return "tg4_offset_logical";
 261    case SHADER_OPCODE_SAMPLEINFO:
 262       return "sampleinfo";
 263    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 264       return "sampleinfo_logical";
 265
 266    case SHADER_OPCODE_SHADER_TIME_ADD:
 267       return "shader_time_add";
 268
 269    case SHADER_OPCODE_UNTYPED_ATOMIC:
 270       return "untyped_atomic";
 271    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 272       return "untyped_atomic_logical";
 273    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 274       return "untyped_surface_read";
 275    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 276       return "untyped_surface_read_logical";
 277    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 278       return "untyped_surface_write";
 279    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 280       return "untyped_surface_write_logical";
 281    case SHADER_OPCODE_TYPED_ATOMIC:
 282       return "typed_atomic";
 283    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 284       return "typed_atomic_logical";
 285    case SHADER_OPCODE_TYPED_SURFACE_READ:
 286       return "typed_surface_read";
 287    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 288       return "typed_surface_read_logical";
 289    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 290       return "typed_surface_write";
 291    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 292       return "typed_surface_write_logical";
 293    case SHADER_OPCODE_MEMORY_FENCE:
 294       return "memory_fence";
 295
 296    case SHADER_OPCODE_LOAD_PAYLOAD:
 297       return "load_payload";
 298    case FS_OPCODE_PACK:
 299       return "pack";
 300
 301    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 302       return "gen4_scratch_read";
 303    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 304       return "gen4_scratch_write";
 305    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 306       return "gen7_scratch_read";
 307    case SHADER_OPCODE_URB_WRITE_SIMD8:
 308       return "gen8_urb_write_simd8";
 309    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 310       return "gen8_urb_write_simd8_per_slot";
 311    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 312       return "gen8_urb_write_simd8_masked";
 313    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 314       return "gen8_urb_write_simd8_masked_per_slot";
 315    case SHADER_OPCODE_URB_READ_SIMD8:
 316       return "urb_read_simd8";
 317    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 318       return "urb_read_simd8_per_slot";
 319
 320    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 321       return "find_live_channel";
 322    case SHADER_OPCODE_BROADCAST:
 323       return "broadcast";
 324
 325    case VEC4_OPCODE_MOV_BYTES:
 326       return "mov_bytes";
 327    case VEC4_OPCODE_PACK_BYTES:
 328       return "pack_bytes";
 329    case VEC4_OPCODE_UNPACK_UNIFORM:
 330       return "unpack_uniform";
 331    case VEC4_OPCODE_DOUBLE_TO_F32:
 332       return "double_to_f32";
 333    case VEC4_OPCODE_DOUBLE_TO_D32:
 334       return "double_to_d32";
 335    case VEC4_OPCODE_DOUBLE_TO_U32:
 336       return "double_to_u32";
 337    case VEC4_OPCODE_TO_DOUBLE:
 338       return "single_to_double";
 339    case VEC4_OPCODE_PICK_LOW_32BIT:
 340       return "pick_low_32bit";
 341    case VEC4_OPCODE_PICK_HIGH_32BIT:
 342       return "pick_high_32bit";
 343    case VEC4_OPCODE_SET_LOW_32BIT:
 344       return "set_low_32bit";
 345    case VEC4_OPCODE_SET_HIGH_32BIT:
 346       return "set_high_32bit";
 347
 348    case FS_OPCODE_DDX_COARSE:
 349       return "ddx_coarse";
 350    case FS_OPCODE_DDX_FINE:
 351       return "ddx_fine";
 352    case FS_OPCODE_DDY_COARSE:
 353       return "ddy_coarse";
 354    case FS_OPCODE_DDY_FINE:
 355       return "ddy_fine";
 356
 357    case FS_OPCODE_CINTERP:
 358       return "cinterp";
 359    case FS_OPCODE_LINTERP:
 360       return "linterp";
 361
 362    case FS_OPCODE_PIXEL_X:
 363       return "pixel_x";
 364    case FS_OPCODE_PIXEL_Y:
 365       return "pixel_y";
 366
 367    case FS_OPCODE_GET_BUFFER_SIZE:
 368       return "fs_get_buffer_size";
 369
 370    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 371       return "uniform_pull_const";
 372    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 373       return "uniform_pull_const_gen7";
 374    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 375       return "varying_pull_const_gen4";
 376    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 377       return "varying_pull_const_gen7";
 378    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 379       return "varying_pull_const_logical";
 380
 381    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 382       return "mov_dispatch_to_flags";
 383    case FS_OPCODE_DISCARD_JUMP:
 384       return "discard_jump";
 385
 386    case FS_OPCODE_SET_SAMPLE_ID:
 387       return "set_sample_id";
 388
 389    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 390       return "pack_half_2x16_split";
 391    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 392       return "unpack_half_2x16_split_x";
 393    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 394       return "unpack_half_2x16_split_y";
 395
 396    case FS_OPCODE_PLACEHOLDER_HALT:
 397       return "placeholder_halt";
 398
 399    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 400       return "interp_sample";
 401    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 402       return "interp_shared_offset";
 403    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 404       return "interp_per_slot_offset";
 405
 406    case VS_OPCODE_URB_WRITE:
 407       return "vs_urb_write";
 408    case VS_OPCODE_PULL_CONSTANT_LOAD:
 409       return "pull_constant_load";
 410    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 411       return "pull_constant_load_gen7";
 412
 413    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 414       return "set_simd4x2_header_gen9";
 415
 416    case VS_OPCODE_GET_BUFFER_SIZE:
 417       return "vs_get_buffer_size";
 418
 419    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 420       return "unpack_flags_simd4x2";
 421
 422    case GS_OPCODE_URB_WRITE:
 423       return "gs_urb_write";
 424    case GS_OPCODE_URB_WRITE_ALLOCATE:
 425       return "gs_urb_write_allocate";
 426    case GS_OPCODE_THREAD_END:
 427       return "gs_thread_end";
 428    case GS_OPCODE_SET_WRITE_OFFSET:
 429       return "set_write_offset";
 430    case GS_OPCODE_SET_VERTEX_COUNT:
 431       return "set_vertex_count";
 432    case GS_OPCODE_SET_DWORD_2:
 433       return "set_dword_2";
 434    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 435       return "prepare_channel_masks";
 436    case GS_OPCODE_SET_CHANNEL_MASKS:
 437       return "set_channel_masks";
 438    case GS_OPCODE_GET_INSTANCE_ID:
 439       return "get_instance_id";
 440    case GS_OPCODE_FF_SYNC:
 441       return "ff_sync";
 442    case GS_OPCODE_SET_PRIMITIVE_ID:
 443       return "set_primitive_id";
 444    case GS_OPCODE_SVB_WRITE:
 445       return "gs_svb_write";
 446    case GS_OPCODE_SVB_SET_DST_INDEX:
 447       return "gs_svb_set_dst_index";
 448    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 449       return "gs_ff_sync_set_primitives";
 450    case CS_OPCODE_CS_TERMINATE:
 451       return "cs_terminate";
 452    case SHADER_OPCODE_BARRIER:
 453       return "barrier";
 454    case SHADER_OPCODE_MULH:
 455       return "mulh";
 456    case SHADER_OPCODE_MOV_INDIRECT:
 457       return "mov_indirect";
 458
 459    case VEC4_OPCODE_URB_READ:
 460       return "urb_read";
 461    case TCS_OPCODE_GET_INSTANCE_ID:
 462       return "tcs_get_instance_id";
 463    case TCS_OPCODE_URB_WRITE:
 464       return "tcs_urb_write";
 465    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 466       return "tcs_set_input_urb_offsets";
 467    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 468       return "tcs_set_output_urb_offsets";
 469    case TCS_OPCODE_GET_PRIMITIVE_ID:
 470       return "tcs_get_primitive_id";
 471    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 472       return "tcs_create_barrier_header";
 473    case TCS_OPCODE_SRC0_010_IS_ZERO:
 474       return "tcs_src0<0,1,0>_is_zero";
 475    case TCS_OPCODE_RELEASE_INPUT:
 476       return "tcs_release_input";
 477    case TCS_OPCODE_THREAD_END:
 478       return "tcs_thread_end";
 479    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 480       return "tes_create_input_read_header";
 481    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 482       return "tes_add_indirect_urb_offset";
 483    case TES_OPCODE_GET_PRIMITIVE_ID:
 484       return "tes_get_primitive_id";
 485    }
 486
 487    unreachable("not reached");
 488 }
 489
 490 bool
 491 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 492 {
 493    union {
 494       unsigned ud;
 495       int d;
 496       float f;
 497       double df;
 498    } imm, sat_imm = { 0 };
 499
 500    const unsigned size = type_sz(type);
 501
 502    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 503     * irrelevant, so just check the size of the type and copy from/to an
 504     * appropriately sized field.
 505     */
 506    if (size < 8)
 507       imm.ud = reg->ud;
 508    else
 509       imm.df = reg->df;
 510
 511    switch (type) {
 512    case BRW_REGISTER_TYPE_UD:
 513    case BRW_REGISTER_TYPE_D:
 514    case BRW_REGISTER_TYPE_UW:
 515    case BRW_REGISTER_TYPE_W:
 516    case BRW_REGISTER_TYPE_UQ:
 517    case BRW_REGISTER_TYPE_Q:
 518       /* Nothing to do. */
 519       return false;
 520    case BRW_REGISTER_TYPE_F:
 521       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 522       break;
 523    case BRW_REGISTER_TYPE_DF:
 524       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 525       break;
 526    case BRW_REGISTER_TYPE_UB:
 527    case BRW_REGISTER_TYPE_B:
 528       unreachable("no UB/B immediates");
 529    case BRW_REGISTER_TYPE_V:
 530    case BRW_REGISTER_TYPE_UV:
 531    case BRW_REGISTER_TYPE_VF:
 532       unreachable("unimplemented: saturate vector immediate");
 533    case BRW_REGISTER_TYPE_HF:
 534       unreachable("unimplemented: saturate HF immediate");
 535    }
 536
 537    if (size < 8) {
 538       if (imm.ud != sat_imm.ud) {
 539          reg->ud = sat_imm.ud;
 540          return true;
 541       }
 542    } else {
 543       if (imm.df != sat_imm.df) {
 544          reg->df = sat_imm.df;
 545          return true;
 546       }
 547    }
 548    return false;
 549 }
 550
 551 bool
 552 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 553 {
 554    switch (type) {
 555    case BRW_REGISTER_TYPE_D:
 556    case BRW_REGISTER_TYPE_UD:
 557       reg->d = -reg->d;
 558       return true;
 559    case BRW_REGISTER_TYPE_W:
 560    case BRW_REGISTER_TYPE_UW:
 561       reg->d = -(int16_t)reg->ud;
 562       return true;
 563    case BRW_REGISTER_TYPE_F:
 564       reg->f = -reg->f;
 565       return true;
 566    case BRW_REGISTER_TYPE_VF:
 567       reg->ud ^= 0x80808080;
 568       return true;
 569    case BRW_REGISTER_TYPE_DF:
 570       reg->df = -reg->df;
 571       return true;
 572    case BRW_REGISTER_TYPE_UQ:
 573    case BRW_REGISTER_TYPE_Q:
 574       reg->d64 = -reg->d64;
 575       return true;
 576    case BRW_REGISTER_TYPE_UB:
 577    case BRW_REGISTER_TYPE_B:
 578       unreachable("no UB/B immediates");
 579    case BRW_REGISTER_TYPE_UV:
 580    case BRW_REGISTER_TYPE_V:
 581       assert(!"unimplemented: negate UV/V immediate");
 582    case BRW_REGISTER_TYPE_HF:
 583       assert(!"unimplemented: negate HF immediate");
 584    }
 585
 586    return false;
 587 }
 588
 589 bool
 590 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 591 {
 592    switch (type) {
 593    case BRW_REGISTER_TYPE_D:
 594       reg->d = abs(reg->d);
 595       return true;
 596    case BRW_REGISTER_TYPE_W:
 597       reg->d = abs((int16_t)reg->ud);
 598       return true;
 599    case BRW_REGISTER_TYPE_F:
 600       reg->f = fabsf(reg->f);
 601       return true;
 602    case BRW_REGISTER_TYPE_DF:
 603       reg->df = fabs(reg->df);
 604       return true;
 605    case BRW_REGISTER_TYPE_VF:
 606       reg->ud &= ~0x80808080;
 607       return true;
 608    case BRW_REGISTER_TYPE_Q:
 609       reg->d64 = imaxabs(reg->d64);
 610       return true;
 611    case BRW_REGISTER_TYPE_UB:
 612    case BRW_REGISTER_TYPE_B:
 613       unreachable("no UB/B immediates");
 614    case BRW_REGISTER_TYPE_UQ:
 615    case BRW_REGISTER_TYPE_UD:
 616    case BRW_REGISTER_TYPE_UW:
 617    case BRW_REGISTER_TYPE_UV:
 618       /* Presumably the absolute value modifier on an unsigned source is a
 619        * nop, but it would be nice to confirm.
 620        */
 621       assert(!"unimplemented: abs unsigned immediate");
 622    case BRW_REGISTER_TYPE_V:
 623       assert(!"unimplemented: abs V immediate");
 624    case BRW_REGISTER_TYPE_HF:
 625       assert(!"unimplemented: abs HF immediate");
 626    }
 627
 628    return false;
 629 }
 630
 631 backend_shader::backend_shader(const struct brw_compiler *compiler,
 632                                void *log_data,
 633                                void *mem_ctx,
 634                                const nir_shader *shader,
 635                                struct brw_stage_prog_data *stage_prog_data)
 636    : compiler(compiler),
 637      log_data(log_data),
 638      devinfo(compiler->devinfo),
 639      nir(shader),
 640      stage_prog_data(stage_prog_data),
 641      mem_ctx(mem_ctx),
 642      cfg(NULL),
 643      stage(shader->info.stage)
 644 {
 645    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 646    stage_name = _mesa_shader_stage_to_string(stage);
 647    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 648 }
 649
 650 backend_shader::~backend_shader()
 651 {
 652 }
 653
 654 bool
 655 backend_reg::equals(const backend_reg &r) const
 656 {
 657    return brw_regs_equal(this, &r) && offset == r.offset;
 658 }
 659
 660 bool
 661 backend_reg::is_zero() const
 662 {
 663    if (file != IMM)
 664       return false;
 665
 666    switch (type) {
 667    case BRW_REGISTER_TYPE_F:
 668       return f == 0;
 669    case BRW_REGISTER_TYPE_DF:
 670       return df == 0;
 671    case BRW_REGISTER_TYPE_D:
 672    case BRW_REGISTER_TYPE_UD:
 673       return d == 0;
 674    case BRW_REGISTER_TYPE_UQ:
 675    case BRW_REGISTER_TYPE_Q:
 676       return u64 == 0;
 677    default:
 678       return false;
 679    }
 680 }
 681
 682 bool
 683 backend_reg::is_one() const
 684 {
 685    if (file != IMM)
 686       return false;
 687
 688    switch (type) {
 689    case BRW_REGISTER_TYPE_F:
 690       return f == 1.0f;
 691    case BRW_REGISTER_TYPE_DF:
 692       return df == 1.0;
 693    case BRW_REGISTER_TYPE_D:
 694    case BRW_REGISTER_TYPE_UD:
 695       return d == 1;
 696    case BRW_REGISTER_TYPE_UQ:
 697    case BRW_REGISTER_TYPE_Q:
 698       return u64 == 1;
 699    default:
 700       return false;
 701    }
 702 }
 703
 704 bool
 705 backend_reg::is_negative_one() const
 706 {
 707    if (file != IMM)
 708       return false;
 709
 710    switch (type) {
 711    case BRW_REGISTER_TYPE_F:
 712       return f == -1.0;
 713    case BRW_REGISTER_TYPE_DF:
 714       return df == -1.0;
 715    case BRW_REGISTER_TYPE_D:
 716       return d == -1;
 717    case BRW_REGISTER_TYPE_Q:
 718       return d64 == -1;
 719    default:
 720       return false;
 721    }
 722 }
 723
 724 bool
 725 backend_reg::is_null() const
 726 {
 727    return file == ARF && nr == BRW_ARF_NULL;
 728 }
 729
 730
 731 bool
 732 backend_reg::is_accumulator() const
 733 {
 734    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 735 }
 736
 737 bool
 738 backend_instruction::is_commutative() const
 739 {
 740    switch (opcode) {
 741    case BRW_OPCODE_AND:
 742    case BRW_OPCODE_OR:
 743    case BRW_OPCODE_XOR:
 744    case BRW_OPCODE_ADD:
 745    case BRW_OPCODE_MUL:
 746    case SHADER_OPCODE_MULH:
 747       return true;
 748    case BRW_OPCODE_SEL:
 749       /* MIN and MAX are commutative. */
 750       if (conditional_mod == BRW_CONDITIONAL_GE ||
 751           conditional_mod == BRW_CONDITIONAL_L) {
 752          return true;
 753       }
 754       /* fallthrough */
 755    default:
 756       return false;
 757    }
 758 }
 759
 760 bool
 761 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 762 {
 763    return ::is_3src(devinfo, opcode);
 764 }
 765
 766 bool
 767 backend_instruction::is_tex() const
 768 {
 769    return (opcode == SHADER_OPCODE_TEX ||
 770            opcode == FS_OPCODE_TXB ||
 771            opcode == SHADER_OPCODE_TXD ||
 772            opcode == SHADER_OPCODE_TXF ||
 773            opcode == SHADER_OPCODE_TXF_LZ ||
 774            opcode == SHADER_OPCODE_TXF_CMS ||
 775            opcode == SHADER_OPCODE_TXF_CMS_W ||
 776            opcode == SHADER_OPCODE_TXF_UMS ||
 777            opcode == SHADER_OPCODE_TXF_MCS ||
 778            opcode == SHADER_OPCODE_TXL ||
 779            opcode == SHADER_OPCODE_TXL_LZ ||
 780            opcode == SHADER_OPCODE_TXS ||
 781            opcode == SHADER_OPCODE_LOD ||
 782            opcode == SHADER_OPCODE_TG4 ||
 783            opcode == SHADER_OPCODE_TG4_OFFSET ||
 784            opcode == SHADER_OPCODE_SAMPLEINFO);
 785 }
 786
 787 bool
 788 backend_instruction::is_math() const
 789 {
 790    return (opcode == SHADER_OPCODE_RCP ||
 791            opcode == SHADER_OPCODE_RSQ ||
 792            opcode == SHADER_OPCODE_SQRT ||
 793            opcode == SHADER_OPCODE_EXP2 ||
 794            opcode == SHADER_OPCODE_LOG2 ||
 795            opcode == SHADER_OPCODE_SIN ||
 796            opcode == SHADER_OPCODE_COS ||
 797            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 798            opcode == SHADER_OPCODE_INT_REMAINDER ||
 799            opcode == SHADER_OPCODE_POW);
 800 }
 801
 802 bool
 803 backend_instruction::is_control_flow() const
 804 {
 805    switch (opcode) {
 806    case BRW_OPCODE_DO:
 807    case BRW_OPCODE_WHILE:
 808    case BRW_OPCODE_IF:
 809    case BRW_OPCODE_ELSE:
 810    case BRW_OPCODE_ENDIF:
 811    case BRW_OPCODE_BREAK:
 812    case BRW_OPCODE_CONTINUE:
 813       return true;
 814    default:
 815       return false;
 816    }
 817 }
 818
 819 bool
 820 backend_instruction::can_do_source_mods() const
 821 {
 822    switch (opcode) {
 823    case BRW_OPCODE_ADDC:
 824    case BRW_OPCODE_BFE:
 825    case BRW_OPCODE_BFI1:
 826    case BRW_OPCODE_BFI2:
 827    case BRW_OPCODE_BFREV:
 828    case BRW_OPCODE_CBIT:
 829    case BRW_OPCODE_FBH:
 830    case BRW_OPCODE_FBL:
 831    case BRW_OPCODE_SUBB:
 832    case SHADER_OPCODE_BROADCAST:
 833    case SHADER_OPCODE_MOV_INDIRECT:
 834       return false;
 835    default:
 836       return true;
 837    }
 838 }
 839
 840 bool
 841 backend_instruction::can_do_saturate() const
 842 {
 843    switch (opcode) {
 844    case BRW_OPCODE_ADD:
 845    case BRW_OPCODE_ASR:
 846    case BRW_OPCODE_AVG:
 847    case BRW_OPCODE_DP2:
 848    case BRW_OPCODE_DP3:
 849    case BRW_OPCODE_DP4:
 850    case BRW_OPCODE_DPH:
 851    case BRW_OPCODE_F16TO32:
 852    case BRW_OPCODE_F32TO16:
 853    case BRW_OPCODE_LINE:
 854    case BRW_OPCODE_LRP:
 855    case BRW_OPCODE_MAC:
 856    case BRW_OPCODE_MAD:
 857    case BRW_OPCODE_MATH:
 858    case BRW_OPCODE_MOV:
 859    case BRW_OPCODE_MUL:
 860    case SHADER_OPCODE_MULH:
 861    case BRW_OPCODE_PLN:
 862    case BRW_OPCODE_RNDD:
 863    case BRW_OPCODE_RNDE:
 864    case BRW_OPCODE_RNDU:
 865    case BRW_OPCODE_RNDZ:
 866    case BRW_OPCODE_SEL:
 867    case BRW_OPCODE_SHL:
 868    case BRW_OPCODE_SHR:
 869    case FS_OPCODE_LINTERP:
 870    case SHADER_OPCODE_COS:
 871    case SHADER_OPCODE_EXP2:
 872    case SHADER_OPCODE_LOG2:
 873    case SHADER_OPCODE_POW:
 874    case SHADER_OPCODE_RCP:
 875    case SHADER_OPCODE_RSQ:
 876    case SHADER_OPCODE_SIN:
 877    case SHADER_OPCODE_SQRT:
 878       return true;
 879    default:
 880       return false;
 881    }
 882 }
 883
 884 bool
 885 backend_instruction::can_do_cmod() const
 886 {
 887    switch (opcode) {
 888    case BRW_OPCODE_ADD:
 889    case BRW_OPCODE_ADDC:
 890    case BRW_OPCODE_AND:
 891    case BRW_OPCODE_ASR:
 892    case BRW_OPCODE_AVG:
 893    case BRW_OPCODE_CMP:
 894    case BRW_OPCODE_CMPN:
 895    case BRW_OPCODE_DP2:
 896    case BRW_OPCODE_DP3:
 897    case BRW_OPCODE_DP4:
 898    case BRW_OPCODE_DPH:
 899    case BRW_OPCODE_F16TO32:
 900    case BRW_OPCODE_F32TO16:
 901    case BRW_OPCODE_FRC:
 902    case BRW_OPCODE_LINE:
 903    case BRW_OPCODE_LRP:
 904    case BRW_OPCODE_LZD:
 905    case BRW_OPCODE_MAC:
 906    case BRW_OPCODE_MACH:
 907    case BRW_OPCODE_MAD:
 908    case BRW_OPCODE_MOV:
 909    case BRW_OPCODE_MUL:
 910    case BRW_OPCODE_NOT:
 911    case BRW_OPCODE_OR:
 912    case BRW_OPCODE_PLN:
 913    case BRW_OPCODE_RNDD:
 914    case BRW_OPCODE_RNDE:
 915    case BRW_OPCODE_RNDU:
 916    case BRW_OPCODE_RNDZ:
 917    case BRW_OPCODE_SAD2:
 918    case BRW_OPCODE_SADA2:
 919    case BRW_OPCODE_SHL:
 920    case BRW_OPCODE_SHR:
 921    case BRW_OPCODE_SUBB:
 922    case BRW_OPCODE_XOR:
 923    case FS_OPCODE_CINTERP:
 924    case FS_OPCODE_LINTERP:
 925       return true;
 926    default:
 927       return false;
 928    }
 929 }
 930
 931 bool
 932 backend_instruction::reads_accumulator_implicitly() const
 933 {
 934    switch (opcode) {
 935    case BRW_OPCODE_MAC:
 936    case BRW_OPCODE_MACH:
 937    case BRW_OPCODE_SADA2:
 938       return true;
 939    default:
 940       return false;
 941    }
 942 }
 943
 944 bool
 945 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 946 {
 947    return writes_accumulator ||
 948           (devinfo->gen < 6 &&
 949            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 950             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 951              opcode != FS_OPCODE_CINTERP)));
 952 }
 953
 954 bool
 955 backend_instruction::has_side_effects() const
 956 {
 957    switch (opcode) {
 958    case SHADER_OPCODE_UNTYPED_ATOMIC:
 959    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 960    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 961    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 962    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 963    case SHADER_OPCODE_TYPED_ATOMIC:
 964    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 965    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 966    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 967    case SHADER_OPCODE_MEMORY_FENCE:
 968    case SHADER_OPCODE_URB_WRITE_SIMD8:
 969    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 970    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 971    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 972    case FS_OPCODE_FB_WRITE:
 973    case FS_OPCODE_FB_WRITE_LOGICAL:
 974    case SHADER_OPCODE_BARRIER:
 975    case TCS_OPCODE_URB_WRITE:
 976    case TCS_OPCODE_RELEASE_INPUT:
 977       return true;
 978    default:
 979       return eot;
 980    }
 981 }
 982
 983 bool
 984 backend_instruction::is_volatile() const
 985 {
 986    switch (opcode) {
 987    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 988    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 989    case SHADER_OPCODE_TYPED_SURFACE_READ:
 990    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 991    case SHADER_OPCODE_URB_READ_SIMD8:
 992    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 993    case VEC4_OPCODE_URB_READ:
 994       return true;
 995    default:
 996       return false;
 997    }
 998 }
 999
1000 #ifndef NDEBUG
1001 static bool
1002 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1003 {
1004    bool found = false;
1005    foreach_inst_in_block (backend_instruction, i, block) {
1006       if (inst == i) {
1007          found = true;
1008       }
1009    }
1010    return found;
1011 }
1012 #endif
1013
1014 static void
1015 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1016 {
1017    for (bblock_t *block_iter = start_block->next();
1018         block_iter;
1019         block_iter = block_iter->next()) {
1020       block_iter->start_ip += ip_adjustment;
1021       block_iter->end_ip += ip_adjustment;
1022    }
1023 }
1024
1025 void
1026 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1027 {
1028    assert(this != inst);
1029
1030    if (!this->is_head_sentinel())
1031       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1032
1033    block->end_ip++;
1034
1035    adjust_later_block_ips(block, 1);
1036
1037    exec_node::insert_after(inst);
1038 }
1039
1040 void
1041 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1042 {
1043    assert(this != inst);
1044
1045    if (!this->is_tail_sentinel())
1046       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1047
1048    block->end_ip++;
1049
1050    adjust_later_block_ips(block, 1);
1051
1052    exec_node::insert_before(inst);
1053 }
1054
1055 void
1056 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1057 {
1058    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1059
1060    unsigned num_inst = list->length();
1061
1062    block->end_ip += num_inst;
1063
1064    adjust_later_block_ips(block, num_inst);
1065
1066    exec_node::insert_before(list);
1067 }
1068
1069 void
1070 backend_instruction::remove(bblock_t *block)
1071 {
1072    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1073
1074    adjust_later_block_ips(block, -1);
1075
1076    if (block->start_ip == block->end_ip) {
1077       block->cfg->remove_block(block);
1078    } else {
1079       block->end_ip--;
1080    }
1081
1082    exec_node::remove();
1083 }
1084
1085 void
1086 backend_shader::dump_instructions()
1087 {
1088    dump_instructions(NULL);
1089 }
1090
1091 void
1092 backend_shader::dump_instructions(const char *name)
1093 {
1094    FILE *file = stderr;
1095    if (name && geteuid() != 0) {
1096       file = fopen(name, "w");
1097       if (!file)
1098          file = stderr;
1099    }
1100
1101    if (cfg) {
1102       int ip = 0;
1103       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1104          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1105             fprintf(file, "%4d: ", ip++);
1106          dump_instruction(inst, file);
1107       }
1108    } else {
1109       int ip = 0;
1110       foreach_in_list(backend_instruction, inst, &instructions) {
1111          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1112             fprintf(file, "%4d: ", ip++);
1113          dump_instruction(inst, file);
1114       }
1115    }
1116
1117    if (file != stderr) {
1118       fclose(file);
1119    }
1120 }
1121
1122 void
1123 backend_shader::calculate_cfg()
1124 {
1125    if (this->cfg)
1126       return;
1127    cfg = new(mem_ctx) cfg_t(&this->instructions);
1128 }
1129
1130 extern "C" const unsigned *
1131 brw_compile_tes(const struct brw_compiler *compiler,
1132                 void *log_data,
1133                 void *mem_ctx,
1134                 const struct brw_tes_prog_key *key,
1135                 const struct brw_vue_map *input_vue_map,
1136                 struct brw_tes_prog_data *prog_data,
1137                 const nir_shader *src_shader,
1138                 struct gl_program *prog,
1139                 int shader_time_index,
1140                 char **error_str)
1141 {
1142    const struct gen_device_info *devinfo = compiler->devinfo;
1143    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1144    const unsigned *assembly;
1145
1146    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1147    nir->info.inputs_read = key->inputs_read;
1148    nir->info.patch_inputs_read = key->patch_inputs_read;
1149
1150    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1151    brw_nir_lower_tes_inputs(nir, input_vue_map);
1152    brw_nir_lower_vue_outputs(nir, is_scalar);
1153    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1154
1155    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1156                        nir->info.outputs_written,
1157                        nir->info.separate_shader);
1158
1159    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1160
1161    assert(output_size_bytes >= 1);
1162    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1163       if (error_str)
1164          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1165       return NULL;
1166    }
1167
1168    prog_data->base.clip_distance_mask =
1169       ((1 << nir->info.clip_distance_array_size) - 1);
1170    prog_data->base.cull_distance_mask =
1171       ((1 << nir->info.cull_distance_array_size) - 1) <<
1172       nir->info.clip_distance_array_size;
1173
1174    /* URB entry sizes are stored as a multiple of 64 bytes. */
1175    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1176
1177    /* On Cannonlake software shall not program an allocation size that
1178     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1179     */
1180    if (devinfo->gen == 10 &&
1181        prog_data->base.urb_entry_size % 3 == 0)
1182       prog_data->base.urb_entry_size++;
1183
1184    prog_data->base.urb_read_length = 0;
1185
1186    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1187    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1188                  TESS_SPACING_FRACTIONAL_ODD - 1);
1189    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1190                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1191
1192    prog_data->partitioning =
1193       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1194
1195    switch (nir->info.tess.primitive_mode) {
1196    case GL_QUADS:
1197       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1198       break;
1199    case GL_TRIANGLES:
1200       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1201       break;
1202    case GL_ISOLINES:
1203       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1204       break;
1205    default:
1206       unreachable("invalid domain shader primitive mode");
1207    }
1208
1209    if (nir->info.tess.point_mode) {
1210       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1211    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1212       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1213    } else {
1214       /* Hardware winding order is backwards from OpenGL */
1215       prog_data->output_topology =
1216          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1217                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1218    }
1219
1220    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1221       fprintf(stderr, "TES Input ");
1222       brw_print_vue_map(stderr, input_vue_map);
1223       fprintf(stderr, "TES Output ");
1224       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1225    }
1226
1227    if (is_scalar) {
1228       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1229                    &prog_data->base.base, NULL, nir, 8,
1230                    shader_time_index, input_vue_map);
1231       if (!v.run_tes()) {
1232          if (error_str)
1233             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1234          return NULL;
1235       }
1236
1237       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1238       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1239
1240       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1241                      &prog_data->base.base, v.promoted_constants, false,
1242                      MESA_SHADER_TESS_EVAL);
1243       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1244          g.enable_debug(ralloc_asprintf(mem_ctx,
1245                                         "%s tessellation evaluation shader %s",
1246                                         nir->info.label ? nir->info.label
1247                                                         : "unnamed",
1248                                         nir->info.name));
1249       }
1250
1251       g.generate_code(v.cfg, 8);
1252
1253       assembly = g.get_assembly(&prog_data->base.base.program_size);
1254    } else {
1255       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1256                               nir, mem_ctx, shader_time_index);
1257       if (!v.run()) {
1258          if (error_str)
1259             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1260          return NULL;
1261       }
1262
1263       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1264          v.dump_instructions();
1265
1266       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1267                                             &prog_data->base, v.cfg,
1268                                             &prog_data->base.base.program_size);
1269    }
1270
1271    return assembly;
1272 }