src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "common/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_UINT:
  48       return BRW_REGISTER_TYPE_UD;
  49    case GLSL_TYPE_UINT16:
  50       return BRW_REGISTER_TYPE_UW;
  51    case GLSL_TYPE_ARRAY:
  52       return brw_type_for_base_type(type->fields.array);
  53    case GLSL_TYPE_STRUCT:
  54    case GLSL_TYPE_SAMPLER:
  55    case GLSL_TYPE_ATOMIC_UINT:
  56       /* These should be overridden with the type of the member when
  57        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  58        * way to trip up if we don't.
  59        */
  60       return BRW_REGISTER_TYPE_UD;
  61    case GLSL_TYPE_IMAGE:
  62       return BRW_REGISTER_TYPE_UD;
  63    case GLSL_TYPE_DOUBLE:
  64       return BRW_REGISTER_TYPE_DF;
  65    case GLSL_TYPE_UINT64:
  66       return BRW_REGISTER_TYPE_UQ;
  67    case GLSL_TYPE_INT64:
  68       return BRW_REGISTER_TYPE_Q;
  69    case GLSL_TYPE_VOID:
  70    case GLSL_TYPE_ERROR:
  71    case GLSL_TYPE_INTERFACE:
  72    case GLSL_TYPE_FUNCTION:
  73       unreachable("not reached");
  74    }
  75
  76    return BRW_REGISTER_TYPE_F;
  77 }
  78
  79 enum brw_conditional_mod
  80 brw_conditional_for_comparison(unsigned int op)
  81 {
  82    switch (op) {
  83    case ir_binop_less:
  84       return BRW_CONDITIONAL_L;
  85    case ir_binop_gequal:
  86       return BRW_CONDITIONAL_GE;
  87    case ir_binop_equal:
  88    case ir_binop_all_equal: /* same as equal for scalars */
  89       return BRW_CONDITIONAL_Z;
  90    case ir_binop_nequal:
  91    case ir_binop_any_nequal: /* same as nequal for scalars */
  92       return BRW_CONDITIONAL_NZ;
  93    default:
  94       unreachable("not reached: bad operation for comparison");
  95    }
  96 }
  97
  98 uint32_t
  99 brw_math_function(enum opcode op)
 100 {
 101    switch (op) {
 102    case SHADER_OPCODE_RCP:
 103       return BRW_MATH_FUNCTION_INV;
 104    case SHADER_OPCODE_RSQ:
 105       return BRW_MATH_FUNCTION_RSQ;
 106    case SHADER_OPCODE_SQRT:
 107       return BRW_MATH_FUNCTION_SQRT;
 108    case SHADER_OPCODE_EXP2:
 109       return BRW_MATH_FUNCTION_EXP;
 110    case SHADER_OPCODE_LOG2:
 111       return BRW_MATH_FUNCTION_LOG;
 112    case SHADER_OPCODE_POW:
 113       return BRW_MATH_FUNCTION_POW;
 114    case SHADER_OPCODE_SIN:
 115       return BRW_MATH_FUNCTION_SIN;
 116    case SHADER_OPCODE_COS:
 117       return BRW_MATH_FUNCTION_COS;
 118    case SHADER_OPCODE_INT_QUOTIENT:
 119       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 120    case SHADER_OPCODE_INT_REMAINDER:
 121       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 122    default:
 123       unreachable("not reached: unknown math function");
 124    }
 125 }
 126
 127 bool
 128 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 129 {
 130    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 131
 132    /* offset out of bounds; caller will handle it. */
 133    for (unsigned i = 0; i < num_components; i++)
 134       if (offsets[i] > 7 || offsets[i] < -8)
 135          return false;
 136
 137    /* Combine all three offsets into a single unsigned dword:
 138     *
 139     *    bits 11:8 - U Offset (X component)
 140     *    bits  7:4 - V Offset (Y component)
 141     *    bits  3:0 - R Offset (Z component)
 142     */
 143    *offset_bits = 0;
 144    for (unsigned i = 0; i < num_components; i++) {
 145       const unsigned shift = 4 * (2 - i);
 146       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 147    }
 148    return true;
 149 }
 150
 151 const char *
 152 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 153 {
 154    switch (op) {
 155    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 156       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 157        * start of a loop in the IR.
 158        */
 159       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 160          return "do";
 161
 162       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 163        * then to mark that we want to do the conversion.
 164        */
 165       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 166          return "f32to16";
 167
 168       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 169          return "f16to32";
 170
 171       assert(brw_opcode_desc(devinfo, op)->name);
 172       return brw_opcode_desc(devinfo, op)->name;
 173    case FS_OPCODE_FB_WRITE:
 174       return "fb_write";
 175    case FS_OPCODE_FB_WRITE_LOGICAL:
 176       return "fb_write_logical";
 177    case FS_OPCODE_REP_FB_WRITE:
 178       return "rep_fb_write";
 179    case FS_OPCODE_FB_READ:
 180       return "fb_read";
 181    case FS_OPCODE_FB_READ_LOGICAL:
 182       return "fb_read_logical";
 183
 184    case SHADER_OPCODE_RCP:
 185       return "rcp";
 186    case SHADER_OPCODE_RSQ:
 187       return "rsq";
 188    case SHADER_OPCODE_SQRT:
 189       return "sqrt";
 190    case SHADER_OPCODE_EXP2:
 191       return "exp2";
 192    case SHADER_OPCODE_LOG2:
 193       return "log2";
 194    case SHADER_OPCODE_POW:
 195       return "pow";
 196    case SHADER_OPCODE_INT_QUOTIENT:
 197       return "int_quot";
 198    case SHADER_OPCODE_INT_REMAINDER:
 199       return "int_rem";
 200    case SHADER_OPCODE_SIN:
 201       return "sin";
 202    case SHADER_OPCODE_COS:
 203       return "cos";
 204
 205    case SHADER_OPCODE_TEX:
 206       return "tex";
 207    case SHADER_OPCODE_TEX_LOGICAL:
 208       return "tex_logical";
 209    case SHADER_OPCODE_TXD:
 210       return "txd";
 211    case SHADER_OPCODE_TXD_LOGICAL:
 212       return "txd_logical";
 213    case SHADER_OPCODE_TXF:
 214       return "txf";
 215    case SHADER_OPCODE_TXF_LOGICAL:
 216       return "txf_logical";
 217    case SHADER_OPCODE_TXF_LZ:
 218       return "txf_lz";
 219    case SHADER_OPCODE_TXL:
 220       return "txl";
 221    case SHADER_OPCODE_TXL_LOGICAL:
 222       return "txl_logical";
 223    case SHADER_OPCODE_TXL_LZ:
 224       return "txl_lz";
 225    case SHADER_OPCODE_TXS:
 226       return "txs";
 227    case SHADER_OPCODE_TXS_LOGICAL:
 228       return "txs_logical";
 229    case FS_OPCODE_TXB:
 230       return "txb";
 231    case FS_OPCODE_TXB_LOGICAL:
 232       return "txb_logical";
 233    case SHADER_OPCODE_TXF_CMS:
 234       return "txf_cms";
 235    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 236       return "txf_cms_logical";
 237    case SHADER_OPCODE_TXF_CMS_W:
 238       return "txf_cms_w";
 239    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 240       return "txf_cms_w_logical";
 241    case SHADER_OPCODE_TXF_UMS:
 242       return "txf_ums";
 243    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 244       return "txf_ums_logical";
 245    case SHADER_OPCODE_TXF_MCS:
 246       return "txf_mcs";
 247    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 248       return "txf_mcs_logical";
 249    case SHADER_OPCODE_LOD:
 250       return "lod";
 251    case SHADER_OPCODE_LOD_LOGICAL:
 252       return "lod_logical";
 253    case SHADER_OPCODE_TG4:
 254       return "tg4";
 255    case SHADER_OPCODE_TG4_LOGICAL:
 256       return "tg4_logical";
 257    case SHADER_OPCODE_TG4_OFFSET:
 258       return "tg4_offset";
 259    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 260       return "tg4_offset_logical";
 261    case SHADER_OPCODE_SAMPLEINFO:
 262       return "sampleinfo";
 263    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 264       return "sampleinfo_logical";
 265
 266    case SHADER_OPCODE_SHADER_TIME_ADD:
 267       return "shader_time_add";
 268
 269    case SHADER_OPCODE_UNTYPED_ATOMIC:
 270       return "untyped_atomic";
 271    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 272       return "untyped_atomic_logical";
 273    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 274       return "untyped_surface_read";
 275    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 276       return "untyped_surface_read_logical";
 277    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 278       return "untyped_surface_write";
 279    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 280       return "untyped_surface_write_logical";
 281    case SHADER_OPCODE_TYPED_ATOMIC:
 282       return "typed_atomic";
 283    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 284       return "typed_atomic_logical";
 285    case SHADER_OPCODE_TYPED_SURFACE_READ:
 286       return "typed_surface_read";
 287    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 288       return "typed_surface_read_logical";
 289    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 290       return "typed_surface_write";
 291    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 292       return "typed_surface_write_logical";
 293    case SHADER_OPCODE_MEMORY_FENCE:
 294       return "memory_fence";
 295
 296    case SHADER_OPCODE_BYTE_SCATTERED_READ:
 297       return "byte_scattered_read";
 298    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 299       return "byte_scattered_read_logical";
 300    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
 301       return "byte_scattered_write";
 302    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 303       return "byte_scattered_write_logical";
 304
 305    case SHADER_OPCODE_LOAD_PAYLOAD:
 306       return "load_payload";
 307    case FS_OPCODE_PACK:
 308       return "pack";
 309
 310    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 311       return "gen4_scratch_read";
 312    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 313       return "gen4_scratch_write";
 314    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 315       return "gen7_scratch_read";
 316    case SHADER_OPCODE_URB_WRITE_SIMD8:
 317       return "gen8_urb_write_simd8";
 318    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 319       return "gen8_urb_write_simd8_per_slot";
 320    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 321       return "gen8_urb_write_simd8_masked";
 322    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 323       return "gen8_urb_write_simd8_masked_per_slot";
 324    case SHADER_OPCODE_URB_READ_SIMD8:
 325       return "urb_read_simd8";
 326    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 327       return "urb_read_simd8_per_slot";
 328
 329    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 330       return "find_live_channel";
 331    case SHADER_OPCODE_BROADCAST:
 332       return "broadcast";
 333    case SHADER_OPCODE_SHUFFLE:
 334       return "shuffle";
 335    case SHADER_OPCODE_SEL_EXEC:
 336       return "sel_exec";
 337    case SHADER_OPCODE_QUAD_SWIZZLE:
 338       return "quad_swizzle";
 339    case SHADER_OPCODE_CLUSTER_BROADCAST:
 340       return "cluster_broadcast";
 341
 342    case SHADER_OPCODE_GET_BUFFER_SIZE:
 343       return "get_buffer_size";
 344
 345    case VEC4_OPCODE_MOV_BYTES:
 346       return "mov_bytes";
 347    case VEC4_OPCODE_PACK_BYTES:
 348       return "pack_bytes";
 349    case VEC4_OPCODE_UNPACK_UNIFORM:
 350       return "unpack_uniform";
 351    case VEC4_OPCODE_DOUBLE_TO_F32:
 352       return "double_to_f32";
 353    case VEC4_OPCODE_DOUBLE_TO_D32:
 354       return "double_to_d32";
 355    case VEC4_OPCODE_DOUBLE_TO_U32:
 356       return "double_to_u32";
 357    case VEC4_OPCODE_TO_DOUBLE:
 358       return "single_to_double";
 359    case VEC4_OPCODE_PICK_LOW_32BIT:
 360       return "pick_low_32bit";
 361    case VEC4_OPCODE_PICK_HIGH_32BIT:
 362       return "pick_high_32bit";
 363    case VEC4_OPCODE_SET_LOW_32BIT:
 364       return "set_low_32bit";
 365    case VEC4_OPCODE_SET_HIGH_32BIT:
 366       return "set_high_32bit";
 367
 368    case FS_OPCODE_DDX_COARSE:
 369       return "ddx_coarse";
 370    case FS_OPCODE_DDX_FINE:
 371       return "ddx_fine";
 372    case FS_OPCODE_DDY_COARSE:
 373       return "ddy_coarse";
 374    case FS_OPCODE_DDY_FINE:
 375       return "ddy_fine";
 376
 377    case FS_OPCODE_CINTERP:
 378       return "cinterp";
 379    case FS_OPCODE_LINTERP:
 380       return "linterp";
 381
 382    case FS_OPCODE_PIXEL_X:
 383       return "pixel_x";
 384    case FS_OPCODE_PIXEL_Y:
 385       return "pixel_y";
 386
 387    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 388       return "uniform_pull_const";
 389    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 390       return "uniform_pull_const_gen7";
 391    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 392       return "varying_pull_const_gen4";
 393    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 394       return "varying_pull_const_gen7";
 395    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 396       return "varying_pull_const_logical";
 397
 398    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 399       return "mov_dispatch_to_flags";
 400    case FS_OPCODE_DISCARD_JUMP:
 401       return "discard_jump";
 402
 403    case FS_OPCODE_SET_SAMPLE_ID:
 404       return "set_sample_id";
 405
 406    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 407       return "pack_half_2x16_split";
 408    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 409       return "unpack_half_2x16_split_x";
 410    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 411       return "unpack_half_2x16_split_y";
 412
 413    case FS_OPCODE_PLACEHOLDER_HALT:
 414       return "placeholder_halt";
 415
 416    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 417       return "interp_sample";
 418    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 419       return "interp_shared_offset";
 420    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 421       return "interp_per_slot_offset";
 422
 423    case VS_OPCODE_URB_WRITE:
 424       return "vs_urb_write";
 425    case VS_OPCODE_PULL_CONSTANT_LOAD:
 426       return "pull_constant_load";
 427    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 428       return "pull_constant_load_gen7";
 429
 430    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 431       return "set_simd4x2_header_gen9";
 432
 433    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 434       return "unpack_flags_simd4x2";
 435
 436    case GS_OPCODE_URB_WRITE:
 437       return "gs_urb_write";
 438    case GS_OPCODE_URB_WRITE_ALLOCATE:
 439       return "gs_urb_write_allocate";
 440    case GS_OPCODE_THREAD_END:
 441       return "gs_thread_end";
 442    case GS_OPCODE_SET_WRITE_OFFSET:
 443       return "set_write_offset";
 444    case GS_OPCODE_SET_VERTEX_COUNT:
 445       return "set_vertex_count";
 446    case GS_OPCODE_SET_DWORD_2:
 447       return "set_dword_2";
 448    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 449       return "prepare_channel_masks";
 450    case GS_OPCODE_SET_CHANNEL_MASKS:
 451       return "set_channel_masks";
 452    case GS_OPCODE_GET_INSTANCE_ID:
 453       return "get_instance_id";
 454    case GS_OPCODE_FF_SYNC:
 455       return "ff_sync";
 456    case GS_OPCODE_SET_PRIMITIVE_ID:
 457       return "set_primitive_id";
 458    case GS_OPCODE_SVB_WRITE:
 459       return "gs_svb_write";
 460    case GS_OPCODE_SVB_SET_DST_INDEX:
 461       return "gs_svb_set_dst_index";
 462    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 463       return "gs_ff_sync_set_primitives";
 464    case CS_OPCODE_CS_TERMINATE:
 465       return "cs_terminate";
 466    case SHADER_OPCODE_BARRIER:
 467       return "barrier";
 468    case SHADER_OPCODE_MULH:
 469       return "mulh";
 470    case SHADER_OPCODE_MOV_INDIRECT:
 471       return "mov_indirect";
 472
 473    case VEC4_OPCODE_URB_READ:
 474       return "urb_read";
 475    case TCS_OPCODE_GET_INSTANCE_ID:
 476       return "tcs_get_instance_id";
 477    case TCS_OPCODE_URB_WRITE:
 478       return "tcs_urb_write";
 479    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 480       return "tcs_set_input_urb_offsets";
 481    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 482       return "tcs_set_output_urb_offsets";
 483    case TCS_OPCODE_GET_PRIMITIVE_ID:
 484       return "tcs_get_primitive_id";
 485    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 486       return "tcs_create_barrier_header";
 487    case TCS_OPCODE_SRC0_010_IS_ZERO:
 488       return "tcs_src0<0,1,0>_is_zero";
 489    case TCS_OPCODE_RELEASE_INPUT:
 490       return "tcs_release_input";
 491    case TCS_OPCODE_THREAD_END:
 492       return "tcs_thread_end";
 493    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 494       return "tes_create_input_read_header";
 495    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 496       return "tes_add_indirect_urb_offset";
 497    case TES_OPCODE_GET_PRIMITIVE_ID:
 498       return "tes_get_primitive_id";
 499
 500    case SHADER_OPCODE_RND_MODE:
 501       return "rnd_mode";
 502    }
 503
 504    unreachable("not reached");
 505 }
 506
 507 bool
 508 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 509 {
 510    union {
 511       unsigned ud;
 512       int d;
 513       float f;
 514       double df;
 515    } imm, sat_imm = { 0 };
 516
 517    const unsigned size = type_sz(type);
 518
 519    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 520     * irrelevant, so just check the size of the type and copy from/to an
 521     * appropriately sized field.
 522     */
 523    if (size < 8)
 524       imm.ud = reg->ud;
 525    else
 526       imm.df = reg->df;
 527
 528    switch (type) {
 529    case BRW_REGISTER_TYPE_UD:
 530    case BRW_REGISTER_TYPE_D:
 531    case BRW_REGISTER_TYPE_UW:
 532    case BRW_REGISTER_TYPE_W:
 533    case BRW_REGISTER_TYPE_UQ:
 534    case BRW_REGISTER_TYPE_Q:
 535       /* Nothing to do. */
 536       return false;
 537    case BRW_REGISTER_TYPE_F:
 538       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 539       break;
 540    case BRW_REGISTER_TYPE_DF:
 541       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 542       break;
 543    case BRW_REGISTER_TYPE_UB:
 544    case BRW_REGISTER_TYPE_B:
 545       unreachable("no UB/B immediates");
 546    case BRW_REGISTER_TYPE_V:
 547    case BRW_REGISTER_TYPE_UV:
 548    case BRW_REGISTER_TYPE_VF:
 549       unreachable("unimplemented: saturate vector immediate");
 550    case BRW_REGISTER_TYPE_HF:
 551       unreachable("unimplemented: saturate HF immediate");
 552    case BRW_REGISTER_TYPE_NF:
 553       unreachable("no NF immediates");
 554    }
 555
 556    if (size < 8) {
 557       if (imm.ud != sat_imm.ud) {
 558          reg->ud = sat_imm.ud;
 559          return true;
 560       }
 561    } else {
 562       if (imm.df != sat_imm.df) {
 563          reg->df = sat_imm.df;
 564          return true;
 565       }
 566    }
 567    return false;
 568 }
 569
 570 bool
 571 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 572 {
 573    switch (type) {
 574    case BRW_REGISTER_TYPE_D:
 575    case BRW_REGISTER_TYPE_UD:
 576       reg->d = -reg->d;
 577       return true;
 578    case BRW_REGISTER_TYPE_W:
 579    case BRW_REGISTER_TYPE_UW:
 580       reg->d = -(int16_t)reg->ud;
 581       return true;
 582    case BRW_REGISTER_TYPE_F:
 583       reg->f = -reg->f;
 584       return true;
 585    case BRW_REGISTER_TYPE_VF:
 586       reg->ud ^= 0x80808080;
 587       return true;
 588    case BRW_REGISTER_TYPE_DF:
 589       reg->df = -reg->df;
 590       return true;
 591    case BRW_REGISTER_TYPE_UQ:
 592    case BRW_REGISTER_TYPE_Q:
 593       reg->d64 = -reg->d64;
 594       return true;
 595    case BRW_REGISTER_TYPE_UB:
 596    case BRW_REGISTER_TYPE_B:
 597       unreachable("no UB/B immediates");
 598    case BRW_REGISTER_TYPE_UV:
 599    case BRW_REGISTER_TYPE_V:
 600       assert(!"unimplemented: negate UV/V immediate");
 601    case BRW_REGISTER_TYPE_HF:
 602       assert(!"unimplemented: negate HF immediate");
 603    case BRW_REGISTER_TYPE_NF:
 604       unreachable("no NF immediates");
 605    }
 606
 607    return false;
 608 }
 609
 610 bool
 611 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 612 {
 613    switch (type) {
 614    case BRW_REGISTER_TYPE_D:
 615       reg->d = abs(reg->d);
 616       return true;
 617    case BRW_REGISTER_TYPE_W:
 618       reg->d = abs((int16_t)reg->ud);
 619       return true;
 620    case BRW_REGISTER_TYPE_F:
 621       reg->f = fabsf(reg->f);
 622       return true;
 623    case BRW_REGISTER_TYPE_DF:
 624       reg->df = fabs(reg->df);
 625       return true;
 626    case BRW_REGISTER_TYPE_VF:
 627       reg->ud &= ~0x80808080;
 628       return true;
 629    case BRW_REGISTER_TYPE_Q:
 630       reg->d64 = imaxabs(reg->d64);
 631       return true;
 632    case BRW_REGISTER_TYPE_UB:
 633    case BRW_REGISTER_TYPE_B:
 634       unreachable("no UB/B immediates");
 635    case BRW_REGISTER_TYPE_UQ:
 636    case BRW_REGISTER_TYPE_UD:
 637    case BRW_REGISTER_TYPE_UW:
 638    case BRW_REGISTER_TYPE_UV:
 639       /* Presumably the absolute value modifier on an unsigned source is a
 640        * nop, but it would be nice to confirm.
 641        */
 642       assert(!"unimplemented: abs unsigned immediate");
 643    case BRW_REGISTER_TYPE_V:
 644       assert(!"unimplemented: abs V immediate");
 645    case BRW_REGISTER_TYPE_HF:
 646       assert(!"unimplemented: abs HF immediate");
 647    case BRW_REGISTER_TYPE_NF:
 648       unreachable("no NF immediates");
 649    }
 650
 651    return false;
 652 }
 653
 654 backend_shader::backend_shader(const struct brw_compiler *compiler,
 655                                void *log_data,
 656                                void *mem_ctx,
 657                                const nir_shader *shader,
 658                                struct brw_stage_prog_data *stage_prog_data)
 659    : compiler(compiler),
 660      log_data(log_data),
 661      devinfo(compiler->devinfo),
 662      nir(shader),
 663      stage_prog_data(stage_prog_data),
 664      mem_ctx(mem_ctx),
 665      cfg(NULL),
 666      stage(shader->info.stage)
 667 {
 668    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 669    stage_name = _mesa_shader_stage_to_string(stage);
 670    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 671 }
 672
 673 backend_shader::~backend_shader()
 674 {
 675 }
 676
 677 bool
 678 backend_reg::equals(const backend_reg &r) const
 679 {
 680    return brw_regs_equal(this, &r) && offset == r.offset;
 681 }
 682
 683 bool
 684 backend_reg::is_zero() const
 685 {
 686    if (file != IMM)
 687       return false;
 688
 689    switch (type) {
 690    case BRW_REGISTER_TYPE_F:
 691       return f == 0;
 692    case BRW_REGISTER_TYPE_DF:
 693       return df == 0;
 694    case BRW_REGISTER_TYPE_D:
 695    case BRW_REGISTER_TYPE_UD:
 696       return d == 0;
 697    case BRW_REGISTER_TYPE_UQ:
 698    case BRW_REGISTER_TYPE_Q:
 699       return u64 == 0;
 700    default:
 701       return false;
 702    }
 703 }
 704
 705 bool
 706 backend_reg::is_one() const
 707 {
 708    if (file != IMM)
 709       return false;
 710
 711    switch (type) {
 712    case BRW_REGISTER_TYPE_F:
 713       return f == 1.0f;
 714    case BRW_REGISTER_TYPE_DF:
 715       return df == 1.0;
 716    case BRW_REGISTER_TYPE_D:
 717    case BRW_REGISTER_TYPE_UD:
 718       return d == 1;
 719    case BRW_REGISTER_TYPE_UQ:
 720    case BRW_REGISTER_TYPE_Q:
 721       return u64 == 1;
 722    default:
 723       return false;
 724    }
 725 }
 726
 727 bool
 728 backend_reg::is_negative_one() const
 729 {
 730    if (file != IMM)
 731       return false;
 732
 733    switch (type) {
 734    case BRW_REGISTER_TYPE_F:
 735       return f == -1.0;
 736    case BRW_REGISTER_TYPE_DF:
 737       return df == -1.0;
 738    case BRW_REGISTER_TYPE_D:
 739       return d == -1;
 740    case BRW_REGISTER_TYPE_Q:
 741       return d64 == -1;
 742    default:
 743       return false;
 744    }
 745 }
 746
 747 bool
 748 backend_reg::is_null() const
 749 {
 750    return file == ARF && nr == BRW_ARF_NULL;
 751 }
 752
 753
 754 bool
 755 backend_reg::is_accumulator() const
 756 {
 757    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 758 }
 759
 760 bool
 761 backend_instruction::is_commutative() const
 762 {
 763    switch (opcode) {
 764    case BRW_OPCODE_AND:
 765    case BRW_OPCODE_OR:
 766    case BRW_OPCODE_XOR:
 767    case BRW_OPCODE_ADD:
 768    case BRW_OPCODE_MUL:
 769    case SHADER_OPCODE_MULH:
 770       return true;
 771    case BRW_OPCODE_SEL:
 772       /* MIN and MAX are commutative. */
 773       if (conditional_mod == BRW_CONDITIONAL_GE ||
 774           conditional_mod == BRW_CONDITIONAL_L) {
 775          return true;
 776       }
 777       /* fallthrough */
 778    default:
 779       return false;
 780    }
 781 }
 782
 783 bool
 784 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 785 {
 786    return ::is_3src(devinfo, opcode);
 787 }
 788
 789 bool
 790 backend_instruction::is_tex() const
 791 {
 792    return (opcode == SHADER_OPCODE_TEX ||
 793            opcode == FS_OPCODE_TXB ||
 794            opcode == SHADER_OPCODE_TXD ||
 795            opcode == SHADER_OPCODE_TXF ||
 796            opcode == SHADER_OPCODE_TXF_LZ ||
 797            opcode == SHADER_OPCODE_TXF_CMS ||
 798            opcode == SHADER_OPCODE_TXF_CMS_W ||
 799            opcode == SHADER_OPCODE_TXF_UMS ||
 800            opcode == SHADER_OPCODE_TXF_MCS ||
 801            opcode == SHADER_OPCODE_TXL ||
 802            opcode == SHADER_OPCODE_TXL_LZ ||
 803            opcode == SHADER_OPCODE_TXS ||
 804            opcode == SHADER_OPCODE_LOD ||
 805            opcode == SHADER_OPCODE_TG4 ||
 806            opcode == SHADER_OPCODE_TG4_OFFSET ||
 807            opcode == SHADER_OPCODE_SAMPLEINFO);
 808 }
 809
 810 bool
 811 backend_instruction::is_math() const
 812 {
 813    return (opcode == SHADER_OPCODE_RCP ||
 814            opcode == SHADER_OPCODE_RSQ ||
 815            opcode == SHADER_OPCODE_SQRT ||
 816            opcode == SHADER_OPCODE_EXP2 ||
 817            opcode == SHADER_OPCODE_LOG2 ||
 818            opcode == SHADER_OPCODE_SIN ||
 819            opcode == SHADER_OPCODE_COS ||
 820            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 821            opcode == SHADER_OPCODE_INT_REMAINDER ||
 822            opcode == SHADER_OPCODE_POW);
 823 }
 824
 825 bool
 826 backend_instruction::is_control_flow() const
 827 {
 828    switch (opcode) {
 829    case BRW_OPCODE_DO:
 830    case BRW_OPCODE_WHILE:
 831    case BRW_OPCODE_IF:
 832    case BRW_OPCODE_ELSE:
 833    case BRW_OPCODE_ENDIF:
 834    case BRW_OPCODE_BREAK:
 835    case BRW_OPCODE_CONTINUE:
 836       return true;
 837    default:
 838       return false;
 839    }
 840 }
 841
 842 bool
 843 backend_instruction::can_do_source_mods() const
 844 {
 845    switch (opcode) {
 846    case BRW_OPCODE_ADDC:
 847    case BRW_OPCODE_BFE:
 848    case BRW_OPCODE_BFI1:
 849    case BRW_OPCODE_BFI2:
 850    case BRW_OPCODE_BFREV:
 851    case BRW_OPCODE_CBIT:
 852    case BRW_OPCODE_FBH:
 853    case BRW_OPCODE_FBL:
 854    case BRW_OPCODE_SUBB:
 855    case SHADER_OPCODE_BROADCAST:
 856    case SHADER_OPCODE_CLUSTER_BROADCAST:
 857    case SHADER_OPCODE_MOV_INDIRECT:
 858       return false;
 859    default:
 860       return true;
 861    }
 862 }
 863
 864 bool
 865 backend_instruction::can_do_saturate() const
 866 {
 867    switch (opcode) {
 868    case BRW_OPCODE_ADD:
 869    case BRW_OPCODE_ASR:
 870    case BRW_OPCODE_AVG:
 871    case BRW_OPCODE_DP2:
 872    case BRW_OPCODE_DP3:
 873    case BRW_OPCODE_DP4:
 874    case BRW_OPCODE_DPH:
 875    case BRW_OPCODE_F16TO32:
 876    case BRW_OPCODE_F32TO16:
 877    case BRW_OPCODE_LINE:
 878    case BRW_OPCODE_LRP:
 879    case BRW_OPCODE_MAC:
 880    case BRW_OPCODE_MAD:
 881    case BRW_OPCODE_MATH:
 882    case BRW_OPCODE_MOV:
 883    case BRW_OPCODE_MUL:
 884    case SHADER_OPCODE_MULH:
 885    case BRW_OPCODE_PLN:
 886    case BRW_OPCODE_RNDD:
 887    case BRW_OPCODE_RNDE:
 888    case BRW_OPCODE_RNDU:
 889    case BRW_OPCODE_RNDZ:
 890    case BRW_OPCODE_SEL:
 891    case BRW_OPCODE_SHL:
 892    case BRW_OPCODE_SHR:
 893    case FS_OPCODE_LINTERP:
 894    case SHADER_OPCODE_COS:
 895    case SHADER_OPCODE_EXP2:
 896    case SHADER_OPCODE_LOG2:
 897    case SHADER_OPCODE_POW:
 898    case SHADER_OPCODE_RCP:
 899    case SHADER_OPCODE_RSQ:
 900    case SHADER_OPCODE_SIN:
 901    case SHADER_OPCODE_SQRT:
 902       return true;
 903    default:
 904       return false;
 905    }
 906 }
 907
 908 bool
 909 backend_instruction::can_do_cmod() const
 910 {
 911    switch (opcode) {
 912    case BRW_OPCODE_ADD:
 913    case BRW_OPCODE_ADDC:
 914    case BRW_OPCODE_AND:
 915    case BRW_OPCODE_ASR:
 916    case BRW_OPCODE_AVG:
 917    case BRW_OPCODE_CMP:
 918    case BRW_OPCODE_CMPN:
 919    case BRW_OPCODE_DP2:
 920    case BRW_OPCODE_DP3:
 921    case BRW_OPCODE_DP4:
 922    case BRW_OPCODE_DPH:
 923    case BRW_OPCODE_F16TO32:
 924    case BRW_OPCODE_F32TO16:
 925    case BRW_OPCODE_FRC:
 926    case BRW_OPCODE_LINE:
 927    case BRW_OPCODE_LRP:
 928    case BRW_OPCODE_LZD:
 929    case BRW_OPCODE_MAC:
 930    case BRW_OPCODE_MACH:
 931    case BRW_OPCODE_MAD:
 932    case BRW_OPCODE_MOV:
 933    case BRW_OPCODE_MUL:
 934    case BRW_OPCODE_NOT:
 935    case BRW_OPCODE_OR:
 936    case BRW_OPCODE_PLN:
 937    case BRW_OPCODE_RNDD:
 938    case BRW_OPCODE_RNDE:
 939    case BRW_OPCODE_RNDU:
 940    case BRW_OPCODE_RNDZ:
 941    case BRW_OPCODE_SAD2:
 942    case BRW_OPCODE_SADA2:
 943    case BRW_OPCODE_SHL:
 944    case BRW_OPCODE_SHR:
 945    case BRW_OPCODE_SUBB:
 946    case BRW_OPCODE_XOR:
 947    case FS_OPCODE_CINTERP:
 948    case FS_OPCODE_LINTERP:
 949       return true;
 950    default:
 951       return false;
 952    }
 953 }
 954
 955 bool
 956 backend_instruction::reads_accumulator_implicitly() const
 957 {
 958    switch (opcode) {
 959    case BRW_OPCODE_MAC:
 960    case BRW_OPCODE_MACH:
 961    case BRW_OPCODE_SADA2:
 962       return true;
 963    default:
 964       return false;
 965    }
 966 }
 967
 968 bool
 969 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 970 {
 971    return writes_accumulator ||
 972           (devinfo->gen < 6 &&
 973            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 974             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 975              opcode != FS_OPCODE_CINTERP)));
 976 }
 977
 978 bool
 979 backend_instruction::has_side_effects() const
 980 {
 981    switch (opcode) {
 982    case SHADER_OPCODE_UNTYPED_ATOMIC:
 983    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 984    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 985    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 986    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 987    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
 988    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 989    case SHADER_OPCODE_TYPED_ATOMIC:
 990    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 991    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 992    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 993    case SHADER_OPCODE_MEMORY_FENCE:
 994    case SHADER_OPCODE_URB_WRITE_SIMD8:
 995    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 996    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 997    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 998    case FS_OPCODE_FB_WRITE:
 999    case FS_OPCODE_FB_WRITE_LOGICAL:
1000    case SHADER_OPCODE_BARRIER:
1001    case TCS_OPCODE_URB_WRITE:
1002    case TCS_OPCODE_RELEASE_INPUT:
1003    case SHADER_OPCODE_RND_MODE:
1004       return true;
1005    default:
1006       return eot;
1007    }
1008 }
1009
1010 bool
1011 backend_instruction::is_volatile() const
1012 {
1013    switch (opcode) {
1014    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1015    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1016    case SHADER_OPCODE_TYPED_SURFACE_READ:
1017    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1018    case SHADER_OPCODE_BYTE_SCATTERED_READ:
1019    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1020    case SHADER_OPCODE_URB_READ_SIMD8:
1021    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1022    case VEC4_OPCODE_URB_READ:
1023       return true;
1024    default:
1025       return false;
1026    }
1027 }
1028
1029 #ifndef NDEBUG
1030 static bool
1031 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1032 {
1033    bool found = false;
1034    foreach_inst_in_block (backend_instruction, i, block) {
1035       if (inst == i) {
1036          found = true;
1037       }
1038    }
1039    return found;
1040 }
1041 #endif
1042
1043 static void
1044 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1045 {
1046    for (bblock_t *block_iter = start_block->next();
1047         block_iter;
1048         block_iter = block_iter->next()) {
1049       block_iter->start_ip += ip_adjustment;
1050       block_iter->end_ip += ip_adjustment;
1051    }
1052 }
1053
1054 void
1055 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1056 {
1057    assert(this != inst);
1058
1059    if (!this->is_head_sentinel())
1060       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1061
1062    block->end_ip++;
1063
1064    adjust_later_block_ips(block, 1);
1065
1066    exec_node::insert_after(inst);
1067 }
1068
1069 void
1070 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1071 {
1072    assert(this != inst);
1073
1074    if (!this->is_tail_sentinel())
1075       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1076
1077    block->end_ip++;
1078
1079    adjust_later_block_ips(block, 1);
1080
1081    exec_node::insert_before(inst);
1082 }
1083
1084 void
1085 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1086 {
1087    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1088
1089    unsigned num_inst = list->length();
1090
1091    block->end_ip += num_inst;
1092
1093    adjust_later_block_ips(block, num_inst);
1094
1095    exec_node::insert_before(list);
1096 }
1097
1098 void
1099 backend_instruction::remove(bblock_t *block)
1100 {
1101    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1102
1103    adjust_later_block_ips(block, -1);
1104
1105    if (block->start_ip == block->end_ip) {
1106       block->cfg->remove_block(block);
1107    } else {
1108       block->end_ip--;
1109    }
1110
1111    exec_node::remove();
1112 }
1113
1114 void
1115 backend_shader::dump_instructions()
1116 {
1117    dump_instructions(NULL);
1118 }
1119
1120 void
1121 backend_shader::dump_instructions(const char *name)
1122 {
1123    FILE *file = stderr;
1124    if (name && geteuid() != 0) {
1125       file = fopen(name, "w");
1126       if (!file)
1127          file = stderr;
1128    }
1129
1130    if (cfg) {
1131       int ip = 0;
1132       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1133          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1134             fprintf(file, "%4d: ", ip++);
1135          dump_instruction(inst, file);
1136       }
1137    } else {
1138       int ip = 0;
1139       foreach_in_list(backend_instruction, inst, &instructions) {
1140          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1141             fprintf(file, "%4d: ", ip++);
1142          dump_instruction(inst, file);
1143       }
1144    }
1145
1146    if (file != stderr) {
1147       fclose(file);
1148    }
1149 }
1150
1151 void
1152 backend_shader::calculate_cfg()
1153 {
1154    if (this->cfg)
1155       return;
1156    cfg = new(mem_ctx) cfg_t(&this->instructions);
1157 }
1158
1159 extern "C" const unsigned *
1160 brw_compile_tes(const struct brw_compiler *compiler,
1161                 void *log_data,
1162                 void *mem_ctx,
1163                 const struct brw_tes_prog_key *key,
1164                 const struct brw_vue_map *input_vue_map,
1165                 struct brw_tes_prog_data *prog_data,
1166                 const nir_shader *src_shader,
1167                 struct gl_program *prog,
1168                 int shader_time_index,
1169                 char **error_str)
1170 {
1171    const struct gen_device_info *devinfo = compiler->devinfo;
1172    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1173    const unsigned *assembly;
1174
1175    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1176    nir->info.inputs_read = key->inputs_read;
1177    nir->info.patch_inputs_read = key->patch_inputs_read;
1178
1179    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1180    brw_nir_lower_tes_inputs(nir, input_vue_map);
1181    brw_nir_lower_vue_outputs(nir, is_scalar);
1182    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1183
1184    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1185                        nir->info.outputs_written,
1186                        nir->info.separate_shader);
1187
1188    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1189
1190    assert(output_size_bytes >= 1);
1191    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1192       if (error_str)
1193          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1194       return NULL;
1195    }
1196
1197    prog_data->base.clip_distance_mask =
1198       ((1 << nir->info.clip_distance_array_size) - 1);
1199    prog_data->base.cull_distance_mask =
1200       ((1 << nir->info.cull_distance_array_size) - 1) <<
1201       nir->info.clip_distance_array_size;
1202
1203    /* URB entry sizes are stored as a multiple of 64 bytes. */
1204    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1205
1206    /* On Cannonlake software shall not program an allocation size that
1207     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1208     */
1209    if (devinfo->gen == 10 &&
1210        prog_data->base.urb_entry_size % 3 == 0)
1211       prog_data->base.urb_entry_size++;
1212
1213    prog_data->base.urb_read_length = 0;
1214
1215    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1216    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1217                  TESS_SPACING_FRACTIONAL_ODD - 1);
1218    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1219                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1220
1221    prog_data->partitioning =
1222       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1223
1224    switch (nir->info.tess.primitive_mode) {
1225    case GL_QUADS:
1226       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1227       break;
1228    case GL_TRIANGLES:
1229       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1230       break;
1231    case GL_ISOLINES:
1232       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1233       break;
1234    default:
1235       unreachable("invalid domain shader primitive mode");
1236    }
1237
1238    if (nir->info.tess.point_mode) {
1239       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1240    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1241       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1242    } else {
1243       /* Hardware winding order is backwards from OpenGL */
1244       prog_data->output_topology =
1245          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1246                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1247    }
1248
1249    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1250       fprintf(stderr, "TES Input ");
1251       brw_print_vue_map(stderr, input_vue_map);
1252       fprintf(stderr, "TES Output ");
1253       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1254    }
1255
1256    if (is_scalar) {
1257       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1258                    &prog_data->base.base, NULL, nir, 8,
1259                    shader_time_index, input_vue_map);
1260       if (!v.run_tes()) {
1261          if (error_str)
1262             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1263          return NULL;
1264       }
1265
1266       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1267       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1268
1269       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1270                      &prog_data->base.base, v.promoted_constants, false,
1271                      MESA_SHADER_TESS_EVAL);
1272       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1273          g.enable_debug(ralloc_asprintf(mem_ctx,
1274                                         "%s tessellation evaluation shader %s",
1275                                         nir->info.label ? nir->info.label
1276                                                         : "unnamed",
1277                                         nir->info.name));
1278       }
1279
1280       g.generate_code(v.cfg, 8);
1281
1282       assembly = g.get_assembly();
1283    } else {
1284       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1285                               nir, mem_ctx, shader_time_index);
1286       if (!v.run()) {
1287          if (error_str)
1288             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1289          return NULL;
1290       }
1291
1292       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1293          v.dump_instructions();
1294
1295       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1296                                             &prog_data->base, v.cfg);
1297    }
1298
1299    return assembly;
1300 }