2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_vec4_tes.h"
29 #include "common/gen_debug.h"
30 #include "main/uniforms.h"
31 #include "util/macros.h"
34 brw_type_for_base_type(const struct glsl_type
*type
)
36 switch (type
->base_type
) {
37 case GLSL_TYPE_FLOAT16
:
38 return BRW_REGISTER_TYPE_HF
;
40 return BRW_REGISTER_TYPE_F
;
43 case GLSL_TYPE_SUBROUTINE
:
44 return BRW_REGISTER_TYPE_D
;
46 return BRW_REGISTER_TYPE_W
;
48 return BRW_REGISTER_TYPE_B
;
50 return BRW_REGISTER_TYPE_UD
;
51 case GLSL_TYPE_UINT16
:
52 return BRW_REGISTER_TYPE_UW
;
54 return BRW_REGISTER_TYPE_UB
;
56 return brw_type_for_base_type(type
->fields
.array
);
57 case GLSL_TYPE_STRUCT
:
58 case GLSL_TYPE_SAMPLER
:
59 case GLSL_TYPE_ATOMIC_UINT
:
60 /* These should be overridden with the type of the member when
61 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
62 * way to trip up if we don't.
64 return BRW_REGISTER_TYPE_UD
;
66 return BRW_REGISTER_TYPE_UD
;
67 case GLSL_TYPE_DOUBLE
:
68 return BRW_REGISTER_TYPE_DF
;
69 case GLSL_TYPE_UINT64
:
70 return BRW_REGISTER_TYPE_UQ
;
72 return BRW_REGISTER_TYPE_Q
;
75 case GLSL_TYPE_INTERFACE
:
76 case GLSL_TYPE_FUNCTION
:
77 unreachable("not reached");
80 return BRW_REGISTER_TYPE_F
;
83 enum brw_conditional_mod
84 brw_conditional_for_comparison(unsigned int op
)
88 return BRW_CONDITIONAL_L
;
90 return BRW_CONDITIONAL_GE
;
92 case ir_binop_all_equal
: /* same as equal for scalars */
93 return BRW_CONDITIONAL_Z
;
95 case ir_binop_any_nequal
: /* same as nequal for scalars */
96 return BRW_CONDITIONAL_NZ
;
98 unreachable("not reached: bad operation for comparison");
103 brw_math_function(enum opcode op
)
106 case SHADER_OPCODE_RCP
:
107 return BRW_MATH_FUNCTION_INV
;
108 case SHADER_OPCODE_RSQ
:
109 return BRW_MATH_FUNCTION_RSQ
;
110 case SHADER_OPCODE_SQRT
:
111 return BRW_MATH_FUNCTION_SQRT
;
112 case SHADER_OPCODE_EXP2
:
113 return BRW_MATH_FUNCTION_EXP
;
114 case SHADER_OPCODE_LOG2
:
115 return BRW_MATH_FUNCTION_LOG
;
116 case SHADER_OPCODE_POW
:
117 return BRW_MATH_FUNCTION_POW
;
118 case SHADER_OPCODE_SIN
:
119 return BRW_MATH_FUNCTION_SIN
;
120 case SHADER_OPCODE_COS
:
121 return BRW_MATH_FUNCTION_COS
;
122 case SHADER_OPCODE_INT_QUOTIENT
:
123 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
124 case SHADER_OPCODE_INT_REMAINDER
:
125 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
127 unreachable("not reached: unknown math function");
132 brw_texture_offset(int *offsets
, unsigned num_components
, uint32_t *offset_bits
)
134 if (!offsets
) return false; /* nonconstant offset; caller will handle it. */
136 /* offset out of bounds; caller will handle it. */
137 for (unsigned i
= 0; i
< num_components
; i
++)
138 if (offsets
[i
] > 7 || offsets
[i
] < -8)
141 /* Combine all three offsets into a single unsigned dword:
143 * bits 11:8 - U Offset (X component)
144 * bits 7:4 - V Offset (Y component)
145 * bits 3:0 - R Offset (Z component)
148 for (unsigned i
= 0; i
< num_components
; i
++) {
149 const unsigned shift
= 4 * (2 - i
);
150 *offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
156 brw_instruction_name(const struct gen_device_info
*devinfo
, enum opcode op
)
159 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
160 /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
161 * start of a loop in the IR.
163 if (devinfo
->gen
>= 6 && op
== BRW_OPCODE_DO
)
166 /* The following conversion opcodes doesn't exist on Gen8+, but we use
167 * then to mark that we want to do the conversion.
169 if (devinfo
->gen
> 7 && op
== BRW_OPCODE_F32TO16
)
172 if (devinfo
->gen
> 7 && op
== BRW_OPCODE_F16TO32
)
175 assert(brw_opcode_desc(devinfo
, op
)->name
);
176 return brw_opcode_desc(devinfo
, op
)->name
;
177 case FS_OPCODE_FB_WRITE
:
179 case FS_OPCODE_FB_WRITE_LOGICAL
:
180 return "fb_write_logical";
181 case FS_OPCODE_REP_FB_WRITE
:
182 return "rep_fb_write";
183 case FS_OPCODE_FB_READ
:
185 case FS_OPCODE_FB_READ_LOGICAL
:
186 return "fb_read_logical";
188 case SHADER_OPCODE_RCP
:
190 case SHADER_OPCODE_RSQ
:
192 case SHADER_OPCODE_SQRT
:
194 case SHADER_OPCODE_EXP2
:
196 case SHADER_OPCODE_LOG2
:
198 case SHADER_OPCODE_POW
:
200 case SHADER_OPCODE_INT_QUOTIENT
:
202 case SHADER_OPCODE_INT_REMAINDER
:
204 case SHADER_OPCODE_SIN
:
206 case SHADER_OPCODE_COS
:
209 case SHADER_OPCODE_TEX
:
211 case SHADER_OPCODE_TEX_LOGICAL
:
212 return "tex_logical";
213 case SHADER_OPCODE_TXD
:
215 case SHADER_OPCODE_TXD_LOGICAL
:
216 return "txd_logical";
217 case SHADER_OPCODE_TXF
:
219 case SHADER_OPCODE_TXF_LOGICAL
:
220 return "txf_logical";
221 case SHADER_OPCODE_TXF_LZ
:
223 case SHADER_OPCODE_TXL
:
225 case SHADER_OPCODE_TXL_LOGICAL
:
226 return "txl_logical";
227 case SHADER_OPCODE_TXL_LZ
:
229 case SHADER_OPCODE_TXS
:
231 case SHADER_OPCODE_TXS_LOGICAL
:
232 return "txs_logical";
235 case FS_OPCODE_TXB_LOGICAL
:
236 return "txb_logical";
237 case SHADER_OPCODE_TXF_CMS
:
239 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
240 return "txf_cms_logical";
241 case SHADER_OPCODE_TXF_CMS_W
:
243 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
244 return "txf_cms_w_logical";
245 case SHADER_OPCODE_TXF_UMS
:
247 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
248 return "txf_ums_logical";
249 case SHADER_OPCODE_TXF_MCS
:
251 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
252 return "txf_mcs_logical";
253 case SHADER_OPCODE_LOD
:
255 case SHADER_OPCODE_LOD_LOGICAL
:
256 return "lod_logical";
257 case SHADER_OPCODE_TG4
:
259 case SHADER_OPCODE_TG4_LOGICAL
:
260 return "tg4_logical";
261 case SHADER_OPCODE_TG4_OFFSET
:
263 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
264 return "tg4_offset_logical";
265 case SHADER_OPCODE_SAMPLEINFO
:
267 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
268 return "sampleinfo_logical";
270 case SHADER_OPCODE_SHADER_TIME_ADD
:
271 return "shader_time_add";
273 case SHADER_OPCODE_UNTYPED_ATOMIC
:
274 return "untyped_atomic";
275 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
276 return "untyped_atomic_logical";
277 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
278 return "untyped_surface_read";
279 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
280 return "untyped_surface_read_logical";
281 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
282 return "untyped_surface_write";
283 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
284 return "untyped_surface_write_logical";
285 case SHADER_OPCODE_TYPED_ATOMIC
:
286 return "typed_atomic";
287 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
288 return "typed_atomic_logical";
289 case SHADER_OPCODE_TYPED_SURFACE_READ
:
290 return "typed_surface_read";
291 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
292 return "typed_surface_read_logical";
293 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
294 return "typed_surface_write";
295 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
296 return "typed_surface_write_logical";
297 case SHADER_OPCODE_MEMORY_FENCE
:
298 return "memory_fence";
300 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
301 return "byte_scattered_read";
302 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
303 return "byte_scattered_read_logical";
304 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
305 return "byte_scattered_write";
306 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
307 return "byte_scattered_write_logical";
309 case SHADER_OPCODE_LOAD_PAYLOAD
:
310 return "load_payload";
314 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
315 return "gen4_scratch_read";
316 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
317 return "gen4_scratch_write";
318 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
319 return "gen7_scratch_read";
320 case SHADER_OPCODE_URB_WRITE_SIMD8
:
321 return "gen8_urb_write_simd8";
322 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
323 return "gen8_urb_write_simd8_per_slot";
324 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
325 return "gen8_urb_write_simd8_masked";
326 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
327 return "gen8_urb_write_simd8_masked_per_slot";
328 case SHADER_OPCODE_URB_READ_SIMD8
:
329 return "urb_read_simd8";
330 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
331 return "urb_read_simd8_per_slot";
333 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
334 return "find_live_channel";
335 case SHADER_OPCODE_BROADCAST
:
337 case SHADER_OPCODE_SHUFFLE
:
339 case SHADER_OPCODE_SEL_EXEC
:
341 case SHADER_OPCODE_QUAD_SWIZZLE
:
342 return "quad_swizzle";
343 case SHADER_OPCODE_CLUSTER_BROADCAST
:
344 return "cluster_broadcast";
346 case SHADER_OPCODE_GET_BUFFER_SIZE
:
347 return "get_buffer_size";
349 case VEC4_OPCODE_MOV_BYTES
:
351 case VEC4_OPCODE_PACK_BYTES
:
353 case VEC4_OPCODE_UNPACK_UNIFORM
:
354 return "unpack_uniform";
355 case VEC4_OPCODE_DOUBLE_TO_F32
:
356 return "double_to_f32";
357 case VEC4_OPCODE_DOUBLE_TO_D32
:
358 return "double_to_d32";
359 case VEC4_OPCODE_DOUBLE_TO_U32
:
360 return "double_to_u32";
361 case VEC4_OPCODE_TO_DOUBLE
:
362 return "single_to_double";
363 case VEC4_OPCODE_PICK_LOW_32BIT
:
364 return "pick_low_32bit";
365 case VEC4_OPCODE_PICK_HIGH_32BIT
:
366 return "pick_high_32bit";
367 case VEC4_OPCODE_SET_LOW_32BIT
:
368 return "set_low_32bit";
369 case VEC4_OPCODE_SET_HIGH_32BIT
:
370 return "set_high_32bit";
372 case FS_OPCODE_DDX_COARSE
:
374 case FS_OPCODE_DDX_FINE
:
376 case FS_OPCODE_DDY_COARSE
:
378 case FS_OPCODE_DDY_FINE
:
381 case FS_OPCODE_CINTERP
:
383 case FS_OPCODE_LINTERP
:
386 case FS_OPCODE_PIXEL_X
:
388 case FS_OPCODE_PIXEL_Y
:
391 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
392 return "uniform_pull_const";
393 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
394 return "uniform_pull_const_gen7";
395 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
396 return "varying_pull_const_gen4";
397 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
398 return "varying_pull_const_gen7";
399 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
400 return "varying_pull_const_logical";
402 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
403 return "mov_dispatch_to_flags";
404 case FS_OPCODE_DISCARD_JUMP
:
405 return "discard_jump";
407 case FS_OPCODE_SET_SAMPLE_ID
:
408 return "set_sample_id";
410 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
411 return "pack_half_2x16_split";
412 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
413 return "unpack_half_2x16_split_x";
414 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
415 return "unpack_half_2x16_split_y";
417 case FS_OPCODE_PLACEHOLDER_HALT
:
418 return "placeholder_halt";
420 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
421 return "interp_sample";
422 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
423 return "interp_shared_offset";
424 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
425 return "interp_per_slot_offset";
427 case VS_OPCODE_URB_WRITE
:
428 return "vs_urb_write";
429 case VS_OPCODE_PULL_CONSTANT_LOAD
:
430 return "pull_constant_load";
431 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
432 return "pull_constant_load_gen7";
434 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
435 return "set_simd4x2_header_gen9";
437 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
438 return "unpack_flags_simd4x2";
440 case GS_OPCODE_URB_WRITE
:
441 return "gs_urb_write";
442 case GS_OPCODE_URB_WRITE_ALLOCATE
:
443 return "gs_urb_write_allocate";
444 case GS_OPCODE_THREAD_END
:
445 return "gs_thread_end";
446 case GS_OPCODE_SET_WRITE_OFFSET
:
447 return "set_write_offset";
448 case GS_OPCODE_SET_VERTEX_COUNT
:
449 return "set_vertex_count";
450 case GS_OPCODE_SET_DWORD_2
:
451 return "set_dword_2";
452 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
453 return "prepare_channel_masks";
454 case GS_OPCODE_SET_CHANNEL_MASKS
:
455 return "set_channel_masks";
456 case GS_OPCODE_GET_INSTANCE_ID
:
457 return "get_instance_id";
458 case GS_OPCODE_FF_SYNC
:
460 case GS_OPCODE_SET_PRIMITIVE_ID
:
461 return "set_primitive_id";
462 case GS_OPCODE_SVB_WRITE
:
463 return "gs_svb_write";
464 case GS_OPCODE_SVB_SET_DST_INDEX
:
465 return "gs_svb_set_dst_index";
466 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
467 return "gs_ff_sync_set_primitives";
468 case CS_OPCODE_CS_TERMINATE
:
469 return "cs_terminate";
470 case SHADER_OPCODE_BARRIER
:
472 case SHADER_OPCODE_MULH
:
474 case SHADER_OPCODE_MOV_INDIRECT
:
475 return "mov_indirect";
477 case VEC4_OPCODE_URB_READ
:
479 case TCS_OPCODE_GET_INSTANCE_ID
:
480 return "tcs_get_instance_id";
481 case TCS_OPCODE_URB_WRITE
:
482 return "tcs_urb_write";
483 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
484 return "tcs_set_input_urb_offsets";
485 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
486 return "tcs_set_output_urb_offsets";
487 case TCS_OPCODE_GET_PRIMITIVE_ID
:
488 return "tcs_get_primitive_id";
489 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
490 return "tcs_create_barrier_header";
491 case TCS_OPCODE_SRC0_010_IS_ZERO
:
492 return "tcs_src0<0,1,0>_is_zero";
493 case TCS_OPCODE_RELEASE_INPUT
:
494 return "tcs_release_input";
495 case TCS_OPCODE_THREAD_END
:
496 return "tcs_thread_end";
497 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
498 return "tes_create_input_read_header";
499 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
500 return "tes_add_indirect_urb_offset";
501 case TES_OPCODE_GET_PRIMITIVE_ID
:
502 return "tes_get_primitive_id";
504 case SHADER_OPCODE_RND_MODE
:
508 unreachable("not reached");
512 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
519 } imm
, sat_imm
= { 0 };
521 const unsigned size
= type_sz(type
);
523 /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
524 * irrelevant, so just check the size of the type and copy from/to an
525 * appropriately sized field.
533 case BRW_REGISTER_TYPE_UD
:
534 case BRW_REGISTER_TYPE_D
:
535 case BRW_REGISTER_TYPE_UW
:
536 case BRW_REGISTER_TYPE_W
:
537 case BRW_REGISTER_TYPE_UQ
:
538 case BRW_REGISTER_TYPE_Q
:
541 case BRW_REGISTER_TYPE_F
:
542 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
544 case BRW_REGISTER_TYPE_DF
:
545 sat_imm
.df
= CLAMP(imm
.df
, 0.0, 1.0);
547 case BRW_REGISTER_TYPE_UB
:
548 case BRW_REGISTER_TYPE_B
:
549 unreachable("no UB/B immediates");
550 case BRW_REGISTER_TYPE_V
:
551 case BRW_REGISTER_TYPE_UV
:
552 case BRW_REGISTER_TYPE_VF
:
553 unreachable("unimplemented: saturate vector immediate");
554 case BRW_REGISTER_TYPE_HF
:
555 unreachable("unimplemented: saturate HF immediate");
556 case BRW_REGISTER_TYPE_NF
:
557 unreachable("no NF immediates");
561 if (imm
.ud
!= sat_imm
.ud
) {
562 reg
->ud
= sat_imm
.ud
;
566 if (imm
.df
!= sat_imm
.df
) {
567 reg
->df
= sat_imm
.df
;
575 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
578 case BRW_REGISTER_TYPE_D
:
579 case BRW_REGISTER_TYPE_UD
:
582 case BRW_REGISTER_TYPE_W
:
583 case BRW_REGISTER_TYPE_UW
:
584 reg
->d
= -(int16_t)reg
->ud
;
586 case BRW_REGISTER_TYPE_F
:
589 case BRW_REGISTER_TYPE_VF
:
590 reg
->ud
^= 0x80808080;
592 case BRW_REGISTER_TYPE_DF
:
595 case BRW_REGISTER_TYPE_UQ
:
596 case BRW_REGISTER_TYPE_Q
:
597 reg
->d64
= -reg
->d64
;
599 case BRW_REGISTER_TYPE_UB
:
600 case BRW_REGISTER_TYPE_B
:
601 unreachable("no UB/B immediates");
602 case BRW_REGISTER_TYPE_UV
:
603 case BRW_REGISTER_TYPE_V
:
604 assert(!"unimplemented: negate UV/V immediate");
605 case BRW_REGISTER_TYPE_HF
:
606 assert(!"unimplemented: negate HF immediate");
607 case BRW_REGISTER_TYPE_NF
:
608 unreachable("no NF immediates");
615 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
618 case BRW_REGISTER_TYPE_D
:
619 reg
->d
= abs(reg
->d
);
621 case BRW_REGISTER_TYPE_W
:
622 reg
->d
= abs((int16_t)reg
->ud
);
624 case BRW_REGISTER_TYPE_F
:
625 reg
->f
= fabsf(reg
->f
);
627 case BRW_REGISTER_TYPE_DF
:
628 reg
->df
= fabs(reg
->df
);
630 case BRW_REGISTER_TYPE_VF
:
631 reg
->ud
&= ~0x80808080;
633 case BRW_REGISTER_TYPE_Q
:
634 reg
->d64
= imaxabs(reg
->d64
);
636 case BRW_REGISTER_TYPE_UB
:
637 case BRW_REGISTER_TYPE_B
:
638 unreachable("no UB/B immediates");
639 case BRW_REGISTER_TYPE_UQ
:
640 case BRW_REGISTER_TYPE_UD
:
641 case BRW_REGISTER_TYPE_UW
:
642 case BRW_REGISTER_TYPE_UV
:
643 /* Presumably the absolute value modifier on an unsigned source is a
644 * nop, but it would be nice to confirm.
646 assert(!"unimplemented: abs unsigned immediate");
647 case BRW_REGISTER_TYPE_V
:
648 assert(!"unimplemented: abs V immediate");
649 case BRW_REGISTER_TYPE_HF
:
650 assert(!"unimplemented: abs HF immediate");
651 case BRW_REGISTER_TYPE_NF
:
652 unreachable("no NF immediates");
658 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
661 const nir_shader
*shader
,
662 struct brw_stage_prog_data
*stage_prog_data
)
663 : compiler(compiler
),
665 devinfo(compiler
->devinfo
),
667 stage_prog_data(stage_prog_data
),
670 stage(shader
->info
.stage
)
672 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
673 stage_name
= _mesa_shader_stage_to_string(stage
);
674 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
677 backend_shader::~backend_shader()
682 backend_reg::equals(const backend_reg
&r
) const
684 return brw_regs_equal(this, &r
) && offset
== r
.offset
;
688 backend_reg::negative_equals(const backend_reg
&r
) const
690 return brw_regs_negative_equal(this, &r
) && offset
== r
.offset
;
694 backend_reg::is_zero() const
700 case BRW_REGISTER_TYPE_F
:
702 case BRW_REGISTER_TYPE_DF
:
704 case BRW_REGISTER_TYPE_D
:
705 case BRW_REGISTER_TYPE_UD
:
707 case BRW_REGISTER_TYPE_UQ
:
708 case BRW_REGISTER_TYPE_Q
:
716 backend_reg::is_one() const
722 case BRW_REGISTER_TYPE_F
:
724 case BRW_REGISTER_TYPE_DF
:
726 case BRW_REGISTER_TYPE_D
:
727 case BRW_REGISTER_TYPE_UD
:
729 case BRW_REGISTER_TYPE_UQ
:
730 case BRW_REGISTER_TYPE_Q
:
738 backend_reg::is_negative_one() const
744 case BRW_REGISTER_TYPE_F
:
746 case BRW_REGISTER_TYPE_DF
:
748 case BRW_REGISTER_TYPE_D
:
750 case BRW_REGISTER_TYPE_Q
:
758 backend_reg::is_null() const
760 return file
== ARF
&& nr
== BRW_ARF_NULL
;
765 backend_reg::is_accumulator() const
767 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
771 backend_instruction::is_commutative() const
779 case SHADER_OPCODE_MULH
:
782 /* MIN and MAX are commutative. */
783 if (conditional_mod
== BRW_CONDITIONAL_GE
||
784 conditional_mod
== BRW_CONDITIONAL_L
) {
794 backend_instruction::is_3src(const struct gen_device_info
*devinfo
) const
796 return ::is_3src(devinfo
, opcode
);
800 backend_instruction::is_tex() const
802 return (opcode
== SHADER_OPCODE_TEX
||
803 opcode
== FS_OPCODE_TXB
||
804 opcode
== SHADER_OPCODE_TXD
||
805 opcode
== SHADER_OPCODE_TXF
||
806 opcode
== SHADER_OPCODE_TXF_LZ
||
807 opcode
== SHADER_OPCODE_TXF_CMS
||
808 opcode
== SHADER_OPCODE_TXF_CMS_W
||
809 opcode
== SHADER_OPCODE_TXF_UMS
||
810 opcode
== SHADER_OPCODE_TXF_MCS
||
811 opcode
== SHADER_OPCODE_TXL
||
812 opcode
== SHADER_OPCODE_TXL_LZ
||
813 opcode
== SHADER_OPCODE_TXS
||
814 opcode
== SHADER_OPCODE_LOD
||
815 opcode
== SHADER_OPCODE_TG4
||
816 opcode
== SHADER_OPCODE_TG4_OFFSET
||
817 opcode
== SHADER_OPCODE_SAMPLEINFO
);
821 backend_instruction::is_math() const
823 return (opcode
== SHADER_OPCODE_RCP
||
824 opcode
== SHADER_OPCODE_RSQ
||
825 opcode
== SHADER_OPCODE_SQRT
||
826 opcode
== SHADER_OPCODE_EXP2
||
827 opcode
== SHADER_OPCODE_LOG2
||
828 opcode
== SHADER_OPCODE_SIN
||
829 opcode
== SHADER_OPCODE_COS
||
830 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
831 opcode
== SHADER_OPCODE_INT_REMAINDER
||
832 opcode
== SHADER_OPCODE_POW
);
836 backend_instruction::is_control_flow() const
840 case BRW_OPCODE_WHILE
:
842 case BRW_OPCODE_ELSE
:
843 case BRW_OPCODE_ENDIF
:
844 case BRW_OPCODE_BREAK
:
845 case BRW_OPCODE_CONTINUE
:
853 backend_instruction::can_do_source_mods() const
856 case BRW_OPCODE_ADDC
:
858 case BRW_OPCODE_BFI1
:
859 case BRW_OPCODE_BFI2
:
860 case BRW_OPCODE_BFREV
:
861 case BRW_OPCODE_CBIT
:
864 case BRW_OPCODE_SUBB
:
865 case SHADER_OPCODE_BROADCAST
:
866 case SHADER_OPCODE_CLUSTER_BROADCAST
:
867 case SHADER_OPCODE_MOV_INDIRECT
:
875 backend_instruction::can_do_saturate() const
885 case BRW_OPCODE_F16TO32
:
886 case BRW_OPCODE_F32TO16
:
887 case BRW_OPCODE_LINE
:
891 case BRW_OPCODE_MATH
:
894 case SHADER_OPCODE_MULH
:
896 case BRW_OPCODE_RNDD
:
897 case BRW_OPCODE_RNDE
:
898 case BRW_OPCODE_RNDU
:
899 case BRW_OPCODE_RNDZ
:
903 case FS_OPCODE_LINTERP
:
904 case SHADER_OPCODE_COS
:
905 case SHADER_OPCODE_EXP2
:
906 case SHADER_OPCODE_LOG2
:
907 case SHADER_OPCODE_POW
:
908 case SHADER_OPCODE_RCP
:
909 case SHADER_OPCODE_RSQ
:
910 case SHADER_OPCODE_SIN
:
911 case SHADER_OPCODE_SQRT
:
919 backend_instruction::can_do_cmod() const
923 case BRW_OPCODE_ADDC
:
928 case BRW_OPCODE_CMPN
:
933 case BRW_OPCODE_F16TO32
:
934 case BRW_OPCODE_F32TO16
:
936 case BRW_OPCODE_LINE
:
940 case BRW_OPCODE_MACH
:
947 case BRW_OPCODE_RNDD
:
948 case BRW_OPCODE_RNDE
:
949 case BRW_OPCODE_RNDU
:
950 case BRW_OPCODE_RNDZ
:
951 case BRW_OPCODE_SAD2
:
952 case BRW_OPCODE_SADA2
:
955 case BRW_OPCODE_SUBB
:
957 case FS_OPCODE_CINTERP
:
958 case FS_OPCODE_LINTERP
:
966 backend_instruction::reads_accumulator_implicitly() const
970 case BRW_OPCODE_MACH
:
971 case BRW_OPCODE_SADA2
:
979 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info
*devinfo
) const
981 return writes_accumulator
||
983 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
984 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
985 opcode
!= FS_OPCODE_CINTERP
)));
989 backend_instruction::has_side_effects() const
992 case SHADER_OPCODE_UNTYPED_ATOMIC
:
993 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
994 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
995 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
996 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
997 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
998 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
999 case SHADER_OPCODE_TYPED_ATOMIC
:
1000 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
1001 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1002 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
1003 case SHADER_OPCODE_MEMORY_FENCE
:
1004 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1005 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
1006 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
1007 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
1008 case FS_OPCODE_FB_WRITE
:
1009 case FS_OPCODE_FB_WRITE_LOGICAL
:
1010 case SHADER_OPCODE_BARRIER
:
1011 case TCS_OPCODE_URB_WRITE
:
1012 case TCS_OPCODE_RELEASE_INPUT
:
1013 case SHADER_OPCODE_RND_MODE
:
1021 backend_instruction::is_volatile() const
1024 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1025 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
1026 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1027 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
1028 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
1029 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
1030 case SHADER_OPCODE_URB_READ_SIMD8
:
1031 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
1032 case VEC4_OPCODE_URB_READ
:
1041 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1044 foreach_inst_in_block (backend_instruction
, i
, block
) {
1054 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1056 for (bblock_t
*block_iter
= start_block
->next();
1058 block_iter
= block_iter
->next()) {
1059 block_iter
->start_ip
+= ip_adjustment
;
1060 block_iter
->end_ip
+= ip_adjustment
;
1065 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1067 assert(this != inst
);
1069 if (!this->is_head_sentinel())
1070 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1074 adjust_later_block_ips(block
, 1);
1076 exec_node::insert_after(inst
);
1080 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1082 assert(this != inst
);
1084 if (!this->is_tail_sentinel())
1085 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1089 adjust_later_block_ips(block
, 1);
1091 exec_node::insert_before(inst
);
1095 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1097 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1099 unsigned num_inst
= list
->length();
1101 block
->end_ip
+= num_inst
;
1103 adjust_later_block_ips(block
, num_inst
);
1105 exec_node::insert_before(list
);
1109 backend_instruction::remove(bblock_t
*block
)
1111 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1113 adjust_later_block_ips(block
, -1);
1115 if (block
->start_ip
== block
->end_ip
) {
1116 block
->cfg
->remove_block(block
);
1121 exec_node::remove();
1125 backend_shader::dump_instructions()
1127 dump_instructions(NULL
);
1131 backend_shader::dump_instructions(const char *name
)
1133 FILE *file
= stderr
;
1134 if (name
&& geteuid() != 0) {
1135 file
= fopen(name
, "w");
1142 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1143 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1144 fprintf(file
, "%4d: ", ip
++);
1145 dump_instruction(inst
, file
);
1149 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1150 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1151 fprintf(file
, "%4d: ", ip
++);
1152 dump_instruction(inst
, file
);
1156 if (file
!= stderr
) {
1162 backend_shader::calculate_cfg()
1166 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1169 extern "C" const unsigned *
1170 brw_compile_tes(const struct brw_compiler
*compiler
,
1173 const struct brw_tes_prog_key
*key
,
1174 const struct brw_vue_map
*input_vue_map
,
1175 struct brw_tes_prog_data
*prog_data
,
1176 const nir_shader
*src_shader
,
1177 struct gl_program
*prog
,
1178 int shader_time_index
,
1181 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
1182 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
];
1183 const unsigned *assembly
;
1185 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
1186 nir
->info
.inputs_read
= key
->inputs_read
;
1187 nir
->info
.patch_inputs_read
= key
->patch_inputs_read
;
1189 nir
= brw_nir_apply_sampler_key(nir
, compiler
, &key
->tex
, is_scalar
);
1190 brw_nir_lower_tes_inputs(nir
, input_vue_map
);
1191 brw_nir_lower_vue_outputs(nir
, is_scalar
);
1192 nir
= brw_postprocess_nir(nir
, compiler
, is_scalar
);
1194 brw_compute_vue_map(devinfo
, &prog_data
->base
.vue_map
,
1195 nir
->info
.outputs_written
,
1196 nir
->info
.separate_shader
);
1198 unsigned output_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 4 * 4;
1200 assert(output_size_bytes
>= 1);
1201 if (output_size_bytes
> GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES
) {
1203 *error_str
= ralloc_strdup(mem_ctx
, "DS outputs exceed maximum size");
1207 prog_data
->base
.clip_distance_mask
=
1208 ((1 << nir
->info
.clip_distance_array_size
) - 1);
1209 prog_data
->base
.cull_distance_mask
=
1210 ((1 << nir
->info
.cull_distance_array_size
) - 1) <<
1211 nir
->info
.clip_distance_array_size
;
1213 /* URB entry sizes are stored as a multiple of 64 bytes. */
1214 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
1216 /* On Cannonlake software shall not program an allocation size that
1217 * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1219 if (devinfo
->gen
== 10 &&
1220 prog_data
->base
.urb_entry_size
% 3 == 0)
1221 prog_data
->base
.urb_entry_size
++;
1223 prog_data
->base
.urb_read_length
= 0;
1225 STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER
== TESS_SPACING_EQUAL
- 1);
1226 STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL
==
1227 TESS_SPACING_FRACTIONAL_ODD
- 1);
1228 STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
==
1229 TESS_SPACING_FRACTIONAL_EVEN
- 1);
1231 prog_data
->partitioning
=
1232 (enum brw_tess_partitioning
) (nir
->info
.tess
.spacing
- 1);
1234 switch (nir
->info
.tess
.primitive_mode
) {
1236 prog_data
->domain
= BRW_TESS_DOMAIN_QUAD
;
1239 prog_data
->domain
= BRW_TESS_DOMAIN_TRI
;
1242 prog_data
->domain
= BRW_TESS_DOMAIN_ISOLINE
;
1245 unreachable("invalid domain shader primitive mode");
1248 if (nir
->info
.tess
.point_mode
) {
1249 prog_data
->output_topology
= BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1250 } else if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
) {
1251 prog_data
->output_topology
= BRW_TESS_OUTPUT_TOPOLOGY_LINE
;
1253 /* Hardware winding order is backwards from OpenGL */
1254 prog_data
->output_topology
=
1255 nir
->info
.tess
.ccw
? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1256 : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
;
1259 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1260 fprintf(stderr
, "TES Input ");
1261 brw_print_vue_map(stderr
, input_vue_map
);
1262 fprintf(stderr
, "TES Output ");
1263 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
1267 fs_visitor
v(compiler
, log_data
, mem_ctx
, (void *) key
,
1268 &prog_data
->base
.base
, NULL
, nir
, 8,
1269 shader_time_index
, input_vue_map
);
1272 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1276 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
1277 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1279 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
1280 &prog_data
->base
.base
, v
.promoted_constants
, false,
1281 MESA_SHADER_TESS_EVAL
);
1282 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1283 g
.enable_debug(ralloc_asprintf(mem_ctx
,
1284 "%s tessellation evaluation shader %s",
1285 nir
->info
.label
? nir
->info
.label
1290 g
.generate_code(v
.cfg
, 8);
1292 assembly
= g
.get_assembly();
1294 brw::vec4_tes_visitor
v(compiler
, log_data
, key
, prog_data
,
1295 nir
, mem_ctx
, shader_time_index
);
1298 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1302 if (unlikely(INTEL_DEBUG
& DEBUG_TES
))
1303 v
.dump_instructions();
1305 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
1306 &prog_data
->base
, v
.cfg
);