src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "common/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_UINT:
  48       return BRW_REGISTER_TYPE_UD;
  49    case GLSL_TYPE_UINT16:
  50       return BRW_REGISTER_TYPE_UW;
  51    case GLSL_TYPE_ARRAY:
  52       return brw_type_for_base_type(type->fields.array);
  53    case GLSL_TYPE_STRUCT:
  54    case GLSL_TYPE_SAMPLER:
  55    case GLSL_TYPE_ATOMIC_UINT:
  56       /* These should be overridden with the type of the member when
  57        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  58        * way to trip up if we don't.
  59        */
  60       return BRW_REGISTER_TYPE_UD;
  61    case GLSL_TYPE_IMAGE:
  62       return BRW_REGISTER_TYPE_UD;
  63    case GLSL_TYPE_DOUBLE:
  64       return BRW_REGISTER_TYPE_DF;
  65    case GLSL_TYPE_UINT64:
  66       return BRW_REGISTER_TYPE_UQ;
  67    case GLSL_TYPE_INT64:
  68       return BRW_REGISTER_TYPE_Q;
  69    case GLSL_TYPE_VOID:
  70    case GLSL_TYPE_ERROR:
  71    case GLSL_TYPE_INTERFACE:
  72    case GLSL_TYPE_FUNCTION:
  73       unreachable("not reached");
  74    }
  75
  76    return BRW_REGISTER_TYPE_F;
  77 }
  78
  79 enum brw_conditional_mod
  80 brw_conditional_for_comparison(unsigned int op)
  81 {
  82    switch (op) {
  83    case ir_binop_less:
  84       return BRW_CONDITIONAL_L;
  85    case ir_binop_gequal:
  86       return BRW_CONDITIONAL_GE;
  87    case ir_binop_equal:
  88    case ir_binop_all_equal: /* same as equal for scalars */
  89       return BRW_CONDITIONAL_Z;
  90    case ir_binop_nequal:
  91    case ir_binop_any_nequal: /* same as nequal for scalars */
  92       return BRW_CONDITIONAL_NZ;
  93    default:
  94       unreachable("not reached: bad operation for comparison");
  95    }
  96 }
  97
  98 uint32_t
  99 brw_math_function(enum opcode op)
 100 {
 101    switch (op) {
 102    case SHADER_OPCODE_RCP:
 103       return BRW_MATH_FUNCTION_INV;
 104    case SHADER_OPCODE_RSQ:
 105       return BRW_MATH_FUNCTION_RSQ;
 106    case SHADER_OPCODE_SQRT:
 107       return BRW_MATH_FUNCTION_SQRT;
 108    case SHADER_OPCODE_EXP2:
 109       return BRW_MATH_FUNCTION_EXP;
 110    case SHADER_OPCODE_LOG2:
 111       return BRW_MATH_FUNCTION_LOG;
 112    case SHADER_OPCODE_POW:
 113       return BRW_MATH_FUNCTION_POW;
 114    case SHADER_OPCODE_SIN:
 115       return BRW_MATH_FUNCTION_SIN;
 116    case SHADER_OPCODE_COS:
 117       return BRW_MATH_FUNCTION_COS;
 118    case SHADER_OPCODE_INT_QUOTIENT:
 119       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 120    case SHADER_OPCODE_INT_REMAINDER:
 121       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 122    default:
 123       unreachable("not reached: unknown math function");
 124    }
 125 }
 126
 127 bool
 128 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 129 {
 130    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 131
 132    /* offset out of bounds; caller will handle it. */
 133    for (unsigned i = 0; i < num_components; i++)
 134       if (offsets[i] > 7 || offsets[i] < -8)
 135          return false;
 136
 137    /* Combine all three offsets into a single unsigned dword:
 138     *
 139     *    bits 11:8 - U Offset (X component)
 140     *    bits  7:4 - V Offset (Y component)
 141     *    bits  3:0 - R Offset (Z component)
 142     */
 143    *offset_bits = 0;
 144    for (unsigned i = 0; i < num_components; i++) {
 145       const unsigned shift = 4 * (2 - i);
 146       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 147    }
 148    return true;
 149 }
 150
 151 const char *
 152 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 153 {
 154    switch (op) {
 155    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 156       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 157        * start of a loop in the IR.
 158        */
 159       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 160          return "do";
 161
 162       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 163        * then to mark that we want to do the conversion.
 164        */
 165       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 166          return "f32to16";
 167
 168       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 169          return "f16to32";
 170
 171       assert(brw_opcode_desc(devinfo, op)->name);
 172       return brw_opcode_desc(devinfo, op)->name;
 173    case FS_OPCODE_FB_WRITE:
 174       return "fb_write";
 175    case FS_OPCODE_FB_WRITE_LOGICAL:
 176       return "fb_write_logical";
 177    case FS_OPCODE_REP_FB_WRITE:
 178       return "rep_fb_write";
 179    case FS_OPCODE_FB_READ:
 180       return "fb_read";
 181    case FS_OPCODE_FB_READ_LOGICAL:
 182       return "fb_read_logical";
 183
 184    case SHADER_OPCODE_RCP:
 185       return "rcp";
 186    case SHADER_OPCODE_RSQ:
 187       return "rsq";
 188    case SHADER_OPCODE_SQRT:
 189       return "sqrt";
 190    case SHADER_OPCODE_EXP2:
 191       return "exp2";
 192    case SHADER_OPCODE_LOG2:
 193       return "log2";
 194    case SHADER_OPCODE_POW:
 195       return "pow";
 196    case SHADER_OPCODE_INT_QUOTIENT:
 197       return "int_quot";
 198    case SHADER_OPCODE_INT_REMAINDER:
 199       return "int_rem";
 200    case SHADER_OPCODE_SIN:
 201       return "sin";
 202    case SHADER_OPCODE_COS:
 203       return "cos";
 204
 205    case SHADER_OPCODE_TEX:
 206       return "tex";
 207    case SHADER_OPCODE_TEX_LOGICAL:
 208       return "tex_logical";
 209    case SHADER_OPCODE_TXD:
 210       return "txd";
 211    case SHADER_OPCODE_TXD_LOGICAL:
 212       return "txd_logical";
 213    case SHADER_OPCODE_TXF:
 214       return "txf";
 215    case SHADER_OPCODE_TXF_LOGICAL:
 216       return "txf_logical";
 217    case SHADER_OPCODE_TXF_LZ:
 218       return "txf_lz";
 219    case SHADER_OPCODE_TXL:
 220       return "txl";
 221    case SHADER_OPCODE_TXL_LOGICAL:
 222       return "txl_logical";
 223    case SHADER_OPCODE_TXL_LZ:
 224       return "txl_lz";
 225    case SHADER_OPCODE_TXS:
 226       return "txs";
 227    case SHADER_OPCODE_TXS_LOGICAL:
 228       return "txs_logical";
 229    case FS_OPCODE_TXB:
 230       return "txb";
 231    case FS_OPCODE_TXB_LOGICAL:
 232       return "txb_logical";
 233    case SHADER_OPCODE_TXF_CMS:
 234       return "txf_cms";
 235    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 236       return "txf_cms_logical";
 237    case SHADER_OPCODE_TXF_CMS_W:
 238       return "txf_cms_w";
 239    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 240       return "txf_cms_w_logical";
 241    case SHADER_OPCODE_TXF_UMS:
 242       return "txf_ums";
 243    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 244       return "txf_ums_logical";
 245    case SHADER_OPCODE_TXF_MCS:
 246       return "txf_mcs";
 247    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 248       return "txf_mcs_logical";
 249    case SHADER_OPCODE_LOD:
 250       return "lod";
 251    case SHADER_OPCODE_LOD_LOGICAL:
 252       return "lod_logical";
 253    case SHADER_OPCODE_TG4:
 254       return "tg4";
 255    case SHADER_OPCODE_TG4_LOGICAL:
 256       return "tg4_logical";
 257    case SHADER_OPCODE_TG4_OFFSET:
 258       return "tg4_offset";
 259    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 260       return "tg4_offset_logical";
 261    case SHADER_OPCODE_SAMPLEINFO:
 262       return "sampleinfo";
 263    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 264       return "sampleinfo_logical";
 265
 266    case SHADER_OPCODE_SHADER_TIME_ADD:
 267       return "shader_time_add";
 268
 269    case SHADER_OPCODE_UNTYPED_ATOMIC:
 270       return "untyped_atomic";
 271    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 272       return "untyped_atomic_logical";
 273    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 274       return "untyped_surface_read";
 275    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 276       return "untyped_surface_read_logical";
 277    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 278       return "untyped_surface_write";
 279    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 280       return "untyped_surface_write_logical";
 281    case SHADER_OPCODE_TYPED_ATOMIC:
 282       return "typed_atomic";
 283    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 284       return "typed_atomic_logical";
 285    case SHADER_OPCODE_TYPED_SURFACE_READ:
 286       return "typed_surface_read";
 287    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 288       return "typed_surface_read_logical";
 289    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 290       return "typed_surface_write";
 291    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 292       return "typed_surface_write_logical";
 293    case SHADER_OPCODE_MEMORY_FENCE:
 294       return "memory_fence";
 295
 296    case SHADER_OPCODE_BYTE_SCATTERED_READ:
 297       return "byte_scattered_read";
 298    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 299       return "byte_scattered_read_logical";
 300    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
 301       return "byte_scattered_write";
 302    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 303       return "byte_scattered_write_logical";
 304
 305    case SHADER_OPCODE_LOAD_PAYLOAD:
 306       return "load_payload";
 307    case FS_OPCODE_PACK:
 308       return "pack";
 309
 310    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 311       return "gen4_scratch_read";
 312    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 313       return "gen4_scratch_write";
 314    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 315       return "gen7_scratch_read";
 316    case SHADER_OPCODE_URB_WRITE_SIMD8:
 317       return "gen8_urb_write_simd8";
 318    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 319       return "gen8_urb_write_simd8_per_slot";
 320    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 321       return "gen8_urb_write_simd8_masked";
 322    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 323       return "gen8_urb_write_simd8_masked_per_slot";
 324    case SHADER_OPCODE_URB_READ_SIMD8:
 325       return "urb_read_simd8";
 326    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 327       return "urb_read_simd8_per_slot";
 328
 329    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 330       return "find_live_channel";
 331    case SHADER_OPCODE_BROADCAST:
 332       return "broadcast";
 333    case SHADER_OPCODE_SHUFFLE:
 334       return "shuffle";
 335
 336    case SHADER_OPCODE_GET_BUFFER_SIZE:
 337       return "get_buffer_size";
 338
 339    case VEC4_OPCODE_MOV_BYTES:
 340       return "mov_bytes";
 341    case VEC4_OPCODE_PACK_BYTES:
 342       return "pack_bytes";
 343    case VEC4_OPCODE_UNPACK_UNIFORM:
 344       return "unpack_uniform";
 345    case VEC4_OPCODE_DOUBLE_TO_F32:
 346       return "double_to_f32";
 347    case VEC4_OPCODE_DOUBLE_TO_D32:
 348       return "double_to_d32";
 349    case VEC4_OPCODE_DOUBLE_TO_U32:
 350       return "double_to_u32";
 351    case VEC4_OPCODE_TO_DOUBLE:
 352       return "single_to_double";
 353    case VEC4_OPCODE_PICK_LOW_32BIT:
 354       return "pick_low_32bit";
 355    case VEC4_OPCODE_PICK_HIGH_32BIT:
 356       return "pick_high_32bit";
 357    case VEC4_OPCODE_SET_LOW_32BIT:
 358       return "set_low_32bit";
 359    case VEC4_OPCODE_SET_HIGH_32BIT:
 360       return "set_high_32bit";
 361
 362    case FS_OPCODE_DDX_COARSE:
 363       return "ddx_coarse";
 364    case FS_OPCODE_DDX_FINE:
 365       return "ddx_fine";
 366    case FS_OPCODE_DDY_COARSE:
 367       return "ddy_coarse";
 368    case FS_OPCODE_DDY_FINE:
 369       return "ddy_fine";
 370
 371    case FS_OPCODE_CINTERP:
 372       return "cinterp";
 373    case FS_OPCODE_LINTERP:
 374       return "linterp";
 375
 376    case FS_OPCODE_PIXEL_X:
 377       return "pixel_x";
 378    case FS_OPCODE_PIXEL_Y:
 379       return "pixel_y";
 380
 381    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 382       return "uniform_pull_const";
 383    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 384       return "uniform_pull_const_gen7";
 385    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 386       return "varying_pull_const_gen4";
 387    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 388       return "varying_pull_const_gen7";
 389    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 390       return "varying_pull_const_logical";
 391
 392    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 393       return "mov_dispatch_to_flags";
 394    case FS_OPCODE_DISCARD_JUMP:
 395       return "discard_jump";
 396
 397    case FS_OPCODE_SET_SAMPLE_ID:
 398       return "set_sample_id";
 399
 400    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 401       return "pack_half_2x16_split";
 402    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 403       return "unpack_half_2x16_split_x";
 404    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 405       return "unpack_half_2x16_split_y";
 406
 407    case FS_OPCODE_PLACEHOLDER_HALT:
 408       return "placeholder_halt";
 409
 410    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 411       return "interp_sample";
 412    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 413       return "interp_shared_offset";
 414    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 415       return "interp_per_slot_offset";
 416
 417    case VS_OPCODE_URB_WRITE:
 418       return "vs_urb_write";
 419    case VS_OPCODE_PULL_CONSTANT_LOAD:
 420       return "pull_constant_load";
 421    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 422       return "pull_constant_load_gen7";
 423
 424    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 425       return "set_simd4x2_header_gen9";
 426
 427    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 428       return "unpack_flags_simd4x2";
 429
 430    case GS_OPCODE_URB_WRITE:
 431       return "gs_urb_write";
 432    case GS_OPCODE_URB_WRITE_ALLOCATE:
 433       return "gs_urb_write_allocate";
 434    case GS_OPCODE_THREAD_END:
 435       return "gs_thread_end";
 436    case GS_OPCODE_SET_WRITE_OFFSET:
 437       return "set_write_offset";
 438    case GS_OPCODE_SET_VERTEX_COUNT:
 439       return "set_vertex_count";
 440    case GS_OPCODE_SET_DWORD_2:
 441       return "set_dword_2";
 442    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 443       return "prepare_channel_masks";
 444    case GS_OPCODE_SET_CHANNEL_MASKS:
 445       return "set_channel_masks";
 446    case GS_OPCODE_GET_INSTANCE_ID:
 447       return "get_instance_id";
 448    case GS_OPCODE_FF_SYNC:
 449       return "ff_sync";
 450    case GS_OPCODE_SET_PRIMITIVE_ID:
 451       return "set_primitive_id";
 452    case GS_OPCODE_SVB_WRITE:
 453       return "gs_svb_write";
 454    case GS_OPCODE_SVB_SET_DST_INDEX:
 455       return "gs_svb_set_dst_index";
 456    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 457       return "gs_ff_sync_set_primitives";
 458    case CS_OPCODE_CS_TERMINATE:
 459       return "cs_terminate";
 460    case SHADER_OPCODE_BARRIER:
 461       return "barrier";
 462    case SHADER_OPCODE_MULH:
 463       return "mulh";
 464    case SHADER_OPCODE_MOV_INDIRECT:
 465       return "mov_indirect";
 466
 467    case VEC4_OPCODE_URB_READ:
 468       return "urb_read";
 469    case TCS_OPCODE_GET_INSTANCE_ID:
 470       return "tcs_get_instance_id";
 471    case TCS_OPCODE_URB_WRITE:
 472       return "tcs_urb_write";
 473    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 474       return "tcs_set_input_urb_offsets";
 475    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 476       return "tcs_set_output_urb_offsets";
 477    case TCS_OPCODE_GET_PRIMITIVE_ID:
 478       return "tcs_get_primitive_id";
 479    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 480       return "tcs_create_barrier_header";
 481    case TCS_OPCODE_SRC0_010_IS_ZERO:
 482       return "tcs_src0<0,1,0>_is_zero";
 483    case TCS_OPCODE_RELEASE_INPUT:
 484       return "tcs_release_input";
 485    case TCS_OPCODE_THREAD_END:
 486       return "tcs_thread_end";
 487    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 488       return "tes_create_input_read_header";
 489    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 490       return "tes_add_indirect_urb_offset";
 491    case TES_OPCODE_GET_PRIMITIVE_ID:
 492       return "tes_get_primitive_id";
 493
 494    case SHADER_OPCODE_RND_MODE:
 495       return "rnd_mode";
 496    }
 497
 498    unreachable("not reached");
 499 }
 500
 501 bool
 502 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 503 {
 504    union {
 505       unsigned ud;
 506       int d;
 507       float f;
 508       double df;
 509    } imm, sat_imm = { 0 };
 510
 511    const unsigned size = type_sz(type);
 512
 513    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 514     * irrelevant, so just check the size of the type and copy from/to an
 515     * appropriately sized field.
 516     */
 517    if (size < 8)
 518       imm.ud = reg->ud;
 519    else
 520       imm.df = reg->df;
 521
 522    switch (type) {
 523    case BRW_REGISTER_TYPE_UD:
 524    case BRW_REGISTER_TYPE_D:
 525    case BRW_REGISTER_TYPE_UW:
 526    case BRW_REGISTER_TYPE_W:
 527    case BRW_REGISTER_TYPE_UQ:
 528    case BRW_REGISTER_TYPE_Q:
 529       /* Nothing to do. */
 530       return false;
 531    case BRW_REGISTER_TYPE_F:
 532       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 533       break;
 534    case BRW_REGISTER_TYPE_DF:
 535       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 536       break;
 537    case BRW_REGISTER_TYPE_UB:
 538    case BRW_REGISTER_TYPE_B:
 539       unreachable("no UB/B immediates");
 540    case BRW_REGISTER_TYPE_V:
 541    case BRW_REGISTER_TYPE_UV:
 542    case BRW_REGISTER_TYPE_VF:
 543       unreachable("unimplemented: saturate vector immediate");
 544    case BRW_REGISTER_TYPE_HF:
 545       unreachable("unimplemented: saturate HF immediate");
 546    case BRW_REGISTER_TYPE_NF:
 547       unreachable("no NF immediates");
 548    }
 549
 550    if (size < 8) {
 551       if (imm.ud != sat_imm.ud) {
 552          reg->ud = sat_imm.ud;
 553          return true;
 554       }
 555    } else {
 556       if (imm.df != sat_imm.df) {
 557          reg->df = sat_imm.df;
 558          return true;
 559       }
 560    }
 561    return false;
 562 }
 563
 564 bool
 565 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 566 {
 567    switch (type) {
 568    case BRW_REGISTER_TYPE_D:
 569    case BRW_REGISTER_TYPE_UD:
 570       reg->d = -reg->d;
 571       return true;
 572    case BRW_REGISTER_TYPE_W:
 573    case BRW_REGISTER_TYPE_UW:
 574       reg->d = -(int16_t)reg->ud;
 575       return true;
 576    case BRW_REGISTER_TYPE_F:
 577       reg->f = -reg->f;
 578       return true;
 579    case BRW_REGISTER_TYPE_VF:
 580       reg->ud ^= 0x80808080;
 581       return true;
 582    case BRW_REGISTER_TYPE_DF:
 583       reg->df = -reg->df;
 584       return true;
 585    case BRW_REGISTER_TYPE_UQ:
 586    case BRW_REGISTER_TYPE_Q:
 587       reg->d64 = -reg->d64;
 588       return true;
 589    case BRW_REGISTER_TYPE_UB:
 590    case BRW_REGISTER_TYPE_B:
 591       unreachable("no UB/B immediates");
 592    case BRW_REGISTER_TYPE_UV:
 593    case BRW_REGISTER_TYPE_V:
 594       assert(!"unimplemented: negate UV/V immediate");
 595    case BRW_REGISTER_TYPE_HF:
 596       assert(!"unimplemented: negate HF immediate");
 597    case BRW_REGISTER_TYPE_NF:
 598       unreachable("no NF immediates");
 599    }
 600
 601    return false;
 602 }
 603
 604 bool
 605 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 606 {
 607    switch (type) {
 608    case BRW_REGISTER_TYPE_D:
 609       reg->d = abs(reg->d);
 610       return true;
 611    case BRW_REGISTER_TYPE_W:
 612       reg->d = abs((int16_t)reg->ud);
 613       return true;
 614    case BRW_REGISTER_TYPE_F:
 615       reg->f = fabsf(reg->f);
 616       return true;
 617    case BRW_REGISTER_TYPE_DF:
 618       reg->df = fabs(reg->df);
 619       return true;
 620    case BRW_REGISTER_TYPE_VF:
 621       reg->ud &= ~0x80808080;
 622       return true;
 623    case BRW_REGISTER_TYPE_Q:
 624       reg->d64 = imaxabs(reg->d64);
 625       return true;
 626    case BRW_REGISTER_TYPE_UB:
 627    case BRW_REGISTER_TYPE_B:
 628       unreachable("no UB/B immediates");
 629    case BRW_REGISTER_TYPE_UQ:
 630    case BRW_REGISTER_TYPE_UD:
 631    case BRW_REGISTER_TYPE_UW:
 632    case BRW_REGISTER_TYPE_UV:
 633       /* Presumably the absolute value modifier on an unsigned source is a
 634        * nop, but it would be nice to confirm.
 635        */
 636       assert(!"unimplemented: abs unsigned immediate");
 637    case BRW_REGISTER_TYPE_V:
 638       assert(!"unimplemented: abs V immediate");
 639    case BRW_REGISTER_TYPE_HF:
 640       assert(!"unimplemented: abs HF immediate");
 641    case BRW_REGISTER_TYPE_NF:
 642       unreachable("no NF immediates");
 643    }
 644
 645    return false;
 646 }
 647
 648 backend_shader::backend_shader(const struct brw_compiler *compiler,
 649                                void *log_data,
 650                                void *mem_ctx,
 651                                const nir_shader *shader,
 652                                struct brw_stage_prog_data *stage_prog_data)
 653    : compiler(compiler),
 654      log_data(log_data),
 655      devinfo(compiler->devinfo),
 656      nir(shader),
 657      stage_prog_data(stage_prog_data),
 658      mem_ctx(mem_ctx),
 659      cfg(NULL),
 660      stage(shader->info.stage)
 661 {
 662    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 663    stage_name = _mesa_shader_stage_to_string(stage);
 664    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 665 }
 666
 667 backend_shader::~backend_shader()
 668 {
 669 }
 670
 671 bool
 672 backend_reg::equals(const backend_reg &r) const
 673 {
 674    return brw_regs_equal(this, &r) && offset == r.offset;
 675 }
 676
 677 bool
 678 backend_reg::is_zero() const
 679 {
 680    if (file != IMM)
 681       return false;
 682
 683    switch (type) {
 684    case BRW_REGISTER_TYPE_F:
 685       return f == 0;
 686    case BRW_REGISTER_TYPE_DF:
 687       return df == 0;
 688    case BRW_REGISTER_TYPE_D:
 689    case BRW_REGISTER_TYPE_UD:
 690       return d == 0;
 691    case BRW_REGISTER_TYPE_UQ:
 692    case BRW_REGISTER_TYPE_Q:
 693       return u64 == 0;
 694    default:
 695       return false;
 696    }
 697 }
 698
 699 bool
 700 backend_reg::is_one() const
 701 {
 702    if (file != IMM)
 703       return false;
 704
 705    switch (type) {
 706    case BRW_REGISTER_TYPE_F:
 707       return f == 1.0f;
 708    case BRW_REGISTER_TYPE_DF:
 709       return df == 1.0;
 710    case BRW_REGISTER_TYPE_D:
 711    case BRW_REGISTER_TYPE_UD:
 712       return d == 1;
 713    case BRW_REGISTER_TYPE_UQ:
 714    case BRW_REGISTER_TYPE_Q:
 715       return u64 == 1;
 716    default:
 717       return false;
 718    }
 719 }
 720
 721 bool
 722 backend_reg::is_negative_one() const
 723 {
 724    if (file != IMM)
 725       return false;
 726
 727    switch (type) {
 728    case BRW_REGISTER_TYPE_F:
 729       return f == -1.0;
 730    case BRW_REGISTER_TYPE_DF:
 731       return df == -1.0;
 732    case BRW_REGISTER_TYPE_D:
 733       return d == -1;
 734    case BRW_REGISTER_TYPE_Q:
 735       return d64 == -1;
 736    default:
 737       return false;
 738    }
 739 }
 740
 741 bool
 742 backend_reg::is_null() const
 743 {
 744    return file == ARF && nr == BRW_ARF_NULL;
 745 }
 746
 747
 748 bool
 749 backend_reg::is_accumulator() const
 750 {
 751    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 752 }
 753
 754 bool
 755 backend_instruction::is_commutative() const
 756 {
 757    switch (opcode) {
 758    case BRW_OPCODE_AND:
 759    case BRW_OPCODE_OR:
 760    case BRW_OPCODE_XOR:
 761    case BRW_OPCODE_ADD:
 762    case BRW_OPCODE_MUL:
 763    case SHADER_OPCODE_MULH:
 764       return true;
 765    case BRW_OPCODE_SEL:
 766       /* MIN and MAX are commutative. */
 767       if (conditional_mod == BRW_CONDITIONAL_GE ||
 768           conditional_mod == BRW_CONDITIONAL_L) {
 769          return true;
 770       }
 771       /* fallthrough */
 772    default:
 773       return false;
 774    }
 775 }
 776
 777 bool
 778 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 779 {
 780    return ::is_3src(devinfo, opcode);
 781 }
 782
 783 bool
 784 backend_instruction::is_tex() const
 785 {
 786    return (opcode == SHADER_OPCODE_TEX ||
 787            opcode == FS_OPCODE_TXB ||
 788            opcode == SHADER_OPCODE_TXD ||
 789            opcode == SHADER_OPCODE_TXF ||
 790            opcode == SHADER_OPCODE_TXF_LZ ||
 791            opcode == SHADER_OPCODE_TXF_CMS ||
 792            opcode == SHADER_OPCODE_TXF_CMS_W ||
 793            opcode == SHADER_OPCODE_TXF_UMS ||
 794            opcode == SHADER_OPCODE_TXF_MCS ||
 795            opcode == SHADER_OPCODE_TXL ||
 796            opcode == SHADER_OPCODE_TXL_LZ ||
 797            opcode == SHADER_OPCODE_TXS ||
 798            opcode == SHADER_OPCODE_LOD ||
 799            opcode == SHADER_OPCODE_TG4 ||
 800            opcode == SHADER_OPCODE_TG4_OFFSET ||
 801            opcode == SHADER_OPCODE_SAMPLEINFO);
 802 }
 803
 804 bool
 805 backend_instruction::is_math() const
 806 {
 807    return (opcode == SHADER_OPCODE_RCP ||
 808            opcode == SHADER_OPCODE_RSQ ||
 809            opcode == SHADER_OPCODE_SQRT ||
 810            opcode == SHADER_OPCODE_EXP2 ||
 811            opcode == SHADER_OPCODE_LOG2 ||
 812            opcode == SHADER_OPCODE_SIN ||
 813            opcode == SHADER_OPCODE_COS ||
 814            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 815            opcode == SHADER_OPCODE_INT_REMAINDER ||
 816            opcode == SHADER_OPCODE_POW);
 817 }
 818
 819 bool
 820 backend_instruction::is_control_flow() const
 821 {
 822    switch (opcode) {
 823    case BRW_OPCODE_DO:
 824    case BRW_OPCODE_WHILE:
 825    case BRW_OPCODE_IF:
 826    case BRW_OPCODE_ELSE:
 827    case BRW_OPCODE_ENDIF:
 828    case BRW_OPCODE_BREAK:
 829    case BRW_OPCODE_CONTINUE:
 830       return true;
 831    default:
 832       return false;
 833    }
 834 }
 835
 836 bool
 837 backend_instruction::can_do_source_mods() const
 838 {
 839    switch (opcode) {
 840    case BRW_OPCODE_ADDC:
 841    case BRW_OPCODE_BFE:
 842    case BRW_OPCODE_BFI1:
 843    case BRW_OPCODE_BFI2:
 844    case BRW_OPCODE_BFREV:
 845    case BRW_OPCODE_CBIT:
 846    case BRW_OPCODE_FBH:
 847    case BRW_OPCODE_FBL:
 848    case BRW_OPCODE_SUBB:
 849    case SHADER_OPCODE_BROADCAST:
 850    case SHADER_OPCODE_MOV_INDIRECT:
 851       return false;
 852    default:
 853       return true;
 854    }
 855 }
 856
 857 bool
 858 backend_instruction::can_do_saturate() const
 859 {
 860    switch (opcode) {
 861    case BRW_OPCODE_ADD:
 862    case BRW_OPCODE_ASR:
 863    case BRW_OPCODE_AVG:
 864    case BRW_OPCODE_DP2:
 865    case BRW_OPCODE_DP3:
 866    case BRW_OPCODE_DP4:
 867    case BRW_OPCODE_DPH:
 868    case BRW_OPCODE_F16TO32:
 869    case BRW_OPCODE_F32TO16:
 870    case BRW_OPCODE_LINE:
 871    case BRW_OPCODE_LRP:
 872    case BRW_OPCODE_MAC:
 873    case BRW_OPCODE_MAD:
 874    case BRW_OPCODE_MATH:
 875    case BRW_OPCODE_MOV:
 876    case BRW_OPCODE_MUL:
 877    case SHADER_OPCODE_MULH:
 878    case BRW_OPCODE_PLN:
 879    case BRW_OPCODE_RNDD:
 880    case BRW_OPCODE_RNDE:
 881    case BRW_OPCODE_RNDU:
 882    case BRW_OPCODE_RNDZ:
 883    case BRW_OPCODE_SEL:
 884    case BRW_OPCODE_SHL:
 885    case BRW_OPCODE_SHR:
 886    case FS_OPCODE_LINTERP:
 887    case SHADER_OPCODE_COS:
 888    case SHADER_OPCODE_EXP2:
 889    case SHADER_OPCODE_LOG2:
 890    case SHADER_OPCODE_POW:
 891    case SHADER_OPCODE_RCP:
 892    case SHADER_OPCODE_RSQ:
 893    case SHADER_OPCODE_SIN:
 894    case SHADER_OPCODE_SQRT:
 895       return true;
 896    default:
 897       return false;
 898    }
 899 }
 900
 901 bool
 902 backend_instruction::can_do_cmod() const
 903 {
 904    switch (opcode) {
 905    case BRW_OPCODE_ADD:
 906    case BRW_OPCODE_ADDC:
 907    case BRW_OPCODE_AND:
 908    case BRW_OPCODE_ASR:
 909    case BRW_OPCODE_AVG:
 910    case BRW_OPCODE_CMP:
 911    case BRW_OPCODE_CMPN:
 912    case BRW_OPCODE_DP2:
 913    case BRW_OPCODE_DP3:
 914    case BRW_OPCODE_DP4:
 915    case BRW_OPCODE_DPH:
 916    case BRW_OPCODE_F16TO32:
 917    case BRW_OPCODE_F32TO16:
 918    case BRW_OPCODE_FRC:
 919    case BRW_OPCODE_LINE:
 920    case BRW_OPCODE_LRP:
 921    case BRW_OPCODE_LZD:
 922    case BRW_OPCODE_MAC:
 923    case BRW_OPCODE_MACH:
 924    case BRW_OPCODE_MAD:
 925    case BRW_OPCODE_MOV:
 926    case BRW_OPCODE_MUL:
 927    case BRW_OPCODE_NOT:
 928    case BRW_OPCODE_OR:
 929    case BRW_OPCODE_PLN:
 930    case BRW_OPCODE_RNDD:
 931    case BRW_OPCODE_RNDE:
 932    case BRW_OPCODE_RNDU:
 933    case BRW_OPCODE_RNDZ:
 934    case BRW_OPCODE_SAD2:
 935    case BRW_OPCODE_SADA2:
 936    case BRW_OPCODE_SHL:
 937    case BRW_OPCODE_SHR:
 938    case BRW_OPCODE_SUBB:
 939    case BRW_OPCODE_XOR:
 940    case FS_OPCODE_CINTERP:
 941    case FS_OPCODE_LINTERP:
 942       return true;
 943    default:
 944       return false;
 945    }
 946 }
 947
 948 bool
 949 backend_instruction::reads_accumulator_implicitly() const
 950 {
 951    switch (opcode) {
 952    case BRW_OPCODE_MAC:
 953    case BRW_OPCODE_MACH:
 954    case BRW_OPCODE_SADA2:
 955       return true;
 956    default:
 957       return false;
 958    }
 959 }
 960
 961 bool
 962 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 963 {
 964    return writes_accumulator ||
 965           (devinfo->gen < 6 &&
 966            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 967             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 968              opcode != FS_OPCODE_CINTERP)));
 969 }
 970
 971 bool
 972 backend_instruction::has_side_effects() const
 973 {
 974    switch (opcode) {
 975    case SHADER_OPCODE_UNTYPED_ATOMIC:
 976    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 977    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 978    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 979    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 980    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
 981    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 982    case SHADER_OPCODE_TYPED_ATOMIC:
 983    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 984    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 985    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 986    case SHADER_OPCODE_MEMORY_FENCE:
 987    case SHADER_OPCODE_URB_WRITE_SIMD8:
 988    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 989    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 990    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 991    case FS_OPCODE_FB_WRITE:
 992    case FS_OPCODE_FB_WRITE_LOGICAL:
 993    case SHADER_OPCODE_BARRIER:
 994    case TCS_OPCODE_URB_WRITE:
 995    case TCS_OPCODE_RELEASE_INPUT:
 996    case SHADER_OPCODE_RND_MODE:
 997       return true;
 998    default:
 999       return eot;
1000    }
1001 }
1002
1003 bool
1004 backend_instruction::is_volatile() const
1005 {
1006    switch (opcode) {
1007    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1008    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1009    case SHADER_OPCODE_TYPED_SURFACE_READ:
1010    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1011    case SHADER_OPCODE_BYTE_SCATTERED_READ:
1012    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1013    case SHADER_OPCODE_URB_READ_SIMD8:
1014    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1015    case VEC4_OPCODE_URB_READ:
1016       return true;
1017    default:
1018       return false;
1019    }
1020 }
1021
1022 #ifndef NDEBUG
1023 static bool
1024 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1025 {
1026    bool found = false;
1027    foreach_inst_in_block (backend_instruction, i, block) {
1028       if (inst == i) {
1029          found = true;
1030       }
1031    }
1032    return found;
1033 }
1034 #endif
1035
1036 static void
1037 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1038 {
1039    for (bblock_t *block_iter = start_block->next();
1040         block_iter;
1041         block_iter = block_iter->next()) {
1042       block_iter->start_ip += ip_adjustment;
1043       block_iter->end_ip += ip_adjustment;
1044    }
1045 }
1046
1047 void
1048 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1049 {
1050    assert(this != inst);
1051
1052    if (!this->is_head_sentinel())
1053       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1054
1055    block->end_ip++;
1056
1057    adjust_later_block_ips(block, 1);
1058
1059    exec_node::insert_after(inst);
1060 }
1061
1062 void
1063 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1064 {
1065    assert(this != inst);
1066
1067    if (!this->is_tail_sentinel())
1068       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1069
1070    block->end_ip++;
1071
1072    adjust_later_block_ips(block, 1);
1073
1074    exec_node::insert_before(inst);
1075 }
1076
1077 void
1078 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1079 {
1080    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1081
1082    unsigned num_inst = list->length();
1083
1084    block->end_ip += num_inst;
1085
1086    adjust_later_block_ips(block, num_inst);
1087
1088    exec_node::insert_before(list);
1089 }
1090
1091 void
1092 backend_instruction::remove(bblock_t *block)
1093 {
1094    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1095
1096    adjust_later_block_ips(block, -1);
1097
1098    if (block->start_ip == block->end_ip) {
1099       block->cfg->remove_block(block);
1100    } else {
1101       block->end_ip--;
1102    }
1103
1104    exec_node::remove();
1105 }
1106
1107 void
1108 backend_shader::dump_instructions()
1109 {
1110    dump_instructions(NULL);
1111 }
1112
1113 void
1114 backend_shader::dump_instructions(const char *name)
1115 {
1116    FILE *file = stderr;
1117    if (name && geteuid() != 0) {
1118       file = fopen(name, "w");
1119       if (!file)
1120          file = stderr;
1121    }
1122
1123    if (cfg) {
1124       int ip = 0;
1125       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1126          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1127             fprintf(file, "%4d: ", ip++);
1128          dump_instruction(inst, file);
1129       }
1130    } else {
1131       int ip = 0;
1132       foreach_in_list(backend_instruction, inst, &instructions) {
1133          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1134             fprintf(file, "%4d: ", ip++);
1135          dump_instruction(inst, file);
1136       }
1137    }
1138
1139    if (file != stderr) {
1140       fclose(file);
1141    }
1142 }
1143
1144 void
1145 backend_shader::calculate_cfg()
1146 {
1147    if (this->cfg)
1148       return;
1149    cfg = new(mem_ctx) cfg_t(&this->instructions);
1150 }
1151
1152 extern "C" const unsigned *
1153 brw_compile_tes(const struct brw_compiler *compiler,
1154                 void *log_data,
1155                 void *mem_ctx,
1156                 const struct brw_tes_prog_key *key,
1157                 const struct brw_vue_map *input_vue_map,
1158                 struct brw_tes_prog_data *prog_data,
1159                 const nir_shader *src_shader,
1160                 struct gl_program *prog,
1161                 int shader_time_index,
1162                 char **error_str)
1163 {
1164    const struct gen_device_info *devinfo = compiler->devinfo;
1165    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1166    const unsigned *assembly;
1167
1168    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1169    nir->info.inputs_read = key->inputs_read;
1170    nir->info.patch_inputs_read = key->patch_inputs_read;
1171
1172    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1173    brw_nir_lower_tes_inputs(nir, input_vue_map);
1174    brw_nir_lower_vue_outputs(nir, is_scalar);
1175    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1176
1177    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1178                        nir->info.outputs_written,
1179                        nir->info.separate_shader);
1180
1181    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1182
1183    assert(output_size_bytes >= 1);
1184    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1185       if (error_str)
1186          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1187       return NULL;
1188    }
1189
1190    prog_data->base.clip_distance_mask =
1191       ((1 << nir->info.clip_distance_array_size) - 1);
1192    prog_data->base.cull_distance_mask =
1193       ((1 << nir->info.cull_distance_array_size) - 1) <<
1194       nir->info.clip_distance_array_size;
1195
1196    /* URB entry sizes are stored as a multiple of 64 bytes. */
1197    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1198
1199    /* On Cannonlake software shall not program an allocation size that
1200     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1201     */
1202    if (devinfo->gen == 10 &&
1203        prog_data->base.urb_entry_size % 3 == 0)
1204       prog_data->base.urb_entry_size++;
1205
1206    prog_data->base.urb_read_length = 0;
1207
1208    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1209    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1210                  TESS_SPACING_FRACTIONAL_ODD - 1);
1211    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1212                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1213
1214    prog_data->partitioning =
1215       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1216
1217    switch (nir->info.tess.primitive_mode) {
1218    case GL_QUADS:
1219       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1220       break;
1221    case GL_TRIANGLES:
1222       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1223       break;
1224    case GL_ISOLINES:
1225       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1226       break;
1227    default:
1228       unreachable("invalid domain shader primitive mode");
1229    }
1230
1231    if (nir->info.tess.point_mode) {
1232       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1233    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1234       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1235    } else {
1236       /* Hardware winding order is backwards from OpenGL */
1237       prog_data->output_topology =
1238          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1239                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1240    }
1241
1242    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1243       fprintf(stderr, "TES Input ");
1244       brw_print_vue_map(stderr, input_vue_map);
1245       fprintf(stderr, "TES Output ");
1246       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1247    }
1248
1249    if (is_scalar) {
1250       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1251                    &prog_data->base.base, NULL, nir, 8,
1252                    shader_time_index, input_vue_map);
1253       if (!v.run_tes()) {
1254          if (error_str)
1255             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1256          return NULL;
1257       }
1258
1259       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1260       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1261
1262       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1263                      &prog_data->base.base, v.promoted_constants, false,
1264                      MESA_SHADER_TESS_EVAL);
1265       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1266          g.enable_debug(ralloc_asprintf(mem_ctx,
1267                                         "%s tessellation evaluation shader %s",
1268                                         nir->info.label ? nir->info.label
1269                                                         : "unnamed",
1270                                         nir->info.name));
1271       }
1272
1273       g.generate_code(v.cfg, 8);
1274
1275       assembly = g.get_assembly();
1276    } else {
1277       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1278                               nir, mem_ctx, shader_time_index);
1279       if (!v.run()) {
1280          if (error_str)
1281             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1282          return NULL;
1283       }
1284
1285       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1286          v.dump_instructions();
1287
1288       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1289                                             &prog_data->base, v.cfg);
1290    }
1291
1292    return assembly;
1293 }