src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "common/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_INT8:
  48       return BRW_REGISTER_TYPE_B;
  49    case GLSL_TYPE_UINT:
  50       return BRW_REGISTER_TYPE_UD;
  51    case GLSL_TYPE_UINT16:
  52       return BRW_REGISTER_TYPE_UW;
  53    case GLSL_TYPE_UINT8:
  54       return BRW_REGISTER_TYPE_UB;
  55    case GLSL_TYPE_ARRAY:
  56       return brw_type_for_base_type(type->fields.array);
  57    case GLSL_TYPE_STRUCT:
  58    case GLSL_TYPE_SAMPLER:
  59    case GLSL_TYPE_ATOMIC_UINT:
  60       /* These should be overridden with the type of the member when
  61        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  62        * way to trip up if we don't.
  63        */
  64       return BRW_REGISTER_TYPE_UD;
  65    case GLSL_TYPE_IMAGE:
  66       return BRW_REGISTER_TYPE_UD;
  67    case GLSL_TYPE_DOUBLE:
  68       return BRW_REGISTER_TYPE_DF;
  69    case GLSL_TYPE_UINT64:
  70       return BRW_REGISTER_TYPE_UQ;
  71    case GLSL_TYPE_INT64:
  72       return BRW_REGISTER_TYPE_Q;
  73    case GLSL_TYPE_VOID:
  74    case GLSL_TYPE_ERROR:
  75    case GLSL_TYPE_INTERFACE:
  76    case GLSL_TYPE_FUNCTION:
  77       unreachable("not reached");
  78    }
  79
  80    return BRW_REGISTER_TYPE_F;
  81 }
  82
  83 enum brw_conditional_mod
  84 brw_conditional_for_comparison(unsigned int op)
  85 {
  86    switch (op) {
  87    case ir_binop_less:
  88       return BRW_CONDITIONAL_L;
  89    case ir_binop_gequal:
  90       return BRW_CONDITIONAL_GE;
  91    case ir_binop_equal:
  92    case ir_binop_all_equal: /* same as equal for scalars */
  93       return BRW_CONDITIONAL_Z;
  94    case ir_binop_nequal:
  95    case ir_binop_any_nequal: /* same as nequal for scalars */
  96       return BRW_CONDITIONAL_NZ;
  97    default:
  98       unreachable("not reached: bad operation for comparison");
  99    }
 100 }
 101
 102 uint32_t
 103 brw_math_function(enum opcode op)
 104 {
 105    switch (op) {
 106    case SHADER_OPCODE_RCP:
 107       return BRW_MATH_FUNCTION_INV;
 108    case SHADER_OPCODE_RSQ:
 109       return BRW_MATH_FUNCTION_RSQ;
 110    case SHADER_OPCODE_SQRT:
 111       return BRW_MATH_FUNCTION_SQRT;
 112    case SHADER_OPCODE_EXP2:
 113       return BRW_MATH_FUNCTION_EXP;
 114    case SHADER_OPCODE_LOG2:
 115       return BRW_MATH_FUNCTION_LOG;
 116    case SHADER_OPCODE_POW:
 117       return BRW_MATH_FUNCTION_POW;
 118    case SHADER_OPCODE_SIN:
 119       return BRW_MATH_FUNCTION_SIN;
 120    case SHADER_OPCODE_COS:
 121       return BRW_MATH_FUNCTION_COS;
 122    case SHADER_OPCODE_INT_QUOTIENT:
 123       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 124    case SHADER_OPCODE_INT_REMAINDER:
 125       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 126    default:
 127       unreachable("not reached: unknown math function");
 128    }
 129 }
 130
 131 bool
 132 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 133 {
 134    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 135
 136    /* offset out of bounds; caller will handle it. */
 137    for (unsigned i = 0; i < num_components; i++)
 138       if (offsets[i] > 7 || offsets[i] < -8)
 139          return false;
 140
 141    /* Combine all three offsets into a single unsigned dword:
 142     *
 143     *    bits 11:8 - U Offset (X component)
 144     *    bits  7:4 - V Offset (Y component)
 145     *    bits  3:0 - R Offset (Z component)
 146     */
 147    *offset_bits = 0;
 148    for (unsigned i = 0; i < num_components; i++) {
 149       const unsigned shift = 4 * (2 - i);
 150       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 151    }
 152    return true;
 153 }
 154
 155 const char *
 156 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 157 {
 158    switch (op) {
 159    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 160       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 161        * start of a loop in the IR.
 162        */
 163       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 164          return "do";
 165
 166       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 167        * then to mark that we want to do the conversion.
 168        */
 169       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 170          return "f32to16";
 171
 172       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 173          return "f16to32";
 174
 175       assert(brw_opcode_desc(devinfo, op)->name);
 176       return brw_opcode_desc(devinfo, op)->name;
 177    case FS_OPCODE_FB_WRITE:
 178       return "fb_write";
 179    case FS_OPCODE_FB_WRITE_LOGICAL:
 180       return "fb_write_logical";
 181    case FS_OPCODE_REP_FB_WRITE:
 182       return "rep_fb_write";
 183    case FS_OPCODE_FB_READ:
 184       return "fb_read";
 185    case FS_OPCODE_FB_READ_LOGICAL:
 186       return "fb_read_logical";
 187
 188    case SHADER_OPCODE_RCP:
 189       return "rcp";
 190    case SHADER_OPCODE_RSQ:
 191       return "rsq";
 192    case SHADER_OPCODE_SQRT:
 193       return "sqrt";
 194    case SHADER_OPCODE_EXP2:
 195       return "exp2";
 196    case SHADER_OPCODE_LOG2:
 197       return "log2";
 198    case SHADER_OPCODE_POW:
 199       return "pow";
 200    case SHADER_OPCODE_INT_QUOTIENT:
 201       return "int_quot";
 202    case SHADER_OPCODE_INT_REMAINDER:
 203       return "int_rem";
 204    case SHADER_OPCODE_SIN:
 205       return "sin";
 206    case SHADER_OPCODE_COS:
 207       return "cos";
 208
 209    case SHADER_OPCODE_SEND:
 210       return "send";
 211
 212    case SHADER_OPCODE_TEX:
 213       return "tex";
 214    case SHADER_OPCODE_TEX_LOGICAL:
 215       return "tex_logical";
 216    case SHADER_OPCODE_TXD:
 217       return "txd";
 218    case SHADER_OPCODE_TXD_LOGICAL:
 219       return "txd_logical";
 220    case SHADER_OPCODE_TXF:
 221       return "txf";
 222    case SHADER_OPCODE_TXF_LOGICAL:
 223       return "txf_logical";
 224    case SHADER_OPCODE_TXF_LZ:
 225       return "txf_lz";
 226    case SHADER_OPCODE_TXL:
 227       return "txl";
 228    case SHADER_OPCODE_TXL_LOGICAL:
 229       return "txl_logical";
 230    case SHADER_OPCODE_TXL_LZ:
 231       return "txl_lz";
 232    case SHADER_OPCODE_TXS:
 233       return "txs";
 234    case SHADER_OPCODE_TXS_LOGICAL:
 235       return "txs_logical";
 236    case FS_OPCODE_TXB:
 237       return "txb";
 238    case FS_OPCODE_TXB_LOGICAL:
 239       return "txb_logical";
 240    case SHADER_OPCODE_TXF_CMS:
 241       return "txf_cms";
 242    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 243       return "txf_cms_logical";
 244    case SHADER_OPCODE_TXF_CMS_W:
 245       return "txf_cms_w";
 246    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 247       return "txf_cms_w_logical";
 248    case SHADER_OPCODE_TXF_UMS:
 249       return "txf_ums";
 250    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 251       return "txf_ums_logical";
 252    case SHADER_OPCODE_TXF_MCS:
 253       return "txf_mcs";
 254    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 255       return "txf_mcs_logical";
 256    case SHADER_OPCODE_LOD:
 257       return "lod";
 258    case SHADER_OPCODE_LOD_LOGICAL:
 259       return "lod_logical";
 260    case SHADER_OPCODE_TG4:
 261       return "tg4";
 262    case SHADER_OPCODE_TG4_LOGICAL:
 263       return "tg4_logical";
 264    case SHADER_OPCODE_TG4_OFFSET:
 265       return "tg4_offset";
 266    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 267       return "tg4_offset_logical";
 268    case SHADER_OPCODE_SAMPLEINFO:
 269       return "sampleinfo";
 270    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 271       return "sampleinfo_logical";
 272
 273    case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
 274       return "image_size_logical";
 275
 276    case SHADER_OPCODE_SHADER_TIME_ADD:
 277       return "shader_time_add";
 278
 279    case SHADER_OPCODE_UNTYPED_ATOMIC:
 280       return "untyped_atomic";
 281    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 282       return "untyped_atomic_logical";
 283    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT:
 284       return "untyped_atomic_float";
 285    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 286       return "untyped_atomic_float_logical";
 287    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 288       return "untyped_surface_read";
 289    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 290       return "untyped_surface_read_logical";
 291    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 292       return "untyped_surface_write";
 293    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 294       return "untyped_surface_write_logical";
 295    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
 296       return "a64_untyped_read_logical";
 297    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
 298       return "a64_untyped_write_logical";
 299    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
 300       return "a64_byte_scattered_read_logical";
 301    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
 302       return "a64_byte_scattered_write_logical";
 303    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
 304       return "a64_untyped_atomic_logical";
 305    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 306       return "a64_untyped_atomic_float_logical";
 307    case SHADER_OPCODE_TYPED_ATOMIC:
 308       return "typed_atomic";
 309    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 310       return "typed_atomic_logical";
 311    case SHADER_OPCODE_TYPED_SURFACE_READ:
 312       return "typed_surface_read";
 313    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 314       return "typed_surface_read_logical";
 315    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 316       return "typed_surface_write";
 317    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 318       return "typed_surface_write_logical";
 319    case SHADER_OPCODE_MEMORY_FENCE:
 320       return "memory_fence";
 321    case SHADER_OPCODE_INTERLOCK:
 322       /* For an interlock we actually issue a memory fence via sendc. */
 323       return "interlock";
 324
 325    case SHADER_OPCODE_BYTE_SCATTERED_READ:
 326       return "byte_scattered_read";
 327    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 328       return "byte_scattered_read_logical";
 329    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
 330       return "byte_scattered_write";
 331    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 332       return "byte_scattered_write_logical";
 333
 334    case SHADER_OPCODE_LOAD_PAYLOAD:
 335       return "load_payload";
 336    case FS_OPCODE_PACK:
 337       return "pack";
 338
 339    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 340       return "gen4_scratch_read";
 341    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 342       return "gen4_scratch_write";
 343    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 344       return "gen7_scratch_read";
 345    case SHADER_OPCODE_URB_WRITE_SIMD8:
 346       return "gen8_urb_write_simd8";
 347    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 348       return "gen8_urb_write_simd8_per_slot";
 349    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 350       return "gen8_urb_write_simd8_masked";
 351    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 352       return "gen8_urb_write_simd8_masked_per_slot";
 353    case SHADER_OPCODE_URB_READ_SIMD8:
 354       return "urb_read_simd8";
 355    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 356       return "urb_read_simd8_per_slot";
 357
 358    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 359       return "find_live_channel";
 360    case SHADER_OPCODE_BROADCAST:
 361       return "broadcast";
 362    case SHADER_OPCODE_SHUFFLE:
 363       return "shuffle";
 364    case SHADER_OPCODE_SEL_EXEC:
 365       return "sel_exec";
 366    case SHADER_OPCODE_QUAD_SWIZZLE:
 367       return "quad_swizzle";
 368    case SHADER_OPCODE_CLUSTER_BROADCAST:
 369       return "cluster_broadcast";
 370
 371    case SHADER_OPCODE_GET_BUFFER_SIZE:
 372       return "get_buffer_size";
 373
 374    case VEC4_OPCODE_MOV_BYTES:
 375       return "mov_bytes";
 376    case VEC4_OPCODE_PACK_BYTES:
 377       return "pack_bytes";
 378    case VEC4_OPCODE_UNPACK_UNIFORM:
 379       return "unpack_uniform";
 380    case VEC4_OPCODE_DOUBLE_TO_F32:
 381       return "double_to_f32";
 382    case VEC4_OPCODE_DOUBLE_TO_D32:
 383       return "double_to_d32";
 384    case VEC4_OPCODE_DOUBLE_TO_U32:
 385       return "double_to_u32";
 386    case VEC4_OPCODE_TO_DOUBLE:
 387       return "single_to_double";
 388    case VEC4_OPCODE_PICK_LOW_32BIT:
 389       return "pick_low_32bit";
 390    case VEC4_OPCODE_PICK_HIGH_32BIT:
 391       return "pick_high_32bit";
 392    case VEC4_OPCODE_SET_LOW_32BIT:
 393       return "set_low_32bit";
 394    case VEC4_OPCODE_SET_HIGH_32BIT:
 395       return "set_high_32bit";
 396
 397    case FS_OPCODE_DDX_COARSE:
 398       return "ddx_coarse";
 399    case FS_OPCODE_DDX_FINE:
 400       return "ddx_fine";
 401    case FS_OPCODE_DDY_COARSE:
 402       return "ddy_coarse";
 403    case FS_OPCODE_DDY_FINE:
 404       return "ddy_fine";
 405
 406    case FS_OPCODE_LINTERP:
 407       return "linterp";
 408
 409    case FS_OPCODE_PIXEL_X:
 410       return "pixel_x";
 411    case FS_OPCODE_PIXEL_Y:
 412       return "pixel_y";
 413
 414    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 415       return "uniform_pull_const";
 416    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 417       return "uniform_pull_const_gen7";
 418    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 419       return "varying_pull_const_gen4";
 420    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 421       return "varying_pull_const_logical";
 422
 423    case FS_OPCODE_DISCARD_JUMP:
 424       return "discard_jump";
 425
 426    case FS_OPCODE_SET_SAMPLE_ID:
 427       return "set_sample_id";
 428
 429    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 430       return "pack_half_2x16_split";
 431
 432    case FS_OPCODE_PLACEHOLDER_HALT:
 433       return "placeholder_halt";
 434
 435    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 436       return "interp_sample";
 437    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 438       return "interp_shared_offset";
 439    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 440       return "interp_per_slot_offset";
 441
 442    case VS_OPCODE_URB_WRITE:
 443       return "vs_urb_write";
 444    case VS_OPCODE_PULL_CONSTANT_LOAD:
 445       return "pull_constant_load";
 446    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 447       return "pull_constant_load_gen7";
 448
 449    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 450       return "set_simd4x2_header_gen9";
 451
 452    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 453       return "unpack_flags_simd4x2";
 454
 455    case GS_OPCODE_URB_WRITE:
 456       return "gs_urb_write";
 457    case GS_OPCODE_URB_WRITE_ALLOCATE:
 458       return "gs_urb_write_allocate";
 459    case GS_OPCODE_THREAD_END:
 460       return "gs_thread_end";
 461    case GS_OPCODE_SET_WRITE_OFFSET:
 462       return "set_write_offset";
 463    case GS_OPCODE_SET_VERTEX_COUNT:
 464       return "set_vertex_count";
 465    case GS_OPCODE_SET_DWORD_2:
 466       return "set_dword_2";
 467    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 468       return "prepare_channel_masks";
 469    case GS_OPCODE_SET_CHANNEL_MASKS:
 470       return "set_channel_masks";
 471    case GS_OPCODE_GET_INSTANCE_ID:
 472       return "get_instance_id";
 473    case GS_OPCODE_FF_SYNC:
 474       return "ff_sync";
 475    case GS_OPCODE_SET_PRIMITIVE_ID:
 476       return "set_primitive_id";
 477    case GS_OPCODE_SVB_WRITE:
 478       return "gs_svb_write";
 479    case GS_OPCODE_SVB_SET_DST_INDEX:
 480       return "gs_svb_set_dst_index";
 481    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 482       return "gs_ff_sync_set_primitives";
 483    case CS_OPCODE_CS_TERMINATE:
 484       return "cs_terminate";
 485    case SHADER_OPCODE_BARRIER:
 486       return "barrier";
 487    case SHADER_OPCODE_MULH:
 488       return "mulh";
 489    case SHADER_OPCODE_MOV_INDIRECT:
 490       return "mov_indirect";
 491
 492    case VEC4_OPCODE_URB_READ:
 493       return "urb_read";
 494    case TCS_OPCODE_GET_INSTANCE_ID:
 495       return "tcs_get_instance_id";
 496    case TCS_OPCODE_URB_WRITE:
 497       return "tcs_urb_write";
 498    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 499       return "tcs_set_input_urb_offsets";
 500    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 501       return "tcs_set_output_urb_offsets";
 502    case TCS_OPCODE_GET_PRIMITIVE_ID:
 503       return "tcs_get_primitive_id";
 504    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 505       return "tcs_create_barrier_header";
 506    case TCS_OPCODE_SRC0_010_IS_ZERO:
 507       return "tcs_src0<0,1,0>_is_zero";
 508    case TCS_OPCODE_RELEASE_INPUT:
 509       return "tcs_release_input";
 510    case TCS_OPCODE_THREAD_END:
 511       return "tcs_thread_end";
 512    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 513       return "tes_create_input_read_header";
 514    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 515       return "tes_add_indirect_urb_offset";
 516    case TES_OPCODE_GET_PRIMITIVE_ID:
 517       return "tes_get_primitive_id";
 518
 519    case SHADER_OPCODE_RND_MODE:
 520       return "rnd_mode";
 521    }
 522
 523    unreachable("not reached");
 524 }
 525
 526 bool
 527 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 528 {
 529    union {
 530       unsigned ud;
 531       int d;
 532       float f;
 533       double df;
 534    } imm, sat_imm = { 0 };
 535
 536    const unsigned size = type_sz(type);
 537
 538    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 539     * irrelevant, so just check the size of the type and copy from/to an
 540     * appropriately sized field.
 541     */
 542    if (size < 8)
 543       imm.ud = reg->ud;
 544    else
 545       imm.df = reg->df;
 546
 547    switch (type) {
 548    case BRW_REGISTER_TYPE_UD:
 549    case BRW_REGISTER_TYPE_D:
 550    case BRW_REGISTER_TYPE_UW:
 551    case BRW_REGISTER_TYPE_W:
 552    case BRW_REGISTER_TYPE_UQ:
 553    case BRW_REGISTER_TYPE_Q:
 554       /* Nothing to do. */
 555       return false;
 556    case BRW_REGISTER_TYPE_F:
 557       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 558       break;
 559    case BRW_REGISTER_TYPE_DF:
 560       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 561       break;
 562    case BRW_REGISTER_TYPE_UB:
 563    case BRW_REGISTER_TYPE_B:
 564       unreachable("no UB/B immediates");
 565    case BRW_REGISTER_TYPE_V:
 566    case BRW_REGISTER_TYPE_UV:
 567    case BRW_REGISTER_TYPE_VF:
 568       unreachable("unimplemented: saturate vector immediate");
 569    case BRW_REGISTER_TYPE_HF:
 570       unreachable("unimplemented: saturate HF immediate");
 571    case BRW_REGISTER_TYPE_NF:
 572       unreachable("no NF immediates");
 573    }
 574
 575    if (size < 8) {
 576       if (imm.ud != sat_imm.ud) {
 577          reg->ud = sat_imm.ud;
 578          return true;
 579       }
 580    } else {
 581       if (imm.df != sat_imm.df) {
 582          reg->df = sat_imm.df;
 583          return true;
 584       }
 585    }
 586    return false;
 587 }
 588
 589 bool
 590 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 591 {
 592    switch (type) {
 593    case BRW_REGISTER_TYPE_D:
 594    case BRW_REGISTER_TYPE_UD:
 595       reg->d = -reg->d;
 596       return true;
 597    case BRW_REGISTER_TYPE_W:
 598    case BRW_REGISTER_TYPE_UW: {
 599       uint16_t value = -(int16_t)reg->ud;
 600       reg->ud = value | (uint32_t)value << 16;
 601       return true;
 602    }
 603    case BRW_REGISTER_TYPE_F:
 604       reg->f = -reg->f;
 605       return true;
 606    case BRW_REGISTER_TYPE_VF:
 607       reg->ud ^= 0x80808080;
 608       return true;
 609    case BRW_REGISTER_TYPE_DF:
 610       reg->df = -reg->df;
 611       return true;
 612    case BRW_REGISTER_TYPE_UQ:
 613    case BRW_REGISTER_TYPE_Q:
 614       reg->d64 = -reg->d64;
 615       return true;
 616    case BRW_REGISTER_TYPE_UB:
 617    case BRW_REGISTER_TYPE_B:
 618       unreachable("no UB/B immediates");
 619    case BRW_REGISTER_TYPE_UV:
 620    case BRW_REGISTER_TYPE_V:
 621       assert(!"unimplemented: negate UV/V immediate");
 622    case BRW_REGISTER_TYPE_HF:
 623       reg->ud ^= 0x80008000;
 624       return true;
 625    case BRW_REGISTER_TYPE_NF:
 626       unreachable("no NF immediates");
 627    }
 628
 629    return false;
 630 }
 631
 632 bool
 633 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 634 {
 635    switch (type) {
 636    case BRW_REGISTER_TYPE_D:
 637       reg->d = abs(reg->d);
 638       return true;
 639    case BRW_REGISTER_TYPE_W: {
 640       uint16_t value = abs((int16_t)reg->ud);
 641       reg->ud = value | (uint32_t)value << 16;
 642       return true;
 643    }
 644    case BRW_REGISTER_TYPE_F:
 645       reg->f = fabsf(reg->f);
 646       return true;
 647    case BRW_REGISTER_TYPE_DF:
 648       reg->df = fabs(reg->df);
 649       return true;
 650    case BRW_REGISTER_TYPE_VF:
 651       reg->ud &= ~0x80808080;
 652       return true;
 653    case BRW_REGISTER_TYPE_Q:
 654       reg->d64 = imaxabs(reg->d64);
 655       return true;
 656    case BRW_REGISTER_TYPE_UB:
 657    case BRW_REGISTER_TYPE_B:
 658       unreachable("no UB/B immediates");
 659    case BRW_REGISTER_TYPE_UQ:
 660    case BRW_REGISTER_TYPE_UD:
 661    case BRW_REGISTER_TYPE_UW:
 662    case BRW_REGISTER_TYPE_UV:
 663       /* Presumably the absolute value modifier on an unsigned source is a
 664        * nop, but it would be nice to confirm.
 665        */
 666       assert(!"unimplemented: abs unsigned immediate");
 667    case BRW_REGISTER_TYPE_V:
 668       assert(!"unimplemented: abs V immediate");
 669    case BRW_REGISTER_TYPE_HF:
 670       reg->ud &= ~0x80008000;
 671       return true;
 672    case BRW_REGISTER_TYPE_NF:
 673       unreachable("no NF immediates");
 674    }
 675
 676    return false;
 677 }
 678
 679 backend_shader::backend_shader(const struct brw_compiler *compiler,
 680                                void *log_data,
 681                                void *mem_ctx,
 682                                const nir_shader *shader,
 683                                struct brw_stage_prog_data *stage_prog_data)
 684    : compiler(compiler),
 685      log_data(log_data),
 686      devinfo(compiler->devinfo),
 687      nir(shader),
 688      stage_prog_data(stage_prog_data),
 689      mem_ctx(mem_ctx),
 690      cfg(NULL),
 691      stage(shader->info.stage)
 692 {
 693    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 694    stage_name = _mesa_shader_stage_to_string(stage);
 695    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 696 }
 697
 698 backend_shader::~backend_shader()
 699 {
 700 }
 701
 702 bool
 703 backend_reg::equals(const backend_reg &r) const
 704 {
 705    return brw_regs_equal(this, &r) && offset == r.offset;
 706 }
 707
 708 bool
 709 backend_reg::negative_equals(const backend_reg &r) const
 710 {
 711    return brw_regs_negative_equal(this, &r) && offset == r.offset;
 712 }
 713
 714 bool
 715 backend_reg::is_zero() const
 716 {
 717    if (file != IMM)
 718       return false;
 719
 720    switch (type) {
 721    case BRW_REGISTER_TYPE_F:
 722       return f == 0;
 723    case BRW_REGISTER_TYPE_DF:
 724       return df == 0;
 725    case BRW_REGISTER_TYPE_D:
 726    case BRW_REGISTER_TYPE_UD:
 727       return d == 0;
 728    case BRW_REGISTER_TYPE_UQ:
 729    case BRW_REGISTER_TYPE_Q:
 730       return u64 == 0;
 731    default:
 732       return false;
 733    }
 734 }
 735
 736 bool
 737 backend_reg::is_one() const
 738 {
 739    if (file != IMM)
 740       return false;
 741
 742    switch (type) {
 743    case BRW_REGISTER_TYPE_F:
 744       return f == 1.0f;
 745    case BRW_REGISTER_TYPE_DF:
 746       return df == 1.0;
 747    case BRW_REGISTER_TYPE_D:
 748    case BRW_REGISTER_TYPE_UD:
 749       return d == 1;
 750    case BRW_REGISTER_TYPE_UQ:
 751    case BRW_REGISTER_TYPE_Q:
 752       return u64 == 1;
 753    default:
 754       return false;
 755    }
 756 }
 757
 758 bool
 759 backend_reg::is_negative_one() const
 760 {
 761    if (file != IMM)
 762       return false;
 763
 764    switch (type) {
 765    case BRW_REGISTER_TYPE_F:
 766       return f == -1.0;
 767    case BRW_REGISTER_TYPE_DF:
 768       return df == -1.0;
 769    case BRW_REGISTER_TYPE_D:
 770       return d == -1;
 771    case BRW_REGISTER_TYPE_Q:
 772       return d64 == -1;
 773    default:
 774       return false;
 775    }
 776 }
 777
 778 bool
 779 backend_reg::is_null() const
 780 {
 781    return file == ARF && nr == BRW_ARF_NULL;
 782 }
 783
 784
 785 bool
 786 backend_reg::is_accumulator() const
 787 {
 788    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 789 }
 790
 791 bool
 792 backend_instruction::is_commutative() const
 793 {
 794    switch (opcode) {
 795    case BRW_OPCODE_AND:
 796    case BRW_OPCODE_OR:
 797    case BRW_OPCODE_XOR:
 798    case BRW_OPCODE_ADD:
 799    case BRW_OPCODE_MUL:
 800    case SHADER_OPCODE_MULH:
 801       return true;
 802    case BRW_OPCODE_SEL:
 803       /* MIN and MAX are commutative. */
 804       if (conditional_mod == BRW_CONDITIONAL_GE ||
 805           conditional_mod == BRW_CONDITIONAL_L) {
 806          return true;
 807       }
 808       /* fallthrough */
 809    default:
 810       return false;
 811    }
 812 }
 813
 814 bool
 815 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 816 {
 817    return ::is_3src(devinfo, opcode);
 818 }
 819
 820 bool
 821 backend_instruction::is_tex() const
 822 {
 823    return (opcode == SHADER_OPCODE_TEX ||
 824            opcode == FS_OPCODE_TXB ||
 825            opcode == SHADER_OPCODE_TXD ||
 826            opcode == SHADER_OPCODE_TXF ||
 827            opcode == SHADER_OPCODE_TXF_LZ ||
 828            opcode == SHADER_OPCODE_TXF_CMS ||
 829            opcode == SHADER_OPCODE_TXF_CMS_W ||
 830            opcode == SHADER_OPCODE_TXF_UMS ||
 831            opcode == SHADER_OPCODE_TXF_MCS ||
 832            opcode == SHADER_OPCODE_TXL ||
 833            opcode == SHADER_OPCODE_TXL_LZ ||
 834            opcode == SHADER_OPCODE_TXS ||
 835            opcode == SHADER_OPCODE_LOD ||
 836            opcode == SHADER_OPCODE_TG4 ||
 837            opcode == SHADER_OPCODE_TG4_OFFSET ||
 838            opcode == SHADER_OPCODE_SAMPLEINFO);
 839 }
 840
 841 bool
 842 backend_instruction::is_math() const
 843 {
 844    return (opcode == SHADER_OPCODE_RCP ||
 845            opcode == SHADER_OPCODE_RSQ ||
 846            opcode == SHADER_OPCODE_SQRT ||
 847            opcode == SHADER_OPCODE_EXP2 ||
 848            opcode == SHADER_OPCODE_LOG2 ||
 849            opcode == SHADER_OPCODE_SIN ||
 850            opcode == SHADER_OPCODE_COS ||
 851            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 852            opcode == SHADER_OPCODE_INT_REMAINDER ||
 853            opcode == SHADER_OPCODE_POW);
 854 }
 855
 856 bool
 857 backend_instruction::is_control_flow() const
 858 {
 859    switch (opcode) {
 860    case BRW_OPCODE_DO:
 861    case BRW_OPCODE_WHILE:
 862    case BRW_OPCODE_IF:
 863    case BRW_OPCODE_ELSE:
 864    case BRW_OPCODE_ENDIF:
 865    case BRW_OPCODE_BREAK:
 866    case BRW_OPCODE_CONTINUE:
 867       return true;
 868    default:
 869       return false;
 870    }
 871 }
 872
 873 bool
 874 backend_instruction::can_do_source_mods() const
 875 {
 876    switch (opcode) {
 877    case BRW_OPCODE_ADDC:
 878    case BRW_OPCODE_BFE:
 879    case BRW_OPCODE_BFI1:
 880    case BRW_OPCODE_BFI2:
 881    case BRW_OPCODE_BFREV:
 882    case BRW_OPCODE_CBIT:
 883    case BRW_OPCODE_FBH:
 884    case BRW_OPCODE_FBL:
 885    case BRW_OPCODE_SUBB:
 886    case SHADER_OPCODE_BROADCAST:
 887    case SHADER_OPCODE_CLUSTER_BROADCAST:
 888    case SHADER_OPCODE_MOV_INDIRECT:
 889       return false;
 890    default:
 891       return true;
 892    }
 893 }
 894
 895 bool
 896 backend_instruction::can_do_saturate() const
 897 {
 898    switch (opcode) {
 899    case BRW_OPCODE_ADD:
 900    case BRW_OPCODE_ASR:
 901    case BRW_OPCODE_AVG:
 902    case BRW_OPCODE_DP2:
 903    case BRW_OPCODE_DP3:
 904    case BRW_OPCODE_DP4:
 905    case BRW_OPCODE_DPH:
 906    case BRW_OPCODE_F16TO32:
 907    case BRW_OPCODE_F32TO16:
 908    case BRW_OPCODE_LINE:
 909    case BRW_OPCODE_LRP:
 910    case BRW_OPCODE_MAC:
 911    case BRW_OPCODE_MAD:
 912    case BRW_OPCODE_MATH:
 913    case BRW_OPCODE_MOV:
 914    case BRW_OPCODE_MUL:
 915    case SHADER_OPCODE_MULH:
 916    case BRW_OPCODE_PLN:
 917    case BRW_OPCODE_RNDD:
 918    case BRW_OPCODE_RNDE:
 919    case BRW_OPCODE_RNDU:
 920    case BRW_OPCODE_RNDZ:
 921    case BRW_OPCODE_SEL:
 922    case BRW_OPCODE_SHL:
 923    case BRW_OPCODE_SHR:
 924    case FS_OPCODE_LINTERP:
 925    case SHADER_OPCODE_COS:
 926    case SHADER_OPCODE_EXP2:
 927    case SHADER_OPCODE_LOG2:
 928    case SHADER_OPCODE_POW:
 929    case SHADER_OPCODE_RCP:
 930    case SHADER_OPCODE_RSQ:
 931    case SHADER_OPCODE_SIN:
 932    case SHADER_OPCODE_SQRT:
 933       return true;
 934    default:
 935       return false;
 936    }
 937 }
 938
 939 bool
 940 backend_instruction::can_do_cmod() const
 941 {
 942    switch (opcode) {
 943    case BRW_OPCODE_ADD:
 944    case BRW_OPCODE_ADDC:
 945    case BRW_OPCODE_AND:
 946    case BRW_OPCODE_ASR:
 947    case BRW_OPCODE_AVG:
 948    case BRW_OPCODE_CMP:
 949    case BRW_OPCODE_CMPN:
 950    case BRW_OPCODE_DP2:
 951    case BRW_OPCODE_DP3:
 952    case BRW_OPCODE_DP4:
 953    case BRW_OPCODE_DPH:
 954    case BRW_OPCODE_F16TO32:
 955    case BRW_OPCODE_F32TO16:
 956    case BRW_OPCODE_FRC:
 957    case BRW_OPCODE_LINE:
 958    case BRW_OPCODE_LRP:
 959    case BRW_OPCODE_LZD:
 960    case BRW_OPCODE_MAC:
 961    case BRW_OPCODE_MACH:
 962    case BRW_OPCODE_MAD:
 963    case BRW_OPCODE_MOV:
 964    case BRW_OPCODE_MUL:
 965    case BRW_OPCODE_NOT:
 966    case BRW_OPCODE_OR:
 967    case BRW_OPCODE_PLN:
 968    case BRW_OPCODE_RNDD:
 969    case BRW_OPCODE_RNDE:
 970    case BRW_OPCODE_RNDU:
 971    case BRW_OPCODE_RNDZ:
 972    case BRW_OPCODE_SAD2:
 973    case BRW_OPCODE_SADA2:
 974    case BRW_OPCODE_SHL:
 975    case BRW_OPCODE_SHR:
 976    case BRW_OPCODE_SUBB:
 977    case BRW_OPCODE_XOR:
 978    case FS_OPCODE_LINTERP:
 979       return true;
 980    default:
 981       return false;
 982    }
 983 }
 984
 985 bool
 986 backend_instruction::reads_accumulator_implicitly() const
 987 {
 988    switch (opcode) {
 989    case BRW_OPCODE_MAC:
 990    case BRW_OPCODE_MACH:
 991    case BRW_OPCODE_SADA2:
 992       return true;
 993    default:
 994       return false;
 995    }
 996 }
 997
 998 bool
 999 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
1000 {
1001    return writes_accumulator ||
1002           (devinfo->gen < 6 &&
1003            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1004             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
1005           (opcode == FS_OPCODE_LINTERP &&
1006            (!devinfo->has_pln || devinfo->gen <= 6));
1007 }
1008
1009 bool
1010 backend_instruction::has_side_effects() const
1011 {
1012    switch (opcode) {
1013    case SHADER_OPCODE_SEND:
1014       return send_has_side_effects;
1015
1016    case SHADER_OPCODE_UNTYPED_ATOMIC:
1017    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1018    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT:
1019    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1020    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1021    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1022    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1023    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
1024    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
1025    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
1026    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1027    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
1028    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1029    case SHADER_OPCODE_TYPED_ATOMIC:
1030    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1031    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1032    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1033    case SHADER_OPCODE_MEMORY_FENCE:
1034    case SHADER_OPCODE_INTERLOCK:
1035    case SHADER_OPCODE_URB_WRITE_SIMD8:
1036    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1037    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1038    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1039    case FS_OPCODE_FB_WRITE:
1040    case FS_OPCODE_FB_WRITE_LOGICAL:
1041    case FS_OPCODE_REP_FB_WRITE:
1042    case SHADER_OPCODE_BARRIER:
1043    case TCS_OPCODE_URB_WRITE:
1044    case TCS_OPCODE_RELEASE_INPUT:
1045    case SHADER_OPCODE_RND_MODE:
1046       return true;
1047    default:
1048       return eot;
1049    }
1050 }
1051
1052 bool
1053 backend_instruction::is_volatile() const
1054 {
1055    switch (opcode) {
1056    case SHADER_OPCODE_SEND:
1057       return send_is_volatile;
1058
1059    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1060    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1061    case SHADER_OPCODE_TYPED_SURFACE_READ:
1062    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1063    case SHADER_OPCODE_BYTE_SCATTERED_READ:
1064    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1065    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
1066    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
1067    case SHADER_OPCODE_URB_READ_SIMD8:
1068    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1069    case VEC4_OPCODE_URB_READ:
1070       return true;
1071    default:
1072       return false;
1073    }
1074 }
1075
1076 #ifndef NDEBUG
1077 static bool
1078 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1079 {
1080    bool found = false;
1081    foreach_inst_in_block (backend_instruction, i, block) {
1082       if (inst == i) {
1083          found = true;
1084       }
1085    }
1086    return found;
1087 }
1088 #endif
1089
1090 static void
1091 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1092 {
1093    for (bblock_t *block_iter = start_block->next();
1094         block_iter;
1095         block_iter = block_iter->next()) {
1096       block_iter->start_ip += ip_adjustment;
1097       block_iter->end_ip += ip_adjustment;
1098    }
1099 }
1100
1101 void
1102 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1103 {
1104    assert(this != inst);
1105
1106    if (!this->is_head_sentinel())
1107       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1108
1109    block->end_ip++;
1110
1111    adjust_later_block_ips(block, 1);
1112
1113    exec_node::insert_after(inst);
1114 }
1115
1116 void
1117 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1118 {
1119    assert(this != inst);
1120
1121    if (!this->is_tail_sentinel())
1122       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1123
1124    block->end_ip++;
1125
1126    adjust_later_block_ips(block, 1);
1127
1128    exec_node::insert_before(inst);
1129 }
1130
1131 void
1132 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1133 {
1134    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1135
1136    unsigned num_inst = list->length();
1137
1138    block->end_ip += num_inst;
1139
1140    adjust_later_block_ips(block, num_inst);
1141
1142    exec_node::insert_before(list);
1143 }
1144
1145 void
1146 backend_instruction::remove(bblock_t *block)
1147 {
1148    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1149
1150    adjust_later_block_ips(block, -1);
1151
1152    if (block->start_ip == block->end_ip) {
1153       block->cfg->remove_block(block);
1154    } else {
1155       block->end_ip--;
1156    }
1157
1158    exec_node::remove();
1159 }
1160
1161 void
1162 backend_shader::dump_instructions()
1163 {
1164    dump_instructions(NULL);
1165 }
1166
1167 void
1168 backend_shader::dump_instructions(const char *name)
1169 {
1170    FILE *file = stderr;
1171    if (name && geteuid() != 0) {
1172       file = fopen(name, "w");
1173       if (!file)
1174          file = stderr;
1175    }
1176
1177    if (cfg) {
1178       int ip = 0;
1179       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1180          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1181             fprintf(file, "%4d: ", ip++);
1182          dump_instruction(inst, file);
1183       }
1184    } else {
1185       int ip = 0;
1186       foreach_in_list(backend_instruction, inst, &instructions) {
1187          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1188             fprintf(file, "%4d: ", ip++);
1189          dump_instruction(inst, file);
1190       }
1191    }
1192
1193    if (file != stderr) {
1194       fclose(file);
1195    }
1196 }
1197
1198 void
1199 backend_shader::calculate_cfg()
1200 {
1201    if (this->cfg)
1202       return;
1203    cfg = new(mem_ctx) cfg_t(&this->instructions);
1204 }
1205
1206 extern "C" const unsigned *
1207 brw_compile_tes(const struct brw_compiler *compiler,
1208                 void *log_data,
1209                 void *mem_ctx,
1210                 const struct brw_tes_prog_key *key,
1211                 const struct brw_vue_map *input_vue_map,
1212                 struct brw_tes_prog_data *prog_data,
1213                 nir_shader *nir,
1214                 struct gl_program *prog,
1215                 int shader_time_index,
1216                 char **error_str)
1217 {
1218    const struct gen_device_info *devinfo = compiler->devinfo;
1219    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1220    const unsigned *assembly;
1221
1222    nir->info.inputs_read = key->inputs_read;
1223    nir->info.patch_inputs_read = key->patch_inputs_read;
1224
1225    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1226    brw_nir_lower_tes_inputs(nir, input_vue_map);
1227    brw_nir_lower_vue_outputs(nir);
1228    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1229
1230    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1231                        nir->info.outputs_written,
1232                        nir->info.separate_shader);
1233
1234    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1235
1236    assert(output_size_bytes >= 1);
1237    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1238       if (error_str)
1239          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1240       return NULL;
1241    }
1242
1243    prog_data->base.clip_distance_mask =
1244       ((1 << nir->info.clip_distance_array_size) - 1);
1245    prog_data->base.cull_distance_mask =
1246       ((1 << nir->info.cull_distance_array_size) - 1) <<
1247       nir->info.clip_distance_array_size;
1248
1249    /* URB entry sizes are stored as a multiple of 64 bytes. */
1250    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1251
1252    /* On Cannonlake software shall not program an allocation size that
1253     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1254     */
1255    if (devinfo->gen == 10 &&
1256        prog_data->base.urb_entry_size % 3 == 0)
1257       prog_data->base.urb_entry_size++;
1258
1259    prog_data->base.urb_read_length = 0;
1260
1261    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1262    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1263                  TESS_SPACING_FRACTIONAL_ODD - 1);
1264    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1265                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1266
1267    prog_data->partitioning =
1268       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1269
1270    switch (nir->info.tess.primitive_mode) {
1271    case GL_QUADS:
1272       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1273       break;
1274    case GL_TRIANGLES:
1275       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1276       break;
1277    case GL_ISOLINES:
1278       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1279       break;
1280    default:
1281       unreachable("invalid domain shader primitive mode");
1282    }
1283
1284    if (nir->info.tess.point_mode) {
1285       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1286    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1287       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1288    } else {
1289       /* Hardware winding order is backwards from OpenGL */
1290       prog_data->output_topology =
1291          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1292                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1293    }
1294
1295    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1296       fprintf(stderr, "TES Input ");
1297       brw_print_vue_map(stderr, input_vue_map);
1298       fprintf(stderr, "TES Output ");
1299       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1300    }
1301
1302    if (is_scalar) {
1303       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1304                    &prog_data->base.base, NULL, nir, 8,
1305                    shader_time_index, input_vue_map);
1306       if (!v.run_tes()) {
1307          if (error_str)
1308             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1309          return NULL;
1310       }
1311
1312       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1313       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1314
1315       fs_generator g(compiler, log_data, mem_ctx,
1316                      &prog_data->base.base, v.promoted_constants, false,
1317                      MESA_SHADER_TESS_EVAL);
1318       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1319          g.enable_debug(ralloc_asprintf(mem_ctx,
1320                                         "%s tessellation evaluation shader %s",
1321                                         nir->info.label ? nir->info.label
1322                                                         : "unnamed",
1323                                         nir->info.name));
1324       }
1325
1326       g.generate_code(v.cfg, 8);
1327
1328       assembly = g.get_assembly();
1329    } else {
1330       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1331                               nir, mem_ctx, shader_time_index);
1332       if (!v.run()) {
1333          if (error_str)
1334             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1335          return NULL;
1336       }
1337
1338       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1339          v.dump_instructions();
1340
1341       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1342                                             &prog_data->base, v.cfg);
1343    }
1344
1345    return assembly;
1346 }