src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "common/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_UINT:
  48       return BRW_REGISTER_TYPE_UD;
  49    case GLSL_TYPE_UINT16:
  50       return BRW_REGISTER_TYPE_UW;
  51    case GLSL_TYPE_ARRAY:
  52       return brw_type_for_base_type(type->fields.array);
  53    case GLSL_TYPE_STRUCT:
  54    case GLSL_TYPE_SAMPLER:
  55    case GLSL_TYPE_ATOMIC_UINT:
  56       /* These should be overridden with the type of the member when
  57        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  58        * way to trip up if we don't.
  59        */
  60       return BRW_REGISTER_TYPE_UD;
  61    case GLSL_TYPE_IMAGE:
  62       return BRW_REGISTER_TYPE_UD;
  63    case GLSL_TYPE_DOUBLE:
  64       return BRW_REGISTER_TYPE_DF;
  65    case GLSL_TYPE_UINT64:
  66       return BRW_REGISTER_TYPE_UQ;
  67    case GLSL_TYPE_INT64:
  68       return BRW_REGISTER_TYPE_Q;
  69    case GLSL_TYPE_VOID:
  70    case GLSL_TYPE_ERROR:
  71    case GLSL_TYPE_INTERFACE:
  72    case GLSL_TYPE_FUNCTION:
  73       unreachable("not reached");
  74    }
  75
  76    return BRW_REGISTER_TYPE_F;
  77 }
  78
  79 enum brw_conditional_mod
  80 brw_conditional_for_comparison(unsigned int op)
  81 {
  82    switch (op) {
  83    case ir_binop_less:
  84       return BRW_CONDITIONAL_L;
  85    case ir_binop_gequal:
  86       return BRW_CONDITIONAL_GE;
  87    case ir_binop_equal:
  88    case ir_binop_all_equal: /* same as equal for scalars */
  89       return BRW_CONDITIONAL_Z;
  90    case ir_binop_nequal:
  91    case ir_binop_any_nequal: /* same as nequal for scalars */
  92       return BRW_CONDITIONAL_NZ;
  93    default:
  94       unreachable("not reached: bad operation for comparison");
  95    }
  96 }
  97
  98 uint32_t
  99 brw_math_function(enum opcode op)
 100 {
 101    switch (op) {
 102    case SHADER_OPCODE_RCP:
 103       return BRW_MATH_FUNCTION_INV;
 104    case SHADER_OPCODE_RSQ:
 105       return BRW_MATH_FUNCTION_RSQ;
 106    case SHADER_OPCODE_SQRT:
 107       return BRW_MATH_FUNCTION_SQRT;
 108    case SHADER_OPCODE_EXP2:
 109       return BRW_MATH_FUNCTION_EXP;
 110    case SHADER_OPCODE_LOG2:
 111       return BRW_MATH_FUNCTION_LOG;
 112    case SHADER_OPCODE_POW:
 113       return BRW_MATH_FUNCTION_POW;
 114    case SHADER_OPCODE_SIN:
 115       return BRW_MATH_FUNCTION_SIN;
 116    case SHADER_OPCODE_COS:
 117       return BRW_MATH_FUNCTION_COS;
 118    case SHADER_OPCODE_INT_QUOTIENT:
 119       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 120    case SHADER_OPCODE_INT_REMAINDER:
 121       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 122    default:
 123       unreachable("not reached: unknown math function");
 124    }
 125 }
 126
 127 bool
 128 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 129 {
 130    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 131
 132    /* offset out of bounds; caller will handle it. */
 133    for (unsigned i = 0; i < num_components; i++)
 134       if (offsets[i] > 7 || offsets[i] < -8)
 135          return false;
 136
 137    /* Combine all three offsets into a single unsigned dword:
 138     *
 139     *    bits 11:8 - U Offset (X component)
 140     *    bits  7:4 - V Offset (Y component)
 141     *    bits  3:0 - R Offset (Z component)
 142     */
 143    *offset_bits = 0;
 144    for (unsigned i = 0; i < num_components; i++) {
 145       const unsigned shift = 4 * (2 - i);
 146       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 147    }
 148    return true;
 149 }
 150
 151 const char *
 152 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 153 {
 154    switch (op) {
 155    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 156       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 157        * start of a loop in the IR.
 158        */
 159       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 160          return "do";
 161
 162       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 163        * then to mark that we want to do the conversion.
 164        */
 165       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 166          return "f32to16";
 167
 168       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 169          return "f16to32";
 170
 171       assert(brw_opcode_desc(devinfo, op)->name);
 172       return brw_opcode_desc(devinfo, op)->name;
 173    case FS_OPCODE_FB_WRITE:
 174       return "fb_write";
 175    case FS_OPCODE_FB_WRITE_LOGICAL:
 176       return "fb_write_logical";
 177    case FS_OPCODE_REP_FB_WRITE:
 178       return "rep_fb_write";
 179    case FS_OPCODE_FB_READ:
 180       return "fb_read";
 181    case FS_OPCODE_FB_READ_LOGICAL:
 182       return "fb_read_logical";
 183
 184    case SHADER_OPCODE_RCP:
 185       return "rcp";
 186    case SHADER_OPCODE_RSQ:
 187       return "rsq";
 188    case SHADER_OPCODE_SQRT:
 189       return "sqrt";
 190    case SHADER_OPCODE_EXP2:
 191       return "exp2";
 192    case SHADER_OPCODE_LOG2:
 193       return "log2";
 194    case SHADER_OPCODE_POW:
 195       return "pow";
 196    case SHADER_OPCODE_INT_QUOTIENT:
 197       return "int_quot";
 198    case SHADER_OPCODE_INT_REMAINDER:
 199       return "int_rem";
 200    case SHADER_OPCODE_SIN:
 201       return "sin";
 202    case SHADER_OPCODE_COS:
 203       return "cos";
 204
 205    case SHADER_OPCODE_TEX:
 206       return "tex";
 207    case SHADER_OPCODE_TEX_LOGICAL:
 208       return "tex_logical";
 209    case SHADER_OPCODE_TXD:
 210       return "txd";
 211    case SHADER_OPCODE_TXD_LOGICAL:
 212       return "txd_logical";
 213    case SHADER_OPCODE_TXF:
 214       return "txf";
 215    case SHADER_OPCODE_TXF_LOGICAL:
 216       return "txf_logical";
 217    case SHADER_OPCODE_TXF_LZ:
 218       return "txf_lz";
 219    case SHADER_OPCODE_TXL:
 220       return "txl";
 221    case SHADER_OPCODE_TXL_LOGICAL:
 222       return "txl_logical";
 223    case SHADER_OPCODE_TXL_LZ:
 224       return "txl_lz";
 225    case SHADER_OPCODE_TXS:
 226       return "txs";
 227    case SHADER_OPCODE_TXS_LOGICAL:
 228       return "txs_logical";
 229    case FS_OPCODE_TXB:
 230       return "txb";
 231    case FS_OPCODE_TXB_LOGICAL:
 232       return "txb_logical";
 233    case SHADER_OPCODE_TXF_CMS:
 234       return "txf_cms";
 235    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 236       return "txf_cms_logical";
 237    case SHADER_OPCODE_TXF_CMS_W:
 238       return "txf_cms_w";
 239    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 240       return "txf_cms_w_logical";
 241    case SHADER_OPCODE_TXF_UMS:
 242       return "txf_ums";
 243    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 244       return "txf_ums_logical";
 245    case SHADER_OPCODE_TXF_MCS:
 246       return "txf_mcs";
 247    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 248       return "txf_mcs_logical";
 249    case SHADER_OPCODE_LOD:
 250       return "lod";
 251    case SHADER_OPCODE_LOD_LOGICAL:
 252       return "lod_logical";
 253    case SHADER_OPCODE_TG4:
 254       return "tg4";
 255    case SHADER_OPCODE_TG4_LOGICAL:
 256       return "tg4_logical";
 257    case SHADER_OPCODE_TG4_OFFSET:
 258       return "tg4_offset";
 259    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 260       return "tg4_offset_logical";
 261    case SHADER_OPCODE_SAMPLEINFO:
 262       return "sampleinfo";
 263    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 264       return "sampleinfo_logical";
 265
 266    case SHADER_OPCODE_SHADER_TIME_ADD:
 267       return "shader_time_add";
 268
 269    case SHADER_OPCODE_UNTYPED_ATOMIC:
 270       return "untyped_atomic";
 271    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 272       return "untyped_atomic_logical";
 273    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 274       return "untyped_surface_read";
 275    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 276       return "untyped_surface_read_logical";
 277    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 278       return "untyped_surface_write";
 279    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 280       return "untyped_surface_write_logical";
 281    case SHADER_OPCODE_TYPED_ATOMIC:
 282       return "typed_atomic";
 283    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 284       return "typed_atomic_logical";
 285    case SHADER_OPCODE_TYPED_SURFACE_READ:
 286       return "typed_surface_read";
 287    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 288       return "typed_surface_read_logical";
 289    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 290       return "typed_surface_write";
 291    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 292       return "typed_surface_write_logical";
 293    case SHADER_OPCODE_MEMORY_FENCE:
 294       return "memory_fence";
 295
 296    case SHADER_OPCODE_BYTE_SCATTERED_READ:
 297       return "byte_scattered_read";
 298    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 299       return "byte_scattered_read_logical";
 300    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
 301       return "byte_scattered_write";
 302    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 303       return "byte_scattered_write_logical";
 304
 305    case SHADER_OPCODE_LOAD_PAYLOAD:
 306       return "load_payload";
 307    case FS_OPCODE_PACK:
 308       return "pack";
 309
 310    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 311       return "gen4_scratch_read";
 312    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 313       return "gen4_scratch_write";
 314    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 315       return "gen7_scratch_read";
 316    case SHADER_OPCODE_URB_WRITE_SIMD8:
 317       return "gen8_urb_write_simd8";
 318    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 319       return "gen8_urb_write_simd8_per_slot";
 320    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 321       return "gen8_urb_write_simd8_masked";
 322    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 323       return "gen8_urb_write_simd8_masked_per_slot";
 324    case SHADER_OPCODE_URB_READ_SIMD8:
 325       return "urb_read_simd8";
 326    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 327       return "urb_read_simd8_per_slot";
 328
 329    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 330       return "find_live_channel";
 331    case SHADER_OPCODE_BROADCAST:
 332       return "broadcast";
 333    case SHADER_OPCODE_SHUFFLE:
 334       return "shuffle";
 335    case SHADER_OPCODE_SEL_EXEC:
 336       return "sel_exec";
 337    case SHADER_OPCODE_CLUSTER_BROADCAST:
 338       return "cluster_broadcast";
 339
 340    case SHADER_OPCODE_GET_BUFFER_SIZE:
 341       return "get_buffer_size";
 342
 343    case VEC4_OPCODE_MOV_BYTES:
 344       return "mov_bytes";
 345    case VEC4_OPCODE_PACK_BYTES:
 346       return "pack_bytes";
 347    case VEC4_OPCODE_UNPACK_UNIFORM:
 348       return "unpack_uniform";
 349    case VEC4_OPCODE_DOUBLE_TO_F32:
 350       return "double_to_f32";
 351    case VEC4_OPCODE_DOUBLE_TO_D32:
 352       return "double_to_d32";
 353    case VEC4_OPCODE_DOUBLE_TO_U32:
 354       return "double_to_u32";
 355    case VEC4_OPCODE_TO_DOUBLE:
 356       return "single_to_double";
 357    case VEC4_OPCODE_PICK_LOW_32BIT:
 358       return "pick_low_32bit";
 359    case VEC4_OPCODE_PICK_HIGH_32BIT:
 360       return "pick_high_32bit";
 361    case VEC4_OPCODE_SET_LOW_32BIT:
 362       return "set_low_32bit";
 363    case VEC4_OPCODE_SET_HIGH_32BIT:
 364       return "set_high_32bit";
 365
 366    case FS_OPCODE_DDX_COARSE:
 367       return "ddx_coarse";
 368    case FS_OPCODE_DDX_FINE:
 369       return "ddx_fine";
 370    case FS_OPCODE_DDY_COARSE:
 371       return "ddy_coarse";
 372    case FS_OPCODE_DDY_FINE:
 373       return "ddy_fine";
 374
 375    case FS_OPCODE_CINTERP:
 376       return "cinterp";
 377    case FS_OPCODE_LINTERP:
 378       return "linterp";
 379
 380    case FS_OPCODE_PIXEL_X:
 381       return "pixel_x";
 382    case FS_OPCODE_PIXEL_Y:
 383       return "pixel_y";
 384
 385    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 386       return "uniform_pull_const";
 387    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 388       return "uniform_pull_const_gen7";
 389    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 390       return "varying_pull_const_gen4";
 391    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 392       return "varying_pull_const_gen7";
 393    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 394       return "varying_pull_const_logical";
 395
 396    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 397       return "mov_dispatch_to_flags";
 398    case FS_OPCODE_DISCARD_JUMP:
 399       return "discard_jump";
 400
 401    case FS_OPCODE_SET_SAMPLE_ID:
 402       return "set_sample_id";
 403
 404    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 405       return "pack_half_2x16_split";
 406    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 407       return "unpack_half_2x16_split_x";
 408    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 409       return "unpack_half_2x16_split_y";
 410
 411    case FS_OPCODE_PLACEHOLDER_HALT:
 412       return "placeholder_halt";
 413
 414    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 415       return "interp_sample";
 416    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 417       return "interp_shared_offset";
 418    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 419       return "interp_per_slot_offset";
 420
 421    case VS_OPCODE_URB_WRITE:
 422       return "vs_urb_write";
 423    case VS_OPCODE_PULL_CONSTANT_LOAD:
 424       return "pull_constant_load";
 425    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 426       return "pull_constant_load_gen7";
 427
 428    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 429       return "set_simd4x2_header_gen9";
 430
 431    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 432       return "unpack_flags_simd4x2";
 433
 434    case GS_OPCODE_URB_WRITE:
 435       return "gs_urb_write";
 436    case GS_OPCODE_URB_WRITE_ALLOCATE:
 437       return "gs_urb_write_allocate";
 438    case GS_OPCODE_THREAD_END:
 439       return "gs_thread_end";
 440    case GS_OPCODE_SET_WRITE_OFFSET:
 441       return "set_write_offset";
 442    case GS_OPCODE_SET_VERTEX_COUNT:
 443       return "set_vertex_count";
 444    case GS_OPCODE_SET_DWORD_2:
 445       return "set_dword_2";
 446    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 447       return "prepare_channel_masks";
 448    case GS_OPCODE_SET_CHANNEL_MASKS:
 449       return "set_channel_masks";
 450    case GS_OPCODE_GET_INSTANCE_ID:
 451       return "get_instance_id";
 452    case GS_OPCODE_FF_SYNC:
 453       return "ff_sync";
 454    case GS_OPCODE_SET_PRIMITIVE_ID:
 455       return "set_primitive_id";
 456    case GS_OPCODE_SVB_WRITE:
 457       return "gs_svb_write";
 458    case GS_OPCODE_SVB_SET_DST_INDEX:
 459       return "gs_svb_set_dst_index";
 460    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 461       return "gs_ff_sync_set_primitives";
 462    case CS_OPCODE_CS_TERMINATE:
 463       return "cs_terminate";
 464    case SHADER_OPCODE_BARRIER:
 465       return "barrier";
 466    case SHADER_OPCODE_MULH:
 467       return "mulh";
 468    case SHADER_OPCODE_MOV_INDIRECT:
 469       return "mov_indirect";
 470
 471    case VEC4_OPCODE_URB_READ:
 472       return "urb_read";
 473    case TCS_OPCODE_GET_INSTANCE_ID:
 474       return "tcs_get_instance_id";
 475    case TCS_OPCODE_URB_WRITE:
 476       return "tcs_urb_write";
 477    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 478       return "tcs_set_input_urb_offsets";
 479    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 480       return "tcs_set_output_urb_offsets";
 481    case TCS_OPCODE_GET_PRIMITIVE_ID:
 482       return "tcs_get_primitive_id";
 483    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 484       return "tcs_create_barrier_header";
 485    case TCS_OPCODE_SRC0_010_IS_ZERO:
 486       return "tcs_src0<0,1,0>_is_zero";
 487    case TCS_OPCODE_RELEASE_INPUT:
 488       return "tcs_release_input";
 489    case TCS_OPCODE_THREAD_END:
 490       return "tcs_thread_end";
 491    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 492       return "tes_create_input_read_header";
 493    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 494       return "tes_add_indirect_urb_offset";
 495    case TES_OPCODE_GET_PRIMITIVE_ID:
 496       return "tes_get_primitive_id";
 497
 498    case SHADER_OPCODE_RND_MODE:
 499       return "rnd_mode";
 500    }
 501
 502    unreachable("not reached");
 503 }
 504
 505 bool
 506 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 507 {
 508    union {
 509       unsigned ud;
 510       int d;
 511       float f;
 512       double df;
 513    } imm, sat_imm = { 0 };
 514
 515    const unsigned size = type_sz(type);
 516
 517    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 518     * irrelevant, so just check the size of the type and copy from/to an
 519     * appropriately sized field.
 520     */
 521    if (size < 8)
 522       imm.ud = reg->ud;
 523    else
 524       imm.df = reg->df;
 525
 526    switch (type) {
 527    case BRW_REGISTER_TYPE_UD:
 528    case BRW_REGISTER_TYPE_D:
 529    case BRW_REGISTER_TYPE_UW:
 530    case BRW_REGISTER_TYPE_W:
 531    case BRW_REGISTER_TYPE_UQ:
 532    case BRW_REGISTER_TYPE_Q:
 533       /* Nothing to do. */
 534       return false;
 535    case BRW_REGISTER_TYPE_F:
 536       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 537       break;
 538    case BRW_REGISTER_TYPE_DF:
 539       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 540       break;
 541    case BRW_REGISTER_TYPE_UB:
 542    case BRW_REGISTER_TYPE_B:
 543       unreachable("no UB/B immediates");
 544    case BRW_REGISTER_TYPE_V:
 545    case BRW_REGISTER_TYPE_UV:
 546    case BRW_REGISTER_TYPE_VF:
 547       unreachable("unimplemented: saturate vector immediate");
 548    case BRW_REGISTER_TYPE_HF:
 549       unreachable("unimplemented: saturate HF immediate");
 550    case BRW_REGISTER_TYPE_NF:
 551       unreachable("no NF immediates");
 552    }
 553
 554    if (size < 8) {
 555       if (imm.ud != sat_imm.ud) {
 556          reg->ud = sat_imm.ud;
 557          return true;
 558       }
 559    } else {
 560       if (imm.df != sat_imm.df) {
 561          reg->df = sat_imm.df;
 562          return true;
 563       }
 564    }
 565    return false;
 566 }
 567
 568 bool
 569 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 570 {
 571    switch (type) {
 572    case BRW_REGISTER_TYPE_D:
 573    case BRW_REGISTER_TYPE_UD:
 574       reg->d = -reg->d;
 575       return true;
 576    case BRW_REGISTER_TYPE_W:
 577    case BRW_REGISTER_TYPE_UW:
 578       reg->d = -(int16_t)reg->ud;
 579       return true;
 580    case BRW_REGISTER_TYPE_F:
 581       reg->f = -reg->f;
 582       return true;
 583    case BRW_REGISTER_TYPE_VF:
 584       reg->ud ^= 0x80808080;
 585       return true;
 586    case BRW_REGISTER_TYPE_DF:
 587       reg->df = -reg->df;
 588       return true;
 589    case BRW_REGISTER_TYPE_UQ:
 590    case BRW_REGISTER_TYPE_Q:
 591       reg->d64 = -reg->d64;
 592       return true;
 593    case BRW_REGISTER_TYPE_UB:
 594    case BRW_REGISTER_TYPE_B:
 595       unreachable("no UB/B immediates");
 596    case BRW_REGISTER_TYPE_UV:
 597    case BRW_REGISTER_TYPE_V:
 598       assert(!"unimplemented: negate UV/V immediate");
 599    case BRW_REGISTER_TYPE_HF:
 600       assert(!"unimplemented: negate HF immediate");
 601    case BRW_REGISTER_TYPE_NF:
 602       unreachable("no NF immediates");
 603    }
 604
 605    return false;
 606 }
 607
 608 bool
 609 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 610 {
 611    switch (type) {
 612    case BRW_REGISTER_TYPE_D:
 613       reg->d = abs(reg->d);
 614       return true;
 615    case BRW_REGISTER_TYPE_W:
 616       reg->d = abs((int16_t)reg->ud);
 617       return true;
 618    case BRW_REGISTER_TYPE_F:
 619       reg->f = fabsf(reg->f);
 620       return true;
 621    case BRW_REGISTER_TYPE_DF:
 622       reg->df = fabs(reg->df);
 623       return true;
 624    case BRW_REGISTER_TYPE_VF:
 625       reg->ud &= ~0x80808080;
 626       return true;
 627    case BRW_REGISTER_TYPE_Q:
 628       reg->d64 = imaxabs(reg->d64);
 629       return true;
 630    case BRW_REGISTER_TYPE_UB:
 631    case BRW_REGISTER_TYPE_B:
 632       unreachable("no UB/B immediates");
 633    case BRW_REGISTER_TYPE_UQ:
 634    case BRW_REGISTER_TYPE_UD:
 635    case BRW_REGISTER_TYPE_UW:
 636    case BRW_REGISTER_TYPE_UV:
 637       /* Presumably the absolute value modifier on an unsigned source is a
 638        * nop, but it would be nice to confirm.
 639        */
 640       assert(!"unimplemented: abs unsigned immediate");
 641    case BRW_REGISTER_TYPE_V:
 642       assert(!"unimplemented: abs V immediate");
 643    case BRW_REGISTER_TYPE_HF:
 644       assert(!"unimplemented: abs HF immediate");
 645    case BRW_REGISTER_TYPE_NF:
 646       unreachable("no NF immediates");
 647    }
 648
 649    return false;
 650 }
 651
 652 backend_shader::backend_shader(const struct brw_compiler *compiler,
 653                                void *log_data,
 654                                void *mem_ctx,
 655                                const nir_shader *shader,
 656                                struct brw_stage_prog_data *stage_prog_data)
 657    : compiler(compiler),
 658      log_data(log_data),
 659      devinfo(compiler->devinfo),
 660      nir(shader),
 661      stage_prog_data(stage_prog_data),
 662      mem_ctx(mem_ctx),
 663      cfg(NULL),
 664      stage(shader->info.stage)
 665 {
 666    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 667    stage_name = _mesa_shader_stage_to_string(stage);
 668    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 669 }
 670
 671 backend_shader::~backend_shader()
 672 {
 673 }
 674
 675 bool
 676 backend_reg::equals(const backend_reg &r) const
 677 {
 678    return brw_regs_equal(this, &r) && offset == r.offset;
 679 }
 680
 681 bool
 682 backend_reg::is_zero() const
 683 {
 684    if (file != IMM)
 685       return false;
 686
 687    switch (type) {
 688    case BRW_REGISTER_TYPE_F:
 689       return f == 0;
 690    case BRW_REGISTER_TYPE_DF:
 691       return df == 0;
 692    case BRW_REGISTER_TYPE_D:
 693    case BRW_REGISTER_TYPE_UD:
 694       return d == 0;
 695    case BRW_REGISTER_TYPE_UQ:
 696    case BRW_REGISTER_TYPE_Q:
 697       return u64 == 0;
 698    default:
 699       return false;
 700    }
 701 }
 702
 703 bool
 704 backend_reg::is_one() const
 705 {
 706    if (file != IMM)
 707       return false;
 708
 709    switch (type) {
 710    case BRW_REGISTER_TYPE_F:
 711       return f == 1.0f;
 712    case BRW_REGISTER_TYPE_DF:
 713       return df == 1.0;
 714    case BRW_REGISTER_TYPE_D:
 715    case BRW_REGISTER_TYPE_UD:
 716       return d == 1;
 717    case BRW_REGISTER_TYPE_UQ:
 718    case BRW_REGISTER_TYPE_Q:
 719       return u64 == 1;
 720    default:
 721       return false;
 722    }
 723 }
 724
 725 bool
 726 backend_reg::is_negative_one() const
 727 {
 728    if (file != IMM)
 729       return false;
 730
 731    switch (type) {
 732    case BRW_REGISTER_TYPE_F:
 733       return f == -1.0;
 734    case BRW_REGISTER_TYPE_DF:
 735       return df == -1.0;
 736    case BRW_REGISTER_TYPE_D:
 737       return d == -1;
 738    case BRW_REGISTER_TYPE_Q:
 739       return d64 == -1;
 740    default:
 741       return false;
 742    }
 743 }
 744
 745 bool
 746 backend_reg::is_null() const
 747 {
 748    return file == ARF && nr == BRW_ARF_NULL;
 749 }
 750
 751
 752 bool
 753 backend_reg::is_accumulator() const
 754 {
 755    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 756 }
 757
 758 bool
 759 backend_instruction::is_commutative() const
 760 {
 761    switch (opcode) {
 762    case BRW_OPCODE_AND:
 763    case BRW_OPCODE_OR:
 764    case BRW_OPCODE_XOR:
 765    case BRW_OPCODE_ADD:
 766    case BRW_OPCODE_MUL:
 767    case SHADER_OPCODE_MULH:
 768       return true;
 769    case BRW_OPCODE_SEL:
 770       /* MIN and MAX are commutative. */
 771       if (conditional_mod == BRW_CONDITIONAL_GE ||
 772           conditional_mod == BRW_CONDITIONAL_L) {
 773          return true;
 774       }
 775       /* fallthrough */
 776    default:
 777       return false;
 778    }
 779 }
 780
 781 bool
 782 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 783 {
 784    return ::is_3src(devinfo, opcode);
 785 }
 786
 787 bool
 788 backend_instruction::is_tex() const
 789 {
 790    return (opcode == SHADER_OPCODE_TEX ||
 791            opcode == FS_OPCODE_TXB ||
 792            opcode == SHADER_OPCODE_TXD ||
 793            opcode == SHADER_OPCODE_TXF ||
 794            opcode == SHADER_OPCODE_TXF_LZ ||
 795            opcode == SHADER_OPCODE_TXF_CMS ||
 796            opcode == SHADER_OPCODE_TXF_CMS_W ||
 797            opcode == SHADER_OPCODE_TXF_UMS ||
 798            opcode == SHADER_OPCODE_TXF_MCS ||
 799            opcode == SHADER_OPCODE_TXL ||
 800            opcode == SHADER_OPCODE_TXL_LZ ||
 801            opcode == SHADER_OPCODE_TXS ||
 802            opcode == SHADER_OPCODE_LOD ||
 803            opcode == SHADER_OPCODE_TG4 ||
 804            opcode == SHADER_OPCODE_TG4_OFFSET ||
 805            opcode == SHADER_OPCODE_SAMPLEINFO);
 806 }
 807
 808 bool
 809 backend_instruction::is_math() const
 810 {
 811    return (opcode == SHADER_OPCODE_RCP ||
 812            opcode == SHADER_OPCODE_RSQ ||
 813            opcode == SHADER_OPCODE_SQRT ||
 814            opcode == SHADER_OPCODE_EXP2 ||
 815            opcode == SHADER_OPCODE_LOG2 ||
 816            opcode == SHADER_OPCODE_SIN ||
 817            opcode == SHADER_OPCODE_COS ||
 818            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 819            opcode == SHADER_OPCODE_INT_REMAINDER ||
 820            opcode == SHADER_OPCODE_POW);
 821 }
 822
 823 bool
 824 backend_instruction::is_control_flow() const
 825 {
 826    switch (opcode) {
 827    case BRW_OPCODE_DO:
 828    case BRW_OPCODE_WHILE:
 829    case BRW_OPCODE_IF:
 830    case BRW_OPCODE_ELSE:
 831    case BRW_OPCODE_ENDIF:
 832    case BRW_OPCODE_BREAK:
 833    case BRW_OPCODE_CONTINUE:
 834       return true;
 835    default:
 836       return false;
 837    }
 838 }
 839
 840 bool
 841 backend_instruction::can_do_source_mods() const
 842 {
 843    switch (opcode) {
 844    case BRW_OPCODE_ADDC:
 845    case BRW_OPCODE_BFE:
 846    case BRW_OPCODE_BFI1:
 847    case BRW_OPCODE_BFI2:
 848    case BRW_OPCODE_BFREV:
 849    case BRW_OPCODE_CBIT:
 850    case BRW_OPCODE_FBH:
 851    case BRW_OPCODE_FBL:
 852    case BRW_OPCODE_SUBB:
 853    case SHADER_OPCODE_BROADCAST:
 854    case SHADER_OPCODE_CLUSTER_BROADCAST:
 855    case SHADER_OPCODE_MOV_INDIRECT:
 856       return false;
 857    default:
 858       return true;
 859    }
 860 }
 861
 862 bool
 863 backend_instruction::can_do_saturate() const
 864 {
 865    switch (opcode) {
 866    case BRW_OPCODE_ADD:
 867    case BRW_OPCODE_ASR:
 868    case BRW_OPCODE_AVG:
 869    case BRW_OPCODE_DP2:
 870    case BRW_OPCODE_DP3:
 871    case BRW_OPCODE_DP4:
 872    case BRW_OPCODE_DPH:
 873    case BRW_OPCODE_F16TO32:
 874    case BRW_OPCODE_F32TO16:
 875    case BRW_OPCODE_LINE:
 876    case BRW_OPCODE_LRP:
 877    case BRW_OPCODE_MAC:
 878    case BRW_OPCODE_MAD:
 879    case BRW_OPCODE_MATH:
 880    case BRW_OPCODE_MOV:
 881    case BRW_OPCODE_MUL:
 882    case SHADER_OPCODE_MULH:
 883    case BRW_OPCODE_PLN:
 884    case BRW_OPCODE_RNDD:
 885    case BRW_OPCODE_RNDE:
 886    case BRW_OPCODE_RNDU:
 887    case BRW_OPCODE_RNDZ:
 888    case BRW_OPCODE_SEL:
 889    case BRW_OPCODE_SHL:
 890    case BRW_OPCODE_SHR:
 891    case FS_OPCODE_LINTERP:
 892    case SHADER_OPCODE_COS:
 893    case SHADER_OPCODE_EXP2:
 894    case SHADER_OPCODE_LOG2:
 895    case SHADER_OPCODE_POW:
 896    case SHADER_OPCODE_RCP:
 897    case SHADER_OPCODE_RSQ:
 898    case SHADER_OPCODE_SIN:
 899    case SHADER_OPCODE_SQRT:
 900       return true;
 901    default:
 902       return false;
 903    }
 904 }
 905
 906 bool
 907 backend_instruction::can_do_cmod() const
 908 {
 909    switch (opcode) {
 910    case BRW_OPCODE_ADD:
 911    case BRW_OPCODE_ADDC:
 912    case BRW_OPCODE_AND:
 913    case BRW_OPCODE_ASR:
 914    case BRW_OPCODE_AVG:
 915    case BRW_OPCODE_CMP:
 916    case BRW_OPCODE_CMPN:
 917    case BRW_OPCODE_DP2:
 918    case BRW_OPCODE_DP3:
 919    case BRW_OPCODE_DP4:
 920    case BRW_OPCODE_DPH:
 921    case BRW_OPCODE_F16TO32:
 922    case BRW_OPCODE_F32TO16:
 923    case BRW_OPCODE_FRC:
 924    case BRW_OPCODE_LINE:
 925    case BRW_OPCODE_LRP:
 926    case BRW_OPCODE_LZD:
 927    case BRW_OPCODE_MAC:
 928    case BRW_OPCODE_MACH:
 929    case BRW_OPCODE_MAD:
 930    case BRW_OPCODE_MOV:
 931    case BRW_OPCODE_MUL:
 932    case BRW_OPCODE_NOT:
 933    case BRW_OPCODE_OR:
 934    case BRW_OPCODE_PLN:
 935    case BRW_OPCODE_RNDD:
 936    case BRW_OPCODE_RNDE:
 937    case BRW_OPCODE_RNDU:
 938    case BRW_OPCODE_RNDZ:
 939    case BRW_OPCODE_SAD2:
 940    case BRW_OPCODE_SADA2:
 941    case BRW_OPCODE_SHL:
 942    case BRW_OPCODE_SHR:
 943    case BRW_OPCODE_SUBB:
 944    case BRW_OPCODE_XOR:
 945    case FS_OPCODE_CINTERP:
 946    case FS_OPCODE_LINTERP:
 947       return true;
 948    default:
 949       return false;
 950    }
 951 }
 952
 953 bool
 954 backend_instruction::reads_accumulator_implicitly() const
 955 {
 956    switch (opcode) {
 957    case BRW_OPCODE_MAC:
 958    case BRW_OPCODE_MACH:
 959    case BRW_OPCODE_SADA2:
 960       return true;
 961    default:
 962       return false;
 963    }
 964 }
 965
 966 bool
 967 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 968 {
 969    return writes_accumulator ||
 970           (devinfo->gen < 6 &&
 971            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 972             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 973              opcode != FS_OPCODE_CINTERP)));
 974 }
 975
 976 bool
 977 backend_instruction::has_side_effects() const
 978 {
 979    switch (opcode) {
 980    case SHADER_OPCODE_UNTYPED_ATOMIC:
 981    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 982    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 983    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 984    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 985    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
 986    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 987    case SHADER_OPCODE_TYPED_ATOMIC:
 988    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 989    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 990    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 991    case SHADER_OPCODE_MEMORY_FENCE:
 992    case SHADER_OPCODE_URB_WRITE_SIMD8:
 993    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 994    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 995    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 996    case FS_OPCODE_FB_WRITE:
 997    case FS_OPCODE_FB_WRITE_LOGICAL:
 998    case SHADER_OPCODE_BARRIER:
 999    case TCS_OPCODE_URB_WRITE:
1000    case TCS_OPCODE_RELEASE_INPUT:
1001    case SHADER_OPCODE_RND_MODE:
1002       return true;
1003    default:
1004       return eot;
1005    }
1006 }
1007
1008 bool
1009 backend_instruction::is_volatile() const
1010 {
1011    switch (opcode) {
1012    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1013    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1014    case SHADER_OPCODE_TYPED_SURFACE_READ:
1015    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1016    case SHADER_OPCODE_BYTE_SCATTERED_READ:
1017    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1018    case SHADER_OPCODE_URB_READ_SIMD8:
1019    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1020    case VEC4_OPCODE_URB_READ:
1021       return true;
1022    default:
1023       return false;
1024    }
1025 }
1026
1027 #ifndef NDEBUG
1028 static bool
1029 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1030 {
1031    bool found = false;
1032    foreach_inst_in_block (backend_instruction, i, block) {
1033       if (inst == i) {
1034          found = true;
1035       }
1036    }
1037    return found;
1038 }
1039 #endif
1040
1041 static void
1042 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1043 {
1044    for (bblock_t *block_iter = start_block->next();
1045         block_iter;
1046         block_iter = block_iter->next()) {
1047       block_iter->start_ip += ip_adjustment;
1048       block_iter->end_ip += ip_adjustment;
1049    }
1050 }
1051
1052 void
1053 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1054 {
1055    assert(this != inst);
1056
1057    if (!this->is_head_sentinel())
1058       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1059
1060    block->end_ip++;
1061
1062    adjust_later_block_ips(block, 1);
1063
1064    exec_node::insert_after(inst);
1065 }
1066
1067 void
1068 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1069 {
1070    assert(this != inst);
1071
1072    if (!this->is_tail_sentinel())
1073       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1074
1075    block->end_ip++;
1076
1077    adjust_later_block_ips(block, 1);
1078
1079    exec_node::insert_before(inst);
1080 }
1081
1082 void
1083 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1084 {
1085    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1086
1087    unsigned num_inst = list->length();
1088
1089    block->end_ip += num_inst;
1090
1091    adjust_later_block_ips(block, num_inst);
1092
1093    exec_node::insert_before(list);
1094 }
1095
1096 void
1097 backend_instruction::remove(bblock_t *block)
1098 {
1099    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1100
1101    adjust_later_block_ips(block, -1);
1102
1103    if (block->start_ip == block->end_ip) {
1104       block->cfg->remove_block(block);
1105    } else {
1106       block->end_ip--;
1107    }
1108
1109    exec_node::remove();
1110 }
1111
1112 void
1113 backend_shader::dump_instructions()
1114 {
1115    dump_instructions(NULL);
1116 }
1117
1118 void
1119 backend_shader::dump_instructions(const char *name)
1120 {
1121    FILE *file = stderr;
1122    if (name && geteuid() != 0) {
1123       file = fopen(name, "w");
1124       if (!file)
1125          file = stderr;
1126    }
1127
1128    if (cfg) {
1129       int ip = 0;
1130       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1131          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1132             fprintf(file, "%4d: ", ip++);
1133          dump_instruction(inst, file);
1134       }
1135    } else {
1136       int ip = 0;
1137       foreach_in_list(backend_instruction, inst, &instructions) {
1138          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1139             fprintf(file, "%4d: ", ip++);
1140          dump_instruction(inst, file);
1141       }
1142    }
1143
1144    if (file != stderr) {
1145       fclose(file);
1146    }
1147 }
1148
1149 void
1150 backend_shader::calculate_cfg()
1151 {
1152    if (this->cfg)
1153       return;
1154    cfg = new(mem_ctx) cfg_t(&this->instructions);
1155 }
1156
1157 extern "C" const unsigned *
1158 brw_compile_tes(const struct brw_compiler *compiler,
1159                 void *log_data,
1160                 void *mem_ctx,
1161                 const struct brw_tes_prog_key *key,
1162                 const struct brw_vue_map *input_vue_map,
1163                 struct brw_tes_prog_data *prog_data,
1164                 const nir_shader *src_shader,
1165                 struct gl_program *prog,
1166                 int shader_time_index,
1167                 char **error_str)
1168 {
1169    const struct gen_device_info *devinfo = compiler->devinfo;
1170    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1171    const unsigned *assembly;
1172
1173    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1174    nir->info.inputs_read = key->inputs_read;
1175    nir->info.patch_inputs_read = key->patch_inputs_read;
1176
1177    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1178    brw_nir_lower_tes_inputs(nir, input_vue_map);
1179    brw_nir_lower_vue_outputs(nir, is_scalar);
1180    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1181
1182    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1183                        nir->info.outputs_written,
1184                        nir->info.separate_shader);
1185
1186    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1187
1188    assert(output_size_bytes >= 1);
1189    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1190       if (error_str)
1191          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1192       return NULL;
1193    }
1194
1195    prog_data->base.clip_distance_mask =
1196       ((1 << nir->info.clip_distance_array_size) - 1);
1197    prog_data->base.cull_distance_mask =
1198       ((1 << nir->info.cull_distance_array_size) - 1) <<
1199       nir->info.clip_distance_array_size;
1200
1201    /* URB entry sizes are stored as a multiple of 64 bytes. */
1202    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1203
1204    /* On Cannonlake software shall not program an allocation size that
1205     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1206     */
1207    if (devinfo->gen == 10 &&
1208        prog_data->base.urb_entry_size % 3 == 0)
1209       prog_data->base.urb_entry_size++;
1210
1211    prog_data->base.urb_read_length = 0;
1212
1213    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1214    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1215                  TESS_SPACING_FRACTIONAL_ODD - 1);
1216    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1217                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1218
1219    prog_data->partitioning =
1220       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1221
1222    switch (nir->info.tess.primitive_mode) {
1223    case GL_QUADS:
1224       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1225       break;
1226    case GL_TRIANGLES:
1227       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1228       break;
1229    case GL_ISOLINES:
1230       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1231       break;
1232    default:
1233       unreachable("invalid domain shader primitive mode");
1234    }
1235
1236    if (nir->info.tess.point_mode) {
1237       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1238    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1239       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1240    } else {
1241       /* Hardware winding order is backwards from OpenGL */
1242       prog_data->output_topology =
1243          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1244                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1245    }
1246
1247    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1248       fprintf(stderr, "TES Input ");
1249       brw_print_vue_map(stderr, input_vue_map);
1250       fprintf(stderr, "TES Output ");
1251       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1252    }
1253
1254    if (is_scalar) {
1255       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1256                    &prog_data->base.base, NULL, nir, 8,
1257                    shader_time_index, input_vue_map);
1258       if (!v.run_tes()) {
1259          if (error_str)
1260             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1261          return NULL;
1262       }
1263
1264       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1265       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1266
1267       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1268                      &prog_data->base.base, v.promoted_constants, false,
1269                      MESA_SHADER_TESS_EVAL);
1270       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1271          g.enable_debug(ralloc_asprintf(mem_ctx,
1272                                         "%s tessellation evaluation shader %s",
1273                                         nir->info.label ? nir->info.label
1274                                                         : "unnamed",
1275                                         nir->info.name));
1276       }
1277
1278       g.generate_code(v.cfg, 8);
1279
1280       assembly = g.get_assembly();
1281    } else {
1282       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1283                               nir, mem_ctx, shader_time_index);
1284       if (!v.run()) {
1285          if (error_str)
1286             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1287          return NULL;
1288       }
1289
1290       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1291          v.dump_instructions();
1292
1293       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1294                                             &prog_data->base, v.cfg);
1295    }
1296
1297    return assembly;
1298 }