2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_vec4_tes.h"
29 #include "common/gen_debug.h"
30 #include "main/uniforms.h"
31 #include "util/macros.h"
34 brw_type_for_base_type(const struct glsl_type
*type
)
36 switch (type
->base_type
) {
37 case GLSL_TYPE_FLOAT16
:
38 return BRW_REGISTER_TYPE_HF
;
40 return BRW_REGISTER_TYPE_F
;
43 case GLSL_TYPE_SUBROUTINE
:
44 return BRW_REGISTER_TYPE_D
;
46 return BRW_REGISTER_TYPE_W
;
48 return BRW_REGISTER_TYPE_B
;
50 return BRW_REGISTER_TYPE_UD
;
51 case GLSL_TYPE_UINT16
:
52 return BRW_REGISTER_TYPE_UW
;
54 return BRW_REGISTER_TYPE_UB
;
56 return brw_type_for_base_type(type
->fields
.array
);
57 case GLSL_TYPE_STRUCT
:
58 case GLSL_TYPE_SAMPLER
:
59 case GLSL_TYPE_ATOMIC_UINT
:
60 /* These should be overridden with the type of the member when
61 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
62 * way to trip up if we don't.
64 return BRW_REGISTER_TYPE_UD
;
66 return BRW_REGISTER_TYPE_UD
;
67 case GLSL_TYPE_DOUBLE
:
68 return BRW_REGISTER_TYPE_DF
;
69 case GLSL_TYPE_UINT64
:
70 return BRW_REGISTER_TYPE_UQ
;
72 return BRW_REGISTER_TYPE_Q
;
75 case GLSL_TYPE_INTERFACE
:
76 case GLSL_TYPE_FUNCTION
:
77 unreachable("not reached");
80 return BRW_REGISTER_TYPE_F
;
83 enum brw_conditional_mod
84 brw_conditional_for_comparison(unsigned int op
)
88 return BRW_CONDITIONAL_L
;
90 return BRW_CONDITIONAL_GE
;
92 case ir_binop_all_equal
: /* same as equal for scalars */
93 return BRW_CONDITIONAL_Z
;
95 case ir_binop_any_nequal
: /* same as nequal for scalars */
96 return BRW_CONDITIONAL_NZ
;
98 unreachable("not reached: bad operation for comparison");
103 brw_math_function(enum opcode op
)
106 case SHADER_OPCODE_RCP
:
107 return BRW_MATH_FUNCTION_INV
;
108 case SHADER_OPCODE_RSQ
:
109 return BRW_MATH_FUNCTION_RSQ
;
110 case SHADER_OPCODE_SQRT
:
111 return BRW_MATH_FUNCTION_SQRT
;
112 case SHADER_OPCODE_EXP2
:
113 return BRW_MATH_FUNCTION_EXP
;
114 case SHADER_OPCODE_LOG2
:
115 return BRW_MATH_FUNCTION_LOG
;
116 case SHADER_OPCODE_POW
:
117 return BRW_MATH_FUNCTION_POW
;
118 case SHADER_OPCODE_SIN
:
119 return BRW_MATH_FUNCTION_SIN
;
120 case SHADER_OPCODE_COS
:
121 return BRW_MATH_FUNCTION_COS
;
122 case SHADER_OPCODE_INT_QUOTIENT
:
123 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
124 case SHADER_OPCODE_INT_REMAINDER
:
125 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
127 unreachable("not reached: unknown math function");
132 brw_texture_offset(int *offsets
, unsigned num_components
, uint32_t *offset_bits
)
134 if (!offsets
) return false; /* nonconstant offset; caller will handle it. */
136 /* offset out of bounds; caller will handle it. */
137 for (unsigned i
= 0; i
< num_components
; i
++)
138 if (offsets
[i
] > 7 || offsets
[i
] < -8)
141 /* Combine all three offsets into a single unsigned dword:
143 * bits 11:8 - U Offset (X component)
144 * bits 7:4 - V Offset (Y component)
145 * bits 3:0 - R Offset (Z component)
148 for (unsigned i
= 0; i
< num_components
; i
++) {
149 const unsigned shift
= 4 * (2 - i
);
150 *offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
156 brw_instruction_name(const struct gen_device_info
*devinfo
, enum opcode op
)
159 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
160 /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
161 * start of a loop in the IR.
163 if (devinfo
->gen
>= 6 && op
== BRW_OPCODE_DO
)
166 /* The following conversion opcodes doesn't exist on Gen8+, but we use
167 * then to mark that we want to do the conversion.
169 if (devinfo
->gen
> 7 && op
== BRW_OPCODE_F32TO16
)
172 if (devinfo
->gen
> 7 && op
== BRW_OPCODE_F16TO32
)
175 assert(brw_opcode_desc(devinfo
, op
)->name
);
176 return brw_opcode_desc(devinfo
, op
)->name
;
177 case FS_OPCODE_FB_WRITE
:
179 case FS_OPCODE_FB_WRITE_LOGICAL
:
180 return "fb_write_logical";
181 case FS_OPCODE_REP_FB_WRITE
:
182 return "rep_fb_write";
183 case FS_OPCODE_FB_READ
:
185 case FS_OPCODE_FB_READ_LOGICAL
:
186 return "fb_read_logical";
188 case SHADER_OPCODE_RCP
:
190 case SHADER_OPCODE_RSQ
:
192 case SHADER_OPCODE_SQRT
:
194 case SHADER_OPCODE_EXP2
:
196 case SHADER_OPCODE_LOG2
:
198 case SHADER_OPCODE_POW
:
200 case SHADER_OPCODE_INT_QUOTIENT
:
202 case SHADER_OPCODE_INT_REMAINDER
:
204 case SHADER_OPCODE_SIN
:
206 case SHADER_OPCODE_COS
:
209 case SHADER_OPCODE_TEX
:
211 case SHADER_OPCODE_TEX_LOGICAL
:
212 return "tex_logical";
213 case SHADER_OPCODE_TXD
:
215 case SHADER_OPCODE_TXD_LOGICAL
:
216 return "txd_logical";
217 case SHADER_OPCODE_TXF
:
219 case SHADER_OPCODE_TXF_LOGICAL
:
220 return "txf_logical";
221 case SHADER_OPCODE_TXF_LZ
:
223 case SHADER_OPCODE_TXL
:
225 case SHADER_OPCODE_TXL_LOGICAL
:
226 return "txl_logical";
227 case SHADER_OPCODE_TXL_LZ
:
229 case SHADER_OPCODE_TXS
:
231 case SHADER_OPCODE_TXS_LOGICAL
:
232 return "txs_logical";
235 case FS_OPCODE_TXB_LOGICAL
:
236 return "txb_logical";
237 case SHADER_OPCODE_TXF_CMS
:
239 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
240 return "txf_cms_logical";
241 case SHADER_OPCODE_TXF_CMS_W
:
243 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
244 return "txf_cms_w_logical";
245 case SHADER_OPCODE_TXF_UMS
:
247 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
248 return "txf_ums_logical";
249 case SHADER_OPCODE_TXF_MCS
:
251 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
252 return "txf_mcs_logical";
253 case SHADER_OPCODE_LOD
:
255 case SHADER_OPCODE_LOD_LOGICAL
:
256 return "lod_logical";
257 case SHADER_OPCODE_TG4
:
259 case SHADER_OPCODE_TG4_LOGICAL
:
260 return "tg4_logical";
261 case SHADER_OPCODE_TG4_OFFSET
:
263 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
264 return "tg4_offset_logical";
265 case SHADER_OPCODE_SAMPLEINFO
:
267 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
268 return "sampleinfo_logical";
270 case SHADER_OPCODE_SHADER_TIME_ADD
:
271 return "shader_time_add";
273 case SHADER_OPCODE_UNTYPED_ATOMIC
:
274 return "untyped_atomic";
275 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
276 return "untyped_atomic_logical";
277 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
278 return "untyped_surface_read";
279 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
280 return "untyped_surface_read_logical";
281 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
282 return "untyped_surface_write";
283 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
284 return "untyped_surface_write_logical";
285 case SHADER_OPCODE_TYPED_ATOMIC
:
286 return "typed_atomic";
287 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
288 return "typed_atomic_logical";
289 case SHADER_OPCODE_TYPED_SURFACE_READ
:
290 return "typed_surface_read";
291 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
292 return "typed_surface_read_logical";
293 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
294 return "typed_surface_write";
295 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
296 return "typed_surface_write_logical";
297 case SHADER_OPCODE_MEMORY_FENCE
:
298 return "memory_fence";
299 case SHADER_OPCODE_INTERLOCK
:
300 /* For an interlock we actually issue a memory fence via sendc. */
303 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
304 return "byte_scattered_read";
305 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
306 return "byte_scattered_read_logical";
307 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
308 return "byte_scattered_write";
309 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
310 return "byte_scattered_write_logical";
312 case SHADER_OPCODE_LOAD_PAYLOAD
:
313 return "load_payload";
317 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
318 return "gen4_scratch_read";
319 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
320 return "gen4_scratch_write";
321 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
322 return "gen7_scratch_read";
323 case SHADER_OPCODE_URB_WRITE_SIMD8
:
324 return "gen8_urb_write_simd8";
325 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
326 return "gen8_urb_write_simd8_per_slot";
327 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
328 return "gen8_urb_write_simd8_masked";
329 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
330 return "gen8_urb_write_simd8_masked_per_slot";
331 case SHADER_OPCODE_URB_READ_SIMD8
:
332 return "urb_read_simd8";
333 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
334 return "urb_read_simd8_per_slot";
336 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
337 return "find_live_channel";
338 case SHADER_OPCODE_BROADCAST
:
340 case SHADER_OPCODE_SHUFFLE
:
342 case SHADER_OPCODE_SEL_EXEC
:
344 case SHADER_OPCODE_QUAD_SWIZZLE
:
345 return "quad_swizzle";
346 case SHADER_OPCODE_CLUSTER_BROADCAST
:
347 return "cluster_broadcast";
349 case SHADER_OPCODE_GET_BUFFER_SIZE
:
350 return "get_buffer_size";
352 case VEC4_OPCODE_MOV_BYTES
:
354 case VEC4_OPCODE_PACK_BYTES
:
356 case VEC4_OPCODE_UNPACK_UNIFORM
:
357 return "unpack_uniform";
358 case VEC4_OPCODE_DOUBLE_TO_F32
:
359 return "double_to_f32";
360 case VEC4_OPCODE_DOUBLE_TO_D32
:
361 return "double_to_d32";
362 case VEC4_OPCODE_DOUBLE_TO_U32
:
363 return "double_to_u32";
364 case VEC4_OPCODE_TO_DOUBLE
:
365 return "single_to_double";
366 case VEC4_OPCODE_PICK_LOW_32BIT
:
367 return "pick_low_32bit";
368 case VEC4_OPCODE_PICK_HIGH_32BIT
:
369 return "pick_high_32bit";
370 case VEC4_OPCODE_SET_LOW_32BIT
:
371 return "set_low_32bit";
372 case VEC4_OPCODE_SET_HIGH_32BIT
:
373 return "set_high_32bit";
375 case FS_OPCODE_DDX_COARSE
:
377 case FS_OPCODE_DDX_FINE
:
379 case FS_OPCODE_DDY_COARSE
:
381 case FS_OPCODE_DDY_FINE
:
384 case FS_OPCODE_LINTERP
:
387 case FS_OPCODE_PIXEL_X
:
389 case FS_OPCODE_PIXEL_Y
:
392 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
393 return "uniform_pull_const";
394 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
395 return "uniform_pull_const_gen7";
396 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
397 return "varying_pull_const_gen4";
398 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
399 return "varying_pull_const_gen7";
400 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
401 return "varying_pull_const_logical";
403 case FS_OPCODE_DISCARD_JUMP
:
404 return "discard_jump";
406 case FS_OPCODE_SET_SAMPLE_ID
:
407 return "set_sample_id";
409 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
410 return "pack_half_2x16_split";
411 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
412 return "unpack_half_2x16_split_x";
413 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
414 return "unpack_half_2x16_split_y";
416 case FS_OPCODE_PLACEHOLDER_HALT
:
417 return "placeholder_halt";
419 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
420 return "interp_sample";
421 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
422 return "interp_shared_offset";
423 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
424 return "interp_per_slot_offset";
426 case VS_OPCODE_URB_WRITE
:
427 return "vs_urb_write";
428 case VS_OPCODE_PULL_CONSTANT_LOAD
:
429 return "pull_constant_load";
430 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
431 return "pull_constant_load_gen7";
433 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
434 return "set_simd4x2_header_gen9";
436 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
437 return "unpack_flags_simd4x2";
439 case GS_OPCODE_URB_WRITE
:
440 return "gs_urb_write";
441 case GS_OPCODE_URB_WRITE_ALLOCATE
:
442 return "gs_urb_write_allocate";
443 case GS_OPCODE_THREAD_END
:
444 return "gs_thread_end";
445 case GS_OPCODE_SET_WRITE_OFFSET
:
446 return "set_write_offset";
447 case GS_OPCODE_SET_VERTEX_COUNT
:
448 return "set_vertex_count";
449 case GS_OPCODE_SET_DWORD_2
:
450 return "set_dword_2";
451 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
452 return "prepare_channel_masks";
453 case GS_OPCODE_SET_CHANNEL_MASKS
:
454 return "set_channel_masks";
455 case GS_OPCODE_GET_INSTANCE_ID
:
456 return "get_instance_id";
457 case GS_OPCODE_FF_SYNC
:
459 case GS_OPCODE_SET_PRIMITIVE_ID
:
460 return "set_primitive_id";
461 case GS_OPCODE_SVB_WRITE
:
462 return "gs_svb_write";
463 case GS_OPCODE_SVB_SET_DST_INDEX
:
464 return "gs_svb_set_dst_index";
465 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
466 return "gs_ff_sync_set_primitives";
467 case CS_OPCODE_CS_TERMINATE
:
468 return "cs_terminate";
469 case SHADER_OPCODE_BARRIER
:
471 case SHADER_OPCODE_MULH
:
473 case SHADER_OPCODE_MOV_INDIRECT
:
474 return "mov_indirect";
476 case VEC4_OPCODE_URB_READ
:
478 case TCS_OPCODE_GET_INSTANCE_ID
:
479 return "tcs_get_instance_id";
480 case TCS_OPCODE_URB_WRITE
:
481 return "tcs_urb_write";
482 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
483 return "tcs_set_input_urb_offsets";
484 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
485 return "tcs_set_output_urb_offsets";
486 case TCS_OPCODE_GET_PRIMITIVE_ID
:
487 return "tcs_get_primitive_id";
488 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
489 return "tcs_create_barrier_header";
490 case TCS_OPCODE_SRC0_010_IS_ZERO
:
491 return "tcs_src0<0,1,0>_is_zero";
492 case TCS_OPCODE_RELEASE_INPUT
:
493 return "tcs_release_input";
494 case TCS_OPCODE_THREAD_END
:
495 return "tcs_thread_end";
496 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
497 return "tes_create_input_read_header";
498 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
499 return "tes_add_indirect_urb_offset";
500 case TES_OPCODE_GET_PRIMITIVE_ID
:
501 return "tes_get_primitive_id";
503 case SHADER_OPCODE_RND_MODE
:
507 unreachable("not reached");
511 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
518 } imm
, sat_imm
= { 0 };
520 const unsigned size
= type_sz(type
);
522 /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
523 * irrelevant, so just check the size of the type and copy from/to an
524 * appropriately sized field.
532 case BRW_REGISTER_TYPE_UD
:
533 case BRW_REGISTER_TYPE_D
:
534 case BRW_REGISTER_TYPE_UW
:
535 case BRW_REGISTER_TYPE_W
:
536 case BRW_REGISTER_TYPE_UQ
:
537 case BRW_REGISTER_TYPE_Q
:
540 case BRW_REGISTER_TYPE_F
:
541 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
543 case BRW_REGISTER_TYPE_DF
:
544 sat_imm
.df
= CLAMP(imm
.df
, 0.0, 1.0);
546 case BRW_REGISTER_TYPE_UB
:
547 case BRW_REGISTER_TYPE_B
:
548 unreachable("no UB/B immediates");
549 case BRW_REGISTER_TYPE_V
:
550 case BRW_REGISTER_TYPE_UV
:
551 case BRW_REGISTER_TYPE_VF
:
552 unreachable("unimplemented: saturate vector immediate");
553 case BRW_REGISTER_TYPE_HF
:
554 unreachable("unimplemented: saturate HF immediate");
555 case BRW_REGISTER_TYPE_NF
:
556 unreachable("no NF immediates");
560 if (imm
.ud
!= sat_imm
.ud
) {
561 reg
->ud
= sat_imm
.ud
;
565 if (imm
.df
!= sat_imm
.df
) {
566 reg
->df
= sat_imm
.df
;
574 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
577 case BRW_REGISTER_TYPE_D
:
578 case BRW_REGISTER_TYPE_UD
:
581 case BRW_REGISTER_TYPE_W
:
582 case BRW_REGISTER_TYPE_UW
: {
583 uint16_t value
= -(int16_t)reg
->ud
;
584 reg
->ud
= value
| (uint32_t)value
<< 16;
587 case BRW_REGISTER_TYPE_F
:
590 case BRW_REGISTER_TYPE_VF
:
591 reg
->ud
^= 0x80808080;
593 case BRW_REGISTER_TYPE_DF
:
596 case BRW_REGISTER_TYPE_UQ
:
597 case BRW_REGISTER_TYPE_Q
:
598 reg
->d64
= -reg
->d64
;
600 case BRW_REGISTER_TYPE_UB
:
601 case BRW_REGISTER_TYPE_B
:
602 unreachable("no UB/B immediates");
603 case BRW_REGISTER_TYPE_UV
:
604 case BRW_REGISTER_TYPE_V
:
605 assert(!"unimplemented: negate UV/V immediate");
606 case BRW_REGISTER_TYPE_HF
:
607 reg
->ud
^= 0x80008000;
609 case BRW_REGISTER_TYPE_NF
:
610 unreachable("no NF immediates");
617 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
620 case BRW_REGISTER_TYPE_D
:
621 reg
->d
= abs(reg
->d
);
623 case BRW_REGISTER_TYPE_W
: {
624 uint16_t value
= abs((int16_t)reg
->ud
);
625 reg
->ud
= value
| (uint32_t)value
<< 16;
628 case BRW_REGISTER_TYPE_F
:
629 reg
->f
= fabsf(reg
->f
);
631 case BRW_REGISTER_TYPE_DF
:
632 reg
->df
= fabs(reg
->df
);
634 case BRW_REGISTER_TYPE_VF
:
635 reg
->ud
&= ~0x80808080;
637 case BRW_REGISTER_TYPE_Q
:
638 reg
->d64
= imaxabs(reg
->d64
);
640 case BRW_REGISTER_TYPE_UB
:
641 case BRW_REGISTER_TYPE_B
:
642 unreachable("no UB/B immediates");
643 case BRW_REGISTER_TYPE_UQ
:
644 case BRW_REGISTER_TYPE_UD
:
645 case BRW_REGISTER_TYPE_UW
:
646 case BRW_REGISTER_TYPE_UV
:
647 /* Presumably the absolute value modifier on an unsigned source is a
648 * nop, but it would be nice to confirm.
650 assert(!"unimplemented: abs unsigned immediate");
651 case BRW_REGISTER_TYPE_V
:
652 assert(!"unimplemented: abs V immediate");
653 case BRW_REGISTER_TYPE_HF
:
654 reg
->ud
&= ~0x80008000;
656 case BRW_REGISTER_TYPE_NF
:
657 unreachable("no NF immediates");
663 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
666 const nir_shader
*shader
,
667 struct brw_stage_prog_data
*stage_prog_data
)
668 : compiler(compiler
),
670 devinfo(compiler
->devinfo
),
672 stage_prog_data(stage_prog_data
),
675 stage(shader
->info
.stage
)
677 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
678 stage_name
= _mesa_shader_stage_to_string(stage
);
679 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
682 backend_shader::~backend_shader()
687 backend_reg::equals(const backend_reg
&r
) const
689 return brw_regs_equal(this, &r
) && offset
== r
.offset
;
693 backend_reg::negative_equals(const backend_reg
&r
) const
695 return brw_regs_negative_equal(this, &r
) && offset
== r
.offset
;
699 backend_reg::is_zero() const
705 case BRW_REGISTER_TYPE_F
:
707 case BRW_REGISTER_TYPE_DF
:
709 case BRW_REGISTER_TYPE_D
:
710 case BRW_REGISTER_TYPE_UD
:
712 case BRW_REGISTER_TYPE_UQ
:
713 case BRW_REGISTER_TYPE_Q
:
721 backend_reg::is_one() const
727 case BRW_REGISTER_TYPE_F
:
729 case BRW_REGISTER_TYPE_DF
:
731 case BRW_REGISTER_TYPE_D
:
732 case BRW_REGISTER_TYPE_UD
:
734 case BRW_REGISTER_TYPE_UQ
:
735 case BRW_REGISTER_TYPE_Q
:
743 backend_reg::is_negative_one() const
749 case BRW_REGISTER_TYPE_F
:
751 case BRW_REGISTER_TYPE_DF
:
753 case BRW_REGISTER_TYPE_D
:
755 case BRW_REGISTER_TYPE_Q
:
763 backend_reg::is_null() const
765 return file
== ARF
&& nr
== BRW_ARF_NULL
;
770 backend_reg::is_accumulator() const
772 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
776 backend_instruction::is_commutative() const
784 case SHADER_OPCODE_MULH
:
787 /* MIN and MAX are commutative. */
788 if (conditional_mod
== BRW_CONDITIONAL_GE
||
789 conditional_mod
== BRW_CONDITIONAL_L
) {
799 backend_instruction::is_3src(const struct gen_device_info
*devinfo
) const
801 return ::is_3src(devinfo
, opcode
);
805 backend_instruction::is_tex() const
807 return (opcode
== SHADER_OPCODE_TEX
||
808 opcode
== FS_OPCODE_TXB
||
809 opcode
== SHADER_OPCODE_TXD
||
810 opcode
== SHADER_OPCODE_TXF
||
811 opcode
== SHADER_OPCODE_TXF_LZ
||
812 opcode
== SHADER_OPCODE_TXF_CMS
||
813 opcode
== SHADER_OPCODE_TXF_CMS_W
||
814 opcode
== SHADER_OPCODE_TXF_UMS
||
815 opcode
== SHADER_OPCODE_TXF_MCS
||
816 opcode
== SHADER_OPCODE_TXL
||
817 opcode
== SHADER_OPCODE_TXL_LZ
||
818 opcode
== SHADER_OPCODE_TXS
||
819 opcode
== SHADER_OPCODE_LOD
||
820 opcode
== SHADER_OPCODE_TG4
||
821 opcode
== SHADER_OPCODE_TG4_OFFSET
||
822 opcode
== SHADER_OPCODE_SAMPLEINFO
);
826 backend_instruction::is_math() const
828 return (opcode
== SHADER_OPCODE_RCP
||
829 opcode
== SHADER_OPCODE_RSQ
||
830 opcode
== SHADER_OPCODE_SQRT
||
831 opcode
== SHADER_OPCODE_EXP2
||
832 opcode
== SHADER_OPCODE_LOG2
||
833 opcode
== SHADER_OPCODE_SIN
||
834 opcode
== SHADER_OPCODE_COS
||
835 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
836 opcode
== SHADER_OPCODE_INT_REMAINDER
||
837 opcode
== SHADER_OPCODE_POW
);
841 backend_instruction::is_control_flow() const
845 case BRW_OPCODE_WHILE
:
847 case BRW_OPCODE_ELSE
:
848 case BRW_OPCODE_ENDIF
:
849 case BRW_OPCODE_BREAK
:
850 case BRW_OPCODE_CONTINUE
:
858 backend_instruction::can_do_source_mods() const
861 case BRW_OPCODE_ADDC
:
863 case BRW_OPCODE_BFI1
:
864 case BRW_OPCODE_BFI2
:
865 case BRW_OPCODE_BFREV
:
866 case BRW_OPCODE_CBIT
:
869 case BRW_OPCODE_SUBB
:
870 case SHADER_OPCODE_BROADCAST
:
871 case SHADER_OPCODE_CLUSTER_BROADCAST
:
872 case SHADER_OPCODE_MOV_INDIRECT
:
880 backend_instruction::can_do_saturate() const
890 case BRW_OPCODE_F16TO32
:
891 case BRW_OPCODE_F32TO16
:
892 case BRW_OPCODE_LINE
:
896 case BRW_OPCODE_MATH
:
899 case SHADER_OPCODE_MULH
:
901 case BRW_OPCODE_RNDD
:
902 case BRW_OPCODE_RNDE
:
903 case BRW_OPCODE_RNDU
:
904 case BRW_OPCODE_RNDZ
:
908 case FS_OPCODE_LINTERP
:
909 case SHADER_OPCODE_COS
:
910 case SHADER_OPCODE_EXP2
:
911 case SHADER_OPCODE_LOG2
:
912 case SHADER_OPCODE_POW
:
913 case SHADER_OPCODE_RCP
:
914 case SHADER_OPCODE_RSQ
:
915 case SHADER_OPCODE_SIN
:
916 case SHADER_OPCODE_SQRT
:
924 backend_instruction::can_do_cmod() const
928 case BRW_OPCODE_ADDC
:
933 case BRW_OPCODE_CMPN
:
938 case BRW_OPCODE_F16TO32
:
939 case BRW_OPCODE_F32TO16
:
941 case BRW_OPCODE_LINE
:
945 case BRW_OPCODE_MACH
:
952 case BRW_OPCODE_RNDD
:
953 case BRW_OPCODE_RNDE
:
954 case BRW_OPCODE_RNDU
:
955 case BRW_OPCODE_RNDZ
:
956 case BRW_OPCODE_SAD2
:
957 case BRW_OPCODE_SADA2
:
960 case BRW_OPCODE_SUBB
:
962 case FS_OPCODE_LINTERP
:
970 backend_instruction::reads_accumulator_implicitly() const
974 case BRW_OPCODE_MACH
:
975 case BRW_OPCODE_SADA2
:
983 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info
*devinfo
) const
985 return writes_accumulator
||
987 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
988 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
))) ||
989 (opcode
== FS_OPCODE_LINTERP
&&
990 (!devinfo
->has_pln
|| devinfo
->gen
<= 6));
994 backend_instruction::has_side_effects() const
997 case SHADER_OPCODE_UNTYPED_ATOMIC
:
998 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
999 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1000 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1001 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
1002 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
1003 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
1004 case SHADER_OPCODE_TYPED_ATOMIC
:
1005 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
1006 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1007 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
1008 case SHADER_OPCODE_MEMORY_FENCE
:
1009 case SHADER_OPCODE_INTERLOCK
:
1010 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1011 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
1012 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
1013 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
1014 case FS_OPCODE_FB_WRITE
:
1015 case FS_OPCODE_FB_WRITE_LOGICAL
:
1016 case FS_OPCODE_REP_FB_WRITE
:
1017 case SHADER_OPCODE_BARRIER
:
1018 case TCS_OPCODE_URB_WRITE
:
1019 case TCS_OPCODE_RELEASE_INPUT
:
1020 case SHADER_OPCODE_RND_MODE
:
1028 backend_instruction::is_volatile() const
1031 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1032 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
1033 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1034 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
1035 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
1036 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
1037 case SHADER_OPCODE_URB_READ_SIMD8
:
1038 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
1039 case VEC4_OPCODE_URB_READ
:
1048 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1051 foreach_inst_in_block (backend_instruction
, i
, block
) {
1061 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1063 for (bblock_t
*block_iter
= start_block
->next();
1065 block_iter
= block_iter
->next()) {
1066 block_iter
->start_ip
+= ip_adjustment
;
1067 block_iter
->end_ip
+= ip_adjustment
;
1072 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1074 assert(this != inst
);
1076 if (!this->is_head_sentinel())
1077 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1081 adjust_later_block_ips(block
, 1);
1083 exec_node::insert_after(inst
);
1087 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1089 assert(this != inst
);
1091 if (!this->is_tail_sentinel())
1092 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1096 adjust_later_block_ips(block
, 1);
1098 exec_node::insert_before(inst
);
1102 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1104 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1106 unsigned num_inst
= list
->length();
1108 block
->end_ip
+= num_inst
;
1110 adjust_later_block_ips(block
, num_inst
);
1112 exec_node::insert_before(list
);
1116 backend_instruction::remove(bblock_t
*block
)
1118 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1120 adjust_later_block_ips(block
, -1);
1122 if (block
->start_ip
== block
->end_ip
) {
1123 block
->cfg
->remove_block(block
);
1128 exec_node::remove();
1132 backend_shader::dump_instructions()
1134 dump_instructions(NULL
);
1138 backend_shader::dump_instructions(const char *name
)
1140 FILE *file
= stderr
;
1141 if (name
&& geteuid() != 0) {
1142 file
= fopen(name
, "w");
1149 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1150 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1151 fprintf(file
, "%4d: ", ip
++);
1152 dump_instruction(inst
, file
);
1156 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1157 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1158 fprintf(file
, "%4d: ", ip
++);
1159 dump_instruction(inst
, file
);
1163 if (file
!= stderr
) {
1169 backend_shader::calculate_cfg()
1173 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1176 extern "C" const unsigned *
1177 brw_compile_tes(const struct brw_compiler
*compiler
,
1180 const struct brw_tes_prog_key
*key
,
1181 const struct brw_vue_map
*input_vue_map
,
1182 struct brw_tes_prog_data
*prog_data
,
1183 const nir_shader
*src_shader
,
1184 struct gl_program
*prog
,
1185 int shader_time_index
,
1188 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
1189 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
];
1190 const unsigned *assembly
;
1192 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
1193 nir
->info
.inputs_read
= key
->inputs_read
;
1194 nir
->info
.patch_inputs_read
= key
->patch_inputs_read
;
1196 nir
= brw_nir_apply_sampler_key(nir
, compiler
, &key
->tex
, is_scalar
);
1197 brw_nir_lower_tes_inputs(nir
, input_vue_map
);
1198 brw_nir_lower_vue_outputs(nir
, is_scalar
);
1199 nir
= brw_postprocess_nir(nir
, compiler
, is_scalar
);
1201 brw_compute_vue_map(devinfo
, &prog_data
->base
.vue_map
,
1202 nir
->info
.outputs_written
,
1203 nir
->info
.separate_shader
);
1205 unsigned output_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 4 * 4;
1207 assert(output_size_bytes
>= 1);
1208 if (output_size_bytes
> GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES
) {
1210 *error_str
= ralloc_strdup(mem_ctx
, "DS outputs exceed maximum size");
1214 prog_data
->base
.clip_distance_mask
=
1215 ((1 << nir
->info
.clip_distance_array_size
) - 1);
1216 prog_data
->base
.cull_distance_mask
=
1217 ((1 << nir
->info
.cull_distance_array_size
) - 1) <<
1218 nir
->info
.clip_distance_array_size
;
1220 /* URB entry sizes are stored as a multiple of 64 bytes. */
1221 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
1223 /* On Cannonlake software shall not program an allocation size that
1224 * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1226 if (devinfo
->gen
== 10 &&
1227 prog_data
->base
.urb_entry_size
% 3 == 0)
1228 prog_data
->base
.urb_entry_size
++;
1230 prog_data
->base
.urb_read_length
= 0;
1232 STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER
== TESS_SPACING_EQUAL
- 1);
1233 STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL
==
1234 TESS_SPACING_FRACTIONAL_ODD
- 1);
1235 STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
==
1236 TESS_SPACING_FRACTIONAL_EVEN
- 1);
1238 prog_data
->partitioning
=
1239 (enum brw_tess_partitioning
) (nir
->info
.tess
.spacing
- 1);
1241 switch (nir
->info
.tess
.primitive_mode
) {
1243 prog_data
->domain
= BRW_TESS_DOMAIN_QUAD
;
1246 prog_data
->domain
= BRW_TESS_DOMAIN_TRI
;
1249 prog_data
->domain
= BRW_TESS_DOMAIN_ISOLINE
;
1252 unreachable("invalid domain shader primitive mode");
1255 if (nir
->info
.tess
.point_mode
) {
1256 prog_data
->output_topology
= BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1257 } else if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
) {
1258 prog_data
->output_topology
= BRW_TESS_OUTPUT_TOPOLOGY_LINE
;
1260 /* Hardware winding order is backwards from OpenGL */
1261 prog_data
->output_topology
=
1262 nir
->info
.tess
.ccw
? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1263 : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
;
1266 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1267 fprintf(stderr
, "TES Input ");
1268 brw_print_vue_map(stderr
, input_vue_map
);
1269 fprintf(stderr
, "TES Output ");
1270 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
1274 fs_visitor
v(compiler
, log_data
, mem_ctx
, (void *) key
,
1275 &prog_data
->base
.base
, NULL
, nir
, 8,
1276 shader_time_index
, input_vue_map
);
1279 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1283 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
1284 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1286 fs_generator
g(compiler
, log_data
, mem_ctx
,
1287 &prog_data
->base
.base
, v
.promoted_constants
, false,
1288 MESA_SHADER_TESS_EVAL
);
1289 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1290 g
.enable_debug(ralloc_asprintf(mem_ctx
,
1291 "%s tessellation evaluation shader %s",
1292 nir
->info
.label
? nir
->info
.label
1297 g
.generate_code(v
.cfg
, 8);
1299 assembly
= g
.get_assembly();
1301 brw::vec4_tes_visitor
v(compiler
, log_data
, key
, prog_data
,
1302 nir
, mem_ctx
, shader_time_index
);
1305 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1309 if (unlikely(INTEL_DEBUG
& DEBUG_TES
))
1310 v
.dump_instructions();
1312 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
1313 &prog_data
->base
, v
.cfg
);