src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "common/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_UINT:
  48       return BRW_REGISTER_TYPE_UD;
  49    case GLSL_TYPE_UINT16:
  50       return BRW_REGISTER_TYPE_UW;
  51    case GLSL_TYPE_ARRAY:
  52       return brw_type_for_base_type(type->fields.array);
  53    case GLSL_TYPE_STRUCT:
  54    case GLSL_TYPE_SAMPLER:
  55    case GLSL_TYPE_ATOMIC_UINT:
  56       /* These should be overridden with the type of the member when
  57        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  58        * way to trip up if we don't.
  59        */
  60       return BRW_REGISTER_TYPE_UD;
  61    case GLSL_TYPE_IMAGE:
  62       return BRW_REGISTER_TYPE_UD;
  63    case GLSL_TYPE_DOUBLE:
  64       return BRW_REGISTER_TYPE_DF;
  65    case GLSL_TYPE_UINT64:
  66       return BRW_REGISTER_TYPE_UQ;
  67    case GLSL_TYPE_INT64:
  68       return BRW_REGISTER_TYPE_Q;
  69    case GLSL_TYPE_VOID:
  70    case GLSL_TYPE_ERROR:
  71    case GLSL_TYPE_INTERFACE:
  72    case GLSL_TYPE_FUNCTION:
  73       unreachable("not reached");
  74    }
  75
  76    return BRW_REGISTER_TYPE_F;
  77 }
  78
  79 enum brw_conditional_mod
  80 brw_conditional_for_comparison(unsigned int op)
  81 {
  82    switch (op) {
  83    case ir_binop_less:
  84       return BRW_CONDITIONAL_L;
  85    case ir_binop_gequal:
  86       return BRW_CONDITIONAL_GE;
  87    case ir_binop_equal:
  88    case ir_binop_all_equal: /* same as equal for scalars */
  89       return BRW_CONDITIONAL_Z;
  90    case ir_binop_nequal:
  91    case ir_binop_any_nequal: /* same as nequal for scalars */
  92       return BRW_CONDITIONAL_NZ;
  93    default:
  94       unreachable("not reached: bad operation for comparison");
  95    }
  96 }
  97
  98 uint32_t
  99 brw_math_function(enum opcode op)
 100 {
 101    switch (op) {
 102    case SHADER_OPCODE_RCP:
 103       return BRW_MATH_FUNCTION_INV;
 104    case SHADER_OPCODE_RSQ:
 105       return BRW_MATH_FUNCTION_RSQ;
 106    case SHADER_OPCODE_SQRT:
 107       return BRW_MATH_FUNCTION_SQRT;
 108    case SHADER_OPCODE_EXP2:
 109       return BRW_MATH_FUNCTION_EXP;
 110    case SHADER_OPCODE_LOG2:
 111       return BRW_MATH_FUNCTION_LOG;
 112    case SHADER_OPCODE_POW:
 113       return BRW_MATH_FUNCTION_POW;
 114    case SHADER_OPCODE_SIN:
 115       return BRW_MATH_FUNCTION_SIN;
 116    case SHADER_OPCODE_COS:
 117       return BRW_MATH_FUNCTION_COS;
 118    case SHADER_OPCODE_INT_QUOTIENT:
 119       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 120    case SHADER_OPCODE_INT_REMAINDER:
 121       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 122    default:
 123       unreachable("not reached: unknown math function");
 124    }
 125 }
 126
 127 bool
 128 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 129 {
 130    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 131
 132    /* offset out of bounds; caller will handle it. */
 133    for (unsigned i = 0; i < num_components; i++)
 134       if (offsets[i] > 7 || offsets[i] < -8)
 135          return false;
 136
 137    /* Combine all three offsets into a single unsigned dword:
 138     *
 139     *    bits 11:8 - U Offset (X component)
 140     *    bits  7:4 - V Offset (Y component)
 141     *    bits  3:0 - R Offset (Z component)
 142     */
 143    *offset_bits = 0;
 144    for (unsigned i = 0; i < num_components; i++) {
 145       const unsigned shift = 4 * (2 - i);
 146       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 147    }
 148    return true;
 149 }
 150
 151 const char *
 152 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 153 {
 154    switch (op) {
 155    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 156       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 157        * start of a loop in the IR.
 158        */
 159       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 160          return "do";
 161
 162       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 163        * then to mark that we want to do the conversion.
 164        */
 165       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 166          return "f32to16";
 167
 168       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 169          return "f16to32";
 170
 171       assert(brw_opcode_desc(devinfo, op)->name);
 172       return brw_opcode_desc(devinfo, op)->name;
 173    case FS_OPCODE_FB_WRITE:
 174       return "fb_write";
 175    case FS_OPCODE_FB_WRITE_LOGICAL:
 176       return "fb_write_logical";
 177    case FS_OPCODE_REP_FB_WRITE:
 178       return "rep_fb_write";
 179    case FS_OPCODE_FB_READ:
 180       return "fb_read";
 181    case FS_OPCODE_FB_READ_LOGICAL:
 182       return "fb_read_logical";
 183
 184    case SHADER_OPCODE_RCP:
 185       return "rcp";
 186    case SHADER_OPCODE_RSQ:
 187       return "rsq";
 188    case SHADER_OPCODE_SQRT:
 189       return "sqrt";
 190    case SHADER_OPCODE_EXP2:
 191       return "exp2";
 192    case SHADER_OPCODE_LOG2:
 193       return "log2";
 194    case SHADER_OPCODE_POW:
 195       return "pow";
 196    case SHADER_OPCODE_INT_QUOTIENT:
 197       return "int_quot";
 198    case SHADER_OPCODE_INT_REMAINDER:
 199       return "int_rem";
 200    case SHADER_OPCODE_SIN:
 201       return "sin";
 202    case SHADER_OPCODE_COS:
 203       return "cos";
 204
 205    case SHADER_OPCODE_TEX:
 206       return "tex";
 207    case SHADER_OPCODE_TEX_LOGICAL:
 208       return "tex_logical";
 209    case SHADER_OPCODE_TXD:
 210       return "txd";
 211    case SHADER_OPCODE_TXD_LOGICAL:
 212       return "txd_logical";
 213    case SHADER_OPCODE_TXF:
 214       return "txf";
 215    case SHADER_OPCODE_TXF_LOGICAL:
 216       return "txf_logical";
 217    case SHADER_OPCODE_TXF_LZ:
 218       return "txf_lz";
 219    case SHADER_OPCODE_TXL:
 220       return "txl";
 221    case SHADER_OPCODE_TXL_LOGICAL:
 222       return "txl_logical";
 223    case SHADER_OPCODE_TXL_LZ:
 224       return "txl_lz";
 225    case SHADER_OPCODE_TXS:
 226       return "txs";
 227    case SHADER_OPCODE_TXS_LOGICAL:
 228       return "txs_logical";
 229    case FS_OPCODE_TXB:
 230       return "txb";
 231    case FS_OPCODE_TXB_LOGICAL:
 232       return "txb_logical";
 233    case SHADER_OPCODE_TXF_CMS:
 234       return "txf_cms";
 235    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 236       return "txf_cms_logical";
 237    case SHADER_OPCODE_TXF_CMS_W:
 238       return "txf_cms_w";
 239    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 240       return "txf_cms_w_logical";
 241    case SHADER_OPCODE_TXF_UMS:
 242       return "txf_ums";
 243    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 244       return "txf_ums_logical";
 245    case SHADER_OPCODE_TXF_MCS:
 246       return "txf_mcs";
 247    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 248       return "txf_mcs_logical";
 249    case SHADER_OPCODE_LOD:
 250       return "lod";
 251    case SHADER_OPCODE_LOD_LOGICAL:
 252       return "lod_logical";
 253    case SHADER_OPCODE_TG4:
 254       return "tg4";
 255    case SHADER_OPCODE_TG4_LOGICAL:
 256       return "tg4_logical";
 257    case SHADER_OPCODE_TG4_OFFSET:
 258       return "tg4_offset";
 259    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 260       return "tg4_offset_logical";
 261    case SHADER_OPCODE_SAMPLEINFO:
 262       return "sampleinfo";
 263    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 264       return "sampleinfo_logical";
 265
 266    case SHADER_OPCODE_SHADER_TIME_ADD:
 267       return "shader_time_add";
 268
 269    case SHADER_OPCODE_UNTYPED_ATOMIC:
 270       return "untyped_atomic";
 271    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 272       return "untyped_atomic_logical";
 273    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 274       return "untyped_surface_read";
 275    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 276       return "untyped_surface_read_logical";
 277    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 278       return "untyped_surface_write";
 279    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 280       return "untyped_surface_write_logical";
 281    case SHADER_OPCODE_TYPED_ATOMIC:
 282       return "typed_atomic";
 283    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 284       return "typed_atomic_logical";
 285    case SHADER_OPCODE_TYPED_SURFACE_READ:
 286       return "typed_surface_read";
 287    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 288       return "typed_surface_read_logical";
 289    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 290       return "typed_surface_write";
 291    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 292       return "typed_surface_write_logical";
 293    case SHADER_OPCODE_MEMORY_FENCE:
 294       return "memory_fence";
 295
 296    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
 297       return "byte_scattered_write";
 298    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 299       return "byte_scattered_write_logical";
 300
 301    case SHADER_OPCODE_LOAD_PAYLOAD:
 302       return "load_payload";
 303    case FS_OPCODE_PACK:
 304       return "pack";
 305
 306    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 307       return "gen4_scratch_read";
 308    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 309       return "gen4_scratch_write";
 310    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 311       return "gen7_scratch_read";
 312    case SHADER_OPCODE_URB_WRITE_SIMD8:
 313       return "gen8_urb_write_simd8";
 314    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 315       return "gen8_urb_write_simd8_per_slot";
 316    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 317       return "gen8_urb_write_simd8_masked";
 318    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 319       return "gen8_urb_write_simd8_masked_per_slot";
 320    case SHADER_OPCODE_URB_READ_SIMD8:
 321       return "urb_read_simd8";
 322    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 323       return "urb_read_simd8_per_slot";
 324
 325    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 326       return "find_live_channel";
 327    case SHADER_OPCODE_BROADCAST:
 328       return "broadcast";
 329
 330    case VEC4_OPCODE_MOV_BYTES:
 331       return "mov_bytes";
 332    case VEC4_OPCODE_PACK_BYTES:
 333       return "pack_bytes";
 334    case VEC4_OPCODE_UNPACK_UNIFORM:
 335       return "unpack_uniform";
 336    case VEC4_OPCODE_DOUBLE_TO_F32:
 337       return "double_to_f32";
 338    case VEC4_OPCODE_DOUBLE_TO_D32:
 339       return "double_to_d32";
 340    case VEC4_OPCODE_DOUBLE_TO_U32:
 341       return "double_to_u32";
 342    case VEC4_OPCODE_TO_DOUBLE:
 343       return "single_to_double";
 344    case VEC4_OPCODE_PICK_LOW_32BIT:
 345       return "pick_low_32bit";
 346    case VEC4_OPCODE_PICK_HIGH_32BIT:
 347       return "pick_high_32bit";
 348    case VEC4_OPCODE_SET_LOW_32BIT:
 349       return "set_low_32bit";
 350    case VEC4_OPCODE_SET_HIGH_32BIT:
 351       return "set_high_32bit";
 352
 353    case FS_OPCODE_DDX_COARSE:
 354       return "ddx_coarse";
 355    case FS_OPCODE_DDX_FINE:
 356       return "ddx_fine";
 357    case FS_OPCODE_DDY_COARSE:
 358       return "ddy_coarse";
 359    case FS_OPCODE_DDY_FINE:
 360       return "ddy_fine";
 361
 362    case FS_OPCODE_CINTERP:
 363       return "cinterp";
 364    case FS_OPCODE_LINTERP:
 365       return "linterp";
 366
 367    case FS_OPCODE_PIXEL_X:
 368       return "pixel_x";
 369    case FS_OPCODE_PIXEL_Y:
 370       return "pixel_y";
 371
 372    case FS_OPCODE_GET_BUFFER_SIZE:
 373       return "fs_get_buffer_size";
 374
 375    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 376       return "uniform_pull_const";
 377    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 378       return "uniform_pull_const_gen7";
 379    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 380       return "varying_pull_const_gen4";
 381    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 382       return "varying_pull_const_gen7";
 383    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 384       return "varying_pull_const_logical";
 385
 386    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 387       return "mov_dispatch_to_flags";
 388    case FS_OPCODE_DISCARD_JUMP:
 389       return "discard_jump";
 390
 391    case FS_OPCODE_SET_SAMPLE_ID:
 392       return "set_sample_id";
 393
 394    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 395       return "pack_half_2x16_split";
 396    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 397       return "unpack_half_2x16_split_x";
 398    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 399       return "unpack_half_2x16_split_y";
 400
 401    case FS_OPCODE_PLACEHOLDER_HALT:
 402       return "placeholder_halt";
 403
 404    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 405       return "interp_sample";
 406    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 407       return "interp_shared_offset";
 408    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 409       return "interp_per_slot_offset";
 410
 411    case VS_OPCODE_URB_WRITE:
 412       return "vs_urb_write";
 413    case VS_OPCODE_PULL_CONSTANT_LOAD:
 414       return "pull_constant_load";
 415    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 416       return "pull_constant_load_gen7";
 417
 418    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 419       return "set_simd4x2_header_gen9";
 420
 421    case VS_OPCODE_GET_BUFFER_SIZE:
 422       return "vs_get_buffer_size";
 423
 424    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 425       return "unpack_flags_simd4x2";
 426
 427    case GS_OPCODE_URB_WRITE:
 428       return "gs_urb_write";
 429    case GS_OPCODE_URB_WRITE_ALLOCATE:
 430       return "gs_urb_write_allocate";
 431    case GS_OPCODE_THREAD_END:
 432       return "gs_thread_end";
 433    case GS_OPCODE_SET_WRITE_OFFSET:
 434       return "set_write_offset";
 435    case GS_OPCODE_SET_VERTEX_COUNT:
 436       return "set_vertex_count";
 437    case GS_OPCODE_SET_DWORD_2:
 438       return "set_dword_2";
 439    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 440       return "prepare_channel_masks";
 441    case GS_OPCODE_SET_CHANNEL_MASKS:
 442       return "set_channel_masks";
 443    case GS_OPCODE_GET_INSTANCE_ID:
 444       return "get_instance_id";
 445    case GS_OPCODE_FF_SYNC:
 446       return "ff_sync";
 447    case GS_OPCODE_SET_PRIMITIVE_ID:
 448       return "set_primitive_id";
 449    case GS_OPCODE_SVB_WRITE:
 450       return "gs_svb_write";
 451    case GS_OPCODE_SVB_SET_DST_INDEX:
 452       return "gs_svb_set_dst_index";
 453    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 454       return "gs_ff_sync_set_primitives";
 455    case CS_OPCODE_CS_TERMINATE:
 456       return "cs_terminate";
 457    case SHADER_OPCODE_BARRIER:
 458       return "barrier";
 459    case SHADER_OPCODE_MULH:
 460       return "mulh";
 461    case SHADER_OPCODE_MOV_INDIRECT:
 462       return "mov_indirect";
 463
 464    case VEC4_OPCODE_URB_READ:
 465       return "urb_read";
 466    case TCS_OPCODE_GET_INSTANCE_ID:
 467       return "tcs_get_instance_id";
 468    case TCS_OPCODE_URB_WRITE:
 469       return "tcs_urb_write";
 470    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 471       return "tcs_set_input_urb_offsets";
 472    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 473       return "tcs_set_output_urb_offsets";
 474    case TCS_OPCODE_GET_PRIMITIVE_ID:
 475       return "tcs_get_primitive_id";
 476    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 477       return "tcs_create_barrier_header";
 478    case TCS_OPCODE_SRC0_010_IS_ZERO:
 479       return "tcs_src0<0,1,0>_is_zero";
 480    case TCS_OPCODE_RELEASE_INPUT:
 481       return "tcs_release_input";
 482    case TCS_OPCODE_THREAD_END:
 483       return "tcs_thread_end";
 484    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 485       return "tes_create_input_read_header";
 486    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 487       return "tes_add_indirect_urb_offset";
 488    case TES_OPCODE_GET_PRIMITIVE_ID:
 489       return "tes_get_primitive_id";
 490
 491    case SHADER_OPCODE_RND_MODE:
 492       return "rnd_mode";
 493    }
 494
 495    unreachable("not reached");
 496 }
 497
 498 bool
 499 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 500 {
 501    union {
 502       unsigned ud;
 503       int d;
 504       float f;
 505       double df;
 506    } imm, sat_imm = { 0 };
 507
 508    const unsigned size = type_sz(type);
 509
 510    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 511     * irrelevant, so just check the size of the type and copy from/to an
 512     * appropriately sized field.
 513     */
 514    if (size < 8)
 515       imm.ud = reg->ud;
 516    else
 517       imm.df = reg->df;
 518
 519    switch (type) {
 520    case BRW_REGISTER_TYPE_UD:
 521    case BRW_REGISTER_TYPE_D:
 522    case BRW_REGISTER_TYPE_UW:
 523    case BRW_REGISTER_TYPE_W:
 524    case BRW_REGISTER_TYPE_UQ:
 525    case BRW_REGISTER_TYPE_Q:
 526       /* Nothing to do. */
 527       return false;
 528    case BRW_REGISTER_TYPE_F:
 529       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 530       break;
 531    case BRW_REGISTER_TYPE_DF:
 532       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 533       break;
 534    case BRW_REGISTER_TYPE_UB:
 535    case BRW_REGISTER_TYPE_B:
 536       unreachable("no UB/B immediates");
 537    case BRW_REGISTER_TYPE_V:
 538    case BRW_REGISTER_TYPE_UV:
 539    case BRW_REGISTER_TYPE_VF:
 540       unreachable("unimplemented: saturate vector immediate");
 541    case BRW_REGISTER_TYPE_HF:
 542       unreachable("unimplemented: saturate HF immediate");
 543    }
 544
 545    if (size < 8) {
 546       if (imm.ud != sat_imm.ud) {
 547          reg->ud = sat_imm.ud;
 548          return true;
 549       }
 550    } else {
 551       if (imm.df != sat_imm.df) {
 552          reg->df = sat_imm.df;
 553          return true;
 554       }
 555    }
 556    return false;
 557 }
 558
 559 bool
 560 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 561 {
 562    switch (type) {
 563    case BRW_REGISTER_TYPE_D:
 564    case BRW_REGISTER_TYPE_UD:
 565       reg->d = -reg->d;
 566       return true;
 567    case BRW_REGISTER_TYPE_W:
 568    case BRW_REGISTER_TYPE_UW:
 569       reg->d = -(int16_t)reg->ud;
 570       return true;
 571    case BRW_REGISTER_TYPE_F:
 572       reg->f = -reg->f;
 573       return true;
 574    case BRW_REGISTER_TYPE_VF:
 575       reg->ud ^= 0x80808080;
 576       return true;
 577    case BRW_REGISTER_TYPE_DF:
 578       reg->df = -reg->df;
 579       return true;
 580    case BRW_REGISTER_TYPE_UQ:
 581    case BRW_REGISTER_TYPE_Q:
 582       reg->d64 = -reg->d64;
 583       return true;
 584    case BRW_REGISTER_TYPE_UB:
 585    case BRW_REGISTER_TYPE_B:
 586       unreachable("no UB/B immediates");
 587    case BRW_REGISTER_TYPE_UV:
 588    case BRW_REGISTER_TYPE_V:
 589       assert(!"unimplemented: negate UV/V immediate");
 590    case BRW_REGISTER_TYPE_HF:
 591       assert(!"unimplemented: negate HF immediate");
 592    }
 593
 594    return false;
 595 }
 596
 597 bool
 598 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 599 {
 600    switch (type) {
 601    case BRW_REGISTER_TYPE_D:
 602       reg->d = abs(reg->d);
 603       return true;
 604    case BRW_REGISTER_TYPE_W:
 605       reg->d = abs((int16_t)reg->ud);
 606       return true;
 607    case BRW_REGISTER_TYPE_F:
 608       reg->f = fabsf(reg->f);
 609       return true;
 610    case BRW_REGISTER_TYPE_DF:
 611       reg->df = fabs(reg->df);
 612       return true;
 613    case BRW_REGISTER_TYPE_VF:
 614       reg->ud &= ~0x80808080;
 615       return true;
 616    case BRW_REGISTER_TYPE_Q:
 617       reg->d64 = imaxabs(reg->d64);
 618       return true;
 619    case BRW_REGISTER_TYPE_UB:
 620    case BRW_REGISTER_TYPE_B:
 621       unreachable("no UB/B immediates");
 622    case BRW_REGISTER_TYPE_UQ:
 623    case BRW_REGISTER_TYPE_UD:
 624    case BRW_REGISTER_TYPE_UW:
 625    case BRW_REGISTER_TYPE_UV:
 626       /* Presumably the absolute value modifier on an unsigned source is a
 627        * nop, but it would be nice to confirm.
 628        */
 629       assert(!"unimplemented: abs unsigned immediate");
 630    case BRW_REGISTER_TYPE_V:
 631       assert(!"unimplemented: abs V immediate");
 632    case BRW_REGISTER_TYPE_HF:
 633       assert(!"unimplemented: abs HF immediate");
 634    }
 635
 636    return false;
 637 }
 638
 639 backend_shader::backend_shader(const struct brw_compiler *compiler,
 640                                void *log_data,
 641                                void *mem_ctx,
 642                                const nir_shader *shader,
 643                                struct brw_stage_prog_data *stage_prog_data)
 644    : compiler(compiler),
 645      log_data(log_data),
 646      devinfo(compiler->devinfo),
 647      nir(shader),
 648      stage_prog_data(stage_prog_data),
 649      mem_ctx(mem_ctx),
 650      cfg(NULL),
 651      stage(shader->info.stage)
 652 {
 653    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 654    stage_name = _mesa_shader_stage_to_string(stage);
 655    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 656 }
 657
 658 backend_shader::~backend_shader()
 659 {
 660 }
 661
 662 bool
 663 backend_reg::equals(const backend_reg &r) const
 664 {
 665    return brw_regs_equal(this, &r) && offset == r.offset;
 666 }
 667
 668 bool
 669 backend_reg::is_zero() const
 670 {
 671    if (file != IMM)
 672       return false;
 673
 674    switch (type) {
 675    case BRW_REGISTER_TYPE_F:
 676       return f == 0;
 677    case BRW_REGISTER_TYPE_DF:
 678       return df == 0;
 679    case BRW_REGISTER_TYPE_D:
 680    case BRW_REGISTER_TYPE_UD:
 681       return d == 0;
 682    case BRW_REGISTER_TYPE_UQ:
 683    case BRW_REGISTER_TYPE_Q:
 684       return u64 == 0;
 685    default:
 686       return false;
 687    }
 688 }
 689
 690 bool
 691 backend_reg::is_one() const
 692 {
 693    if (file != IMM)
 694       return false;
 695
 696    switch (type) {
 697    case BRW_REGISTER_TYPE_F:
 698       return f == 1.0f;
 699    case BRW_REGISTER_TYPE_DF:
 700       return df == 1.0;
 701    case BRW_REGISTER_TYPE_D:
 702    case BRW_REGISTER_TYPE_UD:
 703       return d == 1;
 704    case BRW_REGISTER_TYPE_UQ:
 705    case BRW_REGISTER_TYPE_Q:
 706       return u64 == 1;
 707    default:
 708       return false;
 709    }
 710 }
 711
 712 bool
 713 backend_reg::is_negative_one() const
 714 {
 715    if (file != IMM)
 716       return false;
 717
 718    switch (type) {
 719    case BRW_REGISTER_TYPE_F:
 720       return f == -1.0;
 721    case BRW_REGISTER_TYPE_DF:
 722       return df == -1.0;
 723    case BRW_REGISTER_TYPE_D:
 724       return d == -1;
 725    case BRW_REGISTER_TYPE_Q:
 726       return d64 == -1;
 727    default:
 728       return false;
 729    }
 730 }
 731
 732 bool
 733 backend_reg::is_null() const
 734 {
 735    return file == ARF && nr == BRW_ARF_NULL;
 736 }
 737
 738
 739 bool
 740 backend_reg::is_accumulator() const
 741 {
 742    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 743 }
 744
 745 bool
 746 backend_instruction::is_commutative() const
 747 {
 748    switch (opcode) {
 749    case BRW_OPCODE_AND:
 750    case BRW_OPCODE_OR:
 751    case BRW_OPCODE_XOR:
 752    case BRW_OPCODE_ADD:
 753    case BRW_OPCODE_MUL:
 754    case SHADER_OPCODE_MULH:
 755       return true;
 756    case BRW_OPCODE_SEL:
 757       /* MIN and MAX are commutative. */
 758       if (conditional_mod == BRW_CONDITIONAL_GE ||
 759           conditional_mod == BRW_CONDITIONAL_L) {
 760          return true;
 761       }
 762       /* fallthrough */
 763    default:
 764       return false;
 765    }
 766 }
 767
 768 bool
 769 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 770 {
 771    return ::is_3src(devinfo, opcode);
 772 }
 773
 774 bool
 775 backend_instruction::is_tex() const
 776 {
 777    return (opcode == SHADER_OPCODE_TEX ||
 778            opcode == FS_OPCODE_TXB ||
 779            opcode == SHADER_OPCODE_TXD ||
 780            opcode == SHADER_OPCODE_TXF ||
 781            opcode == SHADER_OPCODE_TXF_LZ ||
 782            opcode == SHADER_OPCODE_TXF_CMS ||
 783            opcode == SHADER_OPCODE_TXF_CMS_W ||
 784            opcode == SHADER_OPCODE_TXF_UMS ||
 785            opcode == SHADER_OPCODE_TXF_MCS ||
 786            opcode == SHADER_OPCODE_TXL ||
 787            opcode == SHADER_OPCODE_TXL_LZ ||
 788            opcode == SHADER_OPCODE_TXS ||
 789            opcode == SHADER_OPCODE_LOD ||
 790            opcode == SHADER_OPCODE_TG4 ||
 791            opcode == SHADER_OPCODE_TG4_OFFSET ||
 792            opcode == SHADER_OPCODE_SAMPLEINFO);
 793 }
 794
 795 bool
 796 backend_instruction::is_math() const
 797 {
 798    return (opcode == SHADER_OPCODE_RCP ||
 799            opcode == SHADER_OPCODE_RSQ ||
 800            opcode == SHADER_OPCODE_SQRT ||
 801            opcode == SHADER_OPCODE_EXP2 ||
 802            opcode == SHADER_OPCODE_LOG2 ||
 803            opcode == SHADER_OPCODE_SIN ||
 804            opcode == SHADER_OPCODE_COS ||
 805            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 806            opcode == SHADER_OPCODE_INT_REMAINDER ||
 807            opcode == SHADER_OPCODE_POW);
 808 }
 809
 810 bool
 811 backend_instruction::is_control_flow() const
 812 {
 813    switch (opcode) {
 814    case BRW_OPCODE_DO:
 815    case BRW_OPCODE_WHILE:
 816    case BRW_OPCODE_IF:
 817    case BRW_OPCODE_ELSE:
 818    case BRW_OPCODE_ENDIF:
 819    case BRW_OPCODE_BREAK:
 820    case BRW_OPCODE_CONTINUE:
 821       return true;
 822    default:
 823       return false;
 824    }
 825 }
 826
 827 bool
 828 backend_instruction::can_do_source_mods() const
 829 {
 830    switch (opcode) {
 831    case BRW_OPCODE_ADDC:
 832    case BRW_OPCODE_BFE:
 833    case BRW_OPCODE_BFI1:
 834    case BRW_OPCODE_BFI2:
 835    case BRW_OPCODE_BFREV:
 836    case BRW_OPCODE_CBIT:
 837    case BRW_OPCODE_FBH:
 838    case BRW_OPCODE_FBL:
 839    case BRW_OPCODE_SUBB:
 840    case SHADER_OPCODE_BROADCAST:
 841    case SHADER_OPCODE_MOV_INDIRECT:
 842       return false;
 843    default:
 844       return true;
 845    }
 846 }
 847
 848 bool
 849 backend_instruction::can_do_saturate() const
 850 {
 851    switch (opcode) {
 852    case BRW_OPCODE_ADD:
 853    case BRW_OPCODE_ASR:
 854    case BRW_OPCODE_AVG:
 855    case BRW_OPCODE_DP2:
 856    case BRW_OPCODE_DP3:
 857    case BRW_OPCODE_DP4:
 858    case BRW_OPCODE_DPH:
 859    case BRW_OPCODE_F16TO32:
 860    case BRW_OPCODE_F32TO16:
 861    case BRW_OPCODE_LINE:
 862    case BRW_OPCODE_LRP:
 863    case BRW_OPCODE_MAC:
 864    case BRW_OPCODE_MAD:
 865    case BRW_OPCODE_MATH:
 866    case BRW_OPCODE_MOV:
 867    case BRW_OPCODE_MUL:
 868    case SHADER_OPCODE_MULH:
 869    case BRW_OPCODE_PLN:
 870    case BRW_OPCODE_RNDD:
 871    case BRW_OPCODE_RNDE:
 872    case BRW_OPCODE_RNDU:
 873    case BRW_OPCODE_RNDZ:
 874    case BRW_OPCODE_SEL:
 875    case BRW_OPCODE_SHL:
 876    case BRW_OPCODE_SHR:
 877    case FS_OPCODE_LINTERP:
 878    case SHADER_OPCODE_COS:
 879    case SHADER_OPCODE_EXP2:
 880    case SHADER_OPCODE_LOG2:
 881    case SHADER_OPCODE_POW:
 882    case SHADER_OPCODE_RCP:
 883    case SHADER_OPCODE_RSQ:
 884    case SHADER_OPCODE_SIN:
 885    case SHADER_OPCODE_SQRT:
 886       return true;
 887    default:
 888       return false;
 889    }
 890 }
 891
 892 bool
 893 backend_instruction::can_do_cmod() const
 894 {
 895    switch (opcode) {
 896    case BRW_OPCODE_ADD:
 897    case BRW_OPCODE_ADDC:
 898    case BRW_OPCODE_AND:
 899    case BRW_OPCODE_ASR:
 900    case BRW_OPCODE_AVG:
 901    case BRW_OPCODE_CMP:
 902    case BRW_OPCODE_CMPN:
 903    case BRW_OPCODE_DP2:
 904    case BRW_OPCODE_DP3:
 905    case BRW_OPCODE_DP4:
 906    case BRW_OPCODE_DPH:
 907    case BRW_OPCODE_F16TO32:
 908    case BRW_OPCODE_F32TO16:
 909    case BRW_OPCODE_FRC:
 910    case BRW_OPCODE_LINE:
 911    case BRW_OPCODE_LRP:
 912    case BRW_OPCODE_LZD:
 913    case BRW_OPCODE_MAC:
 914    case BRW_OPCODE_MACH:
 915    case BRW_OPCODE_MAD:
 916    case BRW_OPCODE_MOV:
 917    case BRW_OPCODE_MUL:
 918    case BRW_OPCODE_NOT:
 919    case BRW_OPCODE_OR:
 920    case BRW_OPCODE_PLN:
 921    case BRW_OPCODE_RNDD:
 922    case BRW_OPCODE_RNDE:
 923    case BRW_OPCODE_RNDU:
 924    case BRW_OPCODE_RNDZ:
 925    case BRW_OPCODE_SAD2:
 926    case BRW_OPCODE_SADA2:
 927    case BRW_OPCODE_SHL:
 928    case BRW_OPCODE_SHR:
 929    case BRW_OPCODE_SUBB:
 930    case BRW_OPCODE_XOR:
 931    case FS_OPCODE_CINTERP:
 932    case FS_OPCODE_LINTERP:
 933       return true;
 934    default:
 935       return false;
 936    }
 937 }
 938
 939 bool
 940 backend_instruction::reads_accumulator_implicitly() const
 941 {
 942    switch (opcode) {
 943    case BRW_OPCODE_MAC:
 944    case BRW_OPCODE_MACH:
 945    case BRW_OPCODE_SADA2:
 946       return true;
 947    default:
 948       return false;
 949    }
 950 }
 951
 952 bool
 953 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 954 {
 955    return writes_accumulator ||
 956           (devinfo->gen < 6 &&
 957            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 958             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 959              opcode != FS_OPCODE_CINTERP)));
 960 }
 961
 962 bool
 963 backend_instruction::has_side_effects() const
 964 {
 965    switch (opcode) {
 966    case SHADER_OPCODE_UNTYPED_ATOMIC:
 967    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 968    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 969    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 970    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 971    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
 972    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 973    case SHADER_OPCODE_TYPED_ATOMIC:
 974    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 975    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 976    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 977    case SHADER_OPCODE_MEMORY_FENCE:
 978    case SHADER_OPCODE_URB_WRITE_SIMD8:
 979    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 980    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 981    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 982    case FS_OPCODE_FB_WRITE:
 983    case FS_OPCODE_FB_WRITE_LOGICAL:
 984    case SHADER_OPCODE_BARRIER:
 985    case TCS_OPCODE_URB_WRITE:
 986    case TCS_OPCODE_RELEASE_INPUT:
 987    case SHADER_OPCODE_RND_MODE:
 988       return true;
 989    default:
 990       return eot;
 991    }
 992 }
 993
 994 bool
 995 backend_instruction::is_volatile() const
 996 {
 997    switch (opcode) {
 998    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 999    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1000    case SHADER_OPCODE_TYPED_SURFACE_READ:
1001    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1002    case SHADER_OPCODE_URB_READ_SIMD8:
1003    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1004    case VEC4_OPCODE_URB_READ:
1005       return true;
1006    default:
1007       return false;
1008    }
1009 }
1010
1011 #ifndef NDEBUG
1012 static bool
1013 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1014 {
1015    bool found = false;
1016    foreach_inst_in_block (backend_instruction, i, block) {
1017       if (inst == i) {
1018          found = true;
1019       }
1020    }
1021    return found;
1022 }
1023 #endif
1024
1025 static void
1026 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1027 {
1028    for (bblock_t *block_iter = start_block->next();
1029         block_iter;
1030         block_iter = block_iter->next()) {
1031       block_iter->start_ip += ip_adjustment;
1032       block_iter->end_ip += ip_adjustment;
1033    }
1034 }
1035
1036 void
1037 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1038 {
1039    assert(this != inst);
1040
1041    if (!this->is_head_sentinel())
1042       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1043
1044    block->end_ip++;
1045
1046    adjust_later_block_ips(block, 1);
1047
1048    exec_node::insert_after(inst);
1049 }
1050
1051 void
1052 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1053 {
1054    assert(this != inst);
1055
1056    if (!this->is_tail_sentinel())
1057       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1058
1059    block->end_ip++;
1060
1061    adjust_later_block_ips(block, 1);
1062
1063    exec_node::insert_before(inst);
1064 }
1065
1066 void
1067 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1068 {
1069    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1070
1071    unsigned num_inst = list->length();
1072
1073    block->end_ip += num_inst;
1074
1075    adjust_later_block_ips(block, num_inst);
1076
1077    exec_node::insert_before(list);
1078 }
1079
1080 void
1081 backend_instruction::remove(bblock_t *block)
1082 {
1083    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1084
1085    adjust_later_block_ips(block, -1);
1086
1087    if (block->start_ip == block->end_ip) {
1088       block->cfg->remove_block(block);
1089    } else {
1090       block->end_ip--;
1091    }
1092
1093    exec_node::remove();
1094 }
1095
1096 void
1097 backend_shader::dump_instructions()
1098 {
1099    dump_instructions(NULL);
1100 }
1101
1102 void
1103 backend_shader::dump_instructions(const char *name)
1104 {
1105    FILE *file = stderr;
1106    if (name && geteuid() != 0) {
1107       file = fopen(name, "w");
1108       if (!file)
1109          file = stderr;
1110    }
1111
1112    if (cfg) {
1113       int ip = 0;
1114       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1115          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1116             fprintf(file, "%4d: ", ip++);
1117          dump_instruction(inst, file);
1118       }
1119    } else {
1120       int ip = 0;
1121       foreach_in_list(backend_instruction, inst, &instructions) {
1122          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1123             fprintf(file, "%4d: ", ip++);
1124          dump_instruction(inst, file);
1125       }
1126    }
1127
1128    if (file != stderr) {
1129       fclose(file);
1130    }
1131 }
1132
1133 void
1134 backend_shader::calculate_cfg()
1135 {
1136    if (this->cfg)
1137       return;
1138    cfg = new(mem_ctx) cfg_t(&this->instructions);
1139 }
1140
1141 extern "C" const unsigned *
1142 brw_compile_tes(const struct brw_compiler *compiler,
1143                 void *log_data,
1144                 void *mem_ctx,
1145                 const struct brw_tes_prog_key *key,
1146                 const struct brw_vue_map *input_vue_map,
1147                 struct brw_tes_prog_data *prog_data,
1148                 const nir_shader *src_shader,
1149                 struct gl_program *prog,
1150                 int shader_time_index,
1151                 char **error_str)
1152 {
1153    const struct gen_device_info *devinfo = compiler->devinfo;
1154    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1155    const unsigned *assembly;
1156
1157    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1158    nir->info.inputs_read = key->inputs_read;
1159    nir->info.patch_inputs_read = key->patch_inputs_read;
1160
1161    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1162    brw_nir_lower_tes_inputs(nir, input_vue_map);
1163    brw_nir_lower_vue_outputs(nir, is_scalar);
1164    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1165
1166    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1167                        nir->info.outputs_written,
1168                        nir->info.separate_shader);
1169
1170    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1171
1172    assert(output_size_bytes >= 1);
1173    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1174       if (error_str)
1175          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1176       return NULL;
1177    }
1178
1179    prog_data->base.clip_distance_mask =
1180       ((1 << nir->info.clip_distance_array_size) - 1);
1181    prog_data->base.cull_distance_mask =
1182       ((1 << nir->info.cull_distance_array_size) - 1) <<
1183       nir->info.clip_distance_array_size;
1184
1185    /* URB entry sizes are stored as a multiple of 64 bytes. */
1186    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1187
1188    /* On Cannonlake software shall not program an allocation size that
1189     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1190     */
1191    if (devinfo->gen == 10 &&
1192        prog_data->base.urb_entry_size % 3 == 0)
1193       prog_data->base.urb_entry_size++;
1194
1195    prog_data->base.urb_read_length = 0;
1196
1197    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1198    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1199                  TESS_SPACING_FRACTIONAL_ODD - 1);
1200    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1201                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1202
1203    prog_data->partitioning =
1204       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1205
1206    switch (nir->info.tess.primitive_mode) {
1207    case GL_QUADS:
1208       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1209       break;
1210    case GL_TRIANGLES:
1211       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1212       break;
1213    case GL_ISOLINES:
1214       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1215       break;
1216    default:
1217       unreachable("invalid domain shader primitive mode");
1218    }
1219
1220    if (nir->info.tess.point_mode) {
1221       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1222    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1223       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1224    } else {
1225       /* Hardware winding order is backwards from OpenGL */
1226       prog_data->output_topology =
1227          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1228                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1229    }
1230
1231    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1232       fprintf(stderr, "TES Input ");
1233       brw_print_vue_map(stderr, input_vue_map);
1234       fprintf(stderr, "TES Output ");
1235       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1236    }
1237
1238    if (is_scalar) {
1239       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1240                    &prog_data->base.base, NULL, nir, 8,
1241                    shader_time_index, input_vue_map);
1242       if (!v.run_tes()) {
1243          if (error_str)
1244             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1245          return NULL;
1246       }
1247
1248       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1249       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1250
1251       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1252                      &prog_data->base.base, v.promoted_constants, false,
1253                      MESA_SHADER_TESS_EVAL);
1254       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1255          g.enable_debug(ralloc_asprintf(mem_ctx,
1256                                         "%s tessellation evaluation shader %s",
1257                                         nir->info.label ? nir->info.label
1258                                                         : "unnamed",
1259                                         nir->info.name));
1260       }
1261
1262       g.generate_code(v.cfg, 8);
1263
1264       assembly = g.get_assembly(&prog_data->base.base.program_size);
1265    } else {
1266       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1267                               nir, mem_ctx, shader_time_index);
1268       if (!v.run()) {
1269          if (error_str)
1270             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1271          return NULL;
1272       }
1273
1274       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1275          v.dump_instructions();
1276
1277       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1278                                             &prog_data->base, v.cfg,
1279                                             &prog_data->base.base.program_size);
1280    }
1281
1282    return assembly;
1283 }