src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "dev/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_INT8:
  48       return BRW_REGISTER_TYPE_B;
  49    case GLSL_TYPE_UINT:
  50       return BRW_REGISTER_TYPE_UD;
  51    case GLSL_TYPE_UINT16:
  52       return BRW_REGISTER_TYPE_UW;
  53    case GLSL_TYPE_UINT8:
  54       return BRW_REGISTER_TYPE_UB;
  55    case GLSL_TYPE_ARRAY:
  56       return brw_type_for_base_type(type->fields.array);
  57    case GLSL_TYPE_STRUCT:
  58    case GLSL_TYPE_INTERFACE:
  59    case GLSL_TYPE_SAMPLER:
  60    case GLSL_TYPE_ATOMIC_UINT:
  61       /* These should be overridden with the type of the member when
  62        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  63        * way to trip up if we don't.
  64        */
  65       return BRW_REGISTER_TYPE_UD;
  66    case GLSL_TYPE_IMAGE:
  67       return BRW_REGISTER_TYPE_UD;
  68    case GLSL_TYPE_DOUBLE:
  69       return BRW_REGISTER_TYPE_DF;
  70    case GLSL_TYPE_UINT64:
  71       return BRW_REGISTER_TYPE_UQ;
  72    case GLSL_TYPE_INT64:
  73       return BRW_REGISTER_TYPE_Q;
  74    case GLSL_TYPE_VOID:
  75    case GLSL_TYPE_ERROR:
  76    case GLSL_TYPE_FUNCTION:
  77       unreachable("not reached");
  78    }
  79
  80    return BRW_REGISTER_TYPE_F;
  81 }
  82
  83 enum brw_conditional_mod
  84 brw_conditional_for_comparison(unsigned int op)
  85 {
  86    switch (op) {
  87    case ir_binop_less:
  88       return BRW_CONDITIONAL_L;
  89    case ir_binop_gequal:
  90       return BRW_CONDITIONAL_GE;
  91    case ir_binop_equal:
  92    case ir_binop_all_equal: /* same as equal for scalars */
  93       return BRW_CONDITIONAL_Z;
  94    case ir_binop_nequal:
  95    case ir_binop_any_nequal: /* same as nequal for scalars */
  96       return BRW_CONDITIONAL_NZ;
  97    default:
  98       unreachable("not reached: bad operation for comparison");
  99    }
 100 }
 101
 102 uint32_t
 103 brw_math_function(enum opcode op)
 104 {
 105    switch (op) {
 106    case SHADER_OPCODE_RCP:
 107       return BRW_MATH_FUNCTION_INV;
 108    case SHADER_OPCODE_RSQ:
 109       return BRW_MATH_FUNCTION_RSQ;
 110    case SHADER_OPCODE_SQRT:
 111       return BRW_MATH_FUNCTION_SQRT;
 112    case SHADER_OPCODE_EXP2:
 113       return BRW_MATH_FUNCTION_EXP;
 114    case SHADER_OPCODE_LOG2:
 115       return BRW_MATH_FUNCTION_LOG;
 116    case SHADER_OPCODE_POW:
 117       return BRW_MATH_FUNCTION_POW;
 118    case SHADER_OPCODE_SIN:
 119       return BRW_MATH_FUNCTION_SIN;
 120    case SHADER_OPCODE_COS:
 121       return BRW_MATH_FUNCTION_COS;
 122    case SHADER_OPCODE_INT_QUOTIENT:
 123       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 124    case SHADER_OPCODE_INT_REMAINDER:
 125       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 126    default:
 127       unreachable("not reached: unknown math function");
 128    }
 129 }
 130
 131 bool
 132 brw_texture_offset(const nir_tex_instr *tex, unsigned src,
 133                    uint32_t *offset_bits_out)
 134 {
 135    if (!nir_src_is_const(tex->src[src].src))
 136       return false;
 137
 138    const unsigned num_components = nir_tex_instr_src_size(tex, src);
 139
 140    /* Combine all three offsets into a single unsigned dword:
 141     *
 142     *    bits 11:8 - U Offset (X component)
 143     *    bits  7:4 - V Offset (Y component)
 144     *    bits  3:0 - R Offset (Z component)
 145     */
 146    uint32_t offset_bits = 0;
 147    for (unsigned i = 0; i < num_components; i++) {
 148       int offset = nir_src_comp_as_int(tex->src[src].src, i);
 149
 150       /* offset out of bounds; caller will handle it. */
 151       if (offset > 7 || offset < -8)
 152          return false;
 153
 154       const unsigned shift = 4 * (2 - i);
 155       offset_bits |= (offset << shift) & (0xF << shift);
 156    }
 157
 158    *offset_bits_out = offset_bits;
 159
 160    return true;
 161 }
 162
 163 const char *
 164 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 165 {
 166    switch (op) {
 167    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 168       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 169        * start of a loop in the IR.
 170        */
 171       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 172          return "do";
 173
 174       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 175        * then to mark that we want to do the conversion.
 176        */
 177       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 178          return "f32to16";
 179
 180       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 181          return "f16to32";
 182
 183       assert(brw_opcode_desc(devinfo, op)->name);
 184       return brw_opcode_desc(devinfo, op)->name;
 185    case FS_OPCODE_FB_WRITE:
 186       return "fb_write";
 187    case FS_OPCODE_FB_WRITE_LOGICAL:
 188       return "fb_write_logical";
 189    case FS_OPCODE_REP_FB_WRITE:
 190       return "rep_fb_write";
 191    case FS_OPCODE_FB_READ:
 192       return "fb_read";
 193    case FS_OPCODE_FB_READ_LOGICAL:
 194       return "fb_read_logical";
 195
 196    case SHADER_OPCODE_RCP:
 197       return "rcp";
 198    case SHADER_OPCODE_RSQ:
 199       return "rsq";
 200    case SHADER_OPCODE_SQRT:
 201       return "sqrt";
 202    case SHADER_OPCODE_EXP2:
 203       return "exp2";
 204    case SHADER_OPCODE_LOG2:
 205       return "log2";
 206    case SHADER_OPCODE_POW:
 207       return "pow";
 208    case SHADER_OPCODE_INT_QUOTIENT:
 209       return "int_quot";
 210    case SHADER_OPCODE_INT_REMAINDER:
 211       return "int_rem";
 212    case SHADER_OPCODE_SIN:
 213       return "sin";
 214    case SHADER_OPCODE_COS:
 215       return "cos";
 216
 217    case SHADER_OPCODE_SEND:
 218       return "send";
 219
 220    case SHADER_OPCODE_UNDEF:
 221       return "undef";
 222
 223    case SHADER_OPCODE_TEX:
 224       return "tex";
 225    case SHADER_OPCODE_TEX_LOGICAL:
 226       return "tex_logical";
 227    case SHADER_OPCODE_TXD:
 228       return "txd";
 229    case SHADER_OPCODE_TXD_LOGICAL:
 230       return "txd_logical";
 231    case SHADER_OPCODE_TXF:
 232       return "txf";
 233    case SHADER_OPCODE_TXF_LOGICAL:
 234       return "txf_logical";
 235    case SHADER_OPCODE_TXF_LZ:
 236       return "txf_lz";
 237    case SHADER_OPCODE_TXL:
 238       return "txl";
 239    case SHADER_OPCODE_TXL_LOGICAL:
 240       return "txl_logical";
 241    case SHADER_OPCODE_TXL_LZ:
 242       return "txl_lz";
 243    case SHADER_OPCODE_TXS:
 244       return "txs";
 245    case SHADER_OPCODE_TXS_LOGICAL:
 246       return "txs_logical";
 247    case FS_OPCODE_TXB:
 248       return "txb";
 249    case FS_OPCODE_TXB_LOGICAL:
 250       return "txb_logical";
 251    case SHADER_OPCODE_TXF_CMS:
 252       return "txf_cms";
 253    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 254       return "txf_cms_logical";
 255    case SHADER_OPCODE_TXF_CMS_W:
 256       return "txf_cms_w";
 257    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 258       return "txf_cms_w_logical";
 259    case SHADER_OPCODE_TXF_UMS:
 260       return "txf_ums";
 261    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 262       return "txf_ums_logical";
 263    case SHADER_OPCODE_TXF_MCS:
 264       return "txf_mcs";
 265    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 266       return "txf_mcs_logical";
 267    case SHADER_OPCODE_LOD:
 268       return "lod";
 269    case SHADER_OPCODE_LOD_LOGICAL:
 270       return "lod_logical";
 271    case SHADER_OPCODE_TG4:
 272       return "tg4";
 273    case SHADER_OPCODE_TG4_LOGICAL:
 274       return "tg4_logical";
 275    case SHADER_OPCODE_TG4_OFFSET:
 276       return "tg4_offset";
 277    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 278       return "tg4_offset_logical";
 279    case SHADER_OPCODE_SAMPLEINFO:
 280       return "sampleinfo";
 281    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 282       return "sampleinfo_logical";
 283
 284    case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
 285       return "image_size_logical";
 286
 287    case SHADER_OPCODE_SHADER_TIME_ADD:
 288       return "shader_time_add";
 289
 290    case VEC4_OPCODE_UNTYPED_ATOMIC:
 291       return "untyped_atomic";
 292    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 293       return "untyped_atomic_logical";
 294    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 295       return "untyped_atomic_float_logical";
 296    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
 297       return "untyped_surface_read";
 298    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 299       return "untyped_surface_read_logical";
 300    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
 301       return "untyped_surface_write";
 302    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 303       return "untyped_surface_write_logical";
 304    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
 305       return "a64_untyped_read_logical";
 306    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
 307       return "a64_untyped_write_logical";
 308    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
 309       return "a64_byte_scattered_read_logical";
 310    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
 311       return "a64_byte_scattered_write_logical";
 312    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
 313       return "a64_untyped_atomic_logical";
 314    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
 315       return "a64_untyped_atomic_int64_logical";
 316    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 317       return "a64_untyped_atomic_float_logical";
 318    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 319       return "typed_atomic_logical";
 320    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 321       return "typed_surface_read_logical";
 322    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 323       return "typed_surface_write_logical";
 324    case SHADER_OPCODE_MEMORY_FENCE:
 325       return "memory_fence";
 326    case SHADER_OPCODE_INTERLOCK:
 327       /* For an interlock we actually issue a memory fence via sendc. */
 328       return "interlock";
 329
 330    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 331       return "byte_scattered_read_logical";
 332    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 333       return "byte_scattered_write_logical";
 334
 335    case SHADER_OPCODE_LOAD_PAYLOAD:
 336       return "load_payload";
 337    case FS_OPCODE_PACK:
 338       return "pack";
 339
 340    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 341       return "gen4_scratch_read";
 342    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 343       return "gen4_scratch_write";
 344    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 345       return "gen7_scratch_read";
 346    case SHADER_OPCODE_URB_WRITE_SIMD8:
 347       return "gen8_urb_write_simd8";
 348    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 349       return "gen8_urb_write_simd8_per_slot";
 350    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 351       return "gen8_urb_write_simd8_masked";
 352    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 353       return "gen8_urb_write_simd8_masked_per_slot";
 354    case SHADER_OPCODE_URB_READ_SIMD8:
 355       return "urb_read_simd8";
 356    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 357       return "urb_read_simd8_per_slot";
 358
 359    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 360       return "find_live_channel";
 361    case SHADER_OPCODE_BROADCAST:
 362       return "broadcast";
 363    case SHADER_OPCODE_SHUFFLE:
 364       return "shuffle";
 365    case SHADER_OPCODE_SEL_EXEC:
 366       return "sel_exec";
 367    case SHADER_OPCODE_QUAD_SWIZZLE:
 368       return "quad_swizzle";
 369    case SHADER_OPCODE_CLUSTER_BROADCAST:
 370       return "cluster_broadcast";
 371
 372    case SHADER_OPCODE_GET_BUFFER_SIZE:
 373       return "get_buffer_size";
 374
 375    case VEC4_OPCODE_MOV_BYTES:
 376       return "mov_bytes";
 377    case VEC4_OPCODE_PACK_BYTES:
 378       return "pack_bytes";
 379    case VEC4_OPCODE_UNPACK_UNIFORM:
 380       return "unpack_uniform";
 381    case VEC4_OPCODE_DOUBLE_TO_F32:
 382       return "double_to_f32";
 383    case VEC4_OPCODE_DOUBLE_TO_D32:
 384       return "double_to_d32";
 385    case VEC4_OPCODE_DOUBLE_TO_U32:
 386       return "double_to_u32";
 387    case VEC4_OPCODE_TO_DOUBLE:
 388       return "single_to_double";
 389    case VEC4_OPCODE_PICK_LOW_32BIT:
 390       return "pick_low_32bit";
 391    case VEC4_OPCODE_PICK_HIGH_32BIT:
 392       return "pick_high_32bit";
 393    case VEC4_OPCODE_SET_LOW_32BIT:
 394       return "set_low_32bit";
 395    case VEC4_OPCODE_SET_HIGH_32BIT:
 396       return "set_high_32bit";
 397
 398    case FS_OPCODE_DDX_COARSE:
 399       return "ddx_coarse";
 400    case FS_OPCODE_DDX_FINE:
 401       return "ddx_fine";
 402    case FS_OPCODE_DDY_COARSE:
 403       return "ddy_coarse";
 404    case FS_OPCODE_DDY_FINE:
 405       return "ddy_fine";
 406
 407    case FS_OPCODE_LINTERP:
 408       return "linterp";
 409
 410    case FS_OPCODE_PIXEL_X:
 411       return "pixel_x";
 412    case FS_OPCODE_PIXEL_Y:
 413       return "pixel_y";
 414
 415    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 416       return "uniform_pull_const";
 417    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 418       return "uniform_pull_const_gen7";
 419    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 420       return "varying_pull_const_gen4";
 421    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 422       return "varying_pull_const_logical";
 423
 424    case FS_OPCODE_DISCARD_JUMP:
 425       return "discard_jump";
 426
 427    case FS_OPCODE_SET_SAMPLE_ID:
 428       return "set_sample_id";
 429
 430    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 431       return "pack_half_2x16_split";
 432
 433    case FS_OPCODE_PLACEHOLDER_HALT:
 434       return "placeholder_halt";
 435
 436    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 437       return "interp_sample";
 438    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 439       return "interp_shared_offset";
 440    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 441       return "interp_per_slot_offset";
 442
 443    case VS_OPCODE_URB_WRITE:
 444       return "vs_urb_write";
 445    case VS_OPCODE_PULL_CONSTANT_LOAD:
 446       return "pull_constant_load";
 447    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 448       return "pull_constant_load_gen7";
 449
 450    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 451       return "set_simd4x2_header_gen9";
 452
 453    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 454       return "unpack_flags_simd4x2";
 455
 456    case GS_OPCODE_URB_WRITE:
 457       return "gs_urb_write";
 458    case GS_OPCODE_URB_WRITE_ALLOCATE:
 459       return "gs_urb_write_allocate";
 460    case GS_OPCODE_THREAD_END:
 461       return "gs_thread_end";
 462    case GS_OPCODE_SET_WRITE_OFFSET:
 463       return "set_write_offset";
 464    case GS_OPCODE_SET_VERTEX_COUNT:
 465       return "set_vertex_count";
 466    case GS_OPCODE_SET_DWORD_2:
 467       return "set_dword_2";
 468    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 469       return "prepare_channel_masks";
 470    case GS_OPCODE_SET_CHANNEL_MASKS:
 471       return "set_channel_masks";
 472    case GS_OPCODE_GET_INSTANCE_ID:
 473       return "get_instance_id";
 474    case GS_OPCODE_FF_SYNC:
 475       return "ff_sync";
 476    case GS_OPCODE_SET_PRIMITIVE_ID:
 477       return "set_primitive_id";
 478    case GS_OPCODE_SVB_WRITE:
 479       return "gs_svb_write";
 480    case GS_OPCODE_SVB_SET_DST_INDEX:
 481       return "gs_svb_set_dst_index";
 482    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 483       return "gs_ff_sync_set_primitives";
 484    case CS_OPCODE_CS_TERMINATE:
 485       return "cs_terminate";
 486    case SHADER_OPCODE_BARRIER:
 487       return "barrier";
 488    case SHADER_OPCODE_MULH:
 489       return "mulh";
 490    case SHADER_OPCODE_MOV_INDIRECT:
 491       return "mov_indirect";
 492
 493    case VEC4_OPCODE_URB_READ:
 494       return "urb_read";
 495    case TCS_OPCODE_GET_INSTANCE_ID:
 496       return "tcs_get_instance_id";
 497    case TCS_OPCODE_URB_WRITE:
 498       return "tcs_urb_write";
 499    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 500       return "tcs_set_input_urb_offsets";
 501    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 502       return "tcs_set_output_urb_offsets";
 503    case TCS_OPCODE_GET_PRIMITIVE_ID:
 504       return "tcs_get_primitive_id";
 505    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 506       return "tcs_create_barrier_header";
 507    case TCS_OPCODE_SRC0_010_IS_ZERO:
 508       return "tcs_src0<0,1,0>_is_zero";
 509    case TCS_OPCODE_RELEASE_INPUT:
 510       return "tcs_release_input";
 511    case TCS_OPCODE_THREAD_END:
 512       return "tcs_thread_end";
 513    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 514       return "tes_create_input_read_header";
 515    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 516       return "tes_add_indirect_urb_offset";
 517    case TES_OPCODE_GET_PRIMITIVE_ID:
 518       return "tes_get_primitive_id";
 519
 520    case SHADER_OPCODE_RND_MODE:
 521       return "rnd_mode";
 522    }
 523
 524    unreachable("not reached");
 525 }
 526
 527 bool
 528 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 529 {
 530    union {
 531       unsigned ud;
 532       int d;
 533       float f;
 534       double df;
 535    } imm, sat_imm = { 0 };
 536
 537    const unsigned size = type_sz(type);
 538
 539    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 540     * irrelevant, so just check the size of the type and copy from/to an
 541     * appropriately sized field.
 542     */
 543    if (size < 8)
 544       imm.ud = reg->ud;
 545    else
 546       imm.df = reg->df;
 547
 548    switch (type) {
 549    case BRW_REGISTER_TYPE_UD:
 550    case BRW_REGISTER_TYPE_D:
 551    case BRW_REGISTER_TYPE_UW:
 552    case BRW_REGISTER_TYPE_W:
 553    case BRW_REGISTER_TYPE_UQ:
 554    case BRW_REGISTER_TYPE_Q:
 555       /* Nothing to do. */
 556       return false;
 557    case BRW_REGISTER_TYPE_F:
 558       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 559       break;
 560    case BRW_REGISTER_TYPE_DF:
 561       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 562       break;
 563    case BRW_REGISTER_TYPE_UB:
 564    case BRW_REGISTER_TYPE_B:
 565       unreachable("no UB/B immediates");
 566    case BRW_REGISTER_TYPE_V:
 567    case BRW_REGISTER_TYPE_UV:
 568    case BRW_REGISTER_TYPE_VF:
 569       unreachable("unimplemented: saturate vector immediate");
 570    case BRW_REGISTER_TYPE_HF:
 571       unreachable("unimplemented: saturate HF immediate");
 572    case BRW_REGISTER_TYPE_NF:
 573       unreachable("no NF immediates");
 574    }
 575
 576    if (size < 8) {
 577       if (imm.ud != sat_imm.ud) {
 578          reg->ud = sat_imm.ud;
 579          return true;
 580       }
 581    } else {
 582       if (imm.df != sat_imm.df) {
 583          reg->df = sat_imm.df;
 584          return true;
 585       }
 586    }
 587    return false;
 588 }
 589
 590 bool
 591 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 592 {
 593    switch (type) {
 594    case BRW_REGISTER_TYPE_D:
 595    case BRW_REGISTER_TYPE_UD:
 596       reg->d = -reg->d;
 597       return true;
 598    case BRW_REGISTER_TYPE_W:
 599    case BRW_REGISTER_TYPE_UW: {
 600       uint16_t value = -(int16_t)reg->ud;
 601       reg->ud = value | (uint32_t)value << 16;
 602       return true;
 603    }
 604    case BRW_REGISTER_TYPE_F:
 605       reg->f = -reg->f;
 606       return true;
 607    case BRW_REGISTER_TYPE_VF:
 608       reg->ud ^= 0x80808080;
 609       return true;
 610    case BRW_REGISTER_TYPE_DF:
 611       reg->df = -reg->df;
 612       return true;
 613    case BRW_REGISTER_TYPE_UQ:
 614    case BRW_REGISTER_TYPE_Q:
 615       reg->d64 = -reg->d64;
 616       return true;
 617    case BRW_REGISTER_TYPE_UB:
 618    case BRW_REGISTER_TYPE_B:
 619       unreachable("no UB/B immediates");
 620    case BRW_REGISTER_TYPE_UV:
 621    case BRW_REGISTER_TYPE_V:
 622       assert(!"unimplemented: negate UV/V immediate");
 623    case BRW_REGISTER_TYPE_HF:
 624       reg->ud ^= 0x80008000;
 625       return true;
 626    case BRW_REGISTER_TYPE_NF:
 627       unreachable("no NF immediates");
 628    }
 629
 630    return false;
 631 }
 632
 633 bool
 634 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 635 {
 636    switch (type) {
 637    case BRW_REGISTER_TYPE_D:
 638       reg->d = abs(reg->d);
 639       return true;
 640    case BRW_REGISTER_TYPE_W: {
 641       uint16_t value = abs((int16_t)reg->ud);
 642       reg->ud = value | (uint32_t)value << 16;
 643       return true;
 644    }
 645    case BRW_REGISTER_TYPE_F:
 646       reg->f = fabsf(reg->f);
 647       return true;
 648    case BRW_REGISTER_TYPE_DF:
 649       reg->df = fabs(reg->df);
 650       return true;
 651    case BRW_REGISTER_TYPE_VF:
 652       reg->ud &= ~0x80808080;
 653       return true;
 654    case BRW_REGISTER_TYPE_Q:
 655       reg->d64 = imaxabs(reg->d64);
 656       return true;
 657    case BRW_REGISTER_TYPE_UB:
 658    case BRW_REGISTER_TYPE_B:
 659       unreachable("no UB/B immediates");
 660    case BRW_REGISTER_TYPE_UQ:
 661    case BRW_REGISTER_TYPE_UD:
 662    case BRW_REGISTER_TYPE_UW:
 663    case BRW_REGISTER_TYPE_UV:
 664       /* Presumably the absolute value modifier on an unsigned source is a
 665        * nop, but it would be nice to confirm.
 666        */
 667       assert(!"unimplemented: abs unsigned immediate");
 668    case BRW_REGISTER_TYPE_V:
 669       assert(!"unimplemented: abs V immediate");
 670    case BRW_REGISTER_TYPE_HF:
 671       reg->ud &= ~0x80008000;
 672       return true;
 673    case BRW_REGISTER_TYPE_NF:
 674       unreachable("no NF immediates");
 675    }
 676
 677    return false;
 678 }
 679
 680 backend_shader::backend_shader(const struct brw_compiler *compiler,
 681                                void *log_data,
 682                                void *mem_ctx,
 683                                const nir_shader *shader,
 684                                struct brw_stage_prog_data *stage_prog_data)
 685    : compiler(compiler),
 686      log_data(log_data),
 687      devinfo(compiler->devinfo),
 688      nir(shader),
 689      stage_prog_data(stage_prog_data),
 690      mem_ctx(mem_ctx),
 691      cfg(NULL),
 692      stage(shader->info.stage)
 693 {
 694    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 695    stage_name = _mesa_shader_stage_to_string(stage);
 696    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 697 }
 698
 699 backend_shader::~backend_shader()
 700 {
 701 }
 702
 703 bool
 704 backend_reg::equals(const backend_reg &r) const
 705 {
 706    return brw_regs_equal(this, &r) && offset == r.offset;
 707 }
 708
 709 bool
 710 backend_reg::negative_equals(const backend_reg &r) const
 711 {
 712    return brw_regs_negative_equal(this, &r) && offset == r.offset;
 713 }
 714
 715 bool
 716 backend_reg::is_zero() const
 717 {
 718    if (file != IMM)
 719       return false;
 720
 721    assert(type_sz(type) > 1);
 722
 723    switch (type) {
 724    case BRW_REGISTER_TYPE_HF:
 725       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 726       return (d & 0xffff) == 0 || (d & 0xffff) == 0x8000;
 727    case BRW_REGISTER_TYPE_F:
 728       return f == 0;
 729    case BRW_REGISTER_TYPE_DF:
 730       return df == 0;
 731    case BRW_REGISTER_TYPE_W:
 732    case BRW_REGISTER_TYPE_UW:
 733       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 734       return (d & 0xffff) == 0;
 735    case BRW_REGISTER_TYPE_D:
 736    case BRW_REGISTER_TYPE_UD:
 737       return d == 0;
 738    case BRW_REGISTER_TYPE_UQ:
 739    case BRW_REGISTER_TYPE_Q:
 740       return u64 == 0;
 741    default:
 742       return false;
 743    }
 744 }
 745
 746 bool
 747 backend_reg::is_one() const
 748 {
 749    if (file != IMM)
 750       return false;
 751
 752    assert(type_sz(type) > 1);
 753
 754    switch (type) {
 755    case BRW_REGISTER_TYPE_HF:
 756       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 757       return (d & 0xffff) == 0x3c00;
 758    case BRW_REGISTER_TYPE_F:
 759       return f == 1.0f;
 760    case BRW_REGISTER_TYPE_DF:
 761       return df == 1.0;
 762    case BRW_REGISTER_TYPE_W:
 763    case BRW_REGISTER_TYPE_UW:
 764       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 765       return (d & 0xffff) == 1;
 766    case BRW_REGISTER_TYPE_D:
 767    case BRW_REGISTER_TYPE_UD:
 768       return d == 1;
 769    case BRW_REGISTER_TYPE_UQ:
 770    case BRW_REGISTER_TYPE_Q:
 771       return u64 == 1;
 772    default:
 773       return false;
 774    }
 775 }
 776
 777 bool
 778 backend_reg::is_negative_one() const
 779 {
 780    if (file != IMM)
 781       return false;
 782
 783    assert(type_sz(type) > 1);
 784
 785    switch (type) {
 786    case BRW_REGISTER_TYPE_HF:
 787       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 788       return (d & 0xffff) == 0xbc00;
 789    case BRW_REGISTER_TYPE_F:
 790       return f == -1.0;
 791    case BRW_REGISTER_TYPE_DF:
 792       return df == -1.0;
 793    case BRW_REGISTER_TYPE_W:
 794       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 795       return (d & 0xffff) == 0xffff;
 796    case BRW_REGISTER_TYPE_D:
 797       return d == -1;
 798    case BRW_REGISTER_TYPE_Q:
 799       return d64 == -1;
 800    default:
 801       return false;
 802    }
 803 }
 804
 805 bool
 806 backend_reg::is_null() const
 807 {
 808    return file == ARF && nr == BRW_ARF_NULL;
 809 }
 810
 811
 812 bool
 813 backend_reg::is_accumulator() const
 814 {
 815    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 816 }
 817
 818 bool
 819 backend_instruction::is_commutative() const
 820 {
 821    switch (opcode) {
 822    case BRW_OPCODE_AND:
 823    case BRW_OPCODE_OR:
 824    case BRW_OPCODE_XOR:
 825    case BRW_OPCODE_ADD:
 826    case BRW_OPCODE_MUL:
 827    case SHADER_OPCODE_MULH:
 828       return true;
 829    case BRW_OPCODE_SEL:
 830       /* MIN and MAX are commutative. */
 831       if (conditional_mod == BRW_CONDITIONAL_GE ||
 832           conditional_mod == BRW_CONDITIONAL_L) {
 833          return true;
 834       }
 835       /* fallthrough */
 836    default:
 837       return false;
 838    }
 839 }
 840
 841 bool
 842 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 843 {
 844    return ::is_3src(devinfo, opcode);
 845 }
 846
 847 bool
 848 backend_instruction::is_tex() const
 849 {
 850    return (opcode == SHADER_OPCODE_TEX ||
 851            opcode == FS_OPCODE_TXB ||
 852            opcode == SHADER_OPCODE_TXD ||
 853            opcode == SHADER_OPCODE_TXF ||
 854            opcode == SHADER_OPCODE_TXF_LZ ||
 855            opcode == SHADER_OPCODE_TXF_CMS ||
 856            opcode == SHADER_OPCODE_TXF_CMS_W ||
 857            opcode == SHADER_OPCODE_TXF_UMS ||
 858            opcode == SHADER_OPCODE_TXF_MCS ||
 859            opcode == SHADER_OPCODE_TXL ||
 860            opcode == SHADER_OPCODE_TXL_LZ ||
 861            opcode == SHADER_OPCODE_TXS ||
 862            opcode == SHADER_OPCODE_LOD ||
 863            opcode == SHADER_OPCODE_TG4 ||
 864            opcode == SHADER_OPCODE_TG4_OFFSET ||
 865            opcode == SHADER_OPCODE_SAMPLEINFO);
 866 }
 867
 868 bool
 869 backend_instruction::is_math() const
 870 {
 871    return (opcode == SHADER_OPCODE_RCP ||
 872            opcode == SHADER_OPCODE_RSQ ||
 873            opcode == SHADER_OPCODE_SQRT ||
 874            opcode == SHADER_OPCODE_EXP2 ||
 875            opcode == SHADER_OPCODE_LOG2 ||
 876            opcode == SHADER_OPCODE_SIN ||
 877            opcode == SHADER_OPCODE_COS ||
 878            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 879            opcode == SHADER_OPCODE_INT_REMAINDER ||
 880            opcode == SHADER_OPCODE_POW);
 881 }
 882
 883 bool
 884 backend_instruction::is_control_flow() const
 885 {
 886    switch (opcode) {
 887    case BRW_OPCODE_DO:
 888    case BRW_OPCODE_WHILE:
 889    case BRW_OPCODE_IF:
 890    case BRW_OPCODE_ELSE:
 891    case BRW_OPCODE_ENDIF:
 892    case BRW_OPCODE_BREAK:
 893    case BRW_OPCODE_CONTINUE:
 894       return true;
 895    default:
 896       return false;
 897    }
 898 }
 899
 900 bool
 901 backend_instruction::can_do_source_mods() const
 902 {
 903    switch (opcode) {
 904    case BRW_OPCODE_ADDC:
 905    case BRW_OPCODE_BFE:
 906    case BRW_OPCODE_BFI1:
 907    case BRW_OPCODE_BFI2:
 908    case BRW_OPCODE_BFREV:
 909    case BRW_OPCODE_CBIT:
 910    case BRW_OPCODE_FBH:
 911    case BRW_OPCODE_FBL:
 912    case BRW_OPCODE_SUBB:
 913    case SHADER_OPCODE_BROADCAST:
 914    case SHADER_OPCODE_CLUSTER_BROADCAST:
 915    case SHADER_OPCODE_MOV_INDIRECT:
 916       return false;
 917    default:
 918       return true;
 919    }
 920 }
 921
 922 bool
 923 backend_instruction::can_do_saturate() const
 924 {
 925    switch (opcode) {
 926    case BRW_OPCODE_ADD:
 927    case BRW_OPCODE_ASR:
 928    case BRW_OPCODE_AVG:
 929    case BRW_OPCODE_DP2:
 930    case BRW_OPCODE_DP3:
 931    case BRW_OPCODE_DP4:
 932    case BRW_OPCODE_DPH:
 933    case BRW_OPCODE_F16TO32:
 934    case BRW_OPCODE_F32TO16:
 935    case BRW_OPCODE_LINE:
 936    case BRW_OPCODE_LRP:
 937    case BRW_OPCODE_MAC:
 938    case BRW_OPCODE_MAD:
 939    case BRW_OPCODE_MATH:
 940    case BRW_OPCODE_MOV:
 941    case BRW_OPCODE_MUL:
 942    case SHADER_OPCODE_MULH:
 943    case BRW_OPCODE_PLN:
 944    case BRW_OPCODE_RNDD:
 945    case BRW_OPCODE_RNDE:
 946    case BRW_OPCODE_RNDU:
 947    case BRW_OPCODE_RNDZ:
 948    case BRW_OPCODE_SEL:
 949    case BRW_OPCODE_SHL:
 950    case BRW_OPCODE_SHR:
 951    case FS_OPCODE_LINTERP:
 952    case SHADER_OPCODE_COS:
 953    case SHADER_OPCODE_EXP2:
 954    case SHADER_OPCODE_LOG2:
 955    case SHADER_OPCODE_POW:
 956    case SHADER_OPCODE_RCP:
 957    case SHADER_OPCODE_RSQ:
 958    case SHADER_OPCODE_SIN:
 959    case SHADER_OPCODE_SQRT:
 960       return true;
 961    default:
 962       return false;
 963    }
 964 }
 965
 966 bool
 967 backend_instruction::can_do_cmod() const
 968 {
 969    switch (opcode) {
 970    case BRW_OPCODE_ADD:
 971    case BRW_OPCODE_ADDC:
 972    case BRW_OPCODE_AND:
 973    case BRW_OPCODE_ASR:
 974    case BRW_OPCODE_AVG:
 975    case BRW_OPCODE_CMP:
 976    case BRW_OPCODE_CMPN:
 977    case BRW_OPCODE_DP2:
 978    case BRW_OPCODE_DP3:
 979    case BRW_OPCODE_DP4:
 980    case BRW_OPCODE_DPH:
 981    case BRW_OPCODE_F16TO32:
 982    case BRW_OPCODE_F32TO16:
 983    case BRW_OPCODE_FRC:
 984    case BRW_OPCODE_LINE:
 985    case BRW_OPCODE_LRP:
 986    case BRW_OPCODE_LZD:
 987    case BRW_OPCODE_MAC:
 988    case BRW_OPCODE_MACH:
 989    case BRW_OPCODE_MAD:
 990    case BRW_OPCODE_MOV:
 991    case BRW_OPCODE_MUL:
 992    case BRW_OPCODE_NOT:
 993    case BRW_OPCODE_OR:
 994    case BRW_OPCODE_PLN:
 995    case BRW_OPCODE_RNDD:
 996    case BRW_OPCODE_RNDE:
 997    case BRW_OPCODE_RNDU:
 998    case BRW_OPCODE_RNDZ:
 999    case BRW_OPCODE_SAD2:
1000    case BRW_OPCODE_SADA2:
1001    case BRW_OPCODE_SHL:
1002    case BRW_OPCODE_SHR:
1003    case BRW_OPCODE_SUBB:
1004    case BRW_OPCODE_XOR:
1005    case FS_OPCODE_LINTERP:
1006       return true;
1007    default:
1008       return false;
1009    }
1010 }
1011
1012 bool
1013 backend_instruction::reads_accumulator_implicitly() const
1014 {
1015    switch (opcode) {
1016    case BRW_OPCODE_MAC:
1017    case BRW_OPCODE_MACH:
1018    case BRW_OPCODE_SADA2:
1019       return true;
1020    default:
1021       return false;
1022    }
1023 }
1024
1025 bool
1026 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
1027 {
1028    return writes_accumulator ||
1029           (devinfo->gen < 6 &&
1030            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1031             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
1032           (opcode == FS_OPCODE_LINTERP &&
1033            (!devinfo->has_pln || devinfo->gen <= 6));
1034 }
1035
1036 bool
1037 backend_instruction::has_side_effects() const
1038 {
1039    switch (opcode) {
1040    case SHADER_OPCODE_SEND:
1041       return send_has_side_effects;
1042
1043    case VEC4_OPCODE_UNTYPED_ATOMIC:
1044    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1045    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1046    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1047    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
1048    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1049    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
1050    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
1051    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
1052    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
1053    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1054    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1055    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1056    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1057    case SHADER_OPCODE_MEMORY_FENCE:
1058    case SHADER_OPCODE_INTERLOCK:
1059    case SHADER_OPCODE_URB_WRITE_SIMD8:
1060    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1061    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1062    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1063    case FS_OPCODE_FB_WRITE:
1064    case FS_OPCODE_FB_WRITE_LOGICAL:
1065    case FS_OPCODE_REP_FB_WRITE:
1066    case SHADER_OPCODE_BARRIER:
1067    case TCS_OPCODE_URB_WRITE:
1068    case TCS_OPCODE_RELEASE_INPUT:
1069    case SHADER_OPCODE_RND_MODE:
1070       return true;
1071    default:
1072       return eot;
1073    }
1074 }
1075
1076 bool
1077 backend_instruction::is_volatile() const
1078 {
1079    switch (opcode) {
1080    case SHADER_OPCODE_SEND:
1081       return send_is_volatile;
1082
1083    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
1084    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1085    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1086    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1087    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
1088    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
1089    case SHADER_OPCODE_URB_READ_SIMD8:
1090    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1091    case VEC4_OPCODE_URB_READ:
1092       return true;
1093    default:
1094       return false;
1095    }
1096 }
1097
1098 #ifndef NDEBUG
1099 static bool
1100 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1101 {
1102    bool found = false;
1103    foreach_inst_in_block (backend_instruction, i, block) {
1104       if (inst == i) {
1105          found = true;
1106       }
1107    }
1108    return found;
1109 }
1110 #endif
1111
1112 static void
1113 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1114 {
1115    for (bblock_t *block_iter = start_block->next();
1116         block_iter;
1117         block_iter = block_iter->next()) {
1118       block_iter->start_ip += ip_adjustment;
1119       block_iter->end_ip += ip_adjustment;
1120    }
1121 }
1122
1123 void
1124 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1125 {
1126    assert(this != inst);
1127
1128    if (!this->is_head_sentinel())
1129       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1130
1131    block->end_ip++;
1132
1133    adjust_later_block_ips(block, 1);
1134
1135    exec_node::insert_after(inst);
1136 }
1137
1138 void
1139 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1140 {
1141    assert(this != inst);
1142
1143    if (!this->is_tail_sentinel())
1144       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1145
1146    block->end_ip++;
1147
1148    adjust_later_block_ips(block, 1);
1149
1150    exec_node::insert_before(inst);
1151 }
1152
1153 void
1154 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1155 {
1156    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1157
1158    unsigned num_inst = list->length();
1159
1160    block->end_ip += num_inst;
1161
1162    adjust_later_block_ips(block, num_inst);
1163
1164    exec_node::insert_before(list);
1165 }
1166
1167 void
1168 backend_instruction::remove(bblock_t *block)
1169 {
1170    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1171
1172    adjust_later_block_ips(block, -1);
1173
1174    if (block->start_ip == block->end_ip) {
1175       block->cfg->remove_block(block);
1176    } else {
1177       block->end_ip--;
1178    }
1179
1180    exec_node::remove();
1181 }
1182
1183 void
1184 backend_shader::dump_instructions()
1185 {
1186    dump_instructions(NULL);
1187 }
1188
1189 void
1190 backend_shader::dump_instructions(const char *name)
1191 {
1192    FILE *file = stderr;
1193    if (name && geteuid() != 0) {
1194       file = fopen(name, "w");
1195       if (!file)
1196          file = stderr;
1197    }
1198
1199    if (cfg) {
1200       int ip = 0;
1201       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1202          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1203             fprintf(file, "%4d: ", ip++);
1204          dump_instruction(inst, file);
1205       }
1206    } else {
1207       int ip = 0;
1208       foreach_in_list(backend_instruction, inst, &instructions) {
1209          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1210             fprintf(file, "%4d: ", ip++);
1211          dump_instruction(inst, file);
1212       }
1213    }
1214
1215    if (file != stderr) {
1216       fclose(file);
1217    }
1218 }
1219
1220 void
1221 backend_shader::calculate_cfg()
1222 {
1223    if (this->cfg)
1224       return;
1225    cfg = new(mem_ctx) cfg_t(&this->instructions);
1226 }
1227
1228 extern "C" const unsigned *
1229 brw_compile_tes(const struct brw_compiler *compiler,
1230                 void *log_data,
1231                 void *mem_ctx,
1232                 const struct brw_tes_prog_key *key,
1233                 const struct brw_vue_map *input_vue_map,
1234                 struct brw_tes_prog_data *prog_data,
1235                 nir_shader *nir,
1236                 struct gl_program *prog,
1237                 int shader_time_index,
1238                 char **error_str)
1239 {
1240    const struct gen_device_info *devinfo = compiler->devinfo;
1241    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1242    const unsigned *assembly;
1243
1244    nir->info.inputs_read = key->inputs_read;
1245    nir->info.patch_inputs_read = key->patch_inputs_read;
1246
1247    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1248    brw_nir_lower_tes_inputs(nir, input_vue_map);
1249    brw_nir_lower_vue_outputs(nir);
1250    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1251
1252    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1253                        nir->info.outputs_written,
1254                        nir->info.separate_shader);
1255
1256    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1257
1258    assert(output_size_bytes >= 1);
1259    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1260       if (error_str)
1261          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1262       return NULL;
1263    }
1264
1265    prog_data->base.clip_distance_mask =
1266       ((1 << nir->info.clip_distance_array_size) - 1);
1267    prog_data->base.cull_distance_mask =
1268       ((1 << nir->info.cull_distance_array_size) - 1) <<
1269       nir->info.clip_distance_array_size;
1270
1271    /* URB entry sizes are stored as a multiple of 64 bytes. */
1272    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1273
1274    /* On Cannonlake software shall not program an allocation size that
1275     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1276     */
1277    if (devinfo->gen == 10 &&
1278        prog_data->base.urb_entry_size % 3 == 0)
1279       prog_data->base.urb_entry_size++;
1280
1281    prog_data->base.urb_read_length = 0;
1282
1283    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1284    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1285                  TESS_SPACING_FRACTIONAL_ODD - 1);
1286    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1287                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1288
1289    prog_data->partitioning =
1290       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1291
1292    switch (nir->info.tess.primitive_mode) {
1293    case GL_QUADS:
1294       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1295       break;
1296    case GL_TRIANGLES:
1297       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1298       break;
1299    case GL_ISOLINES:
1300       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1301       break;
1302    default:
1303       unreachable("invalid domain shader primitive mode");
1304    }
1305
1306    if (nir->info.tess.point_mode) {
1307       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1308    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1309       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1310    } else {
1311       /* Hardware winding order is backwards from OpenGL */
1312       prog_data->output_topology =
1313          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1314                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1315    }
1316
1317    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1318       fprintf(stderr, "TES Input ");
1319       brw_print_vue_map(stderr, input_vue_map);
1320       fprintf(stderr, "TES Output ");
1321       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1322    }
1323
1324    if (is_scalar) {
1325       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1326                    &prog_data->base.base, NULL, nir, 8,
1327                    shader_time_index, input_vue_map);
1328       if (!v.run_tes()) {
1329          if (error_str)
1330             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1331          return NULL;
1332       }
1333
1334       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1335       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1336
1337       fs_generator g(compiler, log_data, mem_ctx,
1338                      &prog_data->base.base, v.promoted_constants, false,
1339                      MESA_SHADER_TESS_EVAL);
1340       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1341          g.enable_debug(ralloc_asprintf(mem_ctx,
1342                                         "%s tessellation evaluation shader %s",
1343                                         nir->info.label ? nir->info.label
1344                                                         : "unnamed",
1345                                         nir->info.name));
1346       }
1347
1348       g.generate_code(v.cfg, 8);
1349
1350       assembly = g.get_assembly();
1351    } else {
1352       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1353                               nir, mem_ctx, shader_time_index);
1354       if (!v.run()) {
1355          if (error_str)
1356             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1357          return NULL;
1358       }
1359
1360       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1361          v.dump_instructions();
1362
1363       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1364                                             &prog_data->base, v.cfg);
1365    }
1366
1367    return assembly;
1368 }