src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "common/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_INT8:
  48       return BRW_REGISTER_TYPE_B;
  49    case GLSL_TYPE_UINT:
  50       return BRW_REGISTER_TYPE_UD;
  51    case GLSL_TYPE_UINT16:
  52       return BRW_REGISTER_TYPE_UW;
  53    case GLSL_TYPE_UINT8:
  54       return BRW_REGISTER_TYPE_UB;
  55    case GLSL_TYPE_ARRAY:
  56       return brw_type_for_base_type(type->fields.array);
  57    case GLSL_TYPE_STRUCT:
  58    case GLSL_TYPE_SAMPLER:
  59    case GLSL_TYPE_ATOMIC_UINT:
  60       /* These should be overridden with the type of the member when
  61        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  62        * way to trip up if we don't.
  63        */
  64       return BRW_REGISTER_TYPE_UD;
  65    case GLSL_TYPE_IMAGE:
  66       return BRW_REGISTER_TYPE_UD;
  67    case GLSL_TYPE_DOUBLE:
  68       return BRW_REGISTER_TYPE_DF;
  69    case GLSL_TYPE_UINT64:
  70       return BRW_REGISTER_TYPE_UQ;
  71    case GLSL_TYPE_INT64:
  72       return BRW_REGISTER_TYPE_Q;
  73    case GLSL_TYPE_VOID:
  74    case GLSL_TYPE_ERROR:
  75    case GLSL_TYPE_INTERFACE:
  76    case GLSL_TYPE_FUNCTION:
  77       unreachable("not reached");
  78    }
  79
  80    return BRW_REGISTER_TYPE_F;
  81 }
  82
  83 enum brw_conditional_mod
  84 brw_conditional_for_comparison(unsigned int op)
  85 {
  86    switch (op) {
  87    case ir_binop_less:
  88       return BRW_CONDITIONAL_L;
  89    case ir_binop_gequal:
  90       return BRW_CONDITIONAL_GE;
  91    case ir_binop_equal:
  92    case ir_binop_all_equal: /* same as equal for scalars */
  93       return BRW_CONDITIONAL_Z;
  94    case ir_binop_nequal:
  95    case ir_binop_any_nequal: /* same as nequal for scalars */
  96       return BRW_CONDITIONAL_NZ;
  97    default:
  98       unreachable("not reached: bad operation for comparison");
  99    }
 100 }
 101
 102 uint32_t
 103 brw_math_function(enum opcode op)
 104 {
 105    switch (op) {
 106    case SHADER_OPCODE_RCP:
 107       return BRW_MATH_FUNCTION_INV;
 108    case SHADER_OPCODE_RSQ:
 109       return BRW_MATH_FUNCTION_RSQ;
 110    case SHADER_OPCODE_SQRT:
 111       return BRW_MATH_FUNCTION_SQRT;
 112    case SHADER_OPCODE_EXP2:
 113       return BRW_MATH_FUNCTION_EXP;
 114    case SHADER_OPCODE_LOG2:
 115       return BRW_MATH_FUNCTION_LOG;
 116    case SHADER_OPCODE_POW:
 117       return BRW_MATH_FUNCTION_POW;
 118    case SHADER_OPCODE_SIN:
 119       return BRW_MATH_FUNCTION_SIN;
 120    case SHADER_OPCODE_COS:
 121       return BRW_MATH_FUNCTION_COS;
 122    case SHADER_OPCODE_INT_QUOTIENT:
 123       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 124    case SHADER_OPCODE_INT_REMAINDER:
 125       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 126    default:
 127       unreachable("not reached: unknown math function");
 128    }
 129 }
 130
 131 bool
 132 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 133 {
 134    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 135
 136    /* offset out of bounds; caller will handle it. */
 137    for (unsigned i = 0; i < num_components; i++)
 138       if (offsets[i] > 7 || offsets[i] < -8)
 139          return false;
 140
 141    /* Combine all three offsets into a single unsigned dword:
 142     *
 143     *    bits 11:8 - U Offset (X component)
 144     *    bits  7:4 - V Offset (Y component)
 145     *    bits  3:0 - R Offset (Z component)
 146     */
 147    *offset_bits = 0;
 148    for (unsigned i = 0; i < num_components; i++) {
 149       const unsigned shift = 4 * (2 - i);
 150       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 151    }
 152    return true;
 153 }
 154
 155 const char *
 156 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 157 {
 158    switch (op) {
 159    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 160       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 161        * start of a loop in the IR.
 162        */
 163       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 164          return "do";
 165
 166       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 167        * then to mark that we want to do the conversion.
 168        */
 169       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 170          return "f32to16";
 171
 172       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 173          return "f16to32";
 174
 175       assert(brw_opcode_desc(devinfo, op)->name);
 176       return brw_opcode_desc(devinfo, op)->name;
 177    case FS_OPCODE_FB_WRITE:
 178       return "fb_write";
 179    case FS_OPCODE_FB_WRITE_LOGICAL:
 180       return "fb_write_logical";
 181    case FS_OPCODE_REP_FB_WRITE:
 182       return "rep_fb_write";
 183    case FS_OPCODE_FB_READ:
 184       return "fb_read";
 185    case FS_OPCODE_FB_READ_LOGICAL:
 186       return "fb_read_logical";
 187
 188    case SHADER_OPCODE_RCP:
 189       return "rcp";
 190    case SHADER_OPCODE_RSQ:
 191       return "rsq";
 192    case SHADER_OPCODE_SQRT:
 193       return "sqrt";
 194    case SHADER_OPCODE_EXP2:
 195       return "exp2";
 196    case SHADER_OPCODE_LOG2:
 197       return "log2";
 198    case SHADER_OPCODE_POW:
 199       return "pow";
 200    case SHADER_OPCODE_INT_QUOTIENT:
 201       return "int_quot";
 202    case SHADER_OPCODE_INT_REMAINDER:
 203       return "int_rem";
 204    case SHADER_OPCODE_SIN:
 205       return "sin";
 206    case SHADER_OPCODE_COS:
 207       return "cos";
 208
 209    case SHADER_OPCODE_SEND:
 210       return "send";
 211
 212    case SHADER_OPCODE_TEX:
 213       return "tex";
 214    case SHADER_OPCODE_TEX_LOGICAL:
 215       return "tex_logical";
 216    case SHADER_OPCODE_TXD:
 217       return "txd";
 218    case SHADER_OPCODE_TXD_LOGICAL:
 219       return "txd_logical";
 220    case SHADER_OPCODE_TXF:
 221       return "txf";
 222    case SHADER_OPCODE_TXF_LOGICAL:
 223       return "txf_logical";
 224    case SHADER_OPCODE_TXF_LZ:
 225       return "txf_lz";
 226    case SHADER_OPCODE_TXL:
 227       return "txl";
 228    case SHADER_OPCODE_TXL_LOGICAL:
 229       return "txl_logical";
 230    case SHADER_OPCODE_TXL_LZ:
 231       return "txl_lz";
 232    case SHADER_OPCODE_TXS:
 233       return "txs";
 234    case SHADER_OPCODE_TXS_LOGICAL:
 235       return "txs_logical";
 236    case FS_OPCODE_TXB:
 237       return "txb";
 238    case FS_OPCODE_TXB_LOGICAL:
 239       return "txb_logical";
 240    case SHADER_OPCODE_TXF_CMS:
 241       return "txf_cms";
 242    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 243       return "txf_cms_logical";
 244    case SHADER_OPCODE_TXF_CMS_W:
 245       return "txf_cms_w";
 246    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 247       return "txf_cms_w_logical";
 248    case SHADER_OPCODE_TXF_UMS:
 249       return "txf_ums";
 250    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 251       return "txf_ums_logical";
 252    case SHADER_OPCODE_TXF_MCS:
 253       return "txf_mcs";
 254    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 255       return "txf_mcs_logical";
 256    case SHADER_OPCODE_LOD:
 257       return "lod";
 258    case SHADER_OPCODE_LOD_LOGICAL:
 259       return "lod_logical";
 260    case SHADER_OPCODE_TG4:
 261       return "tg4";
 262    case SHADER_OPCODE_TG4_LOGICAL:
 263       return "tg4_logical";
 264    case SHADER_OPCODE_TG4_OFFSET:
 265       return "tg4_offset";
 266    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 267       return "tg4_offset_logical";
 268    case SHADER_OPCODE_SAMPLEINFO:
 269       return "sampleinfo";
 270    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 271       return "sampleinfo_logical";
 272
 273    case SHADER_OPCODE_IMAGE_SIZE:
 274       return "image_size";
 275    case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
 276       return "image_size_logical";
 277
 278    case SHADER_OPCODE_SHADER_TIME_ADD:
 279       return "shader_time_add";
 280
 281    case SHADER_OPCODE_UNTYPED_ATOMIC:
 282       return "untyped_atomic";
 283    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 284       return "untyped_atomic_logical";
 285    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT:
 286       return "untyped_atomic_float";
 287    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 288       return "untyped_atomic_float_logical";
 289    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 290       return "untyped_surface_read";
 291    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 292       return "untyped_surface_read_logical";
 293    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 294       return "untyped_surface_write";
 295    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 296       return "untyped_surface_write_logical";
 297    case SHADER_OPCODE_TYPED_ATOMIC:
 298       return "typed_atomic";
 299    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 300       return "typed_atomic_logical";
 301    case SHADER_OPCODE_TYPED_SURFACE_READ:
 302       return "typed_surface_read";
 303    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 304       return "typed_surface_read_logical";
 305    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 306       return "typed_surface_write";
 307    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 308       return "typed_surface_write_logical";
 309    case SHADER_OPCODE_MEMORY_FENCE:
 310       return "memory_fence";
 311    case SHADER_OPCODE_INTERLOCK:
 312       /* For an interlock we actually issue a memory fence via sendc. */
 313       return "interlock";
 314
 315    case SHADER_OPCODE_BYTE_SCATTERED_READ:
 316       return "byte_scattered_read";
 317    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 318       return "byte_scattered_read_logical";
 319    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
 320       return "byte_scattered_write";
 321    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 322       return "byte_scattered_write_logical";
 323
 324    case SHADER_OPCODE_LOAD_PAYLOAD:
 325       return "load_payload";
 326    case FS_OPCODE_PACK:
 327       return "pack";
 328
 329    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 330       return "gen4_scratch_read";
 331    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 332       return "gen4_scratch_write";
 333    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 334       return "gen7_scratch_read";
 335    case SHADER_OPCODE_URB_WRITE_SIMD8:
 336       return "gen8_urb_write_simd8";
 337    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 338       return "gen8_urb_write_simd8_per_slot";
 339    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 340       return "gen8_urb_write_simd8_masked";
 341    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 342       return "gen8_urb_write_simd8_masked_per_slot";
 343    case SHADER_OPCODE_URB_READ_SIMD8:
 344       return "urb_read_simd8";
 345    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 346       return "urb_read_simd8_per_slot";
 347
 348    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 349       return "find_live_channel";
 350    case SHADER_OPCODE_BROADCAST:
 351       return "broadcast";
 352    case SHADER_OPCODE_SHUFFLE:
 353       return "shuffle";
 354    case SHADER_OPCODE_SEL_EXEC:
 355       return "sel_exec";
 356    case SHADER_OPCODE_QUAD_SWIZZLE:
 357       return "quad_swizzle";
 358    case SHADER_OPCODE_CLUSTER_BROADCAST:
 359       return "cluster_broadcast";
 360
 361    case SHADER_OPCODE_GET_BUFFER_SIZE:
 362       return "get_buffer_size";
 363
 364    case VEC4_OPCODE_MOV_BYTES:
 365       return "mov_bytes";
 366    case VEC4_OPCODE_PACK_BYTES:
 367       return "pack_bytes";
 368    case VEC4_OPCODE_UNPACK_UNIFORM:
 369       return "unpack_uniform";
 370    case VEC4_OPCODE_DOUBLE_TO_F32:
 371       return "double_to_f32";
 372    case VEC4_OPCODE_DOUBLE_TO_D32:
 373       return "double_to_d32";
 374    case VEC4_OPCODE_DOUBLE_TO_U32:
 375       return "double_to_u32";
 376    case VEC4_OPCODE_TO_DOUBLE:
 377       return "single_to_double";
 378    case VEC4_OPCODE_PICK_LOW_32BIT:
 379       return "pick_low_32bit";
 380    case VEC4_OPCODE_PICK_HIGH_32BIT:
 381       return "pick_high_32bit";
 382    case VEC4_OPCODE_SET_LOW_32BIT:
 383       return "set_low_32bit";
 384    case VEC4_OPCODE_SET_HIGH_32BIT:
 385       return "set_high_32bit";
 386
 387    case FS_OPCODE_DDX_COARSE:
 388       return "ddx_coarse";
 389    case FS_OPCODE_DDX_FINE:
 390       return "ddx_fine";
 391    case FS_OPCODE_DDY_COARSE:
 392       return "ddy_coarse";
 393    case FS_OPCODE_DDY_FINE:
 394       return "ddy_fine";
 395
 396    case FS_OPCODE_LINTERP:
 397       return "linterp";
 398
 399    case FS_OPCODE_PIXEL_X:
 400       return "pixel_x";
 401    case FS_OPCODE_PIXEL_Y:
 402       return "pixel_y";
 403
 404    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 405       return "uniform_pull_const";
 406    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 407       return "uniform_pull_const_gen7";
 408    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 409       return "varying_pull_const_gen4";
 410    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 411       return "varying_pull_const_gen7";
 412    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 413       return "varying_pull_const_logical";
 414
 415    case FS_OPCODE_DISCARD_JUMP:
 416       return "discard_jump";
 417
 418    case FS_OPCODE_SET_SAMPLE_ID:
 419       return "set_sample_id";
 420
 421    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 422       return "pack_half_2x16_split";
 423
 424    case FS_OPCODE_PLACEHOLDER_HALT:
 425       return "placeholder_halt";
 426
 427    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 428       return "interp_sample";
 429    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 430       return "interp_shared_offset";
 431    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 432       return "interp_per_slot_offset";
 433
 434    case VS_OPCODE_URB_WRITE:
 435       return "vs_urb_write";
 436    case VS_OPCODE_PULL_CONSTANT_LOAD:
 437       return "pull_constant_load";
 438    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 439       return "pull_constant_load_gen7";
 440
 441    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 442       return "set_simd4x2_header_gen9";
 443
 444    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 445       return "unpack_flags_simd4x2";
 446
 447    case GS_OPCODE_URB_WRITE:
 448       return "gs_urb_write";
 449    case GS_OPCODE_URB_WRITE_ALLOCATE:
 450       return "gs_urb_write_allocate";
 451    case GS_OPCODE_THREAD_END:
 452       return "gs_thread_end";
 453    case GS_OPCODE_SET_WRITE_OFFSET:
 454       return "set_write_offset";
 455    case GS_OPCODE_SET_VERTEX_COUNT:
 456       return "set_vertex_count";
 457    case GS_OPCODE_SET_DWORD_2:
 458       return "set_dword_2";
 459    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 460       return "prepare_channel_masks";
 461    case GS_OPCODE_SET_CHANNEL_MASKS:
 462       return "set_channel_masks";
 463    case GS_OPCODE_GET_INSTANCE_ID:
 464       return "get_instance_id";
 465    case GS_OPCODE_FF_SYNC:
 466       return "ff_sync";
 467    case GS_OPCODE_SET_PRIMITIVE_ID:
 468       return "set_primitive_id";
 469    case GS_OPCODE_SVB_WRITE:
 470       return "gs_svb_write";
 471    case GS_OPCODE_SVB_SET_DST_INDEX:
 472       return "gs_svb_set_dst_index";
 473    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 474       return "gs_ff_sync_set_primitives";
 475    case CS_OPCODE_CS_TERMINATE:
 476       return "cs_terminate";
 477    case SHADER_OPCODE_BARRIER:
 478       return "barrier";
 479    case SHADER_OPCODE_MULH:
 480       return "mulh";
 481    case SHADER_OPCODE_MOV_INDIRECT:
 482       return "mov_indirect";
 483
 484    case VEC4_OPCODE_URB_READ:
 485       return "urb_read";
 486    case TCS_OPCODE_GET_INSTANCE_ID:
 487       return "tcs_get_instance_id";
 488    case TCS_OPCODE_URB_WRITE:
 489       return "tcs_urb_write";
 490    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 491       return "tcs_set_input_urb_offsets";
 492    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 493       return "tcs_set_output_urb_offsets";
 494    case TCS_OPCODE_GET_PRIMITIVE_ID:
 495       return "tcs_get_primitive_id";
 496    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 497       return "tcs_create_barrier_header";
 498    case TCS_OPCODE_SRC0_010_IS_ZERO:
 499       return "tcs_src0<0,1,0>_is_zero";
 500    case TCS_OPCODE_RELEASE_INPUT:
 501       return "tcs_release_input";
 502    case TCS_OPCODE_THREAD_END:
 503       return "tcs_thread_end";
 504    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 505       return "tes_create_input_read_header";
 506    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 507       return "tes_add_indirect_urb_offset";
 508    case TES_OPCODE_GET_PRIMITIVE_ID:
 509       return "tes_get_primitive_id";
 510
 511    case SHADER_OPCODE_RND_MODE:
 512       return "rnd_mode";
 513    }
 514
 515    unreachable("not reached");
 516 }
 517
 518 bool
 519 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 520 {
 521    union {
 522       unsigned ud;
 523       int d;
 524       float f;
 525       double df;
 526    } imm, sat_imm = { 0 };
 527
 528    const unsigned size = type_sz(type);
 529
 530    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 531     * irrelevant, so just check the size of the type and copy from/to an
 532     * appropriately sized field.
 533     */
 534    if (size < 8)
 535       imm.ud = reg->ud;
 536    else
 537       imm.df = reg->df;
 538
 539    switch (type) {
 540    case BRW_REGISTER_TYPE_UD:
 541    case BRW_REGISTER_TYPE_D:
 542    case BRW_REGISTER_TYPE_UW:
 543    case BRW_REGISTER_TYPE_W:
 544    case BRW_REGISTER_TYPE_UQ:
 545    case BRW_REGISTER_TYPE_Q:
 546       /* Nothing to do. */
 547       return false;
 548    case BRW_REGISTER_TYPE_F:
 549       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 550       break;
 551    case BRW_REGISTER_TYPE_DF:
 552       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 553       break;
 554    case BRW_REGISTER_TYPE_UB:
 555    case BRW_REGISTER_TYPE_B:
 556       unreachable("no UB/B immediates");
 557    case BRW_REGISTER_TYPE_V:
 558    case BRW_REGISTER_TYPE_UV:
 559    case BRW_REGISTER_TYPE_VF:
 560       unreachable("unimplemented: saturate vector immediate");
 561    case BRW_REGISTER_TYPE_HF:
 562       unreachable("unimplemented: saturate HF immediate");
 563    case BRW_REGISTER_TYPE_NF:
 564       unreachable("no NF immediates");
 565    }
 566
 567    if (size < 8) {
 568       if (imm.ud != sat_imm.ud) {
 569          reg->ud = sat_imm.ud;
 570          return true;
 571       }
 572    } else {
 573       if (imm.df != sat_imm.df) {
 574          reg->df = sat_imm.df;
 575          return true;
 576       }
 577    }
 578    return false;
 579 }
 580
 581 bool
 582 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 583 {
 584    switch (type) {
 585    case BRW_REGISTER_TYPE_D:
 586    case BRW_REGISTER_TYPE_UD:
 587       reg->d = -reg->d;
 588       return true;
 589    case BRW_REGISTER_TYPE_W:
 590    case BRW_REGISTER_TYPE_UW: {
 591       uint16_t value = -(int16_t)reg->ud;
 592       reg->ud = value | (uint32_t)value << 16;
 593       return true;
 594    }
 595    case BRW_REGISTER_TYPE_F:
 596       reg->f = -reg->f;
 597       return true;
 598    case BRW_REGISTER_TYPE_VF:
 599       reg->ud ^= 0x80808080;
 600       return true;
 601    case BRW_REGISTER_TYPE_DF:
 602       reg->df = -reg->df;
 603       return true;
 604    case BRW_REGISTER_TYPE_UQ:
 605    case BRW_REGISTER_TYPE_Q:
 606       reg->d64 = -reg->d64;
 607       return true;
 608    case BRW_REGISTER_TYPE_UB:
 609    case BRW_REGISTER_TYPE_B:
 610       unreachable("no UB/B immediates");
 611    case BRW_REGISTER_TYPE_UV:
 612    case BRW_REGISTER_TYPE_V:
 613       assert(!"unimplemented: negate UV/V immediate");
 614    case BRW_REGISTER_TYPE_HF:
 615       reg->ud ^= 0x80008000;
 616       return true;
 617    case BRW_REGISTER_TYPE_NF:
 618       unreachable("no NF immediates");
 619    }
 620
 621    return false;
 622 }
 623
 624 bool
 625 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 626 {
 627    switch (type) {
 628    case BRW_REGISTER_TYPE_D:
 629       reg->d = abs(reg->d);
 630       return true;
 631    case BRW_REGISTER_TYPE_W: {
 632       uint16_t value = abs((int16_t)reg->ud);
 633       reg->ud = value | (uint32_t)value << 16;
 634       return true;
 635    }
 636    case BRW_REGISTER_TYPE_F:
 637       reg->f = fabsf(reg->f);
 638       return true;
 639    case BRW_REGISTER_TYPE_DF:
 640       reg->df = fabs(reg->df);
 641       return true;
 642    case BRW_REGISTER_TYPE_VF:
 643       reg->ud &= ~0x80808080;
 644       return true;
 645    case BRW_REGISTER_TYPE_Q:
 646       reg->d64 = imaxabs(reg->d64);
 647       return true;
 648    case BRW_REGISTER_TYPE_UB:
 649    case BRW_REGISTER_TYPE_B:
 650       unreachable("no UB/B immediates");
 651    case BRW_REGISTER_TYPE_UQ:
 652    case BRW_REGISTER_TYPE_UD:
 653    case BRW_REGISTER_TYPE_UW:
 654    case BRW_REGISTER_TYPE_UV:
 655       /* Presumably the absolute value modifier on an unsigned source is a
 656        * nop, but it would be nice to confirm.
 657        */
 658       assert(!"unimplemented: abs unsigned immediate");
 659    case BRW_REGISTER_TYPE_V:
 660       assert(!"unimplemented: abs V immediate");
 661    case BRW_REGISTER_TYPE_HF:
 662       reg->ud &= ~0x80008000;
 663       return true;
 664    case BRW_REGISTER_TYPE_NF:
 665       unreachable("no NF immediates");
 666    }
 667
 668    return false;
 669 }
 670
 671 backend_shader::backend_shader(const struct brw_compiler *compiler,
 672                                void *log_data,
 673                                void *mem_ctx,
 674                                const nir_shader *shader,
 675                                struct brw_stage_prog_data *stage_prog_data)
 676    : compiler(compiler),
 677      log_data(log_data),
 678      devinfo(compiler->devinfo),
 679      nir(shader),
 680      stage_prog_data(stage_prog_data),
 681      mem_ctx(mem_ctx),
 682      cfg(NULL),
 683      stage(shader->info.stage)
 684 {
 685    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 686    stage_name = _mesa_shader_stage_to_string(stage);
 687    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 688 }
 689
 690 backend_shader::~backend_shader()
 691 {
 692 }
 693
 694 bool
 695 backend_reg::equals(const backend_reg &r) const
 696 {
 697    return brw_regs_equal(this, &r) && offset == r.offset;
 698 }
 699
 700 bool
 701 backend_reg::negative_equals(const backend_reg &r) const
 702 {
 703    return brw_regs_negative_equal(this, &r) && offset == r.offset;
 704 }
 705
 706 bool
 707 backend_reg::is_zero() const
 708 {
 709    if (file != IMM)
 710       return false;
 711
 712    switch (type) {
 713    case BRW_REGISTER_TYPE_F:
 714       return f == 0;
 715    case BRW_REGISTER_TYPE_DF:
 716       return df == 0;
 717    case BRW_REGISTER_TYPE_D:
 718    case BRW_REGISTER_TYPE_UD:
 719       return d == 0;
 720    case BRW_REGISTER_TYPE_UQ:
 721    case BRW_REGISTER_TYPE_Q:
 722       return u64 == 0;
 723    default:
 724       return false;
 725    }
 726 }
 727
 728 bool
 729 backend_reg::is_one() const
 730 {
 731    if (file != IMM)
 732       return false;
 733
 734    switch (type) {
 735    case BRW_REGISTER_TYPE_F:
 736       return f == 1.0f;
 737    case BRW_REGISTER_TYPE_DF:
 738       return df == 1.0;
 739    case BRW_REGISTER_TYPE_D:
 740    case BRW_REGISTER_TYPE_UD:
 741       return d == 1;
 742    case BRW_REGISTER_TYPE_UQ:
 743    case BRW_REGISTER_TYPE_Q:
 744       return u64 == 1;
 745    default:
 746       return false;
 747    }
 748 }
 749
 750 bool
 751 backend_reg::is_negative_one() const
 752 {
 753    if (file != IMM)
 754       return false;
 755
 756    switch (type) {
 757    case BRW_REGISTER_TYPE_F:
 758       return f == -1.0;
 759    case BRW_REGISTER_TYPE_DF:
 760       return df == -1.0;
 761    case BRW_REGISTER_TYPE_D:
 762       return d == -1;
 763    case BRW_REGISTER_TYPE_Q:
 764       return d64 == -1;
 765    default:
 766       return false;
 767    }
 768 }
 769
 770 bool
 771 backend_reg::is_null() const
 772 {
 773    return file == ARF && nr == BRW_ARF_NULL;
 774 }
 775
 776
 777 bool
 778 backend_reg::is_accumulator() const
 779 {
 780    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 781 }
 782
 783 bool
 784 backend_instruction::is_commutative() const
 785 {
 786    switch (opcode) {
 787    case BRW_OPCODE_AND:
 788    case BRW_OPCODE_OR:
 789    case BRW_OPCODE_XOR:
 790    case BRW_OPCODE_ADD:
 791    case BRW_OPCODE_MUL:
 792    case SHADER_OPCODE_MULH:
 793       return true;
 794    case BRW_OPCODE_SEL:
 795       /* MIN and MAX are commutative. */
 796       if (conditional_mod == BRW_CONDITIONAL_GE ||
 797           conditional_mod == BRW_CONDITIONAL_L) {
 798          return true;
 799       }
 800       /* fallthrough */
 801    default:
 802       return false;
 803    }
 804 }
 805
 806 bool
 807 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 808 {
 809    return ::is_3src(devinfo, opcode);
 810 }
 811
 812 bool
 813 backend_instruction::is_tex() const
 814 {
 815    return (opcode == SHADER_OPCODE_TEX ||
 816            opcode == FS_OPCODE_TXB ||
 817            opcode == SHADER_OPCODE_TXD ||
 818            opcode == SHADER_OPCODE_TXF ||
 819            opcode == SHADER_OPCODE_TXF_LZ ||
 820            opcode == SHADER_OPCODE_TXF_CMS ||
 821            opcode == SHADER_OPCODE_TXF_CMS_W ||
 822            opcode == SHADER_OPCODE_TXF_UMS ||
 823            opcode == SHADER_OPCODE_TXF_MCS ||
 824            opcode == SHADER_OPCODE_TXL ||
 825            opcode == SHADER_OPCODE_TXL_LZ ||
 826            opcode == SHADER_OPCODE_TXS ||
 827            opcode == SHADER_OPCODE_LOD ||
 828            opcode == SHADER_OPCODE_TG4 ||
 829            opcode == SHADER_OPCODE_TG4_OFFSET ||
 830            opcode == SHADER_OPCODE_SAMPLEINFO);
 831 }
 832
 833 bool
 834 backend_instruction::is_math() const
 835 {
 836    return (opcode == SHADER_OPCODE_RCP ||
 837            opcode == SHADER_OPCODE_RSQ ||
 838            opcode == SHADER_OPCODE_SQRT ||
 839            opcode == SHADER_OPCODE_EXP2 ||
 840            opcode == SHADER_OPCODE_LOG2 ||
 841            opcode == SHADER_OPCODE_SIN ||
 842            opcode == SHADER_OPCODE_COS ||
 843            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 844            opcode == SHADER_OPCODE_INT_REMAINDER ||
 845            opcode == SHADER_OPCODE_POW);
 846 }
 847
 848 bool
 849 backend_instruction::is_control_flow() const
 850 {
 851    switch (opcode) {
 852    case BRW_OPCODE_DO:
 853    case BRW_OPCODE_WHILE:
 854    case BRW_OPCODE_IF:
 855    case BRW_OPCODE_ELSE:
 856    case BRW_OPCODE_ENDIF:
 857    case BRW_OPCODE_BREAK:
 858    case BRW_OPCODE_CONTINUE:
 859       return true;
 860    default:
 861       return false;
 862    }
 863 }
 864
 865 bool
 866 backend_instruction::can_do_source_mods() const
 867 {
 868    switch (opcode) {
 869    case BRW_OPCODE_ADDC:
 870    case BRW_OPCODE_BFE:
 871    case BRW_OPCODE_BFI1:
 872    case BRW_OPCODE_BFI2:
 873    case BRW_OPCODE_BFREV:
 874    case BRW_OPCODE_CBIT:
 875    case BRW_OPCODE_FBH:
 876    case BRW_OPCODE_FBL:
 877    case BRW_OPCODE_SUBB:
 878    case SHADER_OPCODE_BROADCAST:
 879    case SHADER_OPCODE_CLUSTER_BROADCAST:
 880    case SHADER_OPCODE_MOV_INDIRECT:
 881       return false;
 882    default:
 883       return true;
 884    }
 885 }
 886
 887 bool
 888 backend_instruction::can_do_saturate() const
 889 {
 890    switch (opcode) {
 891    case BRW_OPCODE_ADD:
 892    case BRW_OPCODE_ASR:
 893    case BRW_OPCODE_AVG:
 894    case BRW_OPCODE_DP2:
 895    case BRW_OPCODE_DP3:
 896    case BRW_OPCODE_DP4:
 897    case BRW_OPCODE_DPH:
 898    case BRW_OPCODE_F16TO32:
 899    case BRW_OPCODE_F32TO16:
 900    case BRW_OPCODE_LINE:
 901    case BRW_OPCODE_LRP:
 902    case BRW_OPCODE_MAC:
 903    case BRW_OPCODE_MAD:
 904    case BRW_OPCODE_MATH:
 905    case BRW_OPCODE_MOV:
 906    case BRW_OPCODE_MUL:
 907    case SHADER_OPCODE_MULH:
 908    case BRW_OPCODE_PLN:
 909    case BRW_OPCODE_RNDD:
 910    case BRW_OPCODE_RNDE:
 911    case BRW_OPCODE_RNDU:
 912    case BRW_OPCODE_RNDZ:
 913    case BRW_OPCODE_SEL:
 914    case BRW_OPCODE_SHL:
 915    case BRW_OPCODE_SHR:
 916    case FS_OPCODE_LINTERP:
 917    case SHADER_OPCODE_COS:
 918    case SHADER_OPCODE_EXP2:
 919    case SHADER_OPCODE_LOG2:
 920    case SHADER_OPCODE_POW:
 921    case SHADER_OPCODE_RCP:
 922    case SHADER_OPCODE_RSQ:
 923    case SHADER_OPCODE_SIN:
 924    case SHADER_OPCODE_SQRT:
 925       return true;
 926    default:
 927       return false;
 928    }
 929 }
 930
 931 bool
 932 backend_instruction::can_do_cmod() const
 933 {
 934    switch (opcode) {
 935    case BRW_OPCODE_ADD:
 936    case BRW_OPCODE_ADDC:
 937    case BRW_OPCODE_AND:
 938    case BRW_OPCODE_ASR:
 939    case BRW_OPCODE_AVG:
 940    case BRW_OPCODE_CMP:
 941    case BRW_OPCODE_CMPN:
 942    case BRW_OPCODE_DP2:
 943    case BRW_OPCODE_DP3:
 944    case BRW_OPCODE_DP4:
 945    case BRW_OPCODE_DPH:
 946    case BRW_OPCODE_F16TO32:
 947    case BRW_OPCODE_F32TO16:
 948    case BRW_OPCODE_FRC:
 949    case BRW_OPCODE_LINE:
 950    case BRW_OPCODE_LRP:
 951    case BRW_OPCODE_LZD:
 952    case BRW_OPCODE_MAC:
 953    case BRW_OPCODE_MACH:
 954    case BRW_OPCODE_MAD:
 955    case BRW_OPCODE_MOV:
 956    case BRW_OPCODE_MUL:
 957    case BRW_OPCODE_NOT:
 958    case BRW_OPCODE_OR:
 959    case BRW_OPCODE_PLN:
 960    case BRW_OPCODE_RNDD:
 961    case BRW_OPCODE_RNDE:
 962    case BRW_OPCODE_RNDU:
 963    case BRW_OPCODE_RNDZ:
 964    case BRW_OPCODE_SAD2:
 965    case BRW_OPCODE_SADA2:
 966    case BRW_OPCODE_SHL:
 967    case BRW_OPCODE_SHR:
 968    case BRW_OPCODE_SUBB:
 969    case BRW_OPCODE_XOR:
 970    case FS_OPCODE_LINTERP:
 971       return true;
 972    default:
 973       return false;
 974    }
 975 }
 976
 977 bool
 978 backend_instruction::reads_accumulator_implicitly() const
 979 {
 980    switch (opcode) {
 981    case BRW_OPCODE_MAC:
 982    case BRW_OPCODE_MACH:
 983    case BRW_OPCODE_SADA2:
 984       return true;
 985    default:
 986       return false;
 987    }
 988 }
 989
 990 bool
 991 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 992 {
 993    return writes_accumulator ||
 994           (devinfo->gen < 6 &&
 995            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 996             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
 997           (opcode == FS_OPCODE_LINTERP &&
 998            (!devinfo->has_pln || devinfo->gen <= 6));
 999 }
1000
1001 bool
1002 backend_instruction::has_side_effects() const
1003 {
1004    switch (opcode) {
1005    case SHADER_OPCODE_SEND:
1006       return send_has_side_effects;
1007
1008    case SHADER_OPCODE_UNTYPED_ATOMIC:
1009    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1010    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT:
1011    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1012    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1013    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1014    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1015    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
1016    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1017    case SHADER_OPCODE_TYPED_ATOMIC:
1018    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1019    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1020    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1021    case SHADER_OPCODE_MEMORY_FENCE:
1022    case SHADER_OPCODE_INTERLOCK:
1023    case SHADER_OPCODE_URB_WRITE_SIMD8:
1024    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1025    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1026    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1027    case FS_OPCODE_FB_WRITE:
1028    case FS_OPCODE_FB_WRITE_LOGICAL:
1029    case FS_OPCODE_REP_FB_WRITE:
1030    case SHADER_OPCODE_BARRIER:
1031    case TCS_OPCODE_URB_WRITE:
1032    case TCS_OPCODE_RELEASE_INPUT:
1033    case SHADER_OPCODE_RND_MODE:
1034       return true;
1035    default:
1036       return eot;
1037    }
1038 }
1039
1040 bool
1041 backend_instruction::is_volatile() const
1042 {
1043    switch (opcode) {
1044    case SHADER_OPCODE_SEND:
1045       return send_is_volatile;
1046
1047    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1048    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1049    case SHADER_OPCODE_TYPED_SURFACE_READ:
1050    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1051    case SHADER_OPCODE_BYTE_SCATTERED_READ:
1052    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1053    case SHADER_OPCODE_URB_READ_SIMD8:
1054    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1055    case VEC4_OPCODE_URB_READ:
1056       return true;
1057    default:
1058       return false;
1059    }
1060 }
1061
1062 #ifndef NDEBUG
1063 static bool
1064 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1065 {
1066    bool found = false;
1067    foreach_inst_in_block (backend_instruction, i, block) {
1068       if (inst == i) {
1069          found = true;
1070       }
1071    }
1072    return found;
1073 }
1074 #endif
1075
1076 static void
1077 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1078 {
1079    for (bblock_t *block_iter = start_block->next();
1080         block_iter;
1081         block_iter = block_iter->next()) {
1082       block_iter->start_ip += ip_adjustment;
1083       block_iter->end_ip += ip_adjustment;
1084    }
1085 }
1086
1087 void
1088 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1089 {
1090    assert(this != inst);
1091
1092    if (!this->is_head_sentinel())
1093       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1094
1095    block->end_ip++;
1096
1097    adjust_later_block_ips(block, 1);
1098
1099    exec_node::insert_after(inst);
1100 }
1101
1102 void
1103 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1104 {
1105    assert(this != inst);
1106
1107    if (!this->is_tail_sentinel())
1108       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1109
1110    block->end_ip++;
1111
1112    adjust_later_block_ips(block, 1);
1113
1114    exec_node::insert_before(inst);
1115 }
1116
1117 void
1118 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1119 {
1120    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1121
1122    unsigned num_inst = list->length();
1123
1124    block->end_ip += num_inst;
1125
1126    adjust_later_block_ips(block, num_inst);
1127
1128    exec_node::insert_before(list);
1129 }
1130
1131 void
1132 backend_instruction::remove(bblock_t *block)
1133 {
1134    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1135
1136    adjust_later_block_ips(block, -1);
1137
1138    if (block->start_ip == block->end_ip) {
1139       block->cfg->remove_block(block);
1140    } else {
1141       block->end_ip--;
1142    }
1143
1144    exec_node::remove();
1145 }
1146
1147 void
1148 backend_shader::dump_instructions()
1149 {
1150    dump_instructions(NULL);
1151 }
1152
1153 void
1154 backend_shader::dump_instructions(const char *name)
1155 {
1156    FILE *file = stderr;
1157    if (name && geteuid() != 0) {
1158       file = fopen(name, "w");
1159       if (!file)
1160          file = stderr;
1161    }
1162
1163    if (cfg) {
1164       int ip = 0;
1165       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1166          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1167             fprintf(file, "%4d: ", ip++);
1168          dump_instruction(inst, file);
1169       }
1170    } else {
1171       int ip = 0;
1172       foreach_in_list(backend_instruction, inst, &instructions) {
1173          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1174             fprintf(file, "%4d: ", ip++);
1175          dump_instruction(inst, file);
1176       }
1177    }
1178
1179    if (file != stderr) {
1180       fclose(file);
1181    }
1182 }
1183
1184 void
1185 backend_shader::calculate_cfg()
1186 {
1187    if (this->cfg)
1188       return;
1189    cfg = new(mem_ctx) cfg_t(&this->instructions);
1190 }
1191
1192 extern "C" const unsigned *
1193 brw_compile_tes(const struct brw_compiler *compiler,
1194                 void *log_data,
1195                 void *mem_ctx,
1196                 const struct brw_tes_prog_key *key,
1197                 const struct brw_vue_map *input_vue_map,
1198                 struct brw_tes_prog_data *prog_data,
1199                 nir_shader *nir,
1200                 struct gl_program *prog,
1201                 int shader_time_index,
1202                 char **error_str)
1203 {
1204    const struct gen_device_info *devinfo = compiler->devinfo;
1205    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1206    const unsigned *assembly;
1207
1208    nir->info.inputs_read = key->inputs_read;
1209    nir->info.patch_inputs_read = key->patch_inputs_read;
1210
1211    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1212    brw_nir_lower_tes_inputs(nir, input_vue_map);
1213    brw_nir_lower_vue_outputs(nir);
1214    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1215
1216    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1217                        nir->info.outputs_written,
1218                        nir->info.separate_shader);
1219
1220    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1221
1222    assert(output_size_bytes >= 1);
1223    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1224       if (error_str)
1225          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1226       return NULL;
1227    }
1228
1229    prog_data->base.clip_distance_mask =
1230       ((1 << nir->info.clip_distance_array_size) - 1);
1231    prog_data->base.cull_distance_mask =
1232       ((1 << nir->info.cull_distance_array_size) - 1) <<
1233       nir->info.clip_distance_array_size;
1234
1235    /* URB entry sizes are stored as a multiple of 64 bytes. */
1236    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1237
1238    /* On Cannonlake software shall not program an allocation size that
1239     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1240     */
1241    if (devinfo->gen == 10 &&
1242        prog_data->base.urb_entry_size % 3 == 0)
1243       prog_data->base.urb_entry_size++;
1244
1245    prog_data->base.urb_read_length = 0;
1246
1247    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1248    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1249                  TESS_SPACING_FRACTIONAL_ODD - 1);
1250    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1251                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1252
1253    prog_data->partitioning =
1254       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1255
1256    switch (nir->info.tess.primitive_mode) {
1257    case GL_QUADS:
1258       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1259       break;
1260    case GL_TRIANGLES:
1261       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1262       break;
1263    case GL_ISOLINES:
1264       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1265       break;
1266    default:
1267       unreachable("invalid domain shader primitive mode");
1268    }
1269
1270    if (nir->info.tess.point_mode) {
1271       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1272    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1273       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1274    } else {
1275       /* Hardware winding order is backwards from OpenGL */
1276       prog_data->output_topology =
1277          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1278                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1279    }
1280
1281    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1282       fprintf(stderr, "TES Input ");
1283       brw_print_vue_map(stderr, input_vue_map);
1284       fprintf(stderr, "TES Output ");
1285       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1286    }
1287
1288    if (is_scalar) {
1289       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1290                    &prog_data->base.base, NULL, nir, 8,
1291                    shader_time_index, input_vue_map);
1292       if (!v.run_tes()) {
1293          if (error_str)
1294             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1295          return NULL;
1296       }
1297
1298       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1299       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1300
1301       fs_generator g(compiler, log_data, mem_ctx,
1302                      &prog_data->base.base, v.promoted_constants, false,
1303                      MESA_SHADER_TESS_EVAL);
1304       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1305          g.enable_debug(ralloc_asprintf(mem_ctx,
1306                                         "%s tessellation evaluation shader %s",
1307                                         nir->info.label ? nir->info.label
1308                                                         : "unnamed",
1309                                         nir->info.name));
1310       }
1311
1312       g.generate_code(v.cfg, 8);
1313
1314       assembly = g.get_assembly();
1315    } else {
1316       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1317                               nir, mem_ctx, shader_time_index);
1318       if (!v.run()) {
1319          if (error_str)
1320             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1321          return NULL;
1322       }
1323
1324       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1325          v.dump_instructions();
1326
1327       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1328                                             &prog_data->base, v.cfg);
1329    }
1330
1331    return assembly;
1332 }