src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "common/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_INT8:
  48       return BRW_REGISTER_TYPE_B;
  49    case GLSL_TYPE_UINT:
  50       return BRW_REGISTER_TYPE_UD;
  51    case GLSL_TYPE_UINT16:
  52       return BRW_REGISTER_TYPE_UW;
  53    case GLSL_TYPE_UINT8:
  54       return BRW_REGISTER_TYPE_UB;
  55    case GLSL_TYPE_ARRAY:
  56       return brw_type_for_base_type(type->fields.array);
  57    case GLSL_TYPE_STRUCT:
  58    case GLSL_TYPE_SAMPLER:
  59    case GLSL_TYPE_ATOMIC_UINT:
  60       /* These should be overridden with the type of the member when
  61        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  62        * way to trip up if we don't.
  63        */
  64       return BRW_REGISTER_TYPE_UD;
  65    case GLSL_TYPE_IMAGE:
  66       return BRW_REGISTER_TYPE_UD;
  67    case GLSL_TYPE_DOUBLE:
  68       return BRW_REGISTER_TYPE_DF;
  69    case GLSL_TYPE_UINT64:
  70       return BRW_REGISTER_TYPE_UQ;
  71    case GLSL_TYPE_INT64:
  72       return BRW_REGISTER_TYPE_Q;
  73    case GLSL_TYPE_VOID:
  74    case GLSL_TYPE_ERROR:
  75    case GLSL_TYPE_INTERFACE:
  76    case GLSL_TYPE_FUNCTION:
  77       unreachable("not reached");
  78    }
  79
  80    return BRW_REGISTER_TYPE_F;
  81 }
  82
  83 enum brw_conditional_mod
  84 brw_conditional_for_comparison(unsigned int op)
  85 {
  86    switch (op) {
  87    case ir_binop_less:
  88       return BRW_CONDITIONAL_L;
  89    case ir_binop_gequal:
  90       return BRW_CONDITIONAL_GE;
  91    case ir_binop_equal:
  92    case ir_binop_all_equal: /* same as equal for scalars */
  93       return BRW_CONDITIONAL_Z;
  94    case ir_binop_nequal:
  95    case ir_binop_any_nequal: /* same as nequal for scalars */
  96       return BRW_CONDITIONAL_NZ;
  97    default:
  98       unreachable("not reached: bad operation for comparison");
  99    }
 100 }
 101
 102 uint32_t
 103 brw_math_function(enum opcode op)
 104 {
 105    switch (op) {
 106    case SHADER_OPCODE_RCP:
 107       return BRW_MATH_FUNCTION_INV;
 108    case SHADER_OPCODE_RSQ:
 109       return BRW_MATH_FUNCTION_RSQ;
 110    case SHADER_OPCODE_SQRT:
 111       return BRW_MATH_FUNCTION_SQRT;
 112    case SHADER_OPCODE_EXP2:
 113       return BRW_MATH_FUNCTION_EXP;
 114    case SHADER_OPCODE_LOG2:
 115       return BRW_MATH_FUNCTION_LOG;
 116    case SHADER_OPCODE_POW:
 117       return BRW_MATH_FUNCTION_POW;
 118    case SHADER_OPCODE_SIN:
 119       return BRW_MATH_FUNCTION_SIN;
 120    case SHADER_OPCODE_COS:
 121       return BRW_MATH_FUNCTION_COS;
 122    case SHADER_OPCODE_INT_QUOTIENT:
 123       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 124    case SHADER_OPCODE_INT_REMAINDER:
 125       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 126    default:
 127       unreachable("not reached: unknown math function");
 128    }
 129 }
 130
 131 bool
 132 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 133 {
 134    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 135
 136    /* offset out of bounds; caller will handle it. */
 137    for (unsigned i = 0; i < num_components; i++)
 138       if (offsets[i] > 7 || offsets[i] < -8)
 139          return false;
 140
 141    /* Combine all three offsets into a single unsigned dword:
 142     *
 143     *    bits 11:8 - U Offset (X component)
 144     *    bits  7:4 - V Offset (Y component)
 145     *    bits  3:0 - R Offset (Z component)
 146     */
 147    *offset_bits = 0;
 148    for (unsigned i = 0; i < num_components; i++) {
 149       const unsigned shift = 4 * (2 - i);
 150       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 151    }
 152    return true;
 153 }
 154
 155 const char *
 156 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 157 {
 158    switch (op) {
 159    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 160       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 161        * start of a loop in the IR.
 162        */
 163       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 164          return "do";
 165
 166       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 167        * then to mark that we want to do the conversion.
 168        */
 169       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 170          return "f32to16";
 171
 172       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 173          return "f16to32";
 174
 175       assert(brw_opcode_desc(devinfo, op)->name);
 176       return brw_opcode_desc(devinfo, op)->name;
 177    case FS_OPCODE_FB_WRITE:
 178       return "fb_write";
 179    case FS_OPCODE_FB_WRITE_LOGICAL:
 180       return "fb_write_logical";
 181    case FS_OPCODE_REP_FB_WRITE:
 182       return "rep_fb_write";
 183    case FS_OPCODE_FB_READ:
 184       return "fb_read";
 185    case FS_OPCODE_FB_READ_LOGICAL:
 186       return "fb_read_logical";
 187
 188    case SHADER_OPCODE_RCP:
 189       return "rcp";
 190    case SHADER_OPCODE_RSQ:
 191       return "rsq";
 192    case SHADER_OPCODE_SQRT:
 193       return "sqrt";
 194    case SHADER_OPCODE_EXP2:
 195       return "exp2";
 196    case SHADER_OPCODE_LOG2:
 197       return "log2";
 198    case SHADER_OPCODE_POW:
 199       return "pow";
 200    case SHADER_OPCODE_INT_QUOTIENT:
 201       return "int_quot";
 202    case SHADER_OPCODE_INT_REMAINDER:
 203       return "int_rem";
 204    case SHADER_OPCODE_SIN:
 205       return "sin";
 206    case SHADER_OPCODE_COS:
 207       return "cos";
 208
 209    case SHADER_OPCODE_TEX:
 210       return "tex";
 211    case SHADER_OPCODE_TEX_LOGICAL:
 212       return "tex_logical";
 213    case SHADER_OPCODE_TXD:
 214       return "txd";
 215    case SHADER_OPCODE_TXD_LOGICAL:
 216       return "txd_logical";
 217    case SHADER_OPCODE_TXF:
 218       return "txf";
 219    case SHADER_OPCODE_TXF_LOGICAL:
 220       return "txf_logical";
 221    case SHADER_OPCODE_TXF_LZ:
 222       return "txf_lz";
 223    case SHADER_OPCODE_TXL:
 224       return "txl";
 225    case SHADER_OPCODE_TXL_LOGICAL:
 226       return "txl_logical";
 227    case SHADER_OPCODE_TXL_LZ:
 228       return "txl_lz";
 229    case SHADER_OPCODE_TXS:
 230       return "txs";
 231    case SHADER_OPCODE_TXS_LOGICAL:
 232       return "txs_logical";
 233    case FS_OPCODE_TXB:
 234       return "txb";
 235    case FS_OPCODE_TXB_LOGICAL:
 236       return "txb_logical";
 237    case SHADER_OPCODE_TXF_CMS:
 238       return "txf_cms";
 239    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 240       return "txf_cms_logical";
 241    case SHADER_OPCODE_TXF_CMS_W:
 242       return "txf_cms_w";
 243    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 244       return "txf_cms_w_logical";
 245    case SHADER_OPCODE_TXF_UMS:
 246       return "txf_ums";
 247    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 248       return "txf_ums_logical";
 249    case SHADER_OPCODE_TXF_MCS:
 250       return "txf_mcs";
 251    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 252       return "txf_mcs_logical";
 253    case SHADER_OPCODE_LOD:
 254       return "lod";
 255    case SHADER_OPCODE_LOD_LOGICAL:
 256       return "lod_logical";
 257    case SHADER_OPCODE_TG4:
 258       return "tg4";
 259    case SHADER_OPCODE_TG4_LOGICAL:
 260       return "tg4_logical";
 261    case SHADER_OPCODE_TG4_OFFSET:
 262       return "tg4_offset";
 263    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 264       return "tg4_offset_logical";
 265    case SHADER_OPCODE_SAMPLEINFO:
 266       return "sampleinfo";
 267    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 268       return "sampleinfo_logical";
 269
 270    case SHADER_OPCODE_SHADER_TIME_ADD:
 271       return "shader_time_add";
 272
 273    case SHADER_OPCODE_UNTYPED_ATOMIC:
 274       return "untyped_atomic";
 275    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 276       return "untyped_atomic_logical";
 277    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 278       return "untyped_surface_read";
 279    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 280       return "untyped_surface_read_logical";
 281    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 282       return "untyped_surface_write";
 283    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 284       return "untyped_surface_write_logical";
 285    case SHADER_OPCODE_TYPED_ATOMIC:
 286       return "typed_atomic";
 287    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 288       return "typed_atomic_logical";
 289    case SHADER_OPCODE_TYPED_SURFACE_READ:
 290       return "typed_surface_read";
 291    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 292       return "typed_surface_read_logical";
 293    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 294       return "typed_surface_write";
 295    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 296       return "typed_surface_write_logical";
 297    case SHADER_OPCODE_MEMORY_FENCE:
 298       return "memory_fence";
 299
 300    case SHADER_OPCODE_BYTE_SCATTERED_READ:
 301       return "byte_scattered_read";
 302    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 303       return "byte_scattered_read_logical";
 304    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
 305       return "byte_scattered_write";
 306    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 307       return "byte_scattered_write_logical";
 308
 309    case SHADER_OPCODE_LOAD_PAYLOAD:
 310       return "load_payload";
 311    case FS_OPCODE_PACK:
 312       return "pack";
 313
 314    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 315       return "gen4_scratch_read";
 316    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 317       return "gen4_scratch_write";
 318    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 319       return "gen7_scratch_read";
 320    case SHADER_OPCODE_URB_WRITE_SIMD8:
 321       return "gen8_urb_write_simd8";
 322    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 323       return "gen8_urb_write_simd8_per_slot";
 324    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 325       return "gen8_urb_write_simd8_masked";
 326    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 327       return "gen8_urb_write_simd8_masked_per_slot";
 328    case SHADER_OPCODE_URB_READ_SIMD8:
 329       return "urb_read_simd8";
 330    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 331       return "urb_read_simd8_per_slot";
 332
 333    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 334       return "find_live_channel";
 335    case SHADER_OPCODE_BROADCAST:
 336       return "broadcast";
 337    case SHADER_OPCODE_SHUFFLE:
 338       return "shuffle";
 339    case SHADER_OPCODE_SEL_EXEC:
 340       return "sel_exec";
 341    case SHADER_OPCODE_QUAD_SWIZZLE:
 342       return "quad_swizzle";
 343    case SHADER_OPCODE_CLUSTER_BROADCAST:
 344       return "cluster_broadcast";
 345
 346    case SHADER_OPCODE_GET_BUFFER_SIZE:
 347       return "get_buffer_size";
 348
 349    case VEC4_OPCODE_MOV_BYTES:
 350       return "mov_bytes";
 351    case VEC4_OPCODE_PACK_BYTES:
 352       return "pack_bytes";
 353    case VEC4_OPCODE_UNPACK_UNIFORM:
 354       return "unpack_uniform";
 355    case VEC4_OPCODE_DOUBLE_TO_F32:
 356       return "double_to_f32";
 357    case VEC4_OPCODE_DOUBLE_TO_D32:
 358       return "double_to_d32";
 359    case VEC4_OPCODE_DOUBLE_TO_U32:
 360       return "double_to_u32";
 361    case VEC4_OPCODE_TO_DOUBLE:
 362       return "single_to_double";
 363    case VEC4_OPCODE_PICK_LOW_32BIT:
 364       return "pick_low_32bit";
 365    case VEC4_OPCODE_PICK_HIGH_32BIT:
 366       return "pick_high_32bit";
 367    case VEC4_OPCODE_SET_LOW_32BIT:
 368       return "set_low_32bit";
 369    case VEC4_OPCODE_SET_HIGH_32BIT:
 370       return "set_high_32bit";
 371
 372    case FS_OPCODE_DDX_COARSE:
 373       return "ddx_coarse";
 374    case FS_OPCODE_DDX_FINE:
 375       return "ddx_fine";
 376    case FS_OPCODE_DDY_COARSE:
 377       return "ddy_coarse";
 378    case FS_OPCODE_DDY_FINE:
 379       return "ddy_fine";
 380
 381    case FS_OPCODE_CINTERP:
 382       return "cinterp";
 383    case FS_OPCODE_LINTERP:
 384       return "linterp";
 385
 386    case FS_OPCODE_PIXEL_X:
 387       return "pixel_x";
 388    case FS_OPCODE_PIXEL_Y:
 389       return "pixel_y";
 390
 391    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 392       return "uniform_pull_const";
 393    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 394       return "uniform_pull_const_gen7";
 395    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 396       return "varying_pull_const_gen4";
 397    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 398       return "varying_pull_const_gen7";
 399    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 400       return "varying_pull_const_logical";
 401
 402    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 403       return "mov_dispatch_to_flags";
 404    case FS_OPCODE_DISCARD_JUMP:
 405       return "discard_jump";
 406
 407    case FS_OPCODE_SET_SAMPLE_ID:
 408       return "set_sample_id";
 409
 410    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 411       return "pack_half_2x16_split";
 412    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 413       return "unpack_half_2x16_split_x";
 414    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 415       return "unpack_half_2x16_split_y";
 416
 417    case FS_OPCODE_PLACEHOLDER_HALT:
 418       return "placeholder_halt";
 419
 420    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 421       return "interp_sample";
 422    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 423       return "interp_shared_offset";
 424    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 425       return "interp_per_slot_offset";
 426
 427    case VS_OPCODE_URB_WRITE:
 428       return "vs_urb_write";
 429    case VS_OPCODE_PULL_CONSTANT_LOAD:
 430       return "pull_constant_load";
 431    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 432       return "pull_constant_load_gen7";
 433
 434    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 435       return "set_simd4x2_header_gen9";
 436
 437    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 438       return "unpack_flags_simd4x2";
 439
 440    case GS_OPCODE_URB_WRITE:
 441       return "gs_urb_write";
 442    case GS_OPCODE_URB_WRITE_ALLOCATE:
 443       return "gs_urb_write_allocate";
 444    case GS_OPCODE_THREAD_END:
 445       return "gs_thread_end";
 446    case GS_OPCODE_SET_WRITE_OFFSET:
 447       return "set_write_offset";
 448    case GS_OPCODE_SET_VERTEX_COUNT:
 449       return "set_vertex_count";
 450    case GS_OPCODE_SET_DWORD_2:
 451       return "set_dword_2";
 452    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 453       return "prepare_channel_masks";
 454    case GS_OPCODE_SET_CHANNEL_MASKS:
 455       return "set_channel_masks";
 456    case GS_OPCODE_GET_INSTANCE_ID:
 457       return "get_instance_id";
 458    case GS_OPCODE_FF_SYNC:
 459       return "ff_sync";
 460    case GS_OPCODE_SET_PRIMITIVE_ID:
 461       return "set_primitive_id";
 462    case GS_OPCODE_SVB_WRITE:
 463       return "gs_svb_write";
 464    case GS_OPCODE_SVB_SET_DST_INDEX:
 465       return "gs_svb_set_dst_index";
 466    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 467       return "gs_ff_sync_set_primitives";
 468    case CS_OPCODE_CS_TERMINATE:
 469       return "cs_terminate";
 470    case SHADER_OPCODE_BARRIER:
 471       return "barrier";
 472    case SHADER_OPCODE_MULH:
 473       return "mulh";
 474    case SHADER_OPCODE_MOV_INDIRECT:
 475       return "mov_indirect";
 476
 477    case VEC4_OPCODE_URB_READ:
 478       return "urb_read";
 479    case TCS_OPCODE_GET_INSTANCE_ID:
 480       return "tcs_get_instance_id";
 481    case TCS_OPCODE_URB_WRITE:
 482       return "tcs_urb_write";
 483    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 484       return "tcs_set_input_urb_offsets";
 485    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 486       return "tcs_set_output_urb_offsets";
 487    case TCS_OPCODE_GET_PRIMITIVE_ID:
 488       return "tcs_get_primitive_id";
 489    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 490       return "tcs_create_barrier_header";
 491    case TCS_OPCODE_SRC0_010_IS_ZERO:
 492       return "tcs_src0<0,1,0>_is_zero";
 493    case TCS_OPCODE_RELEASE_INPUT:
 494       return "tcs_release_input";
 495    case TCS_OPCODE_THREAD_END:
 496       return "tcs_thread_end";
 497    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 498       return "tes_create_input_read_header";
 499    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 500       return "tes_add_indirect_urb_offset";
 501    case TES_OPCODE_GET_PRIMITIVE_ID:
 502       return "tes_get_primitive_id";
 503
 504    case SHADER_OPCODE_RND_MODE:
 505       return "rnd_mode";
 506    }
 507
 508    unreachable("not reached");
 509 }
 510
 511 bool
 512 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 513 {
 514    union {
 515       unsigned ud;
 516       int d;
 517       float f;
 518       double df;
 519    } imm, sat_imm = { 0 };
 520
 521    const unsigned size = type_sz(type);
 522
 523    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 524     * irrelevant, so just check the size of the type and copy from/to an
 525     * appropriately sized field.
 526     */
 527    if (size < 8)
 528       imm.ud = reg->ud;
 529    else
 530       imm.df = reg->df;
 531
 532    switch (type) {
 533    case BRW_REGISTER_TYPE_UD:
 534    case BRW_REGISTER_TYPE_D:
 535    case BRW_REGISTER_TYPE_UW:
 536    case BRW_REGISTER_TYPE_W:
 537    case BRW_REGISTER_TYPE_UQ:
 538    case BRW_REGISTER_TYPE_Q:
 539       /* Nothing to do. */
 540       return false;
 541    case BRW_REGISTER_TYPE_F:
 542       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 543       break;
 544    case BRW_REGISTER_TYPE_DF:
 545       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 546       break;
 547    case BRW_REGISTER_TYPE_UB:
 548    case BRW_REGISTER_TYPE_B:
 549       unreachable("no UB/B immediates");
 550    case BRW_REGISTER_TYPE_V:
 551    case BRW_REGISTER_TYPE_UV:
 552    case BRW_REGISTER_TYPE_VF:
 553       unreachable("unimplemented: saturate vector immediate");
 554    case BRW_REGISTER_TYPE_HF:
 555       unreachable("unimplemented: saturate HF immediate");
 556    case BRW_REGISTER_TYPE_NF:
 557       unreachable("no NF immediates");
 558    }
 559
 560    if (size < 8) {
 561       if (imm.ud != sat_imm.ud) {
 562          reg->ud = sat_imm.ud;
 563          return true;
 564       }
 565    } else {
 566       if (imm.df != sat_imm.df) {
 567          reg->df = sat_imm.df;
 568          return true;
 569       }
 570    }
 571    return false;
 572 }
 573
 574 bool
 575 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 576 {
 577    switch (type) {
 578    case BRW_REGISTER_TYPE_D:
 579    case BRW_REGISTER_TYPE_UD:
 580       reg->d = -reg->d;
 581       return true;
 582    case BRW_REGISTER_TYPE_W:
 583    case BRW_REGISTER_TYPE_UW: {
 584       uint16_t value = -(int16_t)reg->ud;
 585       reg->ud = value | (uint32_t)value << 16;
 586       return true;
 587    }
 588    case BRW_REGISTER_TYPE_F:
 589       reg->f = -reg->f;
 590       return true;
 591    case BRW_REGISTER_TYPE_VF:
 592       reg->ud ^= 0x80808080;
 593       return true;
 594    case BRW_REGISTER_TYPE_DF:
 595       reg->df = -reg->df;
 596       return true;
 597    case BRW_REGISTER_TYPE_UQ:
 598    case BRW_REGISTER_TYPE_Q:
 599       reg->d64 = -reg->d64;
 600       return true;
 601    case BRW_REGISTER_TYPE_UB:
 602    case BRW_REGISTER_TYPE_B:
 603       unreachable("no UB/B immediates");
 604    case BRW_REGISTER_TYPE_UV:
 605    case BRW_REGISTER_TYPE_V:
 606       assert(!"unimplemented: negate UV/V immediate");
 607    case BRW_REGISTER_TYPE_HF:
 608       reg->ud ^= 0x80008000;
 609       return true;
 610    case BRW_REGISTER_TYPE_NF:
 611       unreachable("no NF immediates");
 612    }
 613
 614    return false;
 615 }
 616
 617 bool
 618 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 619 {
 620    switch (type) {
 621    case BRW_REGISTER_TYPE_D:
 622       reg->d = abs(reg->d);
 623       return true;
 624    case BRW_REGISTER_TYPE_W: {
 625       uint16_t value = abs((int16_t)reg->ud);
 626       reg->ud = value | (uint32_t)value << 16;
 627       return true;
 628    }
 629    case BRW_REGISTER_TYPE_F:
 630       reg->f = fabsf(reg->f);
 631       return true;
 632    case BRW_REGISTER_TYPE_DF:
 633       reg->df = fabs(reg->df);
 634       return true;
 635    case BRW_REGISTER_TYPE_VF:
 636       reg->ud &= ~0x80808080;
 637       return true;
 638    case BRW_REGISTER_TYPE_Q:
 639       reg->d64 = imaxabs(reg->d64);
 640       return true;
 641    case BRW_REGISTER_TYPE_UB:
 642    case BRW_REGISTER_TYPE_B:
 643       unreachable("no UB/B immediates");
 644    case BRW_REGISTER_TYPE_UQ:
 645    case BRW_REGISTER_TYPE_UD:
 646    case BRW_REGISTER_TYPE_UW:
 647    case BRW_REGISTER_TYPE_UV:
 648       /* Presumably the absolute value modifier on an unsigned source is a
 649        * nop, but it would be nice to confirm.
 650        */
 651       assert(!"unimplemented: abs unsigned immediate");
 652    case BRW_REGISTER_TYPE_V:
 653       assert(!"unimplemented: abs V immediate");
 654    case BRW_REGISTER_TYPE_HF:
 655       reg->ud &= ~0x80008000;
 656       return true;
 657    case BRW_REGISTER_TYPE_NF:
 658       unreachable("no NF immediates");
 659    }
 660
 661    return false;
 662 }
 663
 664 backend_shader::backend_shader(const struct brw_compiler *compiler,
 665                                void *log_data,
 666                                void *mem_ctx,
 667                                const nir_shader *shader,
 668                                struct brw_stage_prog_data *stage_prog_data)
 669    : compiler(compiler),
 670      log_data(log_data),
 671      devinfo(compiler->devinfo),
 672      nir(shader),
 673      stage_prog_data(stage_prog_data),
 674      mem_ctx(mem_ctx),
 675      cfg(NULL),
 676      stage(shader->info.stage)
 677 {
 678    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 679    stage_name = _mesa_shader_stage_to_string(stage);
 680    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 681 }
 682
 683 backend_shader::~backend_shader()
 684 {
 685 }
 686
 687 bool
 688 backend_reg::equals(const backend_reg &r) const
 689 {
 690    return brw_regs_equal(this, &r) && offset == r.offset;
 691 }
 692
 693 bool
 694 backend_reg::negative_equals(const backend_reg &r) const
 695 {
 696    return brw_regs_negative_equal(this, &r) && offset == r.offset;
 697 }
 698
 699 bool
 700 backend_reg::is_zero() const
 701 {
 702    if (file != IMM)
 703       return false;
 704
 705    switch (type) {
 706    case BRW_REGISTER_TYPE_F:
 707       return f == 0;
 708    case BRW_REGISTER_TYPE_DF:
 709       return df == 0;
 710    case BRW_REGISTER_TYPE_D:
 711    case BRW_REGISTER_TYPE_UD:
 712       return d == 0;
 713    case BRW_REGISTER_TYPE_UQ:
 714    case BRW_REGISTER_TYPE_Q:
 715       return u64 == 0;
 716    default:
 717       return false;
 718    }
 719 }
 720
 721 bool
 722 backend_reg::is_one() const
 723 {
 724    if (file != IMM)
 725       return false;
 726
 727    switch (type) {
 728    case BRW_REGISTER_TYPE_F:
 729       return f == 1.0f;
 730    case BRW_REGISTER_TYPE_DF:
 731       return df == 1.0;
 732    case BRW_REGISTER_TYPE_D:
 733    case BRW_REGISTER_TYPE_UD:
 734       return d == 1;
 735    case BRW_REGISTER_TYPE_UQ:
 736    case BRW_REGISTER_TYPE_Q:
 737       return u64 == 1;
 738    default:
 739       return false;
 740    }
 741 }
 742
 743 bool
 744 backend_reg::is_negative_one() const
 745 {
 746    if (file != IMM)
 747       return false;
 748
 749    switch (type) {
 750    case BRW_REGISTER_TYPE_F:
 751       return f == -1.0;
 752    case BRW_REGISTER_TYPE_DF:
 753       return df == -1.0;
 754    case BRW_REGISTER_TYPE_D:
 755       return d == -1;
 756    case BRW_REGISTER_TYPE_Q:
 757       return d64 == -1;
 758    default:
 759       return false;
 760    }
 761 }
 762
 763 bool
 764 backend_reg::is_null() const
 765 {
 766    return file == ARF && nr == BRW_ARF_NULL;
 767 }
 768
 769
 770 bool
 771 backend_reg::is_accumulator() const
 772 {
 773    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 774 }
 775
 776 bool
 777 backend_instruction::is_commutative() const
 778 {
 779    switch (opcode) {
 780    case BRW_OPCODE_AND:
 781    case BRW_OPCODE_OR:
 782    case BRW_OPCODE_XOR:
 783    case BRW_OPCODE_ADD:
 784    case BRW_OPCODE_MUL:
 785    case SHADER_OPCODE_MULH:
 786       return true;
 787    case BRW_OPCODE_SEL:
 788       /* MIN and MAX are commutative. */
 789       if (conditional_mod == BRW_CONDITIONAL_GE ||
 790           conditional_mod == BRW_CONDITIONAL_L) {
 791          return true;
 792       }
 793       /* fallthrough */
 794    default:
 795       return false;
 796    }
 797 }
 798
 799 bool
 800 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 801 {
 802    return ::is_3src(devinfo, opcode);
 803 }
 804
 805 bool
 806 backend_instruction::is_tex() const
 807 {
 808    return (opcode == SHADER_OPCODE_TEX ||
 809            opcode == FS_OPCODE_TXB ||
 810            opcode == SHADER_OPCODE_TXD ||
 811            opcode == SHADER_OPCODE_TXF ||
 812            opcode == SHADER_OPCODE_TXF_LZ ||
 813            opcode == SHADER_OPCODE_TXF_CMS ||
 814            opcode == SHADER_OPCODE_TXF_CMS_W ||
 815            opcode == SHADER_OPCODE_TXF_UMS ||
 816            opcode == SHADER_OPCODE_TXF_MCS ||
 817            opcode == SHADER_OPCODE_TXL ||
 818            opcode == SHADER_OPCODE_TXL_LZ ||
 819            opcode == SHADER_OPCODE_TXS ||
 820            opcode == SHADER_OPCODE_LOD ||
 821            opcode == SHADER_OPCODE_TG4 ||
 822            opcode == SHADER_OPCODE_TG4_OFFSET ||
 823            opcode == SHADER_OPCODE_SAMPLEINFO);
 824 }
 825
 826 bool
 827 backend_instruction::is_math() const
 828 {
 829    return (opcode == SHADER_OPCODE_RCP ||
 830            opcode == SHADER_OPCODE_RSQ ||
 831            opcode == SHADER_OPCODE_SQRT ||
 832            opcode == SHADER_OPCODE_EXP2 ||
 833            opcode == SHADER_OPCODE_LOG2 ||
 834            opcode == SHADER_OPCODE_SIN ||
 835            opcode == SHADER_OPCODE_COS ||
 836            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 837            opcode == SHADER_OPCODE_INT_REMAINDER ||
 838            opcode == SHADER_OPCODE_POW);
 839 }
 840
 841 bool
 842 backend_instruction::is_control_flow() const
 843 {
 844    switch (opcode) {
 845    case BRW_OPCODE_DO:
 846    case BRW_OPCODE_WHILE:
 847    case BRW_OPCODE_IF:
 848    case BRW_OPCODE_ELSE:
 849    case BRW_OPCODE_ENDIF:
 850    case BRW_OPCODE_BREAK:
 851    case BRW_OPCODE_CONTINUE:
 852       return true;
 853    default:
 854       return false;
 855    }
 856 }
 857
 858 bool
 859 backend_instruction::can_do_source_mods() const
 860 {
 861    switch (opcode) {
 862    case BRW_OPCODE_ADDC:
 863    case BRW_OPCODE_BFE:
 864    case BRW_OPCODE_BFI1:
 865    case BRW_OPCODE_BFI2:
 866    case BRW_OPCODE_BFREV:
 867    case BRW_OPCODE_CBIT:
 868    case BRW_OPCODE_FBH:
 869    case BRW_OPCODE_FBL:
 870    case BRW_OPCODE_SUBB:
 871    case SHADER_OPCODE_BROADCAST:
 872    case SHADER_OPCODE_CLUSTER_BROADCAST:
 873    case SHADER_OPCODE_MOV_INDIRECT:
 874       return false;
 875    default:
 876       return true;
 877    }
 878 }
 879
 880 bool
 881 backend_instruction::can_do_saturate() const
 882 {
 883    switch (opcode) {
 884    case BRW_OPCODE_ADD:
 885    case BRW_OPCODE_ASR:
 886    case BRW_OPCODE_AVG:
 887    case BRW_OPCODE_DP2:
 888    case BRW_OPCODE_DP3:
 889    case BRW_OPCODE_DP4:
 890    case BRW_OPCODE_DPH:
 891    case BRW_OPCODE_F16TO32:
 892    case BRW_OPCODE_F32TO16:
 893    case BRW_OPCODE_LINE:
 894    case BRW_OPCODE_LRP:
 895    case BRW_OPCODE_MAC:
 896    case BRW_OPCODE_MAD:
 897    case BRW_OPCODE_MATH:
 898    case BRW_OPCODE_MOV:
 899    case BRW_OPCODE_MUL:
 900    case SHADER_OPCODE_MULH:
 901    case BRW_OPCODE_PLN:
 902    case BRW_OPCODE_RNDD:
 903    case BRW_OPCODE_RNDE:
 904    case BRW_OPCODE_RNDU:
 905    case BRW_OPCODE_RNDZ:
 906    case BRW_OPCODE_SEL:
 907    case BRW_OPCODE_SHL:
 908    case BRW_OPCODE_SHR:
 909    case FS_OPCODE_LINTERP:
 910    case SHADER_OPCODE_COS:
 911    case SHADER_OPCODE_EXP2:
 912    case SHADER_OPCODE_LOG2:
 913    case SHADER_OPCODE_POW:
 914    case SHADER_OPCODE_RCP:
 915    case SHADER_OPCODE_RSQ:
 916    case SHADER_OPCODE_SIN:
 917    case SHADER_OPCODE_SQRT:
 918       return true;
 919    default:
 920       return false;
 921    }
 922 }
 923
 924 bool
 925 backend_instruction::can_do_cmod() const
 926 {
 927    switch (opcode) {
 928    case BRW_OPCODE_ADD:
 929    case BRW_OPCODE_ADDC:
 930    case BRW_OPCODE_AND:
 931    case BRW_OPCODE_ASR:
 932    case BRW_OPCODE_AVG:
 933    case BRW_OPCODE_CMP:
 934    case BRW_OPCODE_CMPN:
 935    case BRW_OPCODE_DP2:
 936    case BRW_OPCODE_DP3:
 937    case BRW_OPCODE_DP4:
 938    case BRW_OPCODE_DPH:
 939    case BRW_OPCODE_F16TO32:
 940    case BRW_OPCODE_F32TO16:
 941    case BRW_OPCODE_FRC:
 942    case BRW_OPCODE_LINE:
 943    case BRW_OPCODE_LRP:
 944    case BRW_OPCODE_LZD:
 945    case BRW_OPCODE_MAC:
 946    case BRW_OPCODE_MACH:
 947    case BRW_OPCODE_MAD:
 948    case BRW_OPCODE_MOV:
 949    case BRW_OPCODE_MUL:
 950    case BRW_OPCODE_NOT:
 951    case BRW_OPCODE_OR:
 952    case BRW_OPCODE_PLN:
 953    case BRW_OPCODE_RNDD:
 954    case BRW_OPCODE_RNDE:
 955    case BRW_OPCODE_RNDU:
 956    case BRW_OPCODE_RNDZ:
 957    case BRW_OPCODE_SAD2:
 958    case BRW_OPCODE_SADA2:
 959    case BRW_OPCODE_SHL:
 960    case BRW_OPCODE_SHR:
 961    case BRW_OPCODE_SUBB:
 962    case BRW_OPCODE_XOR:
 963    case FS_OPCODE_CINTERP:
 964    case FS_OPCODE_LINTERP:
 965       return true;
 966    default:
 967       return false;
 968    }
 969 }
 970
 971 bool
 972 backend_instruction::reads_accumulator_implicitly() const
 973 {
 974    switch (opcode) {
 975    case BRW_OPCODE_MAC:
 976    case BRW_OPCODE_MACH:
 977    case BRW_OPCODE_SADA2:
 978       return true;
 979    default:
 980       return false;
 981    }
 982 }
 983
 984 bool
 985 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 986 {
 987    return writes_accumulator ||
 988           (devinfo->gen < 6 &&
 989            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 990             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 991              opcode != FS_OPCODE_CINTERP)));
 992 }
 993
 994 bool
 995 backend_instruction::has_side_effects() const
 996 {
 997    switch (opcode) {
 998    case SHADER_OPCODE_UNTYPED_ATOMIC:
 999    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1000    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1001    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1002    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1003    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
1004    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1005    case SHADER_OPCODE_TYPED_ATOMIC:
1006    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1007    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1008    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1009    case SHADER_OPCODE_MEMORY_FENCE:
1010    case SHADER_OPCODE_URB_WRITE_SIMD8:
1011    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1012    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1013    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1014    case FS_OPCODE_FB_WRITE:
1015    case FS_OPCODE_FB_WRITE_LOGICAL:
1016    case SHADER_OPCODE_BARRIER:
1017    case TCS_OPCODE_URB_WRITE:
1018    case TCS_OPCODE_RELEASE_INPUT:
1019    case SHADER_OPCODE_RND_MODE:
1020       return true;
1021    default:
1022       return eot;
1023    }
1024 }
1025
1026 bool
1027 backend_instruction::is_volatile() const
1028 {
1029    switch (opcode) {
1030    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1031    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1032    case SHADER_OPCODE_TYPED_SURFACE_READ:
1033    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1034    case SHADER_OPCODE_BYTE_SCATTERED_READ:
1035    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1036    case SHADER_OPCODE_URB_READ_SIMD8:
1037    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1038    case VEC4_OPCODE_URB_READ:
1039       return true;
1040    default:
1041       return false;
1042    }
1043 }
1044
1045 #ifndef NDEBUG
1046 static bool
1047 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1048 {
1049    bool found = false;
1050    foreach_inst_in_block (backend_instruction, i, block) {
1051       if (inst == i) {
1052          found = true;
1053       }
1054    }
1055    return found;
1056 }
1057 #endif
1058
1059 static void
1060 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1061 {
1062    for (bblock_t *block_iter = start_block->next();
1063         block_iter;
1064         block_iter = block_iter->next()) {
1065       block_iter->start_ip += ip_adjustment;
1066       block_iter->end_ip += ip_adjustment;
1067    }
1068 }
1069
1070 void
1071 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1072 {
1073    assert(this != inst);
1074
1075    if (!this->is_head_sentinel())
1076       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1077
1078    block->end_ip++;
1079
1080    adjust_later_block_ips(block, 1);
1081
1082    exec_node::insert_after(inst);
1083 }
1084
1085 void
1086 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1087 {
1088    assert(this != inst);
1089
1090    if (!this->is_tail_sentinel())
1091       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1092
1093    block->end_ip++;
1094
1095    adjust_later_block_ips(block, 1);
1096
1097    exec_node::insert_before(inst);
1098 }
1099
1100 void
1101 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1102 {
1103    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1104
1105    unsigned num_inst = list->length();
1106
1107    block->end_ip += num_inst;
1108
1109    adjust_later_block_ips(block, num_inst);
1110
1111    exec_node::insert_before(list);
1112 }
1113
1114 void
1115 backend_instruction::remove(bblock_t *block)
1116 {
1117    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1118
1119    adjust_later_block_ips(block, -1);
1120
1121    if (block->start_ip == block->end_ip) {
1122       block->cfg->remove_block(block);
1123    } else {
1124       block->end_ip--;
1125    }
1126
1127    exec_node::remove();
1128 }
1129
1130 void
1131 backend_shader::dump_instructions()
1132 {
1133    dump_instructions(NULL);
1134 }
1135
1136 void
1137 backend_shader::dump_instructions(const char *name)
1138 {
1139    FILE *file = stderr;
1140    if (name && geteuid() != 0) {
1141       file = fopen(name, "w");
1142       if (!file)
1143          file = stderr;
1144    }
1145
1146    if (cfg) {
1147       int ip = 0;
1148       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1149          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1150             fprintf(file, "%4d: ", ip++);
1151          dump_instruction(inst, file);
1152       }
1153    } else {
1154       int ip = 0;
1155       foreach_in_list(backend_instruction, inst, &instructions) {
1156          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1157             fprintf(file, "%4d: ", ip++);
1158          dump_instruction(inst, file);
1159       }
1160    }
1161
1162    if (file != stderr) {
1163       fclose(file);
1164    }
1165 }
1166
1167 void
1168 backend_shader::calculate_cfg()
1169 {
1170    if (this->cfg)
1171       return;
1172    cfg = new(mem_ctx) cfg_t(&this->instructions);
1173 }
1174
1175 extern "C" const unsigned *
1176 brw_compile_tes(const struct brw_compiler *compiler,
1177                 void *log_data,
1178                 void *mem_ctx,
1179                 const struct brw_tes_prog_key *key,
1180                 const struct brw_vue_map *input_vue_map,
1181                 struct brw_tes_prog_data *prog_data,
1182                 const nir_shader *src_shader,
1183                 struct gl_program *prog,
1184                 int shader_time_index,
1185                 char **error_str)
1186 {
1187    const struct gen_device_info *devinfo = compiler->devinfo;
1188    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1189    const unsigned *assembly;
1190
1191    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1192    nir->info.inputs_read = key->inputs_read;
1193    nir->info.patch_inputs_read = key->patch_inputs_read;
1194
1195    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1196    brw_nir_lower_tes_inputs(nir, input_vue_map);
1197    brw_nir_lower_vue_outputs(nir, is_scalar);
1198    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1199
1200    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1201                        nir->info.outputs_written,
1202                        nir->info.separate_shader);
1203
1204    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1205
1206    assert(output_size_bytes >= 1);
1207    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1208       if (error_str)
1209          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1210       return NULL;
1211    }
1212
1213    prog_data->base.clip_distance_mask =
1214       ((1 << nir->info.clip_distance_array_size) - 1);
1215    prog_data->base.cull_distance_mask =
1216       ((1 << nir->info.cull_distance_array_size) - 1) <<
1217       nir->info.clip_distance_array_size;
1218
1219    /* URB entry sizes are stored as a multiple of 64 bytes. */
1220    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1221
1222    /* On Cannonlake software shall not program an allocation size that
1223     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1224     */
1225    if (devinfo->gen == 10 &&
1226        prog_data->base.urb_entry_size % 3 == 0)
1227       prog_data->base.urb_entry_size++;
1228
1229    prog_data->base.urb_read_length = 0;
1230
1231    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1232    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1233                  TESS_SPACING_FRACTIONAL_ODD - 1);
1234    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1235                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1236
1237    prog_data->partitioning =
1238       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1239
1240    switch (nir->info.tess.primitive_mode) {
1241    case GL_QUADS:
1242       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1243       break;
1244    case GL_TRIANGLES:
1245       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1246       break;
1247    case GL_ISOLINES:
1248       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1249       break;
1250    default:
1251       unreachable("invalid domain shader primitive mode");
1252    }
1253
1254    if (nir->info.tess.point_mode) {
1255       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1256    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1257       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1258    } else {
1259       /* Hardware winding order is backwards from OpenGL */
1260       prog_data->output_topology =
1261          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1262                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1263    }
1264
1265    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1266       fprintf(stderr, "TES Input ");
1267       brw_print_vue_map(stderr, input_vue_map);
1268       fprintf(stderr, "TES Output ");
1269       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1270    }
1271
1272    if (is_scalar) {
1273       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1274                    &prog_data->base.base, NULL, nir, 8,
1275                    shader_time_index, input_vue_map);
1276       if (!v.run_tes()) {
1277          if (error_str)
1278             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1279          return NULL;
1280       }
1281
1282       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1283       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1284
1285       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1286                      &prog_data->base.base, v.promoted_constants, false,
1287                      MESA_SHADER_TESS_EVAL);
1288       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1289          g.enable_debug(ralloc_asprintf(mem_ctx,
1290                                         "%s tessellation evaluation shader %s",
1291                                         nir->info.label ? nir->info.label
1292                                                         : "unnamed",
1293                                         nir->info.name));
1294       }
1295
1296       g.generate_code(v.cfg, 8);
1297
1298       assembly = g.get_assembly();
1299    } else {
1300       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1301                               nir, mem_ctx, shader_time_index);
1302       if (!v.run()) {
1303          if (error_str)
1304             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1305          return NULL;
1306       }
1307
1308       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1309          v.dump_instructions();
1310
1311       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1312                                             &prog_data->base, v.cfg);
1313    }
1314
1315    return assembly;
1316 }