src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "common/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT:
  38       return BRW_REGISTER_TYPE_F;
  39    case GLSL_TYPE_INT:
  40    case GLSL_TYPE_BOOL:
  41    case GLSL_TYPE_SUBROUTINE:
  42       return BRW_REGISTER_TYPE_D;
  43    case GLSL_TYPE_UINT:
  44       return BRW_REGISTER_TYPE_UD;
  45    case GLSL_TYPE_ARRAY:
  46       return brw_type_for_base_type(type->fields.array);
  47    case GLSL_TYPE_STRUCT:
  48    case GLSL_TYPE_SAMPLER:
  49    case GLSL_TYPE_ATOMIC_UINT:
  50       /* These should be overridden with the type of the member when
  51        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  52        * way to trip up if we don't.
  53        */
  54       return BRW_REGISTER_TYPE_UD;
  55    case GLSL_TYPE_IMAGE:
  56       return BRW_REGISTER_TYPE_UD;
  57    case GLSL_TYPE_DOUBLE:
  58       return BRW_REGISTER_TYPE_DF;
  59    case GLSL_TYPE_UINT64:
  60       return BRW_REGISTER_TYPE_UQ;
  61    case GLSL_TYPE_INT64:
  62       return BRW_REGISTER_TYPE_Q;
  63    case GLSL_TYPE_VOID:
  64    case GLSL_TYPE_ERROR:
  65    case GLSL_TYPE_INTERFACE:
  66    case GLSL_TYPE_FUNCTION:
  67       unreachable("not reached");
  68    }
  69
  70    return BRW_REGISTER_TYPE_F;
  71 }
  72
  73 enum brw_conditional_mod
  74 brw_conditional_for_comparison(unsigned int op)
  75 {
  76    switch (op) {
  77    case ir_binop_less:
  78       return BRW_CONDITIONAL_L;
  79    case ir_binop_gequal:
  80       return BRW_CONDITIONAL_GE;
  81    case ir_binop_equal:
  82    case ir_binop_all_equal: /* same as equal for scalars */
  83       return BRW_CONDITIONAL_Z;
  84    case ir_binop_nequal:
  85    case ir_binop_any_nequal: /* same as nequal for scalars */
  86       return BRW_CONDITIONAL_NZ;
  87    default:
  88       unreachable("not reached: bad operation for comparison");
  89    }
  90 }
  91
  92 uint32_t
  93 brw_math_function(enum opcode op)
  94 {
  95    switch (op) {
  96    case SHADER_OPCODE_RCP:
  97       return BRW_MATH_FUNCTION_INV;
  98    case SHADER_OPCODE_RSQ:
  99       return BRW_MATH_FUNCTION_RSQ;
 100    case SHADER_OPCODE_SQRT:
 101       return BRW_MATH_FUNCTION_SQRT;
 102    case SHADER_OPCODE_EXP2:
 103       return BRW_MATH_FUNCTION_EXP;
 104    case SHADER_OPCODE_LOG2:
 105       return BRW_MATH_FUNCTION_LOG;
 106    case SHADER_OPCODE_POW:
 107       return BRW_MATH_FUNCTION_POW;
 108    case SHADER_OPCODE_SIN:
 109       return BRW_MATH_FUNCTION_SIN;
 110    case SHADER_OPCODE_COS:
 111       return BRW_MATH_FUNCTION_COS;
 112    case SHADER_OPCODE_INT_QUOTIENT:
 113       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 114    case SHADER_OPCODE_INT_REMAINDER:
 115       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 116    default:
 117       unreachable("not reached: unknown math function");
 118    }
 119 }
 120
 121 bool
 122 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 123 {
 124    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 125
 126    /* offset out of bounds; caller will handle it. */
 127    for (unsigned i = 0; i < num_components; i++)
 128       if (offsets[i] > 7 || offsets[i] < -8)
 129          return false;
 130
 131    /* Combine all three offsets into a single unsigned dword:
 132     *
 133     *    bits 11:8 - U Offset (X component)
 134     *    bits  7:4 - V Offset (Y component)
 135     *    bits  3:0 - R Offset (Z component)
 136     */
 137    *offset_bits = 0;
 138    for (unsigned i = 0; i < num_components; i++) {
 139       const unsigned shift = 4 * (2 - i);
 140       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 141    }
 142    return true;
 143 }
 144
 145 const char *
 146 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 147 {
 148    switch (op) {
 149    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 150       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 151        * start of a loop in the IR.
 152        */
 153       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 154          return "do";
 155
 156       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 157        * then to mark that we want to do the conversion.
 158        */
 159       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 160          return "f32to16";
 161
 162       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 163          return "f16to32";
 164
 165       assert(brw_opcode_desc(devinfo, op)->name);
 166       return brw_opcode_desc(devinfo, op)->name;
 167    case FS_OPCODE_FB_WRITE:
 168       return "fb_write";
 169    case FS_OPCODE_FB_WRITE_LOGICAL:
 170       return "fb_write_logical";
 171    case FS_OPCODE_REP_FB_WRITE:
 172       return "rep_fb_write";
 173    case FS_OPCODE_FB_READ:
 174       return "fb_read";
 175    case FS_OPCODE_FB_READ_LOGICAL:
 176       return "fb_read_logical";
 177
 178    case SHADER_OPCODE_RCP:
 179       return "rcp";
 180    case SHADER_OPCODE_RSQ:
 181       return "rsq";
 182    case SHADER_OPCODE_SQRT:
 183       return "sqrt";
 184    case SHADER_OPCODE_EXP2:
 185       return "exp2";
 186    case SHADER_OPCODE_LOG2:
 187       return "log2";
 188    case SHADER_OPCODE_POW:
 189       return "pow";
 190    case SHADER_OPCODE_INT_QUOTIENT:
 191       return "int_quot";
 192    case SHADER_OPCODE_INT_REMAINDER:
 193       return "int_rem";
 194    case SHADER_OPCODE_SIN:
 195       return "sin";
 196    case SHADER_OPCODE_COS:
 197       return "cos";
 198
 199    case SHADER_OPCODE_TEX:
 200       return "tex";
 201    case SHADER_OPCODE_TEX_LOGICAL:
 202       return "tex_logical";
 203    case SHADER_OPCODE_TXD:
 204       return "txd";
 205    case SHADER_OPCODE_TXD_LOGICAL:
 206       return "txd_logical";
 207    case SHADER_OPCODE_TXF:
 208       return "txf";
 209    case SHADER_OPCODE_TXF_LOGICAL:
 210       return "txf_logical";
 211    case SHADER_OPCODE_TXF_LZ:
 212       return "txf_lz";
 213    case SHADER_OPCODE_TXL:
 214       return "txl";
 215    case SHADER_OPCODE_TXL_LOGICAL:
 216       return "txl_logical";
 217    case SHADER_OPCODE_TXL_LZ:
 218       return "txl_lz";
 219    case SHADER_OPCODE_TXS:
 220       return "txs";
 221    case SHADER_OPCODE_TXS_LOGICAL:
 222       return "txs_logical";
 223    case FS_OPCODE_TXB:
 224       return "txb";
 225    case FS_OPCODE_TXB_LOGICAL:
 226       return "txb_logical";
 227    case SHADER_OPCODE_TXF_CMS:
 228       return "txf_cms";
 229    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 230       return "txf_cms_logical";
 231    case SHADER_OPCODE_TXF_CMS_W:
 232       return "txf_cms_w";
 233    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 234       return "txf_cms_w_logical";
 235    case SHADER_OPCODE_TXF_UMS:
 236       return "txf_ums";
 237    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 238       return "txf_ums_logical";
 239    case SHADER_OPCODE_TXF_MCS:
 240       return "txf_mcs";
 241    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 242       return "txf_mcs_logical";
 243    case SHADER_OPCODE_LOD:
 244       return "lod";
 245    case SHADER_OPCODE_LOD_LOGICAL:
 246       return "lod_logical";
 247    case SHADER_OPCODE_TG4:
 248       return "tg4";
 249    case SHADER_OPCODE_TG4_LOGICAL:
 250       return "tg4_logical";
 251    case SHADER_OPCODE_TG4_OFFSET:
 252       return "tg4_offset";
 253    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 254       return "tg4_offset_logical";
 255    case SHADER_OPCODE_SAMPLEINFO:
 256       return "sampleinfo";
 257    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 258       return "sampleinfo_logical";
 259
 260    case SHADER_OPCODE_SHADER_TIME_ADD:
 261       return "shader_time_add";
 262
 263    case SHADER_OPCODE_UNTYPED_ATOMIC:
 264       return "untyped_atomic";
 265    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 266       return "untyped_atomic_logical";
 267    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 268       return "untyped_surface_read";
 269    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 270       return "untyped_surface_read_logical";
 271    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 272       return "untyped_surface_write";
 273    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 274       return "untyped_surface_write_logical";
 275    case SHADER_OPCODE_TYPED_ATOMIC:
 276       return "typed_atomic";
 277    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 278       return "typed_atomic_logical";
 279    case SHADER_OPCODE_TYPED_SURFACE_READ:
 280       return "typed_surface_read";
 281    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 282       return "typed_surface_read_logical";
 283    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 284       return "typed_surface_write";
 285    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 286       return "typed_surface_write_logical";
 287    case SHADER_OPCODE_MEMORY_FENCE:
 288       return "memory_fence";
 289
 290    case SHADER_OPCODE_LOAD_PAYLOAD:
 291       return "load_payload";
 292    case FS_OPCODE_PACK:
 293       return "pack";
 294
 295    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 296       return "gen4_scratch_read";
 297    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 298       return "gen4_scratch_write";
 299    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 300       return "gen7_scratch_read";
 301    case SHADER_OPCODE_URB_WRITE_SIMD8:
 302       return "gen8_urb_write_simd8";
 303    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 304       return "gen8_urb_write_simd8_per_slot";
 305    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 306       return "gen8_urb_write_simd8_masked";
 307    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 308       return "gen8_urb_write_simd8_masked_per_slot";
 309    case SHADER_OPCODE_URB_READ_SIMD8:
 310       return "urb_read_simd8";
 311    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 312       return "urb_read_simd8_per_slot";
 313
 314    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 315       return "find_live_channel";
 316    case SHADER_OPCODE_BROADCAST:
 317       return "broadcast";
 318
 319    case VEC4_OPCODE_MOV_BYTES:
 320       return "mov_bytes";
 321    case VEC4_OPCODE_PACK_BYTES:
 322       return "pack_bytes";
 323    case VEC4_OPCODE_UNPACK_UNIFORM:
 324       return "unpack_uniform";
 325    case VEC4_OPCODE_DOUBLE_TO_F32:
 326       return "double_to_f32";
 327    case VEC4_OPCODE_DOUBLE_TO_D32:
 328       return "double_to_d32";
 329    case VEC4_OPCODE_DOUBLE_TO_U32:
 330       return "double_to_u32";
 331    case VEC4_OPCODE_TO_DOUBLE:
 332       return "single_to_double";
 333    case VEC4_OPCODE_PICK_LOW_32BIT:
 334       return "pick_low_32bit";
 335    case VEC4_OPCODE_PICK_HIGH_32BIT:
 336       return "pick_high_32bit";
 337    case VEC4_OPCODE_SET_LOW_32BIT:
 338       return "set_low_32bit";
 339    case VEC4_OPCODE_SET_HIGH_32BIT:
 340       return "set_high_32bit";
 341
 342    case FS_OPCODE_DDX_COARSE:
 343       return "ddx_coarse";
 344    case FS_OPCODE_DDX_FINE:
 345       return "ddx_fine";
 346    case FS_OPCODE_DDY_COARSE:
 347       return "ddy_coarse";
 348    case FS_OPCODE_DDY_FINE:
 349       return "ddy_fine";
 350
 351    case FS_OPCODE_CINTERP:
 352       return "cinterp";
 353    case FS_OPCODE_LINTERP:
 354       return "linterp";
 355
 356    case FS_OPCODE_PIXEL_X:
 357       return "pixel_x";
 358    case FS_OPCODE_PIXEL_Y:
 359       return "pixel_y";
 360
 361    case FS_OPCODE_GET_BUFFER_SIZE:
 362       return "fs_get_buffer_size";
 363
 364    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 365       return "uniform_pull_const";
 366    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 367       return "uniform_pull_const_gen7";
 368    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 369       return "varying_pull_const_gen4";
 370    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 371       return "varying_pull_const_gen7";
 372    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 373       return "varying_pull_const_logical";
 374
 375    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 376       return "mov_dispatch_to_flags";
 377    case FS_OPCODE_DISCARD_JUMP:
 378       return "discard_jump";
 379
 380    case FS_OPCODE_SET_SAMPLE_ID:
 381       return "set_sample_id";
 382
 383    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 384       return "pack_half_2x16_split";
 385    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 386       return "unpack_half_2x16_split_x";
 387    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 388       return "unpack_half_2x16_split_y";
 389
 390    case FS_OPCODE_PLACEHOLDER_HALT:
 391       return "placeholder_halt";
 392
 393    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 394       return "interp_sample";
 395    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 396       return "interp_shared_offset";
 397    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 398       return "interp_per_slot_offset";
 399
 400    case VS_OPCODE_URB_WRITE:
 401       return "vs_urb_write";
 402    case VS_OPCODE_PULL_CONSTANT_LOAD:
 403       return "pull_constant_load";
 404    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 405       return "pull_constant_load_gen7";
 406
 407    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 408       return "set_simd4x2_header_gen9";
 409
 410    case VS_OPCODE_GET_BUFFER_SIZE:
 411       return "vs_get_buffer_size";
 412
 413    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 414       return "unpack_flags_simd4x2";
 415
 416    case GS_OPCODE_URB_WRITE:
 417       return "gs_urb_write";
 418    case GS_OPCODE_URB_WRITE_ALLOCATE:
 419       return "gs_urb_write_allocate";
 420    case GS_OPCODE_THREAD_END:
 421       return "gs_thread_end";
 422    case GS_OPCODE_SET_WRITE_OFFSET:
 423       return "set_write_offset";
 424    case GS_OPCODE_SET_VERTEX_COUNT:
 425       return "set_vertex_count";
 426    case GS_OPCODE_SET_DWORD_2:
 427       return "set_dword_2";
 428    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 429       return "prepare_channel_masks";
 430    case GS_OPCODE_SET_CHANNEL_MASKS:
 431       return "set_channel_masks";
 432    case GS_OPCODE_GET_INSTANCE_ID:
 433       return "get_instance_id";
 434    case GS_OPCODE_FF_SYNC:
 435       return "ff_sync";
 436    case GS_OPCODE_SET_PRIMITIVE_ID:
 437       return "set_primitive_id";
 438    case GS_OPCODE_SVB_WRITE:
 439       return "gs_svb_write";
 440    case GS_OPCODE_SVB_SET_DST_INDEX:
 441       return "gs_svb_set_dst_index";
 442    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 443       return "gs_ff_sync_set_primitives";
 444    case CS_OPCODE_CS_TERMINATE:
 445       return "cs_terminate";
 446    case SHADER_OPCODE_BARRIER:
 447       return "barrier";
 448    case SHADER_OPCODE_MULH:
 449       return "mulh";
 450    case SHADER_OPCODE_MOV_INDIRECT:
 451       return "mov_indirect";
 452
 453    case VEC4_OPCODE_URB_READ:
 454       return "urb_read";
 455    case TCS_OPCODE_GET_INSTANCE_ID:
 456       return "tcs_get_instance_id";
 457    case TCS_OPCODE_URB_WRITE:
 458       return "tcs_urb_write";
 459    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 460       return "tcs_set_input_urb_offsets";
 461    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 462       return "tcs_set_output_urb_offsets";
 463    case TCS_OPCODE_GET_PRIMITIVE_ID:
 464       return "tcs_get_primitive_id";
 465    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 466       return "tcs_create_barrier_header";
 467    case TCS_OPCODE_SRC0_010_IS_ZERO:
 468       return "tcs_src0<0,1,0>_is_zero";
 469    case TCS_OPCODE_RELEASE_INPUT:
 470       return "tcs_release_input";
 471    case TCS_OPCODE_THREAD_END:
 472       return "tcs_thread_end";
 473    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 474       return "tes_create_input_read_header";
 475    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 476       return "tes_add_indirect_urb_offset";
 477    case TES_OPCODE_GET_PRIMITIVE_ID:
 478       return "tes_get_primitive_id";
 479    }
 480
 481    unreachable("not reached");
 482 }
 483
 484 bool
 485 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 486 {
 487    union {
 488       unsigned ud;
 489       int d;
 490       float f;
 491       double df;
 492    } imm, sat_imm = { 0 };
 493
 494    const unsigned size = type_sz(type);
 495
 496    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 497     * irrelevant, so just check the size of the type and copy from/to an
 498     * appropriately sized field.
 499     */
 500    if (size < 8)
 501       imm.ud = reg->ud;
 502    else
 503       imm.df = reg->df;
 504
 505    switch (type) {
 506    case BRW_REGISTER_TYPE_UD:
 507    case BRW_REGISTER_TYPE_D:
 508    case BRW_REGISTER_TYPE_UW:
 509    case BRW_REGISTER_TYPE_W:
 510    case BRW_REGISTER_TYPE_UQ:
 511    case BRW_REGISTER_TYPE_Q:
 512       /* Nothing to do. */
 513       return false;
 514    case BRW_REGISTER_TYPE_F:
 515       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 516       break;
 517    case BRW_REGISTER_TYPE_DF:
 518       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 519       break;
 520    case BRW_REGISTER_TYPE_UB:
 521    case BRW_REGISTER_TYPE_B:
 522       unreachable("no UB/B immediates");
 523    case BRW_REGISTER_TYPE_V:
 524    case BRW_REGISTER_TYPE_UV:
 525    case BRW_REGISTER_TYPE_VF:
 526       unreachable("unimplemented: saturate vector immediate");
 527    case BRW_REGISTER_TYPE_HF:
 528       unreachable("unimplemented: saturate HF immediate");
 529    }
 530
 531    if (size < 8) {
 532       if (imm.ud != sat_imm.ud) {
 533          reg->ud = sat_imm.ud;
 534          return true;
 535       }
 536    } else {
 537       if (imm.df != sat_imm.df) {
 538          reg->df = sat_imm.df;
 539          return true;
 540       }
 541    }
 542    return false;
 543 }
 544
 545 bool
 546 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 547 {
 548    switch (type) {
 549    case BRW_REGISTER_TYPE_D:
 550    case BRW_REGISTER_TYPE_UD:
 551       reg->d = -reg->d;
 552       return true;
 553    case BRW_REGISTER_TYPE_W:
 554    case BRW_REGISTER_TYPE_UW:
 555       reg->d = -(int16_t)reg->ud;
 556       return true;
 557    case BRW_REGISTER_TYPE_F:
 558       reg->f = -reg->f;
 559       return true;
 560    case BRW_REGISTER_TYPE_VF:
 561       reg->ud ^= 0x80808080;
 562       return true;
 563    case BRW_REGISTER_TYPE_DF:
 564       reg->df = -reg->df;
 565       return true;
 566    case BRW_REGISTER_TYPE_UQ:
 567    case BRW_REGISTER_TYPE_Q:
 568       reg->d64 = -reg->d64;
 569       return true;
 570    case BRW_REGISTER_TYPE_UB:
 571    case BRW_REGISTER_TYPE_B:
 572       unreachable("no UB/B immediates");
 573    case BRW_REGISTER_TYPE_UV:
 574    case BRW_REGISTER_TYPE_V:
 575       assert(!"unimplemented: negate UV/V immediate");
 576    case BRW_REGISTER_TYPE_HF:
 577       assert(!"unimplemented: negate HF immediate");
 578    }
 579
 580    return false;
 581 }
 582
 583 bool
 584 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 585 {
 586    switch (type) {
 587    case BRW_REGISTER_TYPE_D:
 588       reg->d = abs(reg->d);
 589       return true;
 590    case BRW_REGISTER_TYPE_W:
 591       reg->d = abs((int16_t)reg->ud);
 592       return true;
 593    case BRW_REGISTER_TYPE_F:
 594       reg->f = fabsf(reg->f);
 595       return true;
 596    case BRW_REGISTER_TYPE_DF:
 597       reg->df = fabs(reg->df);
 598       return true;
 599    case BRW_REGISTER_TYPE_VF:
 600       reg->ud &= ~0x80808080;
 601       return true;
 602    case BRW_REGISTER_TYPE_Q:
 603       reg->d64 = imaxabs(reg->d64);
 604       return true;
 605    case BRW_REGISTER_TYPE_UB:
 606    case BRW_REGISTER_TYPE_B:
 607       unreachable("no UB/B immediates");
 608    case BRW_REGISTER_TYPE_UQ:
 609    case BRW_REGISTER_TYPE_UD:
 610    case BRW_REGISTER_TYPE_UW:
 611    case BRW_REGISTER_TYPE_UV:
 612       /* Presumably the absolute value modifier on an unsigned source is a
 613        * nop, but it would be nice to confirm.
 614        */
 615       assert(!"unimplemented: abs unsigned immediate");
 616    case BRW_REGISTER_TYPE_V:
 617       assert(!"unimplemented: abs V immediate");
 618    case BRW_REGISTER_TYPE_HF:
 619       assert(!"unimplemented: abs HF immediate");
 620    }
 621
 622    return false;
 623 }
 624
 625 backend_shader::backend_shader(const struct brw_compiler *compiler,
 626                                void *log_data,
 627                                void *mem_ctx,
 628                                const nir_shader *shader,
 629                                struct brw_stage_prog_data *stage_prog_data)
 630    : compiler(compiler),
 631      log_data(log_data),
 632      devinfo(compiler->devinfo),
 633      nir(shader),
 634      stage_prog_data(stage_prog_data),
 635      mem_ctx(mem_ctx),
 636      cfg(NULL),
 637      stage(shader->info.stage)
 638 {
 639    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 640    stage_name = _mesa_shader_stage_to_string(stage);
 641    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 642 }
 643
 644 backend_shader::~backend_shader()
 645 {
 646 }
 647
 648 bool
 649 backend_reg::equals(const backend_reg &r) const
 650 {
 651    return brw_regs_equal(this, &r) && offset == r.offset;
 652 }
 653
 654 bool
 655 backend_reg::is_zero() const
 656 {
 657    if (file != IMM)
 658       return false;
 659
 660    switch (type) {
 661    case BRW_REGISTER_TYPE_F:
 662       return f == 0;
 663    case BRW_REGISTER_TYPE_DF:
 664       return df == 0;
 665    case BRW_REGISTER_TYPE_D:
 666    case BRW_REGISTER_TYPE_UD:
 667       return d == 0;
 668    case BRW_REGISTER_TYPE_UQ:
 669    case BRW_REGISTER_TYPE_Q:
 670       return u64 == 0;
 671    default:
 672       return false;
 673    }
 674 }
 675
 676 bool
 677 backend_reg::is_one() const
 678 {
 679    if (file != IMM)
 680       return false;
 681
 682    switch (type) {
 683    case BRW_REGISTER_TYPE_F:
 684       return f == 1.0f;
 685    case BRW_REGISTER_TYPE_DF:
 686       return df == 1.0;
 687    case BRW_REGISTER_TYPE_D:
 688    case BRW_REGISTER_TYPE_UD:
 689       return d == 1;
 690    case BRW_REGISTER_TYPE_UQ:
 691    case BRW_REGISTER_TYPE_Q:
 692       return u64 == 1;
 693    default:
 694       return false;
 695    }
 696 }
 697
 698 bool
 699 backend_reg::is_negative_one() const
 700 {
 701    if (file != IMM)
 702       return false;
 703
 704    switch (type) {
 705    case BRW_REGISTER_TYPE_F:
 706       return f == -1.0;
 707    case BRW_REGISTER_TYPE_DF:
 708       return df == -1.0;
 709    case BRW_REGISTER_TYPE_D:
 710       return d == -1;
 711    case BRW_REGISTER_TYPE_Q:
 712       return d64 == -1;
 713    default:
 714       return false;
 715    }
 716 }
 717
 718 bool
 719 backend_reg::is_null() const
 720 {
 721    return file == ARF && nr == BRW_ARF_NULL;
 722 }
 723
 724
 725 bool
 726 backend_reg::is_accumulator() const
 727 {
 728    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 729 }
 730
 731 bool
 732 backend_instruction::is_commutative() const
 733 {
 734    switch (opcode) {
 735    case BRW_OPCODE_AND:
 736    case BRW_OPCODE_OR:
 737    case BRW_OPCODE_XOR:
 738    case BRW_OPCODE_ADD:
 739    case BRW_OPCODE_MUL:
 740    case SHADER_OPCODE_MULH:
 741       return true;
 742    case BRW_OPCODE_SEL:
 743       /* MIN and MAX are commutative. */
 744       if (conditional_mod == BRW_CONDITIONAL_GE ||
 745           conditional_mod == BRW_CONDITIONAL_L) {
 746          return true;
 747       }
 748       /* fallthrough */
 749    default:
 750       return false;
 751    }
 752 }
 753
 754 bool
 755 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 756 {
 757    return ::is_3src(devinfo, opcode);
 758 }
 759
 760 bool
 761 backend_instruction::is_tex() const
 762 {
 763    return (opcode == SHADER_OPCODE_TEX ||
 764            opcode == FS_OPCODE_TXB ||
 765            opcode == SHADER_OPCODE_TXD ||
 766            opcode == SHADER_OPCODE_TXF ||
 767            opcode == SHADER_OPCODE_TXF_LZ ||
 768            opcode == SHADER_OPCODE_TXF_CMS ||
 769            opcode == SHADER_OPCODE_TXF_CMS_W ||
 770            opcode == SHADER_OPCODE_TXF_UMS ||
 771            opcode == SHADER_OPCODE_TXF_MCS ||
 772            opcode == SHADER_OPCODE_TXL ||
 773            opcode == SHADER_OPCODE_TXL_LZ ||
 774            opcode == SHADER_OPCODE_TXS ||
 775            opcode == SHADER_OPCODE_LOD ||
 776            opcode == SHADER_OPCODE_TG4 ||
 777            opcode == SHADER_OPCODE_TG4_OFFSET ||
 778            opcode == SHADER_OPCODE_SAMPLEINFO);
 779 }
 780
 781 bool
 782 backend_instruction::is_math() const
 783 {
 784    return (opcode == SHADER_OPCODE_RCP ||
 785            opcode == SHADER_OPCODE_RSQ ||
 786            opcode == SHADER_OPCODE_SQRT ||
 787            opcode == SHADER_OPCODE_EXP2 ||
 788            opcode == SHADER_OPCODE_LOG2 ||
 789            opcode == SHADER_OPCODE_SIN ||
 790            opcode == SHADER_OPCODE_COS ||
 791            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 792            opcode == SHADER_OPCODE_INT_REMAINDER ||
 793            opcode == SHADER_OPCODE_POW);
 794 }
 795
 796 bool
 797 backend_instruction::is_control_flow() const
 798 {
 799    switch (opcode) {
 800    case BRW_OPCODE_DO:
 801    case BRW_OPCODE_WHILE:
 802    case BRW_OPCODE_IF:
 803    case BRW_OPCODE_ELSE:
 804    case BRW_OPCODE_ENDIF:
 805    case BRW_OPCODE_BREAK:
 806    case BRW_OPCODE_CONTINUE:
 807       return true;
 808    default:
 809       return false;
 810    }
 811 }
 812
 813 bool
 814 backend_instruction::can_do_source_mods() const
 815 {
 816    switch (opcode) {
 817    case BRW_OPCODE_ADDC:
 818    case BRW_OPCODE_BFE:
 819    case BRW_OPCODE_BFI1:
 820    case BRW_OPCODE_BFI2:
 821    case BRW_OPCODE_BFREV:
 822    case BRW_OPCODE_CBIT:
 823    case BRW_OPCODE_FBH:
 824    case BRW_OPCODE_FBL:
 825    case BRW_OPCODE_SUBB:
 826    case SHADER_OPCODE_BROADCAST:
 827    case SHADER_OPCODE_MOV_INDIRECT:
 828       return false;
 829    default:
 830       return true;
 831    }
 832 }
 833
 834 bool
 835 backend_instruction::can_do_saturate() const
 836 {
 837    switch (opcode) {
 838    case BRW_OPCODE_ADD:
 839    case BRW_OPCODE_ASR:
 840    case BRW_OPCODE_AVG:
 841    case BRW_OPCODE_DP2:
 842    case BRW_OPCODE_DP3:
 843    case BRW_OPCODE_DP4:
 844    case BRW_OPCODE_DPH:
 845    case BRW_OPCODE_F16TO32:
 846    case BRW_OPCODE_F32TO16:
 847    case BRW_OPCODE_LINE:
 848    case BRW_OPCODE_LRP:
 849    case BRW_OPCODE_MAC:
 850    case BRW_OPCODE_MAD:
 851    case BRW_OPCODE_MATH:
 852    case BRW_OPCODE_MOV:
 853    case BRW_OPCODE_MUL:
 854    case SHADER_OPCODE_MULH:
 855    case BRW_OPCODE_PLN:
 856    case BRW_OPCODE_RNDD:
 857    case BRW_OPCODE_RNDE:
 858    case BRW_OPCODE_RNDU:
 859    case BRW_OPCODE_RNDZ:
 860    case BRW_OPCODE_SEL:
 861    case BRW_OPCODE_SHL:
 862    case BRW_OPCODE_SHR:
 863    case FS_OPCODE_LINTERP:
 864    case SHADER_OPCODE_COS:
 865    case SHADER_OPCODE_EXP2:
 866    case SHADER_OPCODE_LOG2:
 867    case SHADER_OPCODE_POW:
 868    case SHADER_OPCODE_RCP:
 869    case SHADER_OPCODE_RSQ:
 870    case SHADER_OPCODE_SIN:
 871    case SHADER_OPCODE_SQRT:
 872       return true;
 873    default:
 874       return false;
 875    }
 876 }
 877
 878 bool
 879 backend_instruction::can_do_cmod() const
 880 {
 881    switch (opcode) {
 882    case BRW_OPCODE_ADD:
 883    case BRW_OPCODE_ADDC:
 884    case BRW_OPCODE_AND:
 885    case BRW_OPCODE_ASR:
 886    case BRW_OPCODE_AVG:
 887    case BRW_OPCODE_CMP:
 888    case BRW_OPCODE_CMPN:
 889    case BRW_OPCODE_DP2:
 890    case BRW_OPCODE_DP3:
 891    case BRW_OPCODE_DP4:
 892    case BRW_OPCODE_DPH:
 893    case BRW_OPCODE_F16TO32:
 894    case BRW_OPCODE_F32TO16:
 895    case BRW_OPCODE_FRC:
 896    case BRW_OPCODE_LINE:
 897    case BRW_OPCODE_LRP:
 898    case BRW_OPCODE_LZD:
 899    case BRW_OPCODE_MAC:
 900    case BRW_OPCODE_MACH:
 901    case BRW_OPCODE_MAD:
 902    case BRW_OPCODE_MOV:
 903    case BRW_OPCODE_MUL:
 904    case BRW_OPCODE_NOT:
 905    case BRW_OPCODE_OR:
 906    case BRW_OPCODE_PLN:
 907    case BRW_OPCODE_RNDD:
 908    case BRW_OPCODE_RNDE:
 909    case BRW_OPCODE_RNDU:
 910    case BRW_OPCODE_RNDZ:
 911    case BRW_OPCODE_SAD2:
 912    case BRW_OPCODE_SADA2:
 913    case BRW_OPCODE_SHL:
 914    case BRW_OPCODE_SHR:
 915    case BRW_OPCODE_SUBB:
 916    case BRW_OPCODE_XOR:
 917    case FS_OPCODE_CINTERP:
 918    case FS_OPCODE_LINTERP:
 919       return true;
 920    default:
 921       return false;
 922    }
 923 }
 924
 925 bool
 926 backend_instruction::reads_accumulator_implicitly() const
 927 {
 928    switch (opcode) {
 929    case BRW_OPCODE_MAC:
 930    case BRW_OPCODE_MACH:
 931    case BRW_OPCODE_SADA2:
 932       return true;
 933    default:
 934       return false;
 935    }
 936 }
 937
 938 bool
 939 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 940 {
 941    return writes_accumulator ||
 942           (devinfo->gen < 6 &&
 943            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 944             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 945              opcode != FS_OPCODE_CINTERP)));
 946 }
 947
 948 bool
 949 backend_instruction::has_side_effects() const
 950 {
 951    switch (opcode) {
 952    case SHADER_OPCODE_UNTYPED_ATOMIC:
 953    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 954    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 955    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 956    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 957    case SHADER_OPCODE_TYPED_ATOMIC:
 958    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 959    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 960    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 961    case SHADER_OPCODE_MEMORY_FENCE:
 962    case SHADER_OPCODE_URB_WRITE_SIMD8:
 963    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 964    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 965    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 966    case FS_OPCODE_FB_WRITE:
 967    case FS_OPCODE_FB_WRITE_LOGICAL:
 968    case SHADER_OPCODE_BARRIER:
 969    case TCS_OPCODE_URB_WRITE:
 970    case TCS_OPCODE_RELEASE_INPUT:
 971       return true;
 972    default:
 973       return eot;
 974    }
 975 }
 976
 977 bool
 978 backend_instruction::is_volatile() const
 979 {
 980    switch (opcode) {
 981    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 982    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 983    case SHADER_OPCODE_TYPED_SURFACE_READ:
 984    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 985    case SHADER_OPCODE_URB_READ_SIMD8:
 986    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 987    case VEC4_OPCODE_URB_READ:
 988       return true;
 989    default:
 990       return false;
 991    }
 992 }
 993
 994 #ifndef NDEBUG
 995 static bool
 996 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
 997 {
 998    bool found = false;
 999    foreach_inst_in_block (backend_instruction, i, block) {
1000       if (inst == i) {
1001          found = true;
1002       }
1003    }
1004    return found;
1005 }
1006 #endif
1007
1008 static void
1009 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1010 {
1011    for (bblock_t *block_iter = start_block->next();
1012         block_iter;
1013         block_iter = block_iter->next()) {
1014       block_iter->start_ip += ip_adjustment;
1015       block_iter->end_ip += ip_adjustment;
1016    }
1017 }
1018
1019 void
1020 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1021 {
1022    assert(this != inst);
1023
1024    if (!this->is_head_sentinel())
1025       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1026
1027    block->end_ip++;
1028
1029    adjust_later_block_ips(block, 1);
1030
1031    exec_node::insert_after(inst);
1032 }
1033
1034 void
1035 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1036 {
1037    assert(this != inst);
1038
1039    if (!this->is_tail_sentinel())
1040       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1041
1042    block->end_ip++;
1043
1044    adjust_later_block_ips(block, 1);
1045
1046    exec_node::insert_before(inst);
1047 }
1048
1049 void
1050 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1051 {
1052    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1053
1054    unsigned num_inst = list->length();
1055
1056    block->end_ip += num_inst;
1057
1058    adjust_later_block_ips(block, num_inst);
1059
1060    exec_node::insert_before(list);
1061 }
1062
1063 void
1064 backend_instruction::remove(bblock_t *block)
1065 {
1066    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1067
1068    adjust_later_block_ips(block, -1);
1069
1070    if (block->start_ip == block->end_ip) {
1071       block->cfg->remove_block(block);
1072    } else {
1073       block->end_ip--;
1074    }
1075
1076    exec_node::remove();
1077 }
1078
1079 void
1080 backend_shader::dump_instructions()
1081 {
1082    dump_instructions(NULL);
1083 }
1084
1085 void
1086 backend_shader::dump_instructions(const char *name)
1087 {
1088    FILE *file = stderr;
1089    if (name && geteuid() != 0) {
1090       file = fopen(name, "w");
1091       if (!file)
1092          file = stderr;
1093    }
1094
1095    if (cfg) {
1096       int ip = 0;
1097       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1098          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1099             fprintf(file, "%4d: ", ip++);
1100          dump_instruction(inst, file);
1101       }
1102    } else {
1103       int ip = 0;
1104       foreach_in_list(backend_instruction, inst, &instructions) {
1105          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1106             fprintf(file, "%4d: ", ip++);
1107          dump_instruction(inst, file);
1108       }
1109    }
1110
1111    if (file != stderr) {
1112       fclose(file);
1113    }
1114 }
1115
1116 void
1117 backend_shader::calculate_cfg()
1118 {
1119    if (this->cfg)
1120       return;
1121    cfg = new(mem_ctx) cfg_t(&this->instructions);
1122 }
1123
1124 extern "C" const unsigned *
1125 brw_compile_tes(const struct brw_compiler *compiler,
1126                 void *log_data,
1127                 void *mem_ctx,
1128                 const struct brw_tes_prog_key *key,
1129                 const struct brw_vue_map *input_vue_map,
1130                 struct brw_tes_prog_data *prog_data,
1131                 const nir_shader *src_shader,
1132                 struct gl_program *prog,
1133                 int shader_time_index,
1134                 char **error_str)
1135 {
1136    const struct gen_device_info *devinfo = compiler->devinfo;
1137    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1138    const unsigned *assembly;
1139
1140    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1141    nir->info.inputs_read = key->inputs_read;
1142    nir->info.patch_inputs_read = key->patch_inputs_read;
1143
1144    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1145    brw_nir_lower_tes_inputs(nir, input_vue_map);
1146    brw_nir_lower_vue_outputs(nir, is_scalar);
1147    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1148
1149    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1150                        nir->info.outputs_written,
1151                        nir->info.separate_shader);
1152
1153    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1154
1155    assert(output_size_bytes >= 1);
1156    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1157       if (error_str)
1158          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1159       return NULL;
1160    }
1161
1162    prog_data->base.clip_distance_mask =
1163       ((1 << nir->info.clip_distance_array_size) - 1);
1164    prog_data->base.cull_distance_mask =
1165       ((1 << nir->info.cull_distance_array_size) - 1) <<
1166       nir->info.clip_distance_array_size;
1167
1168    /* URB entry sizes are stored as a multiple of 64 bytes. */
1169    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1170
1171    /* On Cannonlake software shall not program an allocation size that
1172     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1173     */
1174    if (devinfo->gen == 10 &&
1175        prog_data->base.urb_entry_size % 3 == 0)
1176       prog_data->base.urb_entry_size++;
1177
1178    prog_data->base.urb_read_length = 0;
1179
1180    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1181    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1182                  TESS_SPACING_FRACTIONAL_ODD - 1);
1183    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1184                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1185
1186    prog_data->partitioning =
1187       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1188
1189    switch (nir->info.tess.primitive_mode) {
1190    case GL_QUADS:
1191       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1192       break;
1193    case GL_TRIANGLES:
1194       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1195       break;
1196    case GL_ISOLINES:
1197       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1198       break;
1199    default:
1200       unreachable("invalid domain shader primitive mode");
1201    }
1202
1203    if (nir->info.tess.point_mode) {
1204       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1205    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1206       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1207    } else {
1208       /* Hardware winding order is backwards from OpenGL */
1209       prog_data->output_topology =
1210          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1211                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1212    }
1213
1214    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1215       fprintf(stderr, "TES Input ");
1216       brw_print_vue_map(stderr, input_vue_map);
1217       fprintf(stderr, "TES Output ");
1218       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1219    }
1220
1221    if (is_scalar) {
1222       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1223                    &prog_data->base.base, NULL, nir, 8,
1224                    shader_time_index, input_vue_map);
1225       if (!v.run_tes()) {
1226          if (error_str)
1227             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1228          return NULL;
1229       }
1230
1231       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1232       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1233
1234       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1235                      &prog_data->base.base, v.promoted_constants, false,
1236                      MESA_SHADER_TESS_EVAL);
1237       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1238          g.enable_debug(ralloc_asprintf(mem_ctx,
1239                                         "%s tessellation evaluation shader %s",
1240                                         nir->info.label ? nir->info.label
1241                                                         : "unnamed",
1242                                         nir->info.name));
1243       }
1244
1245       g.generate_code(v.cfg, 8);
1246
1247       assembly = g.get_assembly(&prog_data->base.base.program_size);
1248    } else {
1249       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1250                               nir, mem_ctx, shader_time_index);
1251       if (!v.run()) {
1252          if (error_str)
1253             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1254          return NULL;
1255       }
1256
1257       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1258          v.dump_instructions();
1259
1260       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1261                                             &prog_data->base, v.cfg,
1262                                             &prog_data->base.base.program_size);
1263    }
1264
1265    return assembly;
1266 }