2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_compiler.h"
30 #include "brw_eu_defines.h"
32 #include "compiler/nir/nir.h"
35 #include "brw_ir_allocator.h"
38 #define MAX_SAMPLER_MESSAGE_SIZE 11
39 #define MAX_VGRF_SIZE 16
42 struct backend_reg
: private brw_reg
45 backend_reg(const struct brw_reg
®
) : brw_reg(reg
) {}
47 const brw_reg
&as_brw_reg() const
49 assert(file
== ARF
|| file
== FIXED_GRF
|| file
== MRF
|| file
== IMM
);
51 return static_cast<const brw_reg
&>(*this);
56 assert(file
== ARF
|| file
== FIXED_GRF
|| file
== MRF
|| file
== IMM
);
58 return static_cast<brw_reg
&>(*this);
61 bool equals(const backend_reg
&r
) const;
65 bool is_negative_one() const;
67 bool is_accumulator() const;
69 /** Offset from the start of the (virtual) register in bytes. */
74 using brw_reg::negate
;
76 using brw_reg::address_mode
;
80 using brw_reg::swizzle
;
81 using brw_reg::writemask
;
82 using brw_reg::indirect_offset
;
83 using brw_reg::vstride
;
85 using brw_reg::hstride
;
98 struct backend_instruction
: public exec_node
{
99 bool is_3src(const struct gen_device_info
*devinfo
) const;
101 bool is_math() const;
102 bool is_control_flow() const;
103 bool is_commutative() const;
104 bool can_do_source_mods() const;
105 bool can_do_saturate() const;
106 bool can_do_cmod() const;
107 bool reads_accumulator_implicitly() const;
108 bool writes_accumulator_implicitly(const struct gen_device_info
*devinfo
) const;
110 void remove(bblock_t
*block
);
111 void insert_after(bblock_t
*block
, backend_instruction
*inst
);
112 void insert_before(bblock_t
*block
, backend_instruction
*inst
);
113 void insert_before(bblock_t
*block
, exec_list
*list
);
116 * True if the instruction has side effects other than writing to
117 * its destination registers. You are expected not to reorder or
118 * optimize these out unless you know what you are doing.
120 bool has_side_effects() const;
123 * True if the instruction might be affected by side effects of other
126 bool is_volatile() const;
128 struct backend_instruction
{
129 struct exec_node link
;
132 * Annotation for the generated IR. One of the two can be set.
135 const char *annotation
;
139 * Execution size of the instruction. This is used by the generator to
140 * generate the correct binary for the given instruction. Current valid
141 * values are 1, 4, 8, 16, 32.
146 * Channel group from the hardware execution and predication mask that
147 * should be applied to the instruction. The subset of channel enable
148 * signals (calculated from the EU control flow and predication state)
149 * given by [group, group + exec_size) will be used to mask GRF writes and
150 * any other side effects of the instruction.
154 uint32_t offset
; /**< spill/unspill offset or texture offset bitfield */
155 uint8_t mlen
; /**< SEND message length */
156 int8_t base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
157 uint8_t target
; /**< MRT target. */
158 unsigned size_written
; /**< Data written to the destination register in bytes. */
160 enum opcode opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
161 enum brw_conditional_mod conditional_mod
; /**< BRW_CONDITIONAL_* */
162 enum brw_predicate predicate
;
163 bool predicate_inverse
:1;
164 bool writes_accumulator
:1; /**< instruction implicitly writes accumulator */
165 bool force_writemask_all
:1;
169 bool shadow_compare
:1;
172 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
173 * mod and predication.
175 unsigned flag_subreg
:1;
177 /** The number of hardware registers used for a message header. */
183 enum instruction_scheduler_mode
{
185 SCHEDULE_PRE_NON_LIFO
,
190 struct backend_shader
{
193 backend_shader(const struct brw_compiler
*compiler
,
196 const nir_shader
*shader
,
197 struct brw_stage_prog_data
*stage_prog_data
);
200 virtual ~backend_shader();
202 const struct brw_compiler
*compiler
;
203 void *log_data
; /* Passed to compiler->*_log functions */
205 const struct gen_device_info
* const devinfo
;
206 const nir_shader
*nir
;
207 struct brw_stage_prog_data
* const stage_prog_data
;
209 /** ralloc context for temporary data used during compile */
213 * List of either fs_inst or vec4_instruction (inheriting from
214 * backend_instruction)
216 exec_list instructions
;
220 gl_shader_stage stage
;
222 const char *stage_name
;
223 const char *stage_abbrev
;
225 brw::simple_allocator alloc
;
227 virtual void dump_instruction(backend_instruction
*inst
) = 0;
228 virtual void dump_instruction(backend_instruction
*inst
, FILE *file
) = 0;
229 virtual void dump_instructions();
230 virtual void dump_instructions(const char *name
);
232 void calculate_cfg();
234 virtual void invalidate_live_intervals() = 0;
237 bool brw_texture_offset(int *offsets
,
238 unsigned num_components
,
239 uint32_t *offset_bits
);
242 struct backend_shader
;
243 #endif /* __cplusplus */
245 enum brw_reg_type
brw_type_for_base_type(const struct glsl_type
*type
);
246 enum brw_conditional_mod
brw_conditional_for_comparison(unsigned int op
);
247 uint32_t brw_math_function(enum opcode op
);
248 const char *brw_instruction_name(const struct gen_device_info
*devinfo
,
250 bool brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
251 bool brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
252 bool brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
254 bool opt_predicated_break(struct backend_shader
*s
);
260 /* brw_fs_reg_allocate.cpp */
261 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
263 /* brw_vec4_reg_allocate.cpp */
264 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
267 extern const char *const conditional_modifier
[16];
268 extern const char *const pred_ctrl_align16
[16];
270 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
272 brw_get_scratch_size(int size
)
274 return MAX2(1024, util_next_power_of_two(size
));
278 * Scratch data used when compiling a GLSL geometry shader.
280 struct brw_gs_compile
282 struct brw_gs_prog_key key
;
283 struct brw_vue_map input_vue_map
;
285 unsigned control_data_bits_per_vertex
;
286 unsigned control_data_header_size_bits
;
293 #endif /* BRW_SHADER_H */