src/intel/compiler/brw_shader.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_SHADER_H
  25 #define BRW_SHADER_H
  26
  27 #include <stdint.h>
  28 #include "brw_reg.h"
  29 #include "brw_compiler.h"
  30 #include "brw_eu_defines.h"
  31 #include "brw_inst.h"
  32 #include "compiler/nir/nir.h"
  33
  34 #ifdef __cplusplus
  35 #include "brw_ir_allocator.h"
  36 #endif
  37
  38 #define MAX_SAMPLER_MESSAGE_SIZE 11
  39 #define MAX_VGRF_SIZE 16
  40
  41 #ifdef __cplusplus
  42 struct backend_reg : private brw_reg
  43 {
  44    backend_reg() {}
  45    backend_reg(const struct brw_reg &reg) : brw_reg(reg) {}
  46
  47    const brw_reg &as_brw_reg() const
  48    {
  49       assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
  50       assert(offset == 0);
  51       return static_cast<const brw_reg &>(*this);
  52    }
  53
  54    brw_reg &as_brw_reg()
  55    {
  56       assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
  57       assert(offset == 0);
  58       return static_cast<brw_reg &>(*this);
  59    }
  60
  61    bool equals(const backend_reg &r) const;
  62    bool negative_equals(const backend_reg &r) const;
  63
  64    bool is_zero() const;
  65    bool is_one() const;
  66    bool is_negative_one() const;
  67    bool is_null() const;
  68    bool is_accumulator() const;
  69
  70    /** Offset from the start of the (virtual) register in bytes. */
  71    uint16_t offset;
  72
  73    using brw_reg::type;
  74    using brw_reg::file;
  75    using brw_reg::negate;
  76    using brw_reg::abs;
  77    using brw_reg::address_mode;
  78    using brw_reg::subnr;
  79    using brw_reg::nr;
  80
  81    using brw_reg::swizzle;
  82    using brw_reg::writemask;
  83    using brw_reg::indirect_offset;
  84    using brw_reg::vstride;
  85    using brw_reg::width;
  86    using brw_reg::hstride;
  87
  88    using brw_reg::df;
  89    using brw_reg::f;
  90    using brw_reg::d;
  91    using brw_reg::ud;
  92    using brw_reg::d64;
  93    using brw_reg::u64;
  94 };
  95 #endif
  96
  97 struct cfg_t;
  98 struct bblock_t;
  99
 100 #ifdef __cplusplus
 101 struct backend_instruction : public exec_node {
 102    bool is_3src(const struct gen_device_info *devinfo) const;
 103    bool is_tex() const;
 104    bool is_math() const;
 105    bool is_control_flow() const;
 106    bool is_commutative() const;
 107    bool can_do_source_mods() const;
 108    bool can_do_saturate() const;
 109    bool can_do_cmod() const;
 110    bool reads_accumulator_implicitly() const;
 111    bool writes_accumulator_implicitly(const struct gen_device_info *devinfo) const;
 112
 113    void remove(bblock_t *block);
 114    void insert_after(bblock_t *block, backend_instruction *inst);
 115    void insert_before(bblock_t *block, backend_instruction *inst);
 116    void insert_before(bblock_t *block, exec_list *list);
 117
 118    /**
 119     * True if the instruction has side effects other than writing to
 120     * its destination registers.  You are expected not to reorder or
 121     * optimize these out unless you know what you are doing.
 122     */
 123    bool has_side_effects() const;
 124
 125    /**
 126     * True if the instruction might be affected by side effects of other
 127     * instructions.
 128     */
 129    bool is_volatile() const;
 130 #else
 131 struct backend_instruction {
 132    struct exec_node link;
 133 #endif
 134    /** @{
 135     * Annotation for the generated IR.  One of the two can be set.
 136     */
 137    const void *ir;
 138    const char *annotation;
 139    /** @} */
 140
 141    /**
 142     * Execution size of the instruction.  This is used by the generator to
 143     * generate the correct binary for the given instruction.  Current valid
 144     * values are 1, 4, 8, 16, 32.
 145     */
 146    uint8_t exec_size;
 147
 148    /**
 149     * Channel group from the hardware execution and predication mask that
 150     * should be applied to the instruction.  The subset of channel enable
 151     * signals (calculated from the EU control flow and predication state)
 152     * given by [group, group + exec_size) will be used to mask GRF writes and
 153     * any other side effects of the instruction.
 154     */
 155    uint8_t group;
 156
 157    uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
 158    uint8_t mlen; /**< SEND message length */
 159    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 160    uint8_t target; /**< MRT target. */
 161    unsigned size_written; /**< Data written to the destination register in bytes. */
 162
 163    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 164    enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
 165    enum brw_predicate predicate;
 166    bool predicate_inverse:1;
 167    bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
 168    bool force_writemask_all:1;
 169    bool no_dd_clear:1;
 170    bool no_dd_check:1;
 171    bool saturate:1;
 172    bool shadow_compare:1;
 173    bool eot:1;
 174
 175    /* Chooses which flag subregister (f0.0 to f1.1) is used for conditional
 176     * mod and predication.
 177     */
 178    unsigned flag_subreg:2;
 179
 180    /** The number of hardware registers used for a message header. */
 181    uint8_t header_size;
 182 };
 183
 184 #ifdef __cplusplus
 185
 186 enum instruction_scheduler_mode {
 187    SCHEDULE_PRE,
 188    SCHEDULE_PRE_NON_LIFO,
 189    SCHEDULE_PRE_LIFO,
 190    SCHEDULE_POST,
 191 };
 192
 193 struct backend_shader {
 194 protected:
 195
 196    backend_shader(const struct brw_compiler *compiler,
 197                   void *log_data,
 198                   void *mem_ctx,
 199                   const nir_shader *shader,
 200                   struct brw_stage_prog_data *stage_prog_data);
 201
 202 public:
 203    virtual ~backend_shader();
 204
 205    const struct brw_compiler *compiler;
 206    void *log_data; /* Passed to compiler->*_log functions */
 207
 208    const struct gen_device_info * const devinfo;
 209    const nir_shader *nir;
 210    struct brw_stage_prog_data * const stage_prog_data;
 211
 212    /** ralloc context for temporary data used during compile */
 213    void *mem_ctx;
 214
 215    /**
 216     * List of either fs_inst or vec4_instruction (inheriting from
 217     * backend_instruction)
 218     */
 219    exec_list instructions;
 220
 221    cfg_t *cfg;
 222
 223    gl_shader_stage stage;
 224    bool debug_enabled;
 225    const char *stage_name;
 226    const char *stage_abbrev;
 227
 228    brw::simple_allocator alloc;
 229
 230    virtual void dump_instruction(backend_instruction *inst) = 0;
 231    virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
 232    virtual void dump_instructions();
 233    virtual void dump_instructions(const char *name);
 234
 235    void calculate_cfg();
 236
 237    virtual void invalidate_live_intervals() = 0;
 238 };
 239
 240 bool brw_texture_offset(int *offsets,
 241                         unsigned num_components,
 242                         uint32_t *offset_bits);
 243
 244 #else
 245 struct backend_shader;
 246 #endif /* __cplusplus */
 247
 248 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
 249 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
 250 uint32_t brw_math_function(enum opcode op);
 251 const char *brw_instruction_name(const struct gen_device_info *devinfo,
 252                                  enum opcode op);
 253 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 254 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 255 bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
 256
 257 bool opt_predicated_break(struct backend_shader *s);
 258
 259 #ifdef __cplusplus
 260 extern "C" {
 261 #endif
 262
 263 /* brw_fs_reg_allocate.cpp */
 264 void brw_fs_alloc_reg_sets(struct brw_compiler *compiler);
 265
 266 /* brw_vec4_reg_allocate.cpp */
 267 void brw_vec4_alloc_reg_set(struct brw_compiler *compiler);
 268
 269 /* brw_disasm.c */
 270 extern const char *const conditional_modifier[16];
 271 extern const char *const pred_ctrl_align16[16];
 272
 273 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
 274 static inline int
 275 brw_get_scratch_size(int size)
 276 {
 277    return MAX2(1024, util_next_power_of_two(size));
 278 }
 279
 280 /**
 281  * Scratch data used when compiling a GLSL geometry shader.
 282  */
 283 struct brw_gs_compile
 284 {
 285    struct brw_gs_prog_key key;
 286    struct brw_vue_map input_vue_map;
 287
 288    unsigned control_data_bits_per_vertex;
 289    unsigned control_data_header_size_bits;
 290 };
 291
 292 #ifdef __cplusplus
 293 }
 294 #endif
 295
 296 #endif /* BRW_SHADER_H */