2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_vec4_builder.h"
29 #include "brw_vec4_live_variables.h"
30 #include "brw_vec4_vs.h"
31 #include "brw_dead_control_flow.h"
32 #include "dev/gen_debug.h"
33 #include "program/prog_parameter.h"
34 #include "util/u_math.h"
36 #define MAX_INSTRUCTION (1 << 30)
45 memset((void*)this, 0, sizeof(*this));
46 this->file
= BAD_FILE
;
47 this->type
= BRW_REGISTER_TYPE_UD
;
50 src_reg::src_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
)
56 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
57 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
59 this->swizzle
= BRW_SWIZZLE_XYZW
;
61 this->type
= brw_type_for_base_type(type
);
64 /** Generic unset register constructor. */
70 src_reg::src_reg(struct ::brw_reg reg
) :
77 src_reg::src_reg(const dst_reg
®
) :
80 this->reladdr
= reg
.reladdr
;
81 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
87 memset((void*)this, 0, sizeof(*this));
88 this->file
= BAD_FILE
;
89 this->type
= BRW_REGISTER_TYPE_UD
;
90 this->writemask
= WRITEMASK_XYZW
;
98 dst_reg::dst_reg(enum brw_reg_file file
, int nr
)
106 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
,
113 this->type
= brw_type_for_base_type(type
);
114 this->writemask
= writemask
;
117 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, brw_reg_type type
,
125 this->writemask
= writemask
;
128 dst_reg::dst_reg(struct ::brw_reg reg
) :
132 this->reladdr
= NULL
;
135 dst_reg::dst_reg(const src_reg
®
) :
138 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
139 this->reladdr
= reg
.reladdr
;
143 dst_reg::equals(const dst_reg
&r
) const
145 return (this->backend_reg::equals(r
) &&
146 (reladdr
== r
.reladdr
||
147 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))));
151 vec4_instruction::is_send_from_grf()
154 case SHADER_OPCODE_SHADER_TIME_ADD
:
155 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
156 case VEC4_OPCODE_UNTYPED_ATOMIC
:
157 case VEC4_OPCODE_UNTYPED_SURFACE_READ
:
158 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE
:
159 case VEC4_OPCODE_URB_READ
:
160 case TCS_OPCODE_URB_WRITE
:
161 case TCS_OPCODE_RELEASE_INPUT
:
162 case SHADER_OPCODE_BARRIER
:
170 * Returns true if this instruction's sources and destinations cannot
171 * safely be the same register.
173 * In most cases, a register can be written over safely by the same
174 * instruction that is its last use. For a single instruction, the
175 * sources are dereferenced before writing of the destination starts
178 * However, there are a few cases where this can be problematic:
180 * - Virtual opcodes that translate to multiple instructions in the
181 * code generator: if src == dst and one instruction writes the
182 * destination before a later instruction reads the source, then
183 * src will have been clobbered.
185 * The register allocator uses this information to set up conflicts between
186 * GRF sources and the destination.
189 vec4_instruction::has_source_and_destination_hazard() const
192 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
193 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
194 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
197 /* 8-wide compressed DF operations are executed as two 4-wide operations,
198 * so we have a src/dst hazard if the first half of the instruction
199 * overwrites the source of the second half. Prevent this by marking
200 * compressed instructions as having src/dst hazards, so the register
201 * allocator assigns safe register regions for dst and srcs.
203 return size_written
> REG_SIZE
;
208 vec4_instruction::size_read(unsigned arg
) const
211 case SHADER_OPCODE_SHADER_TIME_ADD
:
212 case VEC4_OPCODE_UNTYPED_ATOMIC
:
213 case VEC4_OPCODE_UNTYPED_SURFACE_READ
:
214 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE
:
215 case TCS_OPCODE_URB_WRITE
:
217 return mlen
* REG_SIZE
;
219 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
221 return mlen
* REG_SIZE
;
227 switch (src
[arg
].file
) {
232 return 4 * type_sz(src
[arg
].type
);
234 /* XXX - Represent actual vertical stride. */
235 return exec_size
* type_sz(src
[arg
].type
);
240 vec4_instruction::can_do_source_mods(const struct gen_device_info
*devinfo
)
242 if (devinfo
->gen
== 6 && is_math())
245 if (is_send_from_grf())
248 if (!backend_instruction::can_do_source_mods())
255 vec4_instruction::can_do_cmod()
257 if (!backend_instruction::can_do_cmod())
260 /* The accumulator result appears to get used for the conditional modifier
261 * generation. When negating a UD value, there is a 33rd bit generated for
262 * the sign in the accumulator value, so now you can't check, for example,
263 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
265 for (unsigned i
= 0; i
< 3; i
++) {
266 if (src
[i
].file
!= BAD_FILE
&&
267 type_is_unsigned_int(src
[i
].type
) && src
[i
].negate
)
275 vec4_instruction::can_do_writemask(const struct gen_device_info
*devinfo
)
278 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
279 case VEC4_OPCODE_DOUBLE_TO_F32
:
280 case VEC4_OPCODE_DOUBLE_TO_D32
:
281 case VEC4_OPCODE_DOUBLE_TO_U32
:
282 case VEC4_OPCODE_TO_DOUBLE
:
283 case VEC4_OPCODE_PICK_LOW_32BIT
:
284 case VEC4_OPCODE_PICK_HIGH_32BIT
:
285 case VEC4_OPCODE_SET_LOW_32BIT
:
286 case VEC4_OPCODE_SET_HIGH_32BIT
:
287 case VS_OPCODE_PULL_CONSTANT_LOAD
:
288 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
289 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
290 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
291 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
292 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
293 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
294 case VEC4_OPCODE_URB_READ
:
295 case SHADER_OPCODE_MOV_INDIRECT
:
298 /* The MATH instruction on Gen6 only executes in align1 mode, which does
299 * not support writemasking.
301 if (devinfo
->gen
== 6 && is_math())
312 vec4_instruction::can_change_types() const
314 return dst
.type
== src
[0].type
&&
315 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
316 (opcode
== BRW_OPCODE_MOV
||
317 (opcode
== BRW_OPCODE_SEL
&&
318 dst
.type
== src
[1].type
&&
319 predicate
!= BRW_PREDICATE_NONE
&&
320 !src
[1].abs
&& !src
[1].negate
));
324 * Returns how many MRFs an opcode will write over.
326 * Note that this is not the 0 or 1 implied writes in an actual gen
327 * instruction -- the generate_* functions generate additional MOVs
331 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
333 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
336 switch (inst
->opcode
) {
337 case SHADER_OPCODE_RCP
:
338 case SHADER_OPCODE_RSQ
:
339 case SHADER_OPCODE_SQRT
:
340 case SHADER_OPCODE_EXP2
:
341 case SHADER_OPCODE_LOG2
:
342 case SHADER_OPCODE_SIN
:
343 case SHADER_OPCODE_COS
:
345 case SHADER_OPCODE_INT_QUOTIENT
:
346 case SHADER_OPCODE_INT_REMAINDER
:
347 case SHADER_OPCODE_POW
:
348 case TCS_OPCODE_THREAD_END
:
350 case VS_OPCODE_URB_WRITE
:
352 case VS_OPCODE_PULL_CONSTANT_LOAD
:
354 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
356 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
358 case GS_OPCODE_URB_WRITE
:
359 case GS_OPCODE_URB_WRITE_ALLOCATE
:
360 case GS_OPCODE_THREAD_END
:
362 case GS_OPCODE_FF_SYNC
:
364 case TCS_OPCODE_URB_WRITE
:
366 case SHADER_OPCODE_SHADER_TIME_ADD
:
368 case SHADER_OPCODE_TEX
:
369 case SHADER_OPCODE_TXL
:
370 case SHADER_OPCODE_TXD
:
371 case SHADER_OPCODE_TXF
:
372 case SHADER_OPCODE_TXF_CMS
:
373 case SHADER_OPCODE_TXF_CMS_W
:
374 case SHADER_OPCODE_TXF_MCS
:
375 case SHADER_OPCODE_TXS
:
376 case SHADER_OPCODE_TG4
:
377 case SHADER_OPCODE_TG4_OFFSET
:
378 case SHADER_OPCODE_SAMPLEINFO
:
379 case SHADER_OPCODE_GET_BUFFER_SIZE
:
380 return inst
->header_size
;
382 unreachable("not reached");
387 src_reg::equals(const src_reg
&r
) const
389 return (this->backend_reg::equals(r
) &&
390 !reladdr
&& !r
.reladdr
);
394 src_reg::negative_equals(const src_reg
&r
) const
396 return this->backend_reg::negative_equals(r
) &&
397 !reladdr
&& !r
.reladdr
;
401 vec4_visitor::opt_vector_float()
403 bool progress
= false;
405 foreach_block(block
, cfg
) {
406 unsigned last_reg
= ~0u, last_offset
= ~0u;
407 enum brw_reg_file last_reg_file
= BAD_FILE
;
409 uint8_t imm
[4] = { 0 };
411 vec4_instruction
*imm_inst
[4];
412 unsigned writemask
= 0;
413 enum brw_reg_type dest_type
= BRW_REGISTER_TYPE_F
;
415 foreach_inst_in_block_safe(vec4_instruction
, inst
, block
) {
417 enum brw_reg_type need_type
= BRW_REGISTER_TYPE_LAST
;
419 /* Look for unconditional MOVs from an immediate with a partial
420 * writemask. Skip type-conversion MOVs other than integer 0,
421 * where the type doesn't matter. See if the immediate can be
422 * represented as a VF.
424 if (inst
->opcode
== BRW_OPCODE_MOV
&&
425 inst
->src
[0].file
== IMM
&&
426 inst
->predicate
== BRW_PREDICATE_NONE
&&
427 inst
->dst
.writemask
!= WRITEMASK_XYZW
&&
428 type_sz(inst
->src
[0].type
) < 8 &&
429 (inst
->src
[0].type
== inst
->dst
.type
|| inst
->src
[0].d
== 0)) {
431 vf
= brw_float_to_vf(inst
->src
[0].d
);
432 need_type
= BRW_REGISTER_TYPE_D
;
435 vf
= brw_float_to_vf(inst
->src
[0].f
);
436 need_type
= BRW_REGISTER_TYPE_F
;
442 /* If this wasn't a MOV, or the destination register doesn't match,
443 * or we have to switch destination types, then this breaks our
444 * sequence. Combine anything we've accumulated so far.
446 if (last_reg
!= inst
->dst
.nr
||
447 last_offset
!= inst
->dst
.offset
||
448 last_reg_file
!= inst
->dst
.file
||
449 (vf
> 0 && dest_type
!= need_type
)) {
451 if (inst_count
> 1) {
453 memcpy(&vf
, imm
, sizeof(vf
));
454 vec4_instruction
*mov
= MOV(imm_inst
[0]->dst
, brw_imm_vf(vf
));
455 mov
->dst
.type
= dest_type
;
456 mov
->dst
.writemask
= writemask
;
457 inst
->insert_before(block
, mov
);
459 for (int i
= 0; i
< inst_count
; i
++) {
460 imm_inst
[i
]->remove(block
);
469 dest_type
= BRW_REGISTER_TYPE_F
;
471 for (int i
= 0; i
< 4; i
++) {
476 /* Record this instruction's value (if it was representable). */
478 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
480 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
482 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
484 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
487 writemask
|= inst
->dst
.writemask
;
488 imm_inst
[inst_count
++] = inst
;
490 last_reg
= inst
->dst
.nr
;
491 last_offset
= inst
->dst
.offset
;
492 last_reg_file
= inst
->dst
.file
;
494 dest_type
= need_type
;
500 invalidate_live_intervals();
505 /* Replaces unused channels of a swizzle with channels that are used.
507 * For instance, this pass transforms
509 * mov vgrf4.yz, vgrf5.wxzy
513 * mov vgrf4.yz, vgrf5.xxzx
515 * This eliminates false uses of some channels, letting dead code elimination
516 * remove the instructions that wrote them.
519 vec4_visitor::opt_reduce_swizzle()
521 bool progress
= false;
523 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
524 if (inst
->dst
.file
== BAD_FILE
||
525 inst
->dst
.file
== ARF
||
526 inst
->dst
.file
== FIXED_GRF
||
527 inst
->is_send_from_grf())
532 /* Determine which channels of the sources are read. */
533 switch (inst
->opcode
) {
534 case VEC4_OPCODE_PACK_BYTES
:
536 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
537 * but all four of src1.
539 swizzle
= brw_swizzle_for_size(4);
542 swizzle
= brw_swizzle_for_size(3);
545 swizzle
= brw_swizzle_for_size(2);
548 case VEC4_OPCODE_TO_DOUBLE
:
549 case VEC4_OPCODE_DOUBLE_TO_F32
:
550 case VEC4_OPCODE_DOUBLE_TO_D32
:
551 case VEC4_OPCODE_DOUBLE_TO_U32
:
552 case VEC4_OPCODE_PICK_LOW_32BIT
:
553 case VEC4_OPCODE_PICK_HIGH_32BIT
:
554 case VEC4_OPCODE_SET_LOW_32BIT
:
555 case VEC4_OPCODE_SET_HIGH_32BIT
:
556 swizzle
= brw_swizzle_for_size(4);
560 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
564 /* Update sources' swizzles. */
565 for (int i
= 0; i
< 3; i
++) {
566 if (inst
->src
[i
].file
!= VGRF
&&
567 inst
->src
[i
].file
!= ATTR
&&
568 inst
->src
[i
].file
!= UNIFORM
)
571 const unsigned new_swizzle
=
572 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
573 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
574 inst
->src
[i
].swizzle
= new_swizzle
;
581 invalidate_live_intervals();
587 vec4_visitor::split_uniform_registers()
589 /* Prior to this, uniforms have been in an array sized according to
590 * the number of vector uniforms present, sparsely filled (so an
591 * aggregate results in reg indices being skipped over). Now we're
592 * going to cut those aggregates up so each .nr index is one
593 * vector. The goal is to make elimination of unused uniform
594 * components easier later.
596 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
597 for (int i
= 0 ; i
< 3; i
++) {
598 if (inst
->src
[i
].file
!= UNIFORM
)
601 assert(!inst
->src
[i
].reladdr
);
603 inst
->src
[i
].nr
+= inst
->src
[i
].offset
/ 16;
604 inst
->src
[i
].offset
%= 16;
609 /* This function returns the register number where we placed the uniform */
611 set_push_constant_loc(const int nr_uniforms
, int *new_uniform_count
,
612 const int src
, const int size
, const int channel_size
,
613 int *new_loc
, int *new_chan
,
617 /* Find the lowest place we can slot this uniform in. */
618 for (dst
= 0; dst
< nr_uniforms
; dst
++) {
619 if (ALIGN(new_chans_used
[dst
], channel_size
) + size
<= 4)
623 assert(dst
< nr_uniforms
);
626 new_chan
[src
] = ALIGN(new_chans_used
[dst
], channel_size
);
627 new_chans_used
[dst
] = ALIGN(new_chans_used
[dst
], channel_size
) + size
;
629 *new_uniform_count
= MAX2(*new_uniform_count
, dst
+ 1);
634 vec4_visitor::pack_uniform_registers()
636 uint8_t chans_used
[this->uniforms
];
637 int new_loc
[this->uniforms
];
638 int new_chan
[this->uniforms
];
639 bool is_aligned_to_dvec4
[this->uniforms
];
640 int new_chans_used
[this->uniforms
];
641 int channel_sizes
[this->uniforms
];
643 memset(chans_used
, 0, sizeof(chans_used
));
644 memset(new_loc
, 0, sizeof(new_loc
));
645 memset(new_chan
, 0, sizeof(new_chan
));
646 memset(new_chans_used
, 0, sizeof(new_chans_used
));
647 memset(is_aligned_to_dvec4
, 0, sizeof(is_aligned_to_dvec4
));
648 memset(channel_sizes
, 0, sizeof(channel_sizes
));
650 /* Find which uniform vectors are actually used by the program. We
651 * expect unused vector elements when we've moved array access out
652 * to pull constants, and from some GLSL code generators like wine.
654 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
656 switch (inst
->opcode
) {
657 case VEC4_OPCODE_PACK_BYTES
:
669 readmask
= inst
->dst
.writemask
;
673 for (int i
= 0 ; i
< 3; i
++) {
674 if (inst
->src
[i
].file
!= UNIFORM
)
677 assert(type_sz(inst
->src
[i
].type
) % 4 == 0);
678 int channel_size
= type_sz(inst
->src
[i
].type
) / 4;
680 int reg
= inst
->src
[i
].nr
;
681 for (int c
= 0; c
< 4; c
++) {
682 if (!(readmask
& (1 << c
)))
685 unsigned channel
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1;
686 unsigned used
= MAX2(chans_used
[reg
], channel
* channel_size
);
688 chans_used
[reg
] = used
;
689 channel_sizes
[reg
] = MAX2(channel_sizes
[reg
], channel_size
);
691 is_aligned_to_dvec4
[reg
] = true;
692 is_aligned_to_dvec4
[reg
+ 1] = true;
693 chans_used
[reg
+ 1] = used
- 4;
694 channel_sizes
[reg
+ 1] = MAX2(channel_sizes
[reg
+ 1], channel_size
);
699 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
700 inst
->src
[0].file
== UNIFORM
) {
701 assert(inst
->src
[2].file
== BRW_IMMEDIATE_VALUE
);
702 assert(inst
->src
[0].subnr
== 0);
704 unsigned bytes_read
= inst
->src
[2].ud
;
705 assert(bytes_read
% 4 == 0);
706 unsigned vec4s_read
= DIV_ROUND_UP(bytes_read
, 16);
708 /* We just mark every register touched by a MOV_INDIRECT as being
709 * fully used. This ensures that it doesn't broken up piecewise by
710 * the next part of our packing algorithm.
712 int reg
= inst
->src
[0].nr
;
713 int channel_size
= type_sz(inst
->src
[0].type
) / 4;
714 for (unsigned i
= 0; i
< vec4s_read
; i
++) {
715 chans_used
[reg
+ i
] = 4;
716 channel_sizes
[reg
+ i
] = MAX2(channel_sizes
[reg
+ i
], channel_size
);
721 int new_uniform_count
= 0;
723 /* As the uniforms are going to be reordered, take the data from a temporary
724 * copy of the original param[].
726 uint32_t *param
= ralloc_array(NULL
, uint32_t, stage_prog_data
->nr_params
);
727 memcpy(param
, stage_prog_data
->param
,
728 sizeof(uint32_t) * stage_prog_data
->nr_params
);
730 /* Now, figure out a packing of the live uniform vectors into our
731 * push constants. Start with dvec{3,4} because they are aligned to
732 * dvec4 size (2 vec4).
734 for (int src
= 0; src
< uniforms
; src
++) {
735 int size
= chans_used
[src
];
737 if (size
== 0 || !is_aligned_to_dvec4
[src
])
740 /* dvec3 are aligned to dvec4 size, apply the alignment of the size
741 * to 4 to avoid moving last component of a dvec3 to the available
742 * location at the end of a previous dvec3. These available locations
743 * could be filled by smaller variables in next loop.
745 size
= ALIGN(size
, 4);
746 int dst
= set_push_constant_loc(uniforms
, &new_uniform_count
,
747 src
, size
, channel_sizes
[src
],
750 /* Move the references to the data */
751 for (int j
= 0; j
< size
; j
++) {
752 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
757 /* Continue with the rest of data, which is aligned to vec4. */
758 for (int src
= 0; src
< uniforms
; src
++) {
759 int size
= chans_used
[src
];
761 if (size
== 0 || is_aligned_to_dvec4
[src
])
764 int dst
= set_push_constant_loc(uniforms
, &new_uniform_count
,
765 src
, size
, channel_sizes
[src
],
768 /* Move the references to the data */
769 for (int j
= 0; j
< size
; j
++) {
770 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
776 this->uniforms
= new_uniform_count
;
778 /* Now, update the instructions for our repacked uniforms. */
779 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
780 for (int i
= 0 ; i
< 3; i
++) {
781 int src
= inst
->src
[i
].nr
;
783 if (inst
->src
[i
].file
!= UNIFORM
)
786 int chan
= new_chan
[src
] / channel_sizes
[src
];
787 inst
->src
[i
].nr
= new_loc
[src
];
788 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(chan
, chan
, chan
, chan
);
794 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
796 * While GLSL IR also performs this optimization, we end up with it in
797 * our instruction stream for a couple of reasons. One is that we
798 * sometimes generate silly instructions, for example in array access
799 * where we'll generate "ADD offset, index, base" even if base is 0.
800 * The other is that GLSL IR's constant propagation doesn't track the
801 * components of aggregates, so some VS patterns (initialize matrix to
802 * 0, accumulate in vertex blending factors) end up breaking down to
803 * instructions involving 0.
806 vec4_visitor::opt_algebraic()
808 bool progress
= false;
810 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
811 switch (inst
->opcode
) {
813 if (inst
->src
[0].file
!= IMM
)
816 if (inst
->saturate
) {
817 /* Full mixed-type saturates don't happen. However, we can end up
820 * mov.sat(8) g21<1>DF -1F
822 * Other mixed-size-but-same-base-type cases may also be possible.
824 if (inst
->dst
.type
!= inst
->src
[0].type
&&
825 inst
->dst
.type
!= BRW_REGISTER_TYPE_DF
&&
826 inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
827 assert(!"unimplemented: saturate mixed types");
829 if (brw_saturate_immediate(inst
->src
[0].type
,
830 &inst
->src
[0].as_brw_reg())) {
831 inst
->saturate
= false;
838 if (inst
->src
[1].is_zero()) {
839 inst
->opcode
= BRW_OPCODE_MOV
;
840 inst
->src
[1] = src_reg();
845 case VEC4_OPCODE_UNPACK_UNIFORM
:
846 if (inst
->src
[0].file
!= UNIFORM
) {
847 inst
->opcode
= BRW_OPCODE_MOV
;
853 if (inst
->src
[1].is_zero()) {
854 inst
->opcode
= BRW_OPCODE_MOV
;
855 inst
->src
[1] = src_reg();
861 if (inst
->src
[1].is_zero()) {
862 inst
->opcode
= BRW_OPCODE_MOV
;
863 switch (inst
->src
[0].type
) {
864 case BRW_REGISTER_TYPE_F
:
865 inst
->src
[0] = brw_imm_f(0.0f
);
867 case BRW_REGISTER_TYPE_D
:
868 inst
->src
[0] = brw_imm_d(0);
870 case BRW_REGISTER_TYPE_UD
:
871 inst
->src
[0] = brw_imm_ud(0u);
874 unreachable("not reached");
876 inst
->src
[1] = src_reg();
878 } else if (inst
->src
[1].is_one()) {
879 inst
->opcode
= BRW_OPCODE_MOV
;
880 inst
->src
[1] = src_reg();
882 } else if (inst
->src
[1].is_negative_one()) {
883 inst
->opcode
= BRW_OPCODE_MOV
;
884 inst
->src
[0].negate
= !inst
->src
[0].negate
;
885 inst
->src
[1] = src_reg();
889 case SHADER_OPCODE_BROADCAST
:
890 if (is_uniform(inst
->src
[0]) ||
891 inst
->src
[1].is_zero()) {
892 inst
->opcode
= BRW_OPCODE_MOV
;
893 inst
->src
[1] = src_reg();
894 inst
->force_writemask_all
= true;
905 invalidate_live_intervals();
911 * Only a limited number of hardware registers may be used for push
912 * constants, so this turns access to the overflowed constants into
916 vec4_visitor::move_push_constants_to_pull_constants()
918 int pull_constant_loc
[this->uniforms
];
920 /* Only allow 32 registers (256 uniform components) as push constants,
921 * which is the limit on gen6.
923 * If changing this value, note the limitation about total_regs in
926 int max_uniform_components
= 32 * 8;
927 if (this->uniforms
* 4 <= max_uniform_components
)
930 /* Make some sort of choice as to which uniforms get sent to pull
931 * constants. We could potentially do something clever here like
932 * look for the most infrequently used uniform vec4s, but leave
935 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
936 pull_constant_loc
[i
/ 4] = -1;
938 if (i
>= max_uniform_components
) {
939 uint32_t *values
= &stage_prog_data
->param
[i
];
941 /* Try to find an existing copy of this uniform in the pull
942 * constants if it was part of an array access already.
944 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
947 for (matches
= 0; matches
< 4; matches
++) {
948 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
953 pull_constant_loc
[i
/ 4] = j
/ 4;
958 if (pull_constant_loc
[i
/ 4] == -1) {
959 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
960 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
962 for (int j
= 0; j
< 4; j
++) {
963 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
970 /* Now actually rewrite usage of the things we've moved to pull
973 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
974 for (int i
= 0 ; i
< 3; i
++) {
975 if (inst
->src
[i
].file
!= UNIFORM
||
976 pull_constant_loc
[inst
->src
[i
].nr
] == -1)
979 int uniform
= inst
->src
[i
].nr
;
981 const glsl_type
*temp_type
= type_sz(inst
->src
[i
].type
) == 8 ?
982 glsl_type::dvec4_type
: glsl_type::vec4_type
;
983 dst_reg temp
= dst_reg(this, temp_type
);
985 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
986 pull_constant_loc
[uniform
], src_reg());
988 inst
->src
[i
].file
= temp
.file
;
989 inst
->src
[i
].nr
= temp
.nr
;
990 inst
->src
[i
].offset
%= 16;
991 inst
->src
[i
].reladdr
= NULL
;
995 /* Repack push constants to remove the now-unused ones. */
996 pack_uniform_registers();
999 /* Conditions for which we want to avoid setting the dependency control bits */
1001 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
1003 #define IS_DWORD(reg) \
1004 (reg.type == BRW_REGISTER_TYPE_UD || \
1005 reg.type == BRW_REGISTER_TYPE_D)
1007 #define IS_64BIT(reg) (reg.file != BAD_FILE && type_sz(reg.type) == 8)
1009 /* From the Cherryview and Broadwell PRMs:
1011 * "When source or destination datatype is 64b or operation is integer DWord
1012 * multiply, DepCtrl must not be used."
1014 * SKL PRMs don't include this restriction, however, gen7 seems to be
1015 * affected, at least by the 64b restriction, since DepCtrl with double
1016 * precision instructions seems to produce GPU hangs in some cases.
1018 if (devinfo
->gen
== 8 || gen_device_info_is_9lp(devinfo
)) {
1019 if (inst
->opcode
== BRW_OPCODE_MUL
&&
1020 IS_DWORD(inst
->src
[0]) &&
1021 IS_DWORD(inst
->src
[1]))
1025 if (devinfo
->gen
>= 7 && devinfo
->gen
<= 8) {
1026 if (IS_64BIT(inst
->dst
) || IS_64BIT(inst
->src
[0]) ||
1027 IS_64BIT(inst
->src
[1]) || IS_64BIT(inst
->src
[2]))
1034 if (devinfo
->gen
>= 8) {
1035 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
1041 * In the presence of send messages, totally interrupt dependency
1042 * control. They're long enough that the chance of dependency
1043 * control around them just doesn't matter.
1046 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
1047 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
1048 * completes the scoreboard clear must have a non-zero execution mask. This
1049 * means, if any kind of predication can change the execution mask or channel
1050 * enable of the last instruction, the optimization must be avoided. This is
1051 * to avoid instructions being shot down the pipeline when no writes are
1055 * Dependency control does not work well over math instructions.
1056 * NB: Discovered empirically
1058 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
1062 * Sets the dependency control fields on instructions after register
1063 * allocation and before the generator is run.
1065 * When you have a sequence of instructions like:
1067 * DP4 temp.x vertex uniform[0]
1068 * DP4 temp.y vertex uniform[0]
1069 * DP4 temp.z vertex uniform[0]
1070 * DP4 temp.w vertex uniform[0]
1072 * The hardware doesn't know that it can actually run the later instructions
1073 * while the previous ones are in flight, producing stalls. However, we have
1074 * manual fields we can set in the instructions that let it do so.
1077 vec4_visitor::opt_set_dependency_control()
1079 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
1080 uint8_t grf_channels_written
[BRW_MAX_GRF
];
1081 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
1082 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
1084 assert(prog_data
->total_grf
||
1085 !"Must be called after register allocation");
1087 foreach_block (block
, cfg
) {
1088 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1089 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1091 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
1092 /* If we read from a register that we were doing dependency control
1093 * on, don't do dependency control across the read.
1095 for (int i
= 0; i
< 3; i
++) {
1096 int reg
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ REG_SIZE
;
1097 if (inst
->src
[i
].file
== VGRF
) {
1098 last_grf_write
[reg
] = NULL
;
1099 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1100 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1103 assert(inst
->src
[i
].file
!= MRF
);
1106 if (is_dep_ctrl_unsafe(inst
)) {
1107 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1108 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1112 /* Now, see if we can do dependency control for this instruction
1113 * against a previous one writing to its destination.
1115 int reg
= inst
->dst
.nr
+ inst
->dst
.offset
/ REG_SIZE
;
1116 if (inst
->dst
.file
== VGRF
|| inst
->dst
.file
== FIXED_GRF
) {
1117 if (last_grf_write
[reg
] &&
1118 last_grf_write
[reg
]->dst
.offset
== inst
->dst
.offset
&&
1119 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
1120 last_grf_write
[reg
]->no_dd_clear
= true;
1121 inst
->no_dd_check
= true;
1123 grf_channels_written
[reg
] = 0;
1126 last_grf_write
[reg
] = inst
;
1127 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
1128 } else if (inst
->dst
.file
== MRF
) {
1129 if (last_mrf_write
[reg
] &&
1130 last_mrf_write
[reg
]->dst
.offset
== inst
->dst
.offset
&&
1131 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
1132 last_mrf_write
[reg
]->no_dd_clear
= true;
1133 inst
->no_dd_check
= true;
1135 mrf_channels_written
[reg
] = 0;
1138 last_mrf_write
[reg
] = inst
;
1139 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
1146 vec4_instruction::can_reswizzle(const struct gen_device_info
*devinfo
,
1151 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
1154 if (devinfo
->gen
== 6 && is_math() && swizzle
!= BRW_SWIZZLE_XYZW
)
1157 /* If we write to the flag register changing the swizzle would change
1158 * what channels are written to the flag register.
1163 /* We can't swizzle implicit accumulator access. We'd have to
1164 * reswizzle the producer of the accumulator value in addition
1165 * to the consumer (i.e. both MUL and MACH). Just skip this.
1167 if (reads_accumulator_implicitly())
1170 if (!can_do_writemask(devinfo
) && dst_writemask
!= WRITEMASK_XYZW
)
1173 /* If this instruction sets anything not referenced by swizzle, then we'd
1174 * totally break it when we reswizzle.
1176 if (dst
.writemask
& ~swizzle_mask
)
1182 for (int i
= 0; i
< 3; i
++) {
1183 if (src
[i
].is_accumulator())
1191 * For any channels in the swizzle's source that were populated by this
1192 * instruction, rewrite the instruction to put the appropriate result directly
1193 * in those channels.
1195 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
1198 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
1200 /* Destination write mask doesn't correspond to source swizzle for the dot
1201 * product and pack_bytes instructions.
1203 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
1204 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
1205 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
1206 for (int i
= 0; i
< 3; i
++) {
1207 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
1210 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
1214 /* Apply the specified swizzle and writemask to the original mask of
1215 * written components.
1217 dst
.writemask
= dst_writemask
&
1218 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1222 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1223 * just written and then MOVed into another reg and making the original write
1224 * of the GRF write directly to the final destination instead.
1227 vec4_visitor::opt_register_coalesce()
1229 bool progress
= false;
1232 calculate_live_intervals();
1234 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1238 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1239 (inst
->dst
.file
!= VGRF
&& inst
->dst
.file
!= MRF
) ||
1241 inst
->src
[0].file
!= VGRF
||
1242 inst
->dst
.type
!= inst
->src
[0].type
||
1243 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1246 /* Remove no-op MOVs */
1247 if (inst
->dst
.file
== inst
->src
[0].file
&&
1248 inst
->dst
.nr
== inst
->src
[0].nr
&&
1249 inst
->dst
.offset
== inst
->src
[0].offset
) {
1250 bool is_nop_mov
= true;
1252 for (unsigned c
= 0; c
< 4; c
++) {
1253 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1256 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1263 inst
->remove(block
);
1269 bool to_mrf
= (inst
->dst
.file
== MRF
);
1271 /* Can't coalesce this GRF if someone else was going to
1274 if (var_range_end(var_from_reg(alloc
, dst_reg(inst
->src
[0])), 8) > ip
)
1277 /* We need to check interference with the final destination between this
1278 * instruction and the earliest instruction involved in writing the GRF
1279 * we're eliminating. To do that, keep track of which of our source
1280 * channels we've seen initialized.
1282 const unsigned chans_needed
=
1283 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1284 inst
->dst
.writemask
);
1285 unsigned chans_remaining
= chans_needed
;
1287 /* Now walk up the instruction stream trying to see if we can rewrite
1288 * everything writing to the temporary to write into the destination
1291 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1292 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1294 _scan_inst
= scan_inst
;
1296 if (regions_overlap(inst
->src
[0], inst
->size_read(0),
1297 scan_inst
->dst
, scan_inst
->size_written
)) {
1298 /* Found something writing to the reg we want to coalesce away. */
1300 /* SEND instructions can't have MRF as a destination. */
1301 if (scan_inst
->mlen
)
1304 if (devinfo
->gen
== 6) {
1305 /* gen6 math instructions must have the destination be
1306 * VGRF, so no compute-to-MRF for them.
1308 if (scan_inst
->is_math()) {
1314 /* VS_OPCODE_UNPACK_FLAGS_SIMD4X2 generates a bunch of mov(1)
1315 * instructions, and this optimization pass is not capable of
1316 * handling that. Bail on these instructions and hope that some
1317 * later optimization pass can do the right thing after they are
1320 if (scan_inst
->opcode
== VS_OPCODE_UNPACK_FLAGS_SIMD4X2
)
1323 /* This doesn't handle saturation on the instruction we
1324 * want to coalesce away if the register types do not match.
1325 * But if scan_inst is a non type-converting 'mov', we can fix
1328 if (inst
->saturate
&&
1329 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1330 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1331 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1334 /* Only allow coalescing between registers of the same type size.
1335 * Otherwise we would need to make the pass aware of the fact that
1336 * channel sizes are different for single and double precision.
1338 if (type_sz(inst
->src
[0].type
) != type_sz(scan_inst
->src
[0].type
))
1341 /* Check that scan_inst writes the same amount of data as the
1342 * instruction, otherwise coalescing would lead to writing a
1343 * different (larger or smaller) region of the destination
1345 if (scan_inst
->size_written
!= inst
->size_written
)
1348 /* If we can't handle the swizzle, bail. */
1349 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1350 inst
->src
[0].swizzle
,
1355 /* This only handles coalescing writes of 8 channels (1 register
1356 * for single-precision and 2 registers for double-precision)
1357 * starting at the source offset of the copy instruction.
1359 if (DIV_ROUND_UP(scan_inst
->size_written
,
1360 type_sz(scan_inst
->dst
.type
)) > 8 ||
1361 scan_inst
->dst
.offset
!= inst
->src
[0].offset
)
1364 /* Mark which channels we found unconditional writes for. */
1365 if (!scan_inst
->predicate
)
1366 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1368 if (chans_remaining
== 0)
1372 /* You can't read from an MRF, so if someone else reads our MRF's
1373 * source GRF that we wanted to rewrite, that stops us. If it's a
1374 * GRF we're trying to coalesce to, we don't actually handle
1375 * rewriting sources so bail in that case as well.
1377 bool interfered
= false;
1378 for (int i
= 0; i
< 3; i
++) {
1379 if (regions_overlap(inst
->src
[0], inst
->size_read(0),
1380 scan_inst
->src
[i
], scan_inst
->size_read(i
)))
1386 /* If somebody else writes the same channels of our destination here,
1387 * we can't coalesce before that.
1389 if (regions_overlap(inst
->dst
, inst
->size_written
,
1390 scan_inst
->dst
, scan_inst
->size_written
) &&
1391 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1395 /* Check for reads of the register we're trying to coalesce into. We
1396 * can't go rewriting instructions above that to put some other value
1397 * in the register instead.
1399 if (to_mrf
&& scan_inst
->mlen
> 0) {
1400 unsigned start
= scan_inst
->base_mrf
;
1401 unsigned end
= scan_inst
->base_mrf
+ scan_inst
->mlen
;
1403 if (inst
->dst
.nr
>= start
&& inst
->dst
.nr
< end
) {
1407 for (int i
= 0; i
< 3; i
++) {
1408 if (regions_overlap(inst
->dst
, inst
->size_written
,
1409 scan_inst
->src
[i
], scan_inst
->size_read(i
)))
1417 if (chans_remaining
== 0) {
1418 /* If we've made it here, we have an MOV we want to coalesce out, and
1419 * a scan_inst pointing to the earliest instruction involved in
1420 * computing the value. Now go rewrite the instruction stream
1423 vec4_instruction
*scan_inst
= _scan_inst
;
1424 while (scan_inst
!= inst
) {
1425 if (scan_inst
->dst
.file
== VGRF
&&
1426 scan_inst
->dst
.nr
== inst
->src
[0].nr
&&
1427 scan_inst
->dst
.offset
== inst
->src
[0].offset
) {
1428 scan_inst
->reswizzle(inst
->dst
.writemask
,
1429 inst
->src
[0].swizzle
);
1430 scan_inst
->dst
.file
= inst
->dst
.file
;
1431 scan_inst
->dst
.nr
= inst
->dst
.nr
;
1432 scan_inst
->dst
.offset
= inst
->dst
.offset
;
1433 if (inst
->saturate
&&
1434 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1435 /* If we have reached this point, scan_inst is a non
1436 * type-converting 'mov' and we can modify its register types
1437 * to match the ones in inst. Otherwise, we could have an
1438 * incorrect saturation result.
1440 scan_inst
->dst
.type
= inst
->dst
.type
;
1441 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1443 scan_inst
->saturate
|= inst
->saturate
;
1445 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1447 inst
->remove(block
);
1453 invalidate_live_intervals();
1459 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1460 * flow. We could probably do better here with some form of divergence
1464 vec4_visitor::eliminate_find_live_channel()
1466 bool progress
= false;
1469 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
1470 /* The optimization below assumes that channel zero is live on thread
1471 * dispatch, which may not be the case if the fixed function dispatches
1477 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1478 switch (inst
->opcode
) {
1484 case BRW_OPCODE_ENDIF
:
1485 case BRW_OPCODE_WHILE
:
1489 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1491 inst
->opcode
= BRW_OPCODE_MOV
;
1492 inst
->src
[0] = brw_imm_d(0);
1493 inst
->force_writemask_all
= true;
1507 * Splits virtual GRFs requesting more than one contiguous physical register.
1509 * We initially create large virtual GRFs for temporary structures, arrays,
1510 * and matrices, so that the visitor functions can add offsets to work their
1511 * way down to the actual member being accessed. But when it comes to
1512 * optimization, we'd like to treat each register as individual storage if
1515 * So far, the only thing that might prevent splitting is a send message from
1519 vec4_visitor::split_virtual_grfs()
1521 int num_vars
= this->alloc
.count
;
1522 int new_virtual_grf
[num_vars
];
1523 bool split_grf
[num_vars
];
1525 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1527 /* Try to split anything > 0 sized. */
1528 for (int i
= 0; i
< num_vars
; i
++) {
1529 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1532 /* Check that the instructions are compatible with the registers we're trying
1535 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1536 if (inst
->dst
.file
== VGRF
&& regs_written(inst
) > 1)
1537 split_grf
[inst
->dst
.nr
] = false;
1539 for (int i
= 0; i
< 3; i
++) {
1540 if (inst
->src
[i
].file
== VGRF
&& regs_read(inst
, i
) > 1)
1541 split_grf
[inst
->src
[i
].nr
] = false;
1545 /* Allocate new space for split regs. Note that the virtual
1546 * numbers will be contiguous.
1548 for (int i
= 0; i
< num_vars
; i
++) {
1552 new_virtual_grf
[i
] = alloc
.allocate(1);
1553 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1554 unsigned reg
= alloc
.allocate(1);
1555 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1558 this->alloc
.sizes
[i
] = 1;
1561 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1562 if (inst
->dst
.file
== VGRF
&& split_grf
[inst
->dst
.nr
] &&
1563 inst
->dst
.offset
/ REG_SIZE
!= 0) {
1564 inst
->dst
.nr
= (new_virtual_grf
[inst
->dst
.nr
] +
1565 inst
->dst
.offset
/ REG_SIZE
- 1);
1566 inst
->dst
.offset
%= REG_SIZE
;
1568 for (int i
= 0; i
< 3; i
++) {
1569 if (inst
->src
[i
].file
== VGRF
&& split_grf
[inst
->src
[i
].nr
] &&
1570 inst
->src
[i
].offset
/ REG_SIZE
!= 0) {
1571 inst
->src
[i
].nr
= (new_virtual_grf
[inst
->src
[i
].nr
] +
1572 inst
->src
[i
].offset
/ REG_SIZE
- 1);
1573 inst
->src
[i
].offset
%= REG_SIZE
;
1577 invalidate_live_intervals();
1581 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1583 dump_instruction(be_inst
, stderr
);
1587 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1589 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1591 if (inst
->predicate
) {
1592 fprintf(file
, "(%cf%d.%d%s) ",
1593 inst
->predicate_inverse
? '-' : '+',
1594 inst
->flag_subreg
/ 2,
1595 inst
->flag_subreg
% 2,
1596 pred_ctrl_align16
[inst
->predicate
]);
1599 fprintf(file
, "%s(%d)", brw_instruction_name(devinfo
, inst
->opcode
),
1602 fprintf(file
, ".sat");
1603 if (inst
->conditional_mod
) {
1604 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1605 if (!inst
->predicate
&&
1606 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1607 inst
->opcode
!= BRW_OPCODE_CSEL
&&
1608 inst
->opcode
!= BRW_OPCODE_IF
&&
1609 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1610 fprintf(file
, ".f%d.%d", inst
->flag_subreg
/ 2, inst
->flag_subreg
% 2);
1615 switch (inst
->dst
.file
) {
1617 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
1620 fprintf(file
, "g%d", inst
->dst
.nr
);
1623 fprintf(file
, "m%d", inst
->dst
.nr
);
1626 switch (inst
->dst
.nr
) {
1628 fprintf(file
, "null");
1630 case BRW_ARF_ADDRESS
:
1631 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
1633 case BRW_ARF_ACCUMULATOR
:
1634 fprintf(file
, "acc%d", inst
->dst
.subnr
);
1637 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1640 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1645 fprintf(file
, "(null)");
1650 unreachable("not reached");
1652 if (inst
->dst
.offset
||
1653 (inst
->dst
.file
== VGRF
&&
1654 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
1655 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 16 : REG_SIZE
);
1656 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
1657 inst
->dst
.offset
% reg_size
);
1659 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1661 if (inst
->dst
.writemask
& 1)
1663 if (inst
->dst
.writemask
& 2)
1665 if (inst
->dst
.writemask
& 4)
1667 if (inst
->dst
.writemask
& 8)
1670 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->dst
.type
));
1672 if (inst
->src
[0].file
!= BAD_FILE
)
1673 fprintf(file
, ", ");
1675 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1676 if (inst
->src
[i
].negate
)
1678 if (inst
->src
[i
].abs
)
1680 switch (inst
->src
[i
].file
) {
1682 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
1685 fprintf(file
, "g%d.%d", inst
->src
[i
].nr
, inst
->src
[i
].subnr
);
1688 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
1691 fprintf(file
, "u%d", inst
->src
[i
].nr
);
1694 switch (inst
->src
[i
].type
) {
1695 case BRW_REGISTER_TYPE_F
:
1696 fprintf(file
, "%fF", inst
->src
[i
].f
);
1698 case BRW_REGISTER_TYPE_DF
:
1699 fprintf(file
, "%fDF", inst
->src
[i
].df
);
1701 case BRW_REGISTER_TYPE_D
:
1702 fprintf(file
, "%dD", inst
->src
[i
].d
);
1704 case BRW_REGISTER_TYPE_UD
:
1705 fprintf(file
, "%uU", inst
->src
[i
].ud
);
1707 case BRW_REGISTER_TYPE_VF
:
1708 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1709 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
1710 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
1711 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
1712 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
1715 fprintf(file
, "???");
1720 switch (inst
->src
[i
].nr
) {
1722 fprintf(file
, "null");
1724 case BRW_ARF_ADDRESS
:
1725 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
1727 case BRW_ARF_ACCUMULATOR
:
1728 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
1731 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1734 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1739 fprintf(file
, "(null)");
1742 unreachable("not reached");
1745 if (inst
->src
[i
].offset
||
1746 (inst
->src
[i
].file
== VGRF
&&
1747 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
1748 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 16 : REG_SIZE
);
1749 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
1750 inst
->src
[i
].offset
% reg_size
);
1753 if (inst
->src
[i
].file
!= IMM
) {
1754 static const char *chans
[4] = {"x", "y", "z", "w"};
1756 for (int c
= 0; c
< 4; c
++) {
1757 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1761 if (inst
->src
[i
].abs
)
1764 if (inst
->src
[i
].file
!= IMM
) {
1765 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
1768 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1769 fprintf(file
, ", ");
1772 if (inst
->force_writemask_all
)
1773 fprintf(file
, " NoMask");
1775 if (inst
->exec_size
!= 8)
1776 fprintf(file
, " group%d", inst
->group
);
1778 fprintf(file
, "\n");
1783 vec4_vs_visitor::setup_attributes(int payload_reg
)
1785 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1786 for (int i
= 0; i
< 3; i
++) {
1787 if (inst
->src
[i
].file
== ATTR
) {
1788 assert(inst
->src
[i
].offset
% REG_SIZE
== 0);
1789 int grf
= payload_reg
+ inst
->src
[i
].nr
+
1790 inst
->src
[i
].offset
/ REG_SIZE
;
1792 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1793 reg
.swizzle
= inst
->src
[i
].swizzle
;
1794 reg
.type
= inst
->src
[i
].type
;
1795 reg
.abs
= inst
->src
[i
].abs
;
1796 reg
.negate
= inst
->src
[i
].negate
;
1802 return payload_reg
+ vs_prog_data
->nr_attribute_slots
;
1806 vec4_visitor::setup_uniforms(int reg
)
1808 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1810 /* The pre-gen6 VS requires that some push constants get loaded no
1811 * matter what, or the GPU would hang.
1813 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1814 brw_stage_prog_data_add_params(stage_prog_data
, 4);
1815 for (unsigned int i
= 0; i
< 4; i
++) {
1816 unsigned int slot
= this->uniforms
* 4 + i
;
1817 stage_prog_data
->param
[slot
] = BRW_PARAM_BUILTIN_ZERO
;
1823 reg
+= ALIGN(uniforms
, 2) / 2;
1826 for (int i
= 0; i
< 4; i
++)
1827 reg
+= stage_prog_data
->ubo_ranges
[i
].length
;
1829 stage_prog_data
->nr_params
= this->uniforms
* 4;
1831 prog_data
->base
.curb_read_length
=
1832 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1838 vec4_vs_visitor::setup_payload(void)
1842 /* The payload always contains important data in g0, which contains
1843 * the URB handles that are passed on to the URB write at the end
1844 * of the thread. So, we always start push constants at g1.
1848 reg
= setup_uniforms(reg
);
1850 reg
= setup_attributes(reg
);
1852 this->first_non_payload_grf
= reg
;
1856 vec4_visitor::lower_minmax()
1858 assert(devinfo
->gen
< 6);
1860 bool progress
= false;
1862 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1863 const vec4_builder
ibld(this, block
, inst
);
1865 if (inst
->opcode
== BRW_OPCODE_SEL
&&
1866 inst
->predicate
== BRW_PREDICATE_NONE
) {
1867 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
1868 * the original SEL.L/GE instruction
1870 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
1871 inst
->conditional_mod
);
1872 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1873 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
1880 invalidate_live_intervals();
1886 vec4_visitor::get_timestamp()
1888 assert(devinfo
->gen
>= 7);
1890 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1895 BRW_REGISTER_TYPE_UD
,
1896 BRW_VERTICAL_STRIDE_0
,
1898 BRW_HORIZONTAL_STRIDE_4
,
1902 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1904 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1905 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1906 * even if it's not enabled in the dispatch.
1908 mov
->force_writemask_all
= true;
1910 return src_reg(dst
);
1914 vec4_visitor::emit_shader_time_begin()
1916 current_annotation
= "shader time start";
1917 shader_start_time
= get_timestamp();
1921 vec4_visitor::emit_shader_time_end()
1923 current_annotation
= "shader time end";
1924 src_reg shader_end_time
= get_timestamp();
1927 /* Check that there weren't any timestamp reset events (assuming these
1928 * were the only two timestamp reads that happened).
1930 src_reg reset_end
= shader_end_time
;
1931 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1932 vec4_instruction
*test
= emit(AND(dst_null_ud(), reset_end
, brw_imm_ud(1u)));
1933 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1935 emit(IF(BRW_PREDICATE_NORMAL
));
1937 /* Take the current timestamp and get the delta. */
1938 shader_start_time
.negate
= true;
1939 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1940 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1942 /* If there were no instructions between the two timestamp gets, the diff
1943 * is 2 cycles. Remove that overhead, so I can forget about that when
1944 * trying to determine the time taken for single instructions.
1946 emit(ADD(diff
, src_reg(diff
), brw_imm_ud(-2u)));
1948 emit_shader_time_write(0, src_reg(diff
));
1949 emit_shader_time_write(1, brw_imm_ud(1u));
1950 emit(BRW_OPCODE_ELSE
);
1951 emit_shader_time_write(2, brw_imm_ud(1u));
1952 emit(BRW_OPCODE_ENDIF
);
1956 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1959 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1961 dst_reg offset
= dst
;
1963 time
.offset
+= REG_SIZE
;
1965 offset
.type
= BRW_REGISTER_TYPE_UD
;
1966 int index
= shader_time_index
* 3 + shader_time_subindex
;
1967 emit(MOV(offset
, brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
)));
1969 time
.type
= BRW_REGISTER_TYPE_UD
;
1970 emit(MOV(time
, value
));
1972 vec4_instruction
*inst
=
1973 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1978 is_align1_df(vec4_instruction
*inst
)
1980 switch (inst
->opcode
) {
1981 case VEC4_OPCODE_DOUBLE_TO_F32
:
1982 case VEC4_OPCODE_DOUBLE_TO_D32
:
1983 case VEC4_OPCODE_DOUBLE_TO_U32
:
1984 case VEC4_OPCODE_TO_DOUBLE
:
1985 case VEC4_OPCODE_PICK_LOW_32BIT
:
1986 case VEC4_OPCODE_PICK_HIGH_32BIT
:
1987 case VEC4_OPCODE_SET_LOW_32BIT
:
1988 case VEC4_OPCODE_SET_HIGH_32BIT
:
1996 * Three source instruction must have a GRF/MRF destination register.
1997 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
2000 vec4_visitor::fixup_3src_null_dest()
2002 bool progress
= false;
2004 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
2005 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
2006 const unsigned size_written
= type_sz(inst
->dst
.type
);
2007 const unsigned num_regs
= DIV_ROUND_UP(size_written
, REG_SIZE
);
2009 inst
->dst
= retype(dst_reg(VGRF
, alloc
.allocate(num_regs
)),
2016 invalidate_live_intervals();
2020 vec4_visitor::convert_to_hw_regs()
2022 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
2023 for (int i
= 0; i
< 3; i
++) {
2024 class src_reg
&src
= inst
->src
[i
];
2028 reg
= byte_offset(brw_vecn_grf(4, src
.nr
, 0), src
.offset
);
2029 reg
.type
= src
.type
;
2031 reg
.negate
= src
.negate
;
2036 reg
= stride(byte_offset(brw_vec4_grf(
2037 prog_data
->base
.dispatch_grf_start_reg
+
2038 src
.nr
/ 2, src
.nr
% 2 * 4),
2041 reg
.type
= src
.type
;
2043 reg
.negate
= src
.negate
;
2045 /* This should have been moved to pull constants. */
2046 assert(!src
.reladdr
);
2051 if (type_sz(src
.type
) == 8) {
2052 reg
= src
.as_brw_reg();
2061 /* Probably unused. */
2062 reg
= brw_null_reg();
2063 reg
= retype(reg
, src
.type
);
2068 unreachable("not reached");
2071 apply_logical_swizzle(®
, inst
, i
);
2074 /* From IVB PRM, vol4, part3, "General Restrictions on Regioning
2077 * "If ExecSize = Width and HorzStride ≠ 0, VertStride must be set
2078 * to Width * HorzStride."
2080 * We can break this rule with DF sources on DF align1
2081 * instructions, because the exec_size would be 4 and width is 4.
2082 * As we know we are not accessing to next GRF, it is safe to
2083 * set vstride to the formula given by the rule itself.
2085 if (is_align1_df(inst
) && (cvt(inst
->exec_size
) - 1) == src
.width
)
2086 src
.vstride
= src
.width
+ src
.hstride
;
2089 if (inst
->is_3src(devinfo
)) {
2090 /* 3-src instructions with scalar sources support arbitrary subnr,
2091 * but don't actually use swizzles. Convert swizzle into subnr.
2092 * Skip this for double-precision instructions: RepCtrl=1 is not
2093 * allowed for them and needs special handling.
2095 for (int i
= 0; i
< 3; i
++) {
2096 if (inst
->src
[i
].vstride
== BRW_VERTICAL_STRIDE_0
&&
2097 type_sz(inst
->src
[i
].type
) < 8) {
2098 assert(brw_is_single_value_swizzle(inst
->src
[i
].swizzle
));
2099 inst
->src
[i
].subnr
+= 4 * BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0);
2104 dst_reg
&dst
= inst
->dst
;
2107 switch (inst
->dst
.file
) {
2109 reg
= byte_offset(brw_vec8_grf(dst
.nr
, 0), dst
.offset
);
2110 reg
.type
= dst
.type
;
2111 reg
.writemask
= dst
.writemask
;
2115 reg
= byte_offset(brw_message_reg(dst
.nr
), dst
.offset
);
2116 assert((reg
.nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
2117 reg
.type
= dst
.type
;
2118 reg
.writemask
= dst
.writemask
;
2123 reg
= dst
.as_brw_reg();
2127 reg
= brw_null_reg();
2128 reg
= retype(reg
, dst
.type
);
2134 unreachable("not reached");
2142 stage_uses_interleaved_attributes(unsigned stage
,
2143 enum shader_dispatch_mode dispatch_mode
)
2146 case MESA_SHADER_TESS_EVAL
:
2148 case MESA_SHADER_GEOMETRY
:
2149 return dispatch_mode
!= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2156 * Get the closest native SIMD width supported by the hardware for instruction
2157 * \p inst. The instruction will be left untouched by
2158 * vec4_visitor::lower_simd_width() if the returned value matches the
2159 * instruction's original execution size.
2162 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
2163 enum shader_dispatch_mode dispatch_mode
,
2164 unsigned stage
, const vec4_instruction
*inst
)
2166 /* Do not split some instructions that require special handling */
2167 switch (inst
->opcode
) {
2168 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2169 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2170 return inst
->exec_size
;
2175 unsigned lowered_width
= MIN2(16, inst
->exec_size
);
2177 /* We need to split some cases of double-precision instructions that write
2178 * 2 registers. We only need to care about this in gen7 because that is the
2179 * only hardware that implements fp64 in Align16.
2181 if (devinfo
->gen
== 7 && inst
->size_written
> REG_SIZE
) {
2182 /* Align16 8-wide double-precision SEL does not work well. Verified
2185 if (inst
->opcode
== BRW_OPCODE_SEL
&& type_sz(inst
->dst
.type
) == 8)
2186 lowered_width
= MIN2(lowered_width
, 4);
2188 /* HSW PRM, 3D Media GPGPU Engine, Region Alignment Rules for Direct
2189 * Register Addressing:
2191 * "When destination spans two registers, the source MUST span two
2194 for (unsigned i
= 0; i
< 3; i
++) {
2195 if (inst
->src
[i
].file
== BAD_FILE
)
2197 if (inst
->size_read(i
) <= REG_SIZE
)
2198 lowered_width
= MIN2(lowered_width
, 4);
2200 /* Interleaved attribute setups use a vertical stride of 0, which
2201 * makes them hit the associated instruction decompression bug in gen7.
2202 * Split them to prevent this.
2204 if (inst
->src
[i
].file
== ATTR
&&
2205 stage_uses_interleaved_attributes(stage
, dispatch_mode
))
2206 lowered_width
= MIN2(lowered_width
, 4);
2210 /* IvyBridge can manage a maximum of 4 DFs per SIMD4x2 instruction, since
2211 * it doesn't support compression in Align16 mode, no matter if it has
2212 * force_writemask_all enabled or disabled (the latter is affected by the
2213 * compressed instruction bug in gen7, which is another reason to enforce
2216 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
2217 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8))
2218 lowered_width
= MIN2(lowered_width
, 4);
2220 return lowered_width
;
2224 dst_src_regions_overlap(vec4_instruction
*inst
)
2226 if (inst
->size_written
== 0)
2229 unsigned dst_start
= inst
->dst
.offset
;
2230 unsigned dst_end
= dst_start
+ inst
->size_written
- 1;
2231 for (int i
= 0; i
< 3; i
++) {
2232 if (inst
->src
[i
].file
== BAD_FILE
)
2235 if (inst
->dst
.file
!= inst
->src
[i
].file
||
2236 inst
->dst
.nr
!= inst
->src
[i
].nr
)
2239 unsigned src_start
= inst
->src
[i
].offset
;
2240 unsigned src_end
= src_start
+ inst
->size_read(i
) - 1;
2242 if ((dst_start
>= src_start
&& dst_start
<= src_end
) ||
2243 (dst_end
>= src_start
&& dst_end
<= src_end
) ||
2244 (dst_start
<= src_start
&& dst_end
>= src_end
)) {
2253 vec4_visitor::lower_simd_width()
2255 bool progress
= false;
2257 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
2258 const unsigned lowered_width
=
2259 get_lowered_simd_width(devinfo
, prog_data
->dispatch_mode
, stage
, inst
);
2260 assert(lowered_width
<= inst
->exec_size
);
2261 if (lowered_width
== inst
->exec_size
)
2264 /* We need to deal with source / destination overlaps when splitting.
2265 * The hardware supports reading from and writing to the same register
2266 * in the same instruction, but we need to be careful that each split
2267 * instruction we produce does not corrupt the source of the next.
2269 * The easiest way to handle this is to make the split instructions write
2270 * to temporaries if there is an src/dst overlap and then move from the
2271 * temporaries to the original destination. We also need to consider
2272 * instructions that do partial writes via align1 opcodes, in which case
2273 * we need to make sure that the we initialize the temporary with the
2274 * value of the instruction's dst.
2276 bool needs_temp
= dst_src_regions_overlap(inst
);
2277 for (unsigned n
= 0; n
< inst
->exec_size
/ lowered_width
; n
++) {
2278 unsigned channel_offset
= lowered_width
* n
;
2280 unsigned size_written
= lowered_width
* type_sz(inst
->dst
.type
);
2282 /* Create the split instruction from the original so that we copy all
2283 * relevant instruction fields, then set the width and calculate the
2284 * new dst/src regions.
2286 vec4_instruction
*linst
= new(mem_ctx
) vec4_instruction(*inst
);
2287 linst
->exec_size
= lowered_width
;
2288 linst
->group
= channel_offset
;
2289 linst
->size_written
= size_written
;
2291 /* Compute split dst region */
2294 unsigned num_regs
= DIV_ROUND_UP(size_written
, REG_SIZE
);
2295 dst
= retype(dst_reg(VGRF
, alloc
.allocate(num_regs
)),
2297 if (inst
->is_align1_partial_write()) {
2298 vec4_instruction
*copy
= MOV(dst
, src_reg(inst
->dst
));
2299 copy
->exec_size
= lowered_width
;
2300 copy
->group
= channel_offset
;
2301 copy
->size_written
= size_written
;
2302 inst
->insert_before(block
, copy
);
2305 dst
= horiz_offset(inst
->dst
, channel_offset
);
2309 /* Compute split source regions */
2310 for (int i
= 0; i
< 3; i
++) {
2311 if (linst
->src
[i
].file
== BAD_FILE
)
2314 bool is_interleaved_attr
=
2315 linst
->src
[i
].file
== ATTR
&&
2316 stage_uses_interleaved_attributes(stage
,
2317 prog_data
->dispatch_mode
);
2319 if (!is_uniform(linst
->src
[i
]) && !is_interleaved_attr
)
2320 linst
->src
[i
] = horiz_offset(linst
->src
[i
], channel_offset
);
2323 inst
->insert_before(block
, linst
);
2325 /* If we used a temporary to store the result of the split
2326 * instruction, copy the result to the original destination
2329 vec4_instruction
*mov
=
2330 MOV(offset(inst
->dst
, lowered_width
, n
), src_reg(dst
));
2331 mov
->exec_size
= lowered_width
;
2332 mov
->group
= channel_offset
;
2333 mov
->size_written
= size_written
;
2334 mov
->predicate
= inst
->predicate
;
2335 inst
->insert_before(block
, mov
);
2339 inst
->remove(block
);
2344 invalidate_live_intervals();
2349 static brw_predicate
2350 scalarize_predicate(brw_predicate predicate
, unsigned writemask
)
2352 if (predicate
!= BRW_PREDICATE_NORMAL
)
2355 switch (writemask
) {
2357 return BRW_PREDICATE_ALIGN16_REPLICATE_X
;
2359 return BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
2361 return BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
2363 return BRW_PREDICATE_ALIGN16_REPLICATE_W
;
2365 unreachable("invalid writemask");
2369 /* Gen7 has a hardware decompression bug that we can exploit to represent
2370 * handful of additional swizzles natively.
2373 is_gen7_supported_64bit_swizzle(vec4_instruction
*inst
, unsigned arg
)
2375 switch (inst
->src
[arg
].swizzle
) {
2376 case BRW_SWIZZLE_XXXX
:
2377 case BRW_SWIZZLE_YYYY
:
2378 case BRW_SWIZZLE_ZZZZ
:
2379 case BRW_SWIZZLE_WWWW
:
2380 case BRW_SWIZZLE_XYXY
:
2381 case BRW_SWIZZLE_YXYX
:
2382 case BRW_SWIZZLE_ZWZW
:
2383 case BRW_SWIZZLE_WZWZ
:
2390 /* 64-bit sources use regions with a width of 2. These 2 elements in each row
2391 * can be addressed using 32-bit swizzles (which is what the hardware supports)
2392 * but it also means that the swizzle we apply on the first two components of a
2393 * dvec4 is coupled with the swizzle we use for the last 2. In other words,
2394 * only some specific swizzle combinations can be natively supported.
2396 * FIXME: we can go an step further and implement even more swizzle
2397 * variations using only partial scalarization.
2399 * For more details see:
2400 * https://bugs.freedesktop.org/show_bug.cgi?id=92760#c82
2403 vec4_visitor::is_supported_64bit_region(vec4_instruction
*inst
, unsigned arg
)
2405 const src_reg
&src
= inst
->src
[arg
];
2406 assert(type_sz(src
.type
) == 8);
2408 /* Uniform regions have a vstride=0. Because we use 2-wide rows with
2409 * 64-bit regions it means that we cannot access components Z/W, so
2410 * return false for any such case. Interleaved attributes will also be
2411 * mapped to GRF registers with a vstride of 0, so apply the same
2414 if ((is_uniform(src
) ||
2415 (stage_uses_interleaved_attributes(stage
, prog_data
->dispatch_mode
) &&
2416 src
.file
== ATTR
)) &&
2417 (brw_mask_for_swizzle(src
.swizzle
) & 12))
2420 switch (src
.swizzle
) {
2421 case BRW_SWIZZLE_XYZW
:
2422 case BRW_SWIZZLE_XXZZ
:
2423 case BRW_SWIZZLE_YYWW
:
2424 case BRW_SWIZZLE_YXWZ
:
2427 return devinfo
->gen
== 7 && is_gen7_supported_64bit_swizzle(inst
, arg
);
2432 vec4_visitor::scalarize_df()
2434 bool progress
= false;
2436 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
2437 /* Skip DF instructions that operate in Align1 mode */
2438 if (is_align1_df(inst
))
2441 /* Check if this is a double-precision instruction */
2442 bool is_double
= type_sz(inst
->dst
.type
) == 8;
2443 for (int arg
= 0; !is_double
&& arg
< 3; arg
++) {
2444 is_double
= inst
->src
[arg
].file
!= BAD_FILE
&&
2445 type_sz(inst
->src
[arg
].type
) == 8;
2451 /* Skip the lowering for specific regioning scenarios that we can
2454 bool skip_lowering
= true;
2456 /* XY and ZW writemasks operate in 32-bit, which means that they don't
2457 * have a native 64-bit representation and they should always be split.
2459 if (inst
->dst
.writemask
== WRITEMASK_XY
||
2460 inst
->dst
.writemask
== WRITEMASK_ZW
) {
2461 skip_lowering
= false;
2463 for (unsigned i
= 0; i
< 3; i
++) {
2464 if (inst
->src
[i
].file
== BAD_FILE
|| type_sz(inst
->src
[i
].type
) < 8)
2466 skip_lowering
= skip_lowering
&& is_supported_64bit_region(inst
, i
);
2473 /* Generate scalar instructions for each enabled channel */
2474 for (unsigned chan
= 0; chan
< 4; chan
++) {
2475 unsigned chan_mask
= 1 << chan
;
2476 if (!(inst
->dst
.writemask
& chan_mask
))
2479 vec4_instruction
*scalar_inst
= new(mem_ctx
) vec4_instruction(*inst
);
2481 for (unsigned i
= 0; i
< 3; i
++) {
2482 unsigned swz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, chan
);
2483 scalar_inst
->src
[i
].swizzle
= BRW_SWIZZLE4(swz
, swz
, swz
, swz
);
2486 scalar_inst
->dst
.writemask
= chan_mask
;
2488 if (inst
->predicate
!= BRW_PREDICATE_NONE
) {
2489 scalar_inst
->predicate
=
2490 scalarize_predicate(inst
->predicate
, chan_mask
);
2493 inst
->insert_before(block
, scalar_inst
);
2496 inst
->remove(block
);
2501 invalidate_live_intervals();
2507 vec4_visitor::lower_64bit_mad_to_mul_add()
2509 bool progress
= false;
2511 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
2512 if (inst
->opcode
!= BRW_OPCODE_MAD
)
2515 if (type_sz(inst
->dst
.type
) != 8)
2518 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
2520 /* Use the copy constructor so we copy all relevant instruction fields
2521 * from the original mad into the add and mul instructions
2523 vec4_instruction
*mul
= new(mem_ctx
) vec4_instruction(*inst
);
2524 mul
->opcode
= BRW_OPCODE_MUL
;
2526 mul
->src
[0] = inst
->src
[1];
2527 mul
->src
[1] = inst
->src
[2];
2528 mul
->src
[2].file
= BAD_FILE
;
2530 vec4_instruction
*add
= new(mem_ctx
) vec4_instruction(*inst
);
2531 add
->opcode
= BRW_OPCODE_ADD
;
2532 add
->src
[0] = src_reg(mul_dst
);
2533 add
->src
[1] = inst
->src
[0];
2534 add
->src
[2].file
= BAD_FILE
;
2536 inst
->insert_before(block
, mul
);
2537 inst
->insert_before(block
, add
);
2538 inst
->remove(block
);
2544 invalidate_live_intervals();
2549 /* The align16 hardware can only do 32-bit swizzle channels, so we need to
2550 * translate the logical 64-bit swizzle channels that we use in the Vec4 IR
2551 * to 32-bit swizzle channels in hardware registers.
2553 * @inst and @arg identify the original vec4 IR source operand we need to
2554 * translate the swizzle for and @hw_reg is the hardware register where we
2555 * will write the hardware swizzle to use.
2557 * This pass assumes that Align16/DF instructions have been fully scalarized
2558 * previously so there is just one 64-bit swizzle channel to deal with for any
2559 * given Vec4 IR source.
2562 vec4_visitor::apply_logical_swizzle(struct brw_reg
*hw_reg
,
2563 vec4_instruction
*inst
, int arg
)
2565 src_reg reg
= inst
->src
[arg
];
2567 if (reg
.file
== BAD_FILE
|| reg
.file
== BRW_IMMEDIATE_VALUE
)
2570 /* If this is not a 64-bit operand or this is a scalar instruction we don't
2571 * need to do anything about the swizzles.
2573 if(type_sz(reg
.type
) < 8 || is_align1_df(inst
)) {
2574 hw_reg
->swizzle
= reg
.swizzle
;
2578 /* Take the 64-bit logical swizzle channel and translate it to 32-bit */
2579 assert(brw_is_single_value_swizzle(reg
.swizzle
) ||
2580 is_supported_64bit_region(inst
, arg
));
2582 /* Apply the region <2, 2, 1> for GRF or <0, 2, 1> for uniforms, as align16
2583 * HW can only do 32-bit swizzle channels.
2585 hw_reg
->width
= BRW_WIDTH_2
;
2587 if (is_supported_64bit_region(inst
, arg
) &&
2588 !is_gen7_supported_64bit_swizzle(inst
, arg
)) {
2589 /* Supported 64-bit swizzles are those such that their first two
2590 * components, when expanded to 32-bit swizzles, match the semantics
2591 * of the original 64-bit swizzle with 2-wide row regioning.
2593 unsigned swizzle0
= BRW_GET_SWZ(reg
.swizzle
, 0);
2594 unsigned swizzle1
= BRW_GET_SWZ(reg
.swizzle
, 1);
2595 hw_reg
->swizzle
= BRW_SWIZZLE4(swizzle0
* 2, swizzle0
* 2 + 1,
2596 swizzle1
* 2, swizzle1
* 2 + 1);
2598 /* If we got here then we have one of the following:
2600 * 1. An unsupported swizzle, which should be single-value thanks to the
2601 * scalarization pass.
2603 * 2. A gen7 supported swizzle. These can be single-value or double-value
2604 * swizzles. If the latter, they are never cross-dvec2 channels. For
2605 * these we always need to activate the gen7 vstride=0 exploit.
2607 unsigned swizzle0
= BRW_GET_SWZ(reg
.swizzle
, 0);
2608 unsigned swizzle1
= BRW_GET_SWZ(reg
.swizzle
, 1);
2609 assert((swizzle0
< 2) == (swizzle1
< 2));
2611 /* To gain access to Z/W components we need to select the second half
2612 * of the register and then use a X/Y swizzle to select Z/W respectively.
2614 if (swizzle0
>= 2) {
2615 *hw_reg
= suboffset(*hw_reg
, 2);
2620 /* All gen7-specific supported swizzles require the vstride=0 exploit */
2621 if (devinfo
->gen
== 7 && is_gen7_supported_64bit_swizzle(inst
, arg
))
2622 hw_reg
->vstride
= BRW_VERTICAL_STRIDE_0
;
2624 /* Any 64-bit source with an offset at 16B is intended to address the
2625 * second half of a register and needs a vertical stride of 0 so we:
2627 * 1. Don't violate register region restrictions.
2628 * 2. Activate the gen7 instruction decompresion bug exploit when
2631 if (hw_reg
->subnr
% REG_SIZE
== 16) {
2632 assert(devinfo
->gen
== 7);
2633 hw_reg
->vstride
= BRW_VERTICAL_STRIDE_0
;
2636 hw_reg
->swizzle
= BRW_SWIZZLE4(swizzle0
* 2, swizzle0
* 2 + 1,
2637 swizzle1
* 2, swizzle1
* 2 + 1);
2644 if (shader_time_index
>= 0)
2645 emit_shader_time_begin();
2658 /* Before any optimization, push array accesses out to scratch
2659 * space where we need them to be. This pass may allocate new
2660 * virtual GRFs, so we want to do it early. It also makes sure
2661 * that we have reladdr computations available for CSE, since we'll
2662 * often do repeated subexpressions for those.
2664 move_grf_array_access_to_scratch();
2665 move_uniform_array_access_to_pull_constants();
2667 pack_uniform_registers();
2668 move_push_constants_to_pull_constants();
2669 split_virtual_grfs();
2671 #define OPT(pass, args...) ({ \
2673 bool this_progress = pass(args); \
2675 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
2676 char filename[64]; \
2677 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
2678 stage_abbrev, nir->info.name, iteration, pass_num); \
2680 backend_shader::dump_instructions(filename); \
2683 progress = progress || this_progress; \
2688 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
2690 snprintf(filename
, 64, "%s-%s-00-00-start",
2691 stage_abbrev
, nir
->info
.name
);
2693 backend_shader::dump_instructions(filename
);
2704 OPT(opt_predicated_break
, this);
2705 OPT(opt_reduce_swizzle
);
2706 OPT(dead_code_eliminate
);
2707 OPT(dead_control_flow_eliminate
, this);
2708 OPT(opt_copy_propagation
);
2709 OPT(opt_cmod_propagation
);
2712 OPT(opt_register_coalesce
);
2713 OPT(eliminate_find_live_channel
);
2718 if (OPT(opt_vector_float
)) {
2720 OPT(opt_copy_propagation
, false);
2721 OPT(opt_copy_propagation
, true);
2722 OPT(dead_code_eliminate
);
2725 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
2726 OPT(opt_cmod_propagation
);
2728 OPT(opt_copy_propagation
);
2729 OPT(dead_code_eliminate
);
2732 if (OPT(lower_simd_width
)) {
2733 OPT(opt_copy_propagation
);
2734 OPT(dead_code_eliminate
);
2740 OPT(lower_64bit_mad_to_mul_add
);
2742 /* Run this before payload setup because tesselation shaders
2743 * rely on it to prevent cross dvec2 regioning on DF attributes
2744 * that are setup so that XY are on the second half of register and
2745 * ZW are in the first half of the next.
2751 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
2752 /* Debug of register spilling: Go spill everything. */
2753 const int grf_count
= alloc
.count
;
2754 float spill_costs
[alloc
.count
];
2755 bool no_spill
[alloc
.count
];
2756 evaluate_spill_costs(spill_costs
, no_spill
);
2757 for (int i
= 0; i
< grf_count
; i
++) {
2763 /* We want to run this after spilling because 64-bit (un)spills need to
2764 * emit code to shuffle 64-bit data for the 32-bit scratch read/write
2765 * messages that can produce unsupported 64-bit swizzle regions.
2770 fixup_3src_null_dest();
2772 bool allocated_without_spills
= reg_allocate();
2774 if (!allocated_without_spills
) {
2775 compiler
->shader_perf_log(log_data
,
2776 "%s shader triggered register spilling. "
2777 "Try reducing the number of live vec4 values "
2778 "to improve performance.\n",
2781 while (!reg_allocate()) {
2786 /* We want to run this after spilling because 64-bit (un)spills need to
2787 * emit code to shuffle 64-bit data for the 32-bit scratch read/write
2788 * messages that can produce unsupported 64-bit swizzle regions.
2793 opt_schedule_instructions();
2795 opt_set_dependency_control();
2797 convert_to_hw_regs();
2799 if (last_scratch
> 0) {
2800 prog_data
->base
.total_scratch
=
2801 brw_get_scratch_size(last_scratch
* REG_SIZE
);
2807 } /* namespace brw */
2812 * Compile a vertex shader.
2814 * Returns the final assembly and the program's size.
2817 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
2819 const struct brw_vs_prog_key
*key
,
2820 struct brw_vs_prog_data
*prog_data
,
2822 int shader_time_index
,
2825 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_VERTEX
];
2826 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, is_scalar
);
2828 const unsigned *assembly
= NULL
;
2830 if (prog_data
->base
.vue_map
.varying_to_slot
[VARYING_SLOT_EDGE
] != -1) {
2831 /* If the output VUE map contains VARYING_SLOT_EDGE then we need to copy
2832 * the edge flag from VERT_ATTRIB_EDGEFLAG. This will be done
2833 * automatically by brw_vec4_visitor::emit_urb_slot but we need to
2834 * ensure that prog_data->inputs_read is accurate.
2836 * In order to make late NIR passes aware of the change, we actually
2837 * whack shader->info.inputs_read instead. This is safe because we just
2838 * made a copy of the shader.
2841 assert(key
->copy_edgeflag
);
2842 shader
->info
.inputs_read
|= VERT_BIT_EDGEFLAG
;
2845 prog_data
->inputs_read
= shader
->info
.inputs_read
;
2846 prog_data
->double_inputs_read
= shader
->info
.vs
.double_inputs
;
2848 brw_nir_lower_vs_inputs(shader
, key
->gl_attrib_wa_flags
);
2849 brw_nir_lower_vue_outputs(shader
);
2850 shader
= brw_postprocess_nir(shader
, compiler
, is_scalar
);
2852 prog_data
->base
.clip_distance_mask
=
2853 ((1 << shader
->info
.clip_distance_array_size
) - 1);
2854 prog_data
->base
.cull_distance_mask
=
2855 ((1 << shader
->info
.cull_distance_array_size
) - 1) <<
2856 shader
->info
.clip_distance_array_size
;
2858 unsigned nr_attribute_slots
= util_bitcount64(prog_data
->inputs_read
);
2860 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
2861 * incoming vertex attribute. So, add an extra slot.
2863 if (shader
->info
.system_values_read
&
2864 (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX
) |
2865 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
2866 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
2867 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
2868 nr_attribute_slots
++;
2871 /* gl_DrawID and IsIndexedDraw share its very own vec4 */
2872 if (shader
->info
.system_values_read
&
2873 (BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
) |
2874 BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW
))) {
2875 nr_attribute_slots
++;
2878 if (shader
->info
.system_values_read
&
2879 BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW
))
2880 prog_data
->uses_is_indexed_draw
= true;
2882 if (shader
->info
.system_values_read
&
2883 BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX
))
2884 prog_data
->uses_firstvertex
= true;
2886 if (shader
->info
.system_values_read
&
2887 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
))
2888 prog_data
->uses_baseinstance
= true;
2890 if (shader
->info
.system_values_read
&
2891 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
))
2892 prog_data
->uses_vertexid
= true;
2894 if (shader
->info
.system_values_read
&
2895 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))
2896 prog_data
->uses_instanceid
= true;
2898 if (shader
->info
.system_values_read
&
2899 BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
))
2900 prog_data
->uses_drawid
= true;
2902 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
2903 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
2904 * vec4 mode, the hardware appears to wedge unless we read something.
2907 prog_data
->base
.urb_read_length
=
2908 DIV_ROUND_UP(nr_attribute_slots
, 2);
2910 prog_data
->base
.urb_read_length
=
2911 DIV_ROUND_UP(MAX2(nr_attribute_slots
, 1), 2);
2913 prog_data
->nr_attribute_slots
= nr_attribute_slots
;
2915 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
2916 * (overwriting the original contents), we need to make sure the size is
2917 * the larger of the two.
2919 const unsigned vue_entries
=
2920 MAX2(nr_attribute_slots
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
2922 if (compiler
->devinfo
->gen
== 6) {
2923 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
2925 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
2926 /* On Cannonlake software shall not program an allocation size that
2927 * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
2929 if (compiler
->devinfo
->gen
== 10 &&
2930 prog_data
->base
.urb_entry_size
% 3 == 0)
2931 prog_data
->base
.urb_entry_size
++;
2934 if (INTEL_DEBUG
& DEBUG_VS
) {
2935 fprintf(stderr
, "VS Output ");
2936 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
2940 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
2942 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
2943 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
2944 shader
, 8, shader_time_index
);
2947 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2952 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
2954 fs_generator
g(compiler
, log_data
, mem_ctx
,
2955 &prog_data
->base
.base
, v
.promoted_constants
,
2956 v
.runtime_check_aads_emit
, MESA_SHADER_VERTEX
);
2957 if (INTEL_DEBUG
& DEBUG_VS
) {
2958 const char *debug_name
=
2959 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
2960 shader
->info
.label
? shader
->info
.label
:
2964 g
.enable_debug(debug_name
);
2966 g
.generate_code(v
.cfg
, 8);
2967 assembly
= g
.get_assembly();
2971 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2973 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2974 shader
, mem_ctx
, shader_time_index
);
2977 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2982 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
2983 shader
, &prog_data
->base
, v
.cfg
);