2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_vec4_builder.h"
29 #include "brw_vec4_live_variables.h"
30 #include "brw_vec4_vs.h"
31 #include "brw_dead_control_flow.h"
32 #include "common/gen_debug.h"
33 #include "program/prog_parameter.h"
34 #include "util/u_math.h"
36 #define MAX_INSTRUCTION (1 << 30)
45 memset((void*)this, 0, sizeof(*this));
46 this->file
= BAD_FILE
;
47 this->type
= BRW_REGISTER_TYPE_UD
;
50 src_reg::src_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
)
56 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
57 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
59 this->swizzle
= BRW_SWIZZLE_XYZW
;
61 this->type
= brw_type_for_base_type(type
);
64 /** Generic unset register constructor. */
70 src_reg::src_reg(struct ::brw_reg reg
) :
77 src_reg::src_reg(const dst_reg
®
) :
80 this->reladdr
= reg
.reladdr
;
81 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
87 memset((void*)this, 0, sizeof(*this));
88 this->file
= BAD_FILE
;
89 this->type
= BRW_REGISTER_TYPE_UD
;
90 this->writemask
= WRITEMASK_XYZW
;
98 dst_reg::dst_reg(enum brw_reg_file file
, int nr
)
106 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
,
113 this->type
= brw_type_for_base_type(type
);
114 this->writemask
= writemask
;
117 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, brw_reg_type type
,
125 this->writemask
= writemask
;
128 dst_reg::dst_reg(struct ::brw_reg reg
) :
132 this->reladdr
= NULL
;
135 dst_reg::dst_reg(const src_reg
®
) :
138 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
139 this->reladdr
= reg
.reladdr
;
143 dst_reg::equals(const dst_reg
&r
) const
145 return (this->backend_reg::equals(r
) &&
146 (reladdr
== r
.reladdr
||
147 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))));
151 vec4_instruction::is_send_from_grf()
154 case SHADER_OPCODE_SHADER_TIME_ADD
:
155 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
156 case SHADER_OPCODE_UNTYPED_ATOMIC
:
157 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
158 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
159 case SHADER_OPCODE_TYPED_ATOMIC
:
160 case SHADER_OPCODE_TYPED_SURFACE_READ
:
161 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
162 case VEC4_OPCODE_URB_READ
:
163 case TCS_OPCODE_URB_WRITE
:
164 case TCS_OPCODE_RELEASE_INPUT
:
165 case SHADER_OPCODE_BARRIER
:
173 * Returns true if this instruction's sources and destinations cannot
174 * safely be the same register.
176 * In most cases, a register can be written over safely by the same
177 * instruction that is its last use. For a single instruction, the
178 * sources are dereferenced before writing of the destination starts
181 * However, there are a few cases where this can be problematic:
183 * - Virtual opcodes that translate to multiple instructions in the
184 * code generator: if src == dst and one instruction writes the
185 * destination before a later instruction reads the source, then
186 * src will have been clobbered.
188 * The register allocator uses this information to set up conflicts between
189 * GRF sources and the destination.
192 vec4_instruction::has_source_and_destination_hazard() const
195 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
196 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
197 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
200 /* 8-wide compressed DF operations are executed as two 4-wide operations,
201 * so we have a src/dst hazard if the first half of the instruction
202 * overwrites the source of the second half. Prevent this by marking
203 * compressed instructions as having src/dst hazards, so the register
204 * allocator assigns safe register regions for dst and srcs.
206 return size_written
> REG_SIZE
;
211 vec4_instruction::size_read(unsigned arg
) const
214 case SHADER_OPCODE_SHADER_TIME_ADD
:
215 case SHADER_OPCODE_UNTYPED_ATOMIC
:
216 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
217 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
218 case SHADER_OPCODE_TYPED_ATOMIC
:
219 case SHADER_OPCODE_TYPED_SURFACE_READ
:
220 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
221 case TCS_OPCODE_URB_WRITE
:
223 return mlen
* REG_SIZE
;
225 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
227 return mlen
* REG_SIZE
;
233 switch (src
[arg
].file
) {
238 return 4 * type_sz(src
[arg
].type
);
240 /* XXX - Represent actual vertical stride. */
241 return exec_size
* type_sz(src
[arg
].type
);
246 vec4_instruction::can_do_source_mods(const struct gen_device_info
*devinfo
)
248 if (devinfo
->gen
== 6 && is_math())
251 if (is_send_from_grf())
254 if (!backend_instruction::can_do_source_mods())
261 vec4_instruction::can_do_writemask(const struct gen_device_info
*devinfo
)
264 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
265 case VEC4_OPCODE_DOUBLE_TO_F32
:
266 case VEC4_OPCODE_DOUBLE_TO_D32
:
267 case VEC4_OPCODE_DOUBLE_TO_U32
:
268 case VEC4_OPCODE_TO_DOUBLE
:
269 case VEC4_OPCODE_PICK_LOW_32BIT
:
270 case VEC4_OPCODE_PICK_HIGH_32BIT
:
271 case VEC4_OPCODE_SET_LOW_32BIT
:
272 case VEC4_OPCODE_SET_HIGH_32BIT
:
273 case VS_OPCODE_PULL_CONSTANT_LOAD
:
274 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
275 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
276 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
277 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
278 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
279 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
280 case VEC4_OPCODE_URB_READ
:
281 case SHADER_OPCODE_MOV_INDIRECT
:
284 /* The MATH instruction on Gen6 only executes in align1 mode, which does
285 * not support writemasking.
287 if (devinfo
->gen
== 6 && is_math())
298 vec4_instruction::can_change_types() const
300 return dst
.type
== src
[0].type
&&
301 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
302 (opcode
== BRW_OPCODE_MOV
||
303 (opcode
== BRW_OPCODE_SEL
&&
304 dst
.type
== src
[1].type
&&
305 predicate
!= BRW_PREDICATE_NONE
&&
306 !src
[1].abs
&& !src
[1].negate
));
310 * Returns how many MRFs an opcode will write over.
312 * Note that this is not the 0 or 1 implied writes in an actual gen
313 * instruction -- the generate_* functions generate additional MOVs
317 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
319 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
322 switch (inst
->opcode
) {
323 case SHADER_OPCODE_RCP
:
324 case SHADER_OPCODE_RSQ
:
325 case SHADER_OPCODE_SQRT
:
326 case SHADER_OPCODE_EXP2
:
327 case SHADER_OPCODE_LOG2
:
328 case SHADER_OPCODE_SIN
:
329 case SHADER_OPCODE_COS
:
331 case SHADER_OPCODE_INT_QUOTIENT
:
332 case SHADER_OPCODE_INT_REMAINDER
:
333 case SHADER_OPCODE_POW
:
334 case TCS_OPCODE_THREAD_END
:
336 case VS_OPCODE_URB_WRITE
:
338 case VS_OPCODE_PULL_CONSTANT_LOAD
:
340 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
342 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
344 case GS_OPCODE_URB_WRITE
:
345 case GS_OPCODE_URB_WRITE_ALLOCATE
:
346 case GS_OPCODE_THREAD_END
:
348 case GS_OPCODE_FF_SYNC
:
350 case TCS_OPCODE_URB_WRITE
:
352 case SHADER_OPCODE_SHADER_TIME_ADD
:
354 case SHADER_OPCODE_TEX
:
355 case SHADER_OPCODE_TXL
:
356 case SHADER_OPCODE_TXD
:
357 case SHADER_OPCODE_TXF
:
358 case SHADER_OPCODE_TXF_CMS
:
359 case SHADER_OPCODE_TXF_CMS_W
:
360 case SHADER_OPCODE_TXF_MCS
:
361 case SHADER_OPCODE_TXS
:
362 case SHADER_OPCODE_TG4
:
363 case SHADER_OPCODE_TG4_OFFSET
:
364 case SHADER_OPCODE_SAMPLEINFO
:
365 case SHADER_OPCODE_GET_BUFFER_SIZE
:
366 return inst
->header_size
;
368 unreachable("not reached");
373 src_reg::equals(const src_reg
&r
) const
375 return (this->backend_reg::equals(r
) &&
376 !reladdr
&& !r
.reladdr
);
380 src_reg::negative_equals(const src_reg
&r
) const
382 return this->backend_reg::negative_equals(r
) &&
383 !reladdr
&& !r
.reladdr
;
387 vec4_visitor::opt_vector_float()
389 bool progress
= false;
391 foreach_block(block
, cfg
) {
392 int last_reg
= -1, last_offset
= -1;
393 enum brw_reg_file last_reg_file
= BAD_FILE
;
395 uint8_t imm
[4] = { 0 };
397 vec4_instruction
*imm_inst
[4];
398 unsigned writemask
= 0;
399 enum brw_reg_type dest_type
= BRW_REGISTER_TYPE_F
;
401 foreach_inst_in_block_safe(vec4_instruction
, inst
, block
) {
403 enum brw_reg_type need_type
;
405 /* Look for unconditional MOVs from an immediate with a partial
406 * writemask. Skip type-conversion MOVs other than integer 0,
407 * where the type doesn't matter. See if the immediate can be
408 * represented as a VF.
410 if (inst
->opcode
== BRW_OPCODE_MOV
&&
411 inst
->src
[0].file
== IMM
&&
412 inst
->predicate
== BRW_PREDICATE_NONE
&&
413 inst
->dst
.writemask
!= WRITEMASK_XYZW
&&
414 type_sz(inst
->src
[0].type
) < 8 &&
415 (inst
->src
[0].type
== inst
->dst
.type
|| inst
->src
[0].d
== 0)) {
417 vf
= brw_float_to_vf(inst
->src
[0].d
);
418 need_type
= BRW_REGISTER_TYPE_D
;
421 vf
= brw_float_to_vf(inst
->src
[0].f
);
422 need_type
= BRW_REGISTER_TYPE_F
;
428 /* If this wasn't a MOV, or the destination register doesn't match,
429 * or we have to switch destination types, then this breaks our
430 * sequence. Combine anything we've accumulated so far.
432 if (last_reg
!= inst
->dst
.nr
||
433 last_offset
!= inst
->dst
.offset
||
434 last_reg_file
!= inst
->dst
.file
||
435 (vf
> 0 && dest_type
!= need_type
)) {
437 if (inst_count
> 1) {
439 memcpy(&vf
, imm
, sizeof(vf
));
440 vec4_instruction
*mov
= MOV(imm_inst
[0]->dst
, brw_imm_vf(vf
));
441 mov
->dst
.type
= dest_type
;
442 mov
->dst
.writemask
= writemask
;
443 inst
->insert_before(block
, mov
);
445 for (int i
= 0; i
< inst_count
; i
++) {
446 imm_inst
[i
]->remove(block
);
455 dest_type
= BRW_REGISTER_TYPE_F
;
457 for (int i
= 0; i
< 4; i
++) {
462 /* Record this instruction's value (if it was representable). */
464 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
466 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
468 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
470 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
473 writemask
|= inst
->dst
.writemask
;
474 imm_inst
[inst_count
++] = inst
;
476 last_reg
= inst
->dst
.nr
;
477 last_offset
= inst
->dst
.offset
;
478 last_reg_file
= inst
->dst
.file
;
480 dest_type
= need_type
;
486 invalidate_live_intervals();
491 /* Replaces unused channels of a swizzle with channels that are used.
493 * For instance, this pass transforms
495 * mov vgrf4.yz, vgrf5.wxzy
499 * mov vgrf4.yz, vgrf5.xxzx
501 * This eliminates false uses of some channels, letting dead code elimination
502 * remove the instructions that wrote them.
505 vec4_visitor::opt_reduce_swizzle()
507 bool progress
= false;
509 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
510 if (inst
->dst
.file
== BAD_FILE
||
511 inst
->dst
.file
== ARF
||
512 inst
->dst
.file
== FIXED_GRF
||
513 inst
->is_send_from_grf())
518 /* Determine which channels of the sources are read. */
519 switch (inst
->opcode
) {
520 case VEC4_OPCODE_PACK_BYTES
:
522 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
523 * but all four of src1.
525 swizzle
= brw_swizzle_for_size(4);
528 swizzle
= brw_swizzle_for_size(3);
531 swizzle
= brw_swizzle_for_size(2);
534 case VEC4_OPCODE_TO_DOUBLE
:
535 case VEC4_OPCODE_DOUBLE_TO_F32
:
536 case VEC4_OPCODE_DOUBLE_TO_D32
:
537 case VEC4_OPCODE_DOUBLE_TO_U32
:
538 case VEC4_OPCODE_PICK_LOW_32BIT
:
539 case VEC4_OPCODE_PICK_HIGH_32BIT
:
540 case VEC4_OPCODE_SET_LOW_32BIT
:
541 case VEC4_OPCODE_SET_HIGH_32BIT
:
542 swizzle
= brw_swizzle_for_size(4);
546 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
550 /* Update sources' swizzles. */
551 for (int i
= 0; i
< 3; i
++) {
552 if (inst
->src
[i
].file
!= VGRF
&&
553 inst
->src
[i
].file
!= ATTR
&&
554 inst
->src
[i
].file
!= UNIFORM
)
557 const unsigned new_swizzle
=
558 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
559 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
560 inst
->src
[i
].swizzle
= new_swizzle
;
567 invalidate_live_intervals();
573 vec4_visitor::split_uniform_registers()
575 /* Prior to this, uniforms have been in an array sized according to
576 * the number of vector uniforms present, sparsely filled (so an
577 * aggregate results in reg indices being skipped over). Now we're
578 * going to cut those aggregates up so each .nr index is one
579 * vector. The goal is to make elimination of unused uniform
580 * components easier later.
582 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
583 for (int i
= 0 ; i
< 3; i
++) {
584 if (inst
->src
[i
].file
!= UNIFORM
)
587 assert(!inst
->src
[i
].reladdr
);
589 inst
->src
[i
].nr
+= inst
->src
[i
].offset
/ 16;
590 inst
->src
[i
].offset
%= 16;
595 /* This function returns the register number where we placed the uniform */
597 set_push_constant_loc(const int nr_uniforms
, int *new_uniform_count
,
598 const int src
, const int size
, const int channel_size
,
599 int *new_loc
, int *new_chan
,
603 /* Find the lowest place we can slot this uniform in. */
604 for (dst
= 0; dst
< nr_uniforms
; dst
++) {
605 if (ALIGN(new_chans_used
[dst
], channel_size
) + size
<= 4)
609 assert(dst
< nr_uniforms
);
612 new_chan
[src
] = ALIGN(new_chans_used
[dst
], channel_size
);
613 new_chans_used
[dst
] = ALIGN(new_chans_used
[dst
], channel_size
) + size
;
615 *new_uniform_count
= MAX2(*new_uniform_count
, dst
+ 1);
620 vec4_visitor::pack_uniform_registers()
622 uint8_t chans_used
[this->uniforms
];
623 int new_loc
[this->uniforms
];
624 int new_chan
[this->uniforms
];
625 bool is_aligned_to_dvec4
[this->uniforms
];
626 int new_chans_used
[this->uniforms
];
627 int channel_sizes
[this->uniforms
];
629 memset(chans_used
, 0, sizeof(chans_used
));
630 memset(new_loc
, 0, sizeof(new_loc
));
631 memset(new_chan
, 0, sizeof(new_chan
));
632 memset(new_chans_used
, 0, sizeof(new_chans_used
));
633 memset(is_aligned_to_dvec4
, 0, sizeof(is_aligned_to_dvec4
));
634 memset(channel_sizes
, 0, sizeof(channel_sizes
));
636 /* Find which uniform vectors are actually used by the program. We
637 * expect unused vector elements when we've moved array access out
638 * to pull constants, and from some GLSL code generators like wine.
640 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
642 switch (inst
->opcode
) {
643 case VEC4_OPCODE_PACK_BYTES
:
655 readmask
= inst
->dst
.writemask
;
659 for (int i
= 0 ; i
< 3; i
++) {
660 if (inst
->src
[i
].file
!= UNIFORM
)
663 assert(type_sz(inst
->src
[i
].type
) % 4 == 0);
664 int channel_size
= type_sz(inst
->src
[i
].type
) / 4;
666 int reg
= inst
->src
[i
].nr
;
667 for (int c
= 0; c
< 4; c
++) {
668 if (!(readmask
& (1 << c
)))
671 unsigned channel
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1;
672 unsigned used
= MAX2(chans_used
[reg
], channel
* channel_size
);
674 chans_used
[reg
] = used
;
675 channel_sizes
[reg
] = MAX2(channel_sizes
[reg
], channel_size
);
677 is_aligned_to_dvec4
[reg
] = true;
678 is_aligned_to_dvec4
[reg
+ 1] = true;
679 chans_used
[reg
+ 1] = used
- 4;
680 channel_sizes
[reg
+ 1] = MAX2(channel_sizes
[reg
+ 1], channel_size
);
685 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
686 inst
->src
[0].file
== UNIFORM
) {
687 assert(inst
->src
[2].file
== BRW_IMMEDIATE_VALUE
);
688 assert(inst
->src
[0].subnr
== 0);
690 unsigned bytes_read
= inst
->src
[2].ud
;
691 assert(bytes_read
% 4 == 0);
692 unsigned vec4s_read
= DIV_ROUND_UP(bytes_read
, 16);
694 /* We just mark every register touched by a MOV_INDIRECT as being
695 * fully used. This ensures that it doesn't broken up piecewise by
696 * the next part of our packing algorithm.
698 int reg
= inst
->src
[0].nr
;
699 int channel_size
= type_sz(inst
->src
[0].type
) / 4;
700 for (unsigned i
= 0; i
< vec4s_read
; i
++) {
701 chans_used
[reg
+ i
] = 4;
702 channel_sizes
[reg
+ i
] = MAX2(channel_sizes
[reg
+ i
], channel_size
);
707 int new_uniform_count
= 0;
709 /* As the uniforms are going to be reordered, take the data from a temporary
710 * copy of the original param[].
712 uint32_t *param
= ralloc_array(NULL
, uint32_t, stage_prog_data
->nr_params
);
713 memcpy(param
, stage_prog_data
->param
,
714 sizeof(uint32_t) * stage_prog_data
->nr_params
);
716 /* Now, figure out a packing of the live uniform vectors into our
717 * push constants. Start with dvec{3,4} because they are aligned to
718 * dvec4 size (2 vec4).
720 for (int src
= 0; src
< uniforms
; src
++) {
721 int size
= chans_used
[src
];
723 if (size
== 0 || !is_aligned_to_dvec4
[src
])
726 /* dvec3 are aligned to dvec4 size, apply the alignment of the size
727 * to 4 to avoid moving last component of a dvec3 to the available
728 * location at the end of a previous dvec3. These available locations
729 * could be filled by smaller variables in next loop.
731 size
= ALIGN(size
, 4);
732 int dst
= set_push_constant_loc(uniforms
, &new_uniform_count
,
733 src
, size
, channel_sizes
[src
],
736 /* Move the references to the data */
737 for (int j
= 0; j
< size
; j
++) {
738 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
743 /* Continue with the rest of data, which is aligned to vec4. */
744 for (int src
= 0; src
< uniforms
; src
++) {
745 int size
= chans_used
[src
];
747 if (size
== 0 || is_aligned_to_dvec4
[src
])
750 int dst
= set_push_constant_loc(uniforms
, &new_uniform_count
,
751 src
, size
, channel_sizes
[src
],
754 /* Move the references to the data */
755 for (int j
= 0; j
< size
; j
++) {
756 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
762 this->uniforms
= new_uniform_count
;
764 /* Now, update the instructions for our repacked uniforms. */
765 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
766 for (int i
= 0 ; i
< 3; i
++) {
767 int src
= inst
->src
[i
].nr
;
769 if (inst
->src
[i
].file
!= UNIFORM
)
772 int chan
= new_chan
[src
] / channel_sizes
[src
];
773 inst
->src
[i
].nr
= new_loc
[src
];
774 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(chan
, chan
, chan
, chan
);
780 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
782 * While GLSL IR also performs this optimization, we end up with it in
783 * our instruction stream for a couple of reasons. One is that we
784 * sometimes generate silly instructions, for example in array access
785 * where we'll generate "ADD offset, index, base" even if base is 0.
786 * The other is that GLSL IR's constant propagation doesn't track the
787 * components of aggregates, so some VS patterns (initialize matrix to
788 * 0, accumulate in vertex blending factors) end up breaking down to
789 * instructions involving 0.
792 vec4_visitor::opt_algebraic()
794 bool progress
= false;
796 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
797 switch (inst
->opcode
) {
799 if (inst
->src
[0].file
!= IMM
)
802 if (inst
->saturate
) {
803 /* Full mixed-type saturates don't happen. However, we can end up
806 * mov.sat(8) g21<1>DF -1F
808 * Other mixed-size-but-same-base-type cases may also be possible.
810 if (inst
->dst
.type
!= inst
->src
[0].type
&&
811 inst
->dst
.type
!= BRW_REGISTER_TYPE_DF
&&
812 inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
813 assert(!"unimplemented: saturate mixed types");
815 if (brw_saturate_immediate(inst
->src
[0].type
,
816 &inst
->src
[0].as_brw_reg())) {
817 inst
->saturate
= false;
824 if (inst
->src
[1].is_zero()) {
825 inst
->opcode
= BRW_OPCODE_MOV
;
826 inst
->src
[1] = src_reg();
831 case VEC4_OPCODE_UNPACK_UNIFORM
:
832 if (inst
->src
[0].file
!= UNIFORM
) {
833 inst
->opcode
= BRW_OPCODE_MOV
;
839 if (inst
->src
[1].is_zero()) {
840 inst
->opcode
= BRW_OPCODE_MOV
;
841 inst
->src
[1] = src_reg();
847 if (inst
->src
[1].is_zero()) {
848 inst
->opcode
= BRW_OPCODE_MOV
;
849 switch (inst
->src
[0].type
) {
850 case BRW_REGISTER_TYPE_F
:
851 inst
->src
[0] = brw_imm_f(0.0f
);
853 case BRW_REGISTER_TYPE_D
:
854 inst
->src
[0] = brw_imm_d(0);
856 case BRW_REGISTER_TYPE_UD
:
857 inst
->src
[0] = brw_imm_ud(0u);
860 unreachable("not reached");
862 inst
->src
[1] = src_reg();
864 } else if (inst
->src
[1].is_one()) {
865 inst
->opcode
= BRW_OPCODE_MOV
;
866 inst
->src
[1] = src_reg();
868 } else if (inst
->src
[1].is_negative_one()) {
869 inst
->opcode
= BRW_OPCODE_MOV
;
870 inst
->src
[0].negate
= !inst
->src
[0].negate
;
871 inst
->src
[1] = src_reg();
876 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
878 inst
->src
[0].negate
&&
879 inst
->src
[1].is_zero()) {
880 inst
->src
[0].abs
= false;
881 inst
->src
[0].negate
= false;
882 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
887 case SHADER_OPCODE_BROADCAST
:
888 if (is_uniform(inst
->src
[0]) ||
889 inst
->src
[1].is_zero()) {
890 inst
->opcode
= BRW_OPCODE_MOV
;
891 inst
->src
[1] = src_reg();
892 inst
->force_writemask_all
= true;
903 invalidate_live_intervals();
909 * Only a limited number of hardware registers may be used for push
910 * constants, so this turns access to the overflowed constants into
914 vec4_visitor::move_push_constants_to_pull_constants()
916 int pull_constant_loc
[this->uniforms
];
918 /* Only allow 32 registers (256 uniform components) as push constants,
919 * which is the limit on gen6.
921 * If changing this value, note the limitation about total_regs in
924 int max_uniform_components
= 32 * 8;
925 if (this->uniforms
* 4 <= max_uniform_components
)
928 /* Make some sort of choice as to which uniforms get sent to pull
929 * constants. We could potentially do something clever here like
930 * look for the most infrequently used uniform vec4s, but leave
933 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
934 pull_constant_loc
[i
/ 4] = -1;
936 if (i
>= max_uniform_components
) {
937 uint32_t *values
= &stage_prog_data
->param
[i
];
939 /* Try to find an existing copy of this uniform in the pull
940 * constants if it was part of an array access already.
942 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
945 for (matches
= 0; matches
< 4; matches
++) {
946 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
951 pull_constant_loc
[i
/ 4] = j
/ 4;
956 if (pull_constant_loc
[i
/ 4] == -1) {
957 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
958 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
960 for (int j
= 0; j
< 4; j
++) {
961 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
968 /* Now actually rewrite usage of the things we've moved to pull
971 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
972 for (int i
= 0 ; i
< 3; i
++) {
973 if (inst
->src
[i
].file
!= UNIFORM
||
974 pull_constant_loc
[inst
->src
[i
].nr
] == -1)
977 int uniform
= inst
->src
[i
].nr
;
979 const glsl_type
*temp_type
= type_sz(inst
->src
[i
].type
) == 8 ?
980 glsl_type::dvec4_type
: glsl_type::vec4_type
;
981 dst_reg temp
= dst_reg(this, temp_type
);
983 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
984 pull_constant_loc
[uniform
], src_reg());
986 inst
->src
[i
].file
= temp
.file
;
987 inst
->src
[i
].nr
= temp
.nr
;
988 inst
->src
[i
].offset
%= 16;
989 inst
->src
[i
].reladdr
= NULL
;
993 /* Repack push constants to remove the now-unused ones. */
994 pack_uniform_registers();
997 /* Conditions for which we want to avoid setting the dependency control bits */
999 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
1001 #define IS_DWORD(reg) \
1002 (reg.type == BRW_REGISTER_TYPE_UD || \
1003 reg.type == BRW_REGISTER_TYPE_D)
1005 #define IS_64BIT(reg) (reg.file != BAD_FILE && type_sz(reg.type) == 8)
1007 /* From the Cherryview and Broadwell PRMs:
1009 * "When source or destination datatype is 64b or operation is integer DWord
1010 * multiply, DepCtrl must not be used."
1012 * SKL PRMs don't include this restriction, however, gen7 seems to be
1013 * affected, at least by the 64b restriction, since DepCtrl with double
1014 * precision instructions seems to produce GPU hangs in some cases.
1016 if (devinfo
->gen
== 8 || gen_device_info_is_9lp(devinfo
)) {
1017 if (inst
->opcode
== BRW_OPCODE_MUL
&&
1018 IS_DWORD(inst
->src
[0]) &&
1019 IS_DWORD(inst
->src
[1]))
1023 if (devinfo
->gen
>= 7 && devinfo
->gen
<= 8) {
1024 if (IS_64BIT(inst
->dst
) || IS_64BIT(inst
->src
[0]) ||
1025 IS_64BIT(inst
->src
[1]) || IS_64BIT(inst
->src
[2]))
1032 if (devinfo
->gen
>= 8) {
1033 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
1039 * In the presence of send messages, totally interrupt dependency
1040 * control. They're long enough that the chance of dependency
1041 * control around them just doesn't matter.
1044 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
1045 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
1046 * completes the scoreboard clear must have a non-zero execution mask. This
1047 * means, if any kind of predication can change the execution mask or channel
1048 * enable of the last instruction, the optimization must be avoided. This is
1049 * to avoid instructions being shot down the pipeline when no writes are
1053 * Dependency control does not work well over math instructions.
1054 * NB: Discovered empirically
1056 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
1060 * Sets the dependency control fields on instructions after register
1061 * allocation and before the generator is run.
1063 * When you have a sequence of instructions like:
1065 * DP4 temp.x vertex uniform[0]
1066 * DP4 temp.y vertex uniform[0]
1067 * DP4 temp.z vertex uniform[0]
1068 * DP4 temp.w vertex uniform[0]
1070 * The hardware doesn't know that it can actually run the later instructions
1071 * while the previous ones are in flight, producing stalls. However, we have
1072 * manual fields we can set in the instructions that let it do so.
1075 vec4_visitor::opt_set_dependency_control()
1077 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
1078 uint8_t grf_channels_written
[BRW_MAX_GRF
];
1079 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
1080 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
1082 assert(prog_data
->total_grf
||
1083 !"Must be called after register allocation");
1085 foreach_block (block
, cfg
) {
1086 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1087 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1089 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
1090 /* If we read from a register that we were doing dependency control
1091 * on, don't do dependency control across the read.
1093 for (int i
= 0; i
< 3; i
++) {
1094 int reg
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ REG_SIZE
;
1095 if (inst
->src
[i
].file
== VGRF
) {
1096 last_grf_write
[reg
] = NULL
;
1097 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1098 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1101 assert(inst
->src
[i
].file
!= MRF
);
1104 if (is_dep_ctrl_unsafe(inst
)) {
1105 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1106 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1110 /* Now, see if we can do dependency control for this instruction
1111 * against a previous one writing to its destination.
1113 int reg
= inst
->dst
.nr
+ inst
->dst
.offset
/ REG_SIZE
;
1114 if (inst
->dst
.file
== VGRF
|| inst
->dst
.file
== FIXED_GRF
) {
1115 if (last_grf_write
[reg
] &&
1116 last_grf_write
[reg
]->dst
.offset
== inst
->dst
.offset
&&
1117 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
1118 last_grf_write
[reg
]->no_dd_clear
= true;
1119 inst
->no_dd_check
= true;
1121 grf_channels_written
[reg
] = 0;
1124 last_grf_write
[reg
] = inst
;
1125 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
1126 } else if (inst
->dst
.file
== MRF
) {
1127 if (last_mrf_write
[reg
] &&
1128 last_mrf_write
[reg
]->dst
.offset
== inst
->dst
.offset
&&
1129 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
1130 last_mrf_write
[reg
]->no_dd_clear
= true;
1131 inst
->no_dd_check
= true;
1133 mrf_channels_written
[reg
] = 0;
1136 last_mrf_write
[reg
] = inst
;
1137 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
1144 vec4_instruction::can_reswizzle(const struct gen_device_info
*devinfo
,
1149 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
1152 if (devinfo
->gen
== 6 && is_math() && swizzle
!= BRW_SWIZZLE_XYZW
)
1155 /* We can't swizzle implicit accumulator access. We'd have to
1156 * reswizzle the producer of the accumulator value in addition
1157 * to the consumer (i.e. both MUL and MACH). Just skip this.
1159 if (reads_accumulator_implicitly())
1162 if (!can_do_writemask(devinfo
) && dst_writemask
!= WRITEMASK_XYZW
)
1165 /* If this instruction sets anything not referenced by swizzle, then we'd
1166 * totally break it when we reswizzle.
1168 if (dst
.writemask
& ~swizzle_mask
)
1174 for (int i
= 0; i
< 3; i
++) {
1175 if (src
[i
].is_accumulator())
1183 * For any channels in the swizzle's source that were populated by this
1184 * instruction, rewrite the instruction to put the appropriate result directly
1185 * in those channels.
1187 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
1190 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
1192 /* Destination write mask doesn't correspond to source swizzle for the dot
1193 * product and pack_bytes instructions.
1195 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
1196 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
1197 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
1198 for (int i
= 0; i
< 3; i
++) {
1199 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
1202 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
1206 /* Apply the specified swizzle and writemask to the original mask of
1207 * written components.
1209 dst
.writemask
= dst_writemask
&
1210 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1214 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1215 * just written and then MOVed into another reg and making the original write
1216 * of the GRF write directly to the final destination instead.
1219 vec4_visitor::opt_register_coalesce()
1221 bool progress
= false;
1224 calculate_live_intervals();
1226 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1230 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1231 (inst
->dst
.file
!= VGRF
&& inst
->dst
.file
!= MRF
) ||
1233 inst
->src
[0].file
!= VGRF
||
1234 inst
->dst
.type
!= inst
->src
[0].type
||
1235 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1238 /* Remove no-op MOVs */
1239 if (inst
->dst
.file
== inst
->src
[0].file
&&
1240 inst
->dst
.nr
== inst
->src
[0].nr
&&
1241 inst
->dst
.offset
== inst
->src
[0].offset
) {
1242 bool is_nop_mov
= true;
1244 for (unsigned c
= 0; c
< 4; c
++) {
1245 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1248 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1255 inst
->remove(block
);
1261 bool to_mrf
= (inst
->dst
.file
== MRF
);
1263 /* Can't coalesce this GRF if someone else was going to
1266 if (var_range_end(var_from_reg(alloc
, dst_reg(inst
->src
[0])), 8) > ip
)
1269 /* We need to check interference with the final destination between this
1270 * instruction and the earliest instruction involved in writing the GRF
1271 * we're eliminating. To do that, keep track of which of our source
1272 * channels we've seen initialized.
1274 const unsigned chans_needed
=
1275 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1276 inst
->dst
.writemask
);
1277 unsigned chans_remaining
= chans_needed
;
1279 /* Now walk up the instruction stream trying to see if we can rewrite
1280 * everything writing to the temporary to write into the destination
1283 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1284 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1286 _scan_inst
= scan_inst
;
1288 if (regions_overlap(inst
->src
[0], inst
->size_read(0),
1289 scan_inst
->dst
, scan_inst
->size_written
)) {
1290 /* Found something writing to the reg we want to coalesce away. */
1292 /* SEND instructions can't have MRF as a destination. */
1293 if (scan_inst
->mlen
)
1296 if (devinfo
->gen
== 6) {
1297 /* gen6 math instructions must have the destination be
1298 * VGRF, so no compute-to-MRF for them.
1300 if (scan_inst
->is_math()) {
1306 /* VS_OPCODE_UNPACK_FLAGS_SIMD4X2 generates a bunch of mov(1)
1307 * instructions, and this optimization pass is not capable of
1308 * handling that. Bail on these instructions and hope that some
1309 * later optimization pass can do the right thing after they are
1312 if (scan_inst
->opcode
== VS_OPCODE_UNPACK_FLAGS_SIMD4X2
)
1315 /* This doesn't handle saturation on the instruction we
1316 * want to coalesce away if the register types do not match.
1317 * But if scan_inst is a non type-converting 'mov', we can fix
1320 if (inst
->saturate
&&
1321 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1322 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1323 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1326 /* Only allow coalescing between registers of the same type size.
1327 * Otherwise we would need to make the pass aware of the fact that
1328 * channel sizes are different for single and double precision.
1330 if (type_sz(inst
->src
[0].type
) != type_sz(scan_inst
->src
[0].type
))
1333 /* Check that scan_inst writes the same amount of data as the
1334 * instruction, otherwise coalescing would lead to writing a
1335 * different (larger or smaller) region of the destination
1337 if (scan_inst
->size_written
!= inst
->size_written
)
1340 /* If we can't handle the swizzle, bail. */
1341 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1342 inst
->src
[0].swizzle
,
1347 /* This only handles coalescing writes of 8 channels (1 register
1348 * for single-precision and 2 registers for double-precision)
1349 * starting at the source offset of the copy instruction.
1351 if (DIV_ROUND_UP(scan_inst
->size_written
,
1352 type_sz(scan_inst
->dst
.type
)) > 8 ||
1353 scan_inst
->dst
.offset
!= inst
->src
[0].offset
)
1356 /* Mark which channels we found unconditional writes for. */
1357 if (!scan_inst
->predicate
)
1358 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1360 if (chans_remaining
== 0)
1364 /* You can't read from an MRF, so if someone else reads our MRF's
1365 * source GRF that we wanted to rewrite, that stops us. If it's a
1366 * GRF we're trying to coalesce to, we don't actually handle
1367 * rewriting sources so bail in that case as well.
1369 bool interfered
= false;
1370 for (int i
= 0; i
< 3; i
++) {
1371 if (regions_overlap(inst
->src
[0], inst
->size_read(0),
1372 scan_inst
->src
[i
], scan_inst
->size_read(i
)))
1378 /* If somebody else writes the same channels of our destination here,
1379 * we can't coalesce before that.
1381 if (regions_overlap(inst
->dst
, inst
->size_written
,
1382 scan_inst
->dst
, scan_inst
->size_written
) &&
1383 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1387 /* Check for reads of the register we're trying to coalesce into. We
1388 * can't go rewriting instructions above that to put some other value
1389 * in the register instead.
1391 if (to_mrf
&& scan_inst
->mlen
> 0) {
1392 if (inst
->dst
.nr
>= scan_inst
->base_mrf
&&
1393 inst
->dst
.nr
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1397 for (int i
= 0; i
< 3; i
++) {
1398 if (regions_overlap(inst
->dst
, inst
->size_written
,
1399 scan_inst
->src
[i
], scan_inst
->size_read(i
)))
1407 if (chans_remaining
== 0) {
1408 /* If we've made it here, we have an MOV we want to coalesce out, and
1409 * a scan_inst pointing to the earliest instruction involved in
1410 * computing the value. Now go rewrite the instruction stream
1413 vec4_instruction
*scan_inst
= _scan_inst
;
1414 while (scan_inst
!= inst
) {
1415 if (scan_inst
->dst
.file
== VGRF
&&
1416 scan_inst
->dst
.nr
== inst
->src
[0].nr
&&
1417 scan_inst
->dst
.offset
== inst
->src
[0].offset
) {
1418 scan_inst
->reswizzle(inst
->dst
.writemask
,
1419 inst
->src
[0].swizzle
);
1420 scan_inst
->dst
.file
= inst
->dst
.file
;
1421 scan_inst
->dst
.nr
= inst
->dst
.nr
;
1422 scan_inst
->dst
.offset
= inst
->dst
.offset
;
1423 if (inst
->saturate
&&
1424 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1425 /* If we have reached this point, scan_inst is a non
1426 * type-converting 'mov' and we can modify its register types
1427 * to match the ones in inst. Otherwise, we could have an
1428 * incorrect saturation result.
1430 scan_inst
->dst
.type
= inst
->dst
.type
;
1431 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1433 scan_inst
->saturate
|= inst
->saturate
;
1435 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1437 inst
->remove(block
);
1443 invalidate_live_intervals();
1449 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1450 * flow. We could probably do better here with some form of divergence
1454 vec4_visitor::eliminate_find_live_channel()
1456 bool progress
= false;
1459 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
1460 /* The optimization below assumes that channel zero is live on thread
1461 * dispatch, which may not be the case if the fixed function dispatches
1467 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1468 switch (inst
->opcode
) {
1474 case BRW_OPCODE_ENDIF
:
1475 case BRW_OPCODE_WHILE
:
1479 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1481 inst
->opcode
= BRW_OPCODE_MOV
;
1482 inst
->src
[0] = brw_imm_d(0);
1483 inst
->force_writemask_all
= true;
1497 * Splits virtual GRFs requesting more than one contiguous physical register.
1499 * We initially create large virtual GRFs for temporary structures, arrays,
1500 * and matrices, so that the visitor functions can add offsets to work their
1501 * way down to the actual member being accessed. But when it comes to
1502 * optimization, we'd like to treat each register as individual storage if
1505 * So far, the only thing that might prevent splitting is a send message from
1509 vec4_visitor::split_virtual_grfs()
1511 int num_vars
= this->alloc
.count
;
1512 int new_virtual_grf
[num_vars
];
1513 bool split_grf
[num_vars
];
1515 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1517 /* Try to split anything > 0 sized. */
1518 for (int i
= 0; i
< num_vars
; i
++) {
1519 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1522 /* Check that the instructions are compatible with the registers we're trying
1525 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1526 if (inst
->dst
.file
== VGRF
&& regs_written(inst
) > 1)
1527 split_grf
[inst
->dst
.nr
] = false;
1529 for (int i
= 0; i
< 3; i
++) {
1530 if (inst
->src
[i
].file
== VGRF
&& regs_read(inst
, i
) > 1)
1531 split_grf
[inst
->src
[i
].nr
] = false;
1535 /* Allocate new space for split regs. Note that the virtual
1536 * numbers will be contiguous.
1538 for (int i
= 0; i
< num_vars
; i
++) {
1542 new_virtual_grf
[i
] = alloc
.allocate(1);
1543 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1544 unsigned reg
= alloc
.allocate(1);
1545 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1548 this->alloc
.sizes
[i
] = 1;
1551 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1552 if (inst
->dst
.file
== VGRF
&& split_grf
[inst
->dst
.nr
] &&
1553 inst
->dst
.offset
/ REG_SIZE
!= 0) {
1554 inst
->dst
.nr
= (new_virtual_grf
[inst
->dst
.nr
] +
1555 inst
->dst
.offset
/ REG_SIZE
- 1);
1556 inst
->dst
.offset
%= REG_SIZE
;
1558 for (int i
= 0; i
< 3; i
++) {
1559 if (inst
->src
[i
].file
== VGRF
&& split_grf
[inst
->src
[i
].nr
] &&
1560 inst
->src
[i
].offset
/ REG_SIZE
!= 0) {
1561 inst
->src
[i
].nr
= (new_virtual_grf
[inst
->src
[i
].nr
] +
1562 inst
->src
[i
].offset
/ REG_SIZE
- 1);
1563 inst
->src
[i
].offset
%= REG_SIZE
;
1567 invalidate_live_intervals();
1571 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1573 dump_instruction(be_inst
, stderr
);
1577 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1579 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1581 if (inst
->predicate
) {
1582 fprintf(file
, "(%cf%d.%d%s) ",
1583 inst
->predicate_inverse
? '-' : '+',
1584 inst
->flag_subreg
/ 2,
1585 inst
->flag_subreg
% 2,
1586 pred_ctrl_align16
[inst
->predicate
]);
1589 fprintf(file
, "%s(%d)", brw_instruction_name(devinfo
, inst
->opcode
),
1592 fprintf(file
, ".sat");
1593 if (inst
->conditional_mod
) {
1594 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1595 if (!inst
->predicate
&&
1596 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1597 inst
->opcode
!= BRW_OPCODE_CSEL
&&
1598 inst
->opcode
!= BRW_OPCODE_IF
&&
1599 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1600 fprintf(file
, ".f%d.%d", inst
->flag_subreg
/ 2, inst
->flag_subreg
% 2);
1605 switch (inst
->dst
.file
) {
1607 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
1610 fprintf(file
, "g%d", inst
->dst
.nr
);
1613 fprintf(file
, "m%d", inst
->dst
.nr
);
1616 switch (inst
->dst
.nr
) {
1618 fprintf(file
, "null");
1620 case BRW_ARF_ADDRESS
:
1621 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
1623 case BRW_ARF_ACCUMULATOR
:
1624 fprintf(file
, "acc%d", inst
->dst
.subnr
);
1627 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1630 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1635 fprintf(file
, "(null)");
1640 unreachable("not reached");
1642 if (inst
->dst
.offset
||
1643 (inst
->dst
.file
== VGRF
&&
1644 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
1645 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 16 : REG_SIZE
);
1646 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
1647 inst
->dst
.offset
% reg_size
);
1649 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1651 if (inst
->dst
.writemask
& 1)
1653 if (inst
->dst
.writemask
& 2)
1655 if (inst
->dst
.writemask
& 4)
1657 if (inst
->dst
.writemask
& 8)
1660 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->dst
.type
));
1662 if (inst
->src
[0].file
!= BAD_FILE
)
1663 fprintf(file
, ", ");
1665 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1666 if (inst
->src
[i
].negate
)
1668 if (inst
->src
[i
].abs
)
1670 switch (inst
->src
[i
].file
) {
1672 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
1675 fprintf(file
, "g%d.%d", inst
->src
[i
].nr
, inst
->src
[i
].subnr
);
1678 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
1681 fprintf(file
, "u%d", inst
->src
[i
].nr
);
1684 switch (inst
->src
[i
].type
) {
1685 case BRW_REGISTER_TYPE_F
:
1686 fprintf(file
, "%fF", inst
->src
[i
].f
);
1688 case BRW_REGISTER_TYPE_DF
:
1689 fprintf(file
, "%fDF", inst
->src
[i
].df
);
1691 case BRW_REGISTER_TYPE_D
:
1692 fprintf(file
, "%dD", inst
->src
[i
].d
);
1694 case BRW_REGISTER_TYPE_UD
:
1695 fprintf(file
, "%uU", inst
->src
[i
].ud
);
1697 case BRW_REGISTER_TYPE_VF
:
1698 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1699 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
1700 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
1701 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
1702 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
1705 fprintf(file
, "???");
1710 switch (inst
->src
[i
].nr
) {
1712 fprintf(file
, "null");
1714 case BRW_ARF_ADDRESS
:
1715 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
1717 case BRW_ARF_ACCUMULATOR
:
1718 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
1721 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1724 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1729 fprintf(file
, "(null)");
1732 unreachable("not reached");
1735 if (inst
->src
[i
].offset
||
1736 (inst
->src
[i
].file
== VGRF
&&
1737 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
1738 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 16 : REG_SIZE
);
1739 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
1740 inst
->src
[i
].offset
% reg_size
);
1743 if (inst
->src
[i
].file
!= IMM
) {
1744 static const char *chans
[4] = {"x", "y", "z", "w"};
1746 for (int c
= 0; c
< 4; c
++) {
1747 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1751 if (inst
->src
[i
].abs
)
1754 if (inst
->src
[i
].file
!= IMM
) {
1755 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
1758 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1759 fprintf(file
, ", ");
1762 if (inst
->force_writemask_all
)
1763 fprintf(file
, " NoMask");
1765 if (inst
->exec_size
!= 8)
1766 fprintf(file
, " group%d", inst
->group
);
1768 fprintf(file
, "\n");
1773 vec4_vs_visitor::setup_attributes(int payload_reg
)
1775 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1776 for (int i
= 0; i
< 3; i
++) {
1777 if (inst
->src
[i
].file
== ATTR
) {
1778 assert(inst
->src
[i
].offset
% REG_SIZE
== 0);
1779 int grf
= payload_reg
+ inst
->src
[i
].nr
+
1780 inst
->src
[i
].offset
/ REG_SIZE
;
1782 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1783 reg
.swizzle
= inst
->src
[i
].swizzle
;
1784 reg
.type
= inst
->src
[i
].type
;
1785 reg
.abs
= inst
->src
[i
].abs
;
1786 reg
.negate
= inst
->src
[i
].negate
;
1792 return payload_reg
+ vs_prog_data
->nr_attribute_slots
;
1796 vec4_visitor::setup_uniforms(int reg
)
1798 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1800 /* The pre-gen6 VS requires that some push constants get loaded no
1801 * matter what, or the GPU would hang.
1803 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1804 brw_stage_prog_data_add_params(stage_prog_data
, 4);
1805 for (unsigned int i
= 0; i
< 4; i
++) {
1806 unsigned int slot
= this->uniforms
* 4 + i
;
1807 stage_prog_data
->param
[slot
] = BRW_PARAM_BUILTIN_ZERO
;
1813 reg
+= ALIGN(uniforms
, 2) / 2;
1816 for (int i
= 0; i
< 4; i
++)
1817 reg
+= stage_prog_data
->ubo_ranges
[i
].length
;
1819 stage_prog_data
->nr_params
= this->uniforms
* 4;
1821 prog_data
->base
.curb_read_length
=
1822 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1828 vec4_vs_visitor::setup_payload(void)
1832 /* The payload always contains important data in g0, which contains
1833 * the URB handles that are passed on to the URB write at the end
1834 * of the thread. So, we always start push constants at g1.
1838 reg
= setup_uniforms(reg
);
1840 reg
= setup_attributes(reg
);
1842 this->first_non_payload_grf
= reg
;
1846 vec4_visitor::lower_minmax()
1848 assert(devinfo
->gen
< 6);
1850 bool progress
= false;
1852 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1853 const vec4_builder
ibld(this, block
, inst
);
1855 if (inst
->opcode
== BRW_OPCODE_SEL
&&
1856 inst
->predicate
== BRW_PREDICATE_NONE
) {
1857 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
1858 * the original SEL.L/GE instruction
1860 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
1861 inst
->conditional_mod
);
1862 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1863 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
1870 invalidate_live_intervals();
1876 vec4_visitor::get_timestamp()
1878 assert(devinfo
->gen
>= 7);
1880 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1885 BRW_REGISTER_TYPE_UD
,
1886 BRW_VERTICAL_STRIDE_0
,
1888 BRW_HORIZONTAL_STRIDE_4
,
1892 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1894 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1895 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1896 * even if it's not enabled in the dispatch.
1898 mov
->force_writemask_all
= true;
1900 return src_reg(dst
);
1904 vec4_visitor::emit_shader_time_begin()
1906 current_annotation
= "shader time start";
1907 shader_start_time
= get_timestamp();
1911 vec4_visitor::emit_shader_time_end()
1913 current_annotation
= "shader time end";
1914 src_reg shader_end_time
= get_timestamp();
1917 /* Check that there weren't any timestamp reset events (assuming these
1918 * were the only two timestamp reads that happened).
1920 src_reg reset_end
= shader_end_time
;
1921 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1922 vec4_instruction
*test
= emit(AND(dst_null_ud(), reset_end
, brw_imm_ud(1u)));
1923 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1925 emit(IF(BRW_PREDICATE_NORMAL
));
1927 /* Take the current timestamp and get the delta. */
1928 shader_start_time
.negate
= true;
1929 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1930 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1932 /* If there were no instructions between the two timestamp gets, the diff
1933 * is 2 cycles. Remove that overhead, so I can forget about that when
1934 * trying to determine the time taken for single instructions.
1936 emit(ADD(diff
, src_reg(diff
), brw_imm_ud(-2u)));
1938 emit_shader_time_write(0, src_reg(diff
));
1939 emit_shader_time_write(1, brw_imm_ud(1u));
1940 emit(BRW_OPCODE_ELSE
);
1941 emit_shader_time_write(2, brw_imm_ud(1u));
1942 emit(BRW_OPCODE_ENDIF
);
1946 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1949 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1951 dst_reg offset
= dst
;
1953 time
.offset
+= REG_SIZE
;
1955 offset
.type
= BRW_REGISTER_TYPE_UD
;
1956 int index
= shader_time_index
* 3 + shader_time_subindex
;
1957 emit(MOV(offset
, brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
)));
1959 time
.type
= BRW_REGISTER_TYPE_UD
;
1960 emit(MOV(time
, value
));
1962 vec4_instruction
*inst
=
1963 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1968 is_align1_df(vec4_instruction
*inst
)
1970 switch (inst
->opcode
) {
1971 case VEC4_OPCODE_DOUBLE_TO_F32
:
1972 case VEC4_OPCODE_DOUBLE_TO_D32
:
1973 case VEC4_OPCODE_DOUBLE_TO_U32
:
1974 case VEC4_OPCODE_TO_DOUBLE
:
1975 case VEC4_OPCODE_PICK_LOW_32BIT
:
1976 case VEC4_OPCODE_PICK_HIGH_32BIT
:
1977 case VEC4_OPCODE_SET_LOW_32BIT
:
1978 case VEC4_OPCODE_SET_HIGH_32BIT
:
1986 * Three source instruction must have a GRF/MRF destination register.
1987 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
1990 vec4_visitor::fixup_3src_null_dest()
1992 bool progress
= false;
1994 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1995 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
1996 const unsigned size_written
= type_sz(inst
->dst
.type
);
1997 const unsigned num_regs
= DIV_ROUND_UP(size_written
, REG_SIZE
);
1999 inst
->dst
= retype(dst_reg(VGRF
, alloc
.allocate(num_regs
)),
2006 invalidate_live_intervals();
2010 vec4_visitor::convert_to_hw_regs()
2012 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
2013 for (int i
= 0; i
< 3; i
++) {
2014 class src_reg
&src
= inst
->src
[i
];
2018 reg
= byte_offset(brw_vecn_grf(4, src
.nr
, 0), src
.offset
);
2019 reg
.type
= src
.type
;
2021 reg
.negate
= src
.negate
;
2026 reg
= stride(byte_offset(brw_vec4_grf(
2027 prog_data
->base
.dispatch_grf_start_reg
+
2028 src
.nr
/ 2, src
.nr
% 2 * 4),
2031 reg
.type
= src
.type
;
2033 reg
.negate
= src
.negate
;
2035 /* This should have been moved to pull constants. */
2036 assert(!src
.reladdr
);
2041 if (type_sz(src
.type
) == 8) {
2042 reg
= src
.as_brw_reg();
2051 /* Probably unused. */
2052 reg
= brw_null_reg();
2053 reg
= retype(reg
, src
.type
);
2058 unreachable("not reached");
2061 apply_logical_swizzle(®
, inst
, i
);
2064 /* From IVB PRM, vol4, part3, "General Restrictions on Regioning
2067 * "If ExecSize = Width and HorzStride ≠ 0, VertStride must be set
2068 * to Width * HorzStride."
2070 * We can break this rule with DF sources on DF align1
2071 * instructions, because the exec_size would be 4 and width is 4.
2072 * As we know we are not accessing to next GRF, it is safe to
2073 * set vstride to the formula given by the rule itself.
2075 if (is_align1_df(inst
) && (cvt(inst
->exec_size
) - 1) == src
.width
)
2076 src
.vstride
= src
.width
+ src
.hstride
;
2079 if (inst
->is_3src(devinfo
)) {
2080 /* 3-src instructions with scalar sources support arbitrary subnr,
2081 * but don't actually use swizzles. Convert swizzle into subnr.
2082 * Skip this for double-precision instructions: RepCtrl=1 is not
2083 * allowed for them and needs special handling.
2085 for (int i
= 0; i
< 3; i
++) {
2086 if (inst
->src
[i
].vstride
== BRW_VERTICAL_STRIDE_0
&&
2087 type_sz(inst
->src
[i
].type
) < 8) {
2088 assert(brw_is_single_value_swizzle(inst
->src
[i
].swizzle
));
2089 inst
->src
[i
].subnr
+= 4 * BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0);
2094 dst_reg
&dst
= inst
->dst
;
2097 switch (inst
->dst
.file
) {
2099 reg
= byte_offset(brw_vec8_grf(dst
.nr
, 0), dst
.offset
);
2100 reg
.type
= dst
.type
;
2101 reg
.writemask
= dst
.writemask
;
2105 reg
= byte_offset(brw_message_reg(dst
.nr
), dst
.offset
);
2106 assert((reg
.nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
2107 reg
.type
= dst
.type
;
2108 reg
.writemask
= dst
.writemask
;
2113 reg
= dst
.as_brw_reg();
2117 reg
= brw_null_reg();
2118 reg
= retype(reg
, dst
.type
);
2124 unreachable("not reached");
2132 stage_uses_interleaved_attributes(unsigned stage
,
2133 enum shader_dispatch_mode dispatch_mode
)
2136 case MESA_SHADER_TESS_EVAL
:
2138 case MESA_SHADER_GEOMETRY
:
2139 return dispatch_mode
!= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2146 * Get the closest native SIMD width supported by the hardware for instruction
2147 * \p inst. The instruction will be left untouched by
2148 * vec4_visitor::lower_simd_width() if the returned value matches the
2149 * instruction's original execution size.
2152 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
2153 enum shader_dispatch_mode dispatch_mode
,
2154 unsigned stage
, const vec4_instruction
*inst
)
2156 /* Do not split some instructions that require special handling */
2157 switch (inst
->opcode
) {
2158 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2159 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2160 return inst
->exec_size
;
2165 unsigned lowered_width
= MIN2(16, inst
->exec_size
);
2167 /* We need to split some cases of double-precision instructions that write
2168 * 2 registers. We only need to care about this in gen7 because that is the
2169 * only hardware that implements fp64 in Align16.
2171 if (devinfo
->gen
== 7 && inst
->size_written
> REG_SIZE
) {
2172 /* Align16 8-wide double-precision SEL does not work well. Verified
2175 if (inst
->opcode
== BRW_OPCODE_SEL
&& type_sz(inst
->dst
.type
) == 8)
2176 lowered_width
= MIN2(lowered_width
, 4);
2178 /* HSW PRM, 3D Media GPGPU Engine, Region Alignment Rules for Direct
2179 * Register Addressing:
2181 * "When destination spans two registers, the source MUST span two
2184 for (unsigned i
= 0; i
< 3; i
++) {
2185 if (inst
->src
[i
].file
== BAD_FILE
)
2187 if (inst
->size_read(i
) <= REG_SIZE
)
2188 lowered_width
= MIN2(lowered_width
, 4);
2190 /* Interleaved attribute setups use a vertical stride of 0, which
2191 * makes them hit the associated instruction decompression bug in gen7.
2192 * Split them to prevent this.
2194 if (inst
->src
[i
].file
== ATTR
&&
2195 stage_uses_interleaved_attributes(stage
, dispatch_mode
))
2196 lowered_width
= MIN2(lowered_width
, 4);
2200 /* IvyBridge can manage a maximum of 4 DFs per SIMD4x2 instruction, since
2201 * it doesn't support compression in Align16 mode, no matter if it has
2202 * force_writemask_all enabled or disabled (the latter is affected by the
2203 * compressed instruction bug in gen7, which is another reason to enforce
2206 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
2207 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8))
2208 lowered_width
= MIN2(lowered_width
, 4);
2210 return lowered_width
;
2214 dst_src_regions_overlap(vec4_instruction
*inst
)
2216 if (inst
->size_written
== 0)
2219 unsigned dst_start
= inst
->dst
.offset
;
2220 unsigned dst_end
= dst_start
+ inst
->size_written
- 1;
2221 for (int i
= 0; i
< 3; i
++) {
2222 if (inst
->src
[i
].file
== BAD_FILE
)
2225 if (inst
->dst
.file
!= inst
->src
[i
].file
||
2226 inst
->dst
.nr
!= inst
->src
[i
].nr
)
2229 unsigned src_start
= inst
->src
[i
].offset
;
2230 unsigned src_end
= src_start
+ inst
->size_read(i
) - 1;
2232 if ((dst_start
>= src_start
&& dst_start
<= src_end
) ||
2233 (dst_end
>= src_start
&& dst_end
<= src_end
) ||
2234 (dst_start
<= src_start
&& dst_end
>= src_end
)) {
2243 vec4_visitor::lower_simd_width()
2245 bool progress
= false;
2247 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
2248 const unsigned lowered_width
=
2249 get_lowered_simd_width(devinfo
, prog_data
->dispatch_mode
, stage
, inst
);
2250 assert(lowered_width
<= inst
->exec_size
);
2251 if (lowered_width
== inst
->exec_size
)
2254 /* We need to deal with source / destination overlaps when splitting.
2255 * The hardware supports reading from and writing to the same register
2256 * in the same instruction, but we need to be careful that each split
2257 * instruction we produce does not corrupt the source of the next.
2259 * The easiest way to handle this is to make the split instructions write
2260 * to temporaries if there is an src/dst overlap and then move from the
2261 * temporaries to the original destination. We also need to consider
2262 * instructions that do partial writes via align1 opcodes, in which case
2263 * we need to make sure that the we initialize the temporary with the
2264 * value of the instruction's dst.
2266 bool needs_temp
= dst_src_regions_overlap(inst
);
2267 for (unsigned n
= 0; n
< inst
->exec_size
/ lowered_width
; n
++) {
2268 unsigned channel_offset
= lowered_width
* n
;
2270 unsigned size_written
= lowered_width
* type_sz(inst
->dst
.type
);
2272 /* Create the split instruction from the original so that we copy all
2273 * relevant instruction fields, then set the width and calculate the
2274 * new dst/src regions.
2276 vec4_instruction
*linst
= new(mem_ctx
) vec4_instruction(*inst
);
2277 linst
->exec_size
= lowered_width
;
2278 linst
->group
= channel_offset
;
2279 linst
->size_written
= size_written
;
2281 /* Compute split dst region */
2284 unsigned num_regs
= DIV_ROUND_UP(size_written
, REG_SIZE
);
2285 dst
= retype(dst_reg(VGRF
, alloc
.allocate(num_regs
)),
2287 if (inst
->is_align1_partial_write()) {
2288 vec4_instruction
*copy
= MOV(dst
, src_reg(inst
->dst
));
2289 copy
->exec_size
= lowered_width
;
2290 copy
->group
= channel_offset
;
2291 copy
->size_written
= size_written
;
2292 inst
->insert_before(block
, copy
);
2295 dst
= horiz_offset(inst
->dst
, channel_offset
);
2299 /* Compute split source regions */
2300 for (int i
= 0; i
< 3; i
++) {
2301 if (linst
->src
[i
].file
== BAD_FILE
)
2304 bool is_interleaved_attr
=
2305 linst
->src
[i
].file
== ATTR
&&
2306 stage_uses_interleaved_attributes(stage
,
2307 prog_data
->dispatch_mode
);
2309 if (!is_uniform(linst
->src
[i
]) && !is_interleaved_attr
)
2310 linst
->src
[i
] = horiz_offset(linst
->src
[i
], channel_offset
);
2313 inst
->insert_before(block
, linst
);
2315 /* If we used a temporary to store the result of the split
2316 * instruction, copy the result to the original destination
2319 vec4_instruction
*mov
=
2320 MOV(offset(inst
->dst
, lowered_width
, n
), src_reg(dst
));
2321 mov
->exec_size
= lowered_width
;
2322 mov
->group
= channel_offset
;
2323 mov
->size_written
= size_written
;
2324 mov
->predicate
= inst
->predicate
;
2325 inst
->insert_before(block
, mov
);
2329 inst
->remove(block
);
2334 invalidate_live_intervals();
2339 static brw_predicate
2340 scalarize_predicate(brw_predicate predicate
, unsigned writemask
)
2342 if (predicate
!= BRW_PREDICATE_NORMAL
)
2345 switch (writemask
) {
2347 return BRW_PREDICATE_ALIGN16_REPLICATE_X
;
2349 return BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
2351 return BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
2353 return BRW_PREDICATE_ALIGN16_REPLICATE_W
;
2355 unreachable("invalid writemask");
2359 /* Gen7 has a hardware decompression bug that we can exploit to represent
2360 * handful of additional swizzles natively.
2363 is_gen7_supported_64bit_swizzle(vec4_instruction
*inst
, unsigned arg
)
2365 switch (inst
->src
[arg
].swizzle
) {
2366 case BRW_SWIZZLE_XXXX
:
2367 case BRW_SWIZZLE_YYYY
:
2368 case BRW_SWIZZLE_ZZZZ
:
2369 case BRW_SWIZZLE_WWWW
:
2370 case BRW_SWIZZLE_XYXY
:
2371 case BRW_SWIZZLE_YXYX
:
2372 case BRW_SWIZZLE_ZWZW
:
2373 case BRW_SWIZZLE_WZWZ
:
2380 /* 64-bit sources use regions with a width of 2. These 2 elements in each row
2381 * can be addressed using 32-bit swizzles (which is what the hardware supports)
2382 * but it also means that the swizzle we apply on the first two components of a
2383 * dvec4 is coupled with the swizzle we use for the last 2. In other words,
2384 * only some specific swizzle combinations can be natively supported.
2386 * FIXME: we can go an step further and implement even more swizzle
2387 * variations using only partial scalarization.
2389 * For more details see:
2390 * https://bugs.freedesktop.org/show_bug.cgi?id=92760#c82
2393 vec4_visitor::is_supported_64bit_region(vec4_instruction
*inst
, unsigned arg
)
2395 const src_reg
&src
= inst
->src
[arg
];
2396 assert(type_sz(src
.type
) == 8);
2398 /* Uniform regions have a vstride=0. Because we use 2-wide rows with
2399 * 64-bit regions it means that we cannot access components Z/W, so
2400 * return false for any such case. Interleaved attributes will also be
2401 * mapped to GRF registers with a vstride of 0, so apply the same
2404 if ((is_uniform(src
) ||
2405 (stage_uses_interleaved_attributes(stage
, prog_data
->dispatch_mode
) &&
2406 src
.file
== ATTR
)) &&
2407 (brw_mask_for_swizzle(src
.swizzle
) & 12))
2410 switch (src
.swizzle
) {
2411 case BRW_SWIZZLE_XYZW
:
2412 case BRW_SWIZZLE_XXZZ
:
2413 case BRW_SWIZZLE_YYWW
:
2414 case BRW_SWIZZLE_YXWZ
:
2417 return devinfo
->gen
== 7 && is_gen7_supported_64bit_swizzle(inst
, arg
);
2422 vec4_visitor::scalarize_df()
2424 bool progress
= false;
2426 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
2427 /* Skip DF instructions that operate in Align1 mode */
2428 if (is_align1_df(inst
))
2431 /* Check if this is a double-precision instruction */
2432 bool is_double
= type_sz(inst
->dst
.type
) == 8;
2433 for (int arg
= 0; !is_double
&& arg
< 3; arg
++) {
2434 is_double
= inst
->src
[arg
].file
!= BAD_FILE
&&
2435 type_sz(inst
->src
[arg
].type
) == 8;
2441 /* Skip the lowering for specific regioning scenarios that we can
2444 bool skip_lowering
= true;
2446 /* XY and ZW writemasks operate in 32-bit, which means that they don't
2447 * have a native 64-bit representation and they should always be split.
2449 if (inst
->dst
.writemask
== WRITEMASK_XY
||
2450 inst
->dst
.writemask
== WRITEMASK_ZW
) {
2451 skip_lowering
= false;
2453 for (unsigned i
= 0; i
< 3; i
++) {
2454 if (inst
->src
[i
].file
== BAD_FILE
|| type_sz(inst
->src
[i
].type
) < 8)
2456 skip_lowering
= skip_lowering
&& is_supported_64bit_region(inst
, i
);
2463 /* Generate scalar instructions for each enabled channel */
2464 for (unsigned chan
= 0; chan
< 4; chan
++) {
2465 unsigned chan_mask
= 1 << chan
;
2466 if (!(inst
->dst
.writemask
& chan_mask
))
2469 vec4_instruction
*scalar_inst
= new(mem_ctx
) vec4_instruction(*inst
);
2471 for (unsigned i
= 0; i
< 3; i
++) {
2472 unsigned swz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, chan
);
2473 scalar_inst
->src
[i
].swizzle
= BRW_SWIZZLE4(swz
, swz
, swz
, swz
);
2476 scalar_inst
->dst
.writemask
= chan_mask
;
2478 if (inst
->predicate
!= BRW_PREDICATE_NONE
) {
2479 scalar_inst
->predicate
=
2480 scalarize_predicate(inst
->predicate
, chan_mask
);
2483 inst
->insert_before(block
, scalar_inst
);
2486 inst
->remove(block
);
2491 invalidate_live_intervals();
2497 vec4_visitor::lower_64bit_mad_to_mul_add()
2499 bool progress
= false;
2501 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
2502 if (inst
->opcode
!= BRW_OPCODE_MAD
)
2505 if (type_sz(inst
->dst
.type
) != 8)
2508 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
2510 /* Use the copy constructor so we copy all relevant instruction fields
2511 * from the original mad into the add and mul instructions
2513 vec4_instruction
*mul
= new(mem_ctx
) vec4_instruction(*inst
);
2514 mul
->opcode
= BRW_OPCODE_MUL
;
2516 mul
->src
[0] = inst
->src
[1];
2517 mul
->src
[1] = inst
->src
[2];
2518 mul
->src
[2].file
= BAD_FILE
;
2520 vec4_instruction
*add
= new(mem_ctx
) vec4_instruction(*inst
);
2521 add
->opcode
= BRW_OPCODE_ADD
;
2522 add
->src
[0] = src_reg(mul_dst
);
2523 add
->src
[1] = inst
->src
[0];
2524 add
->src
[2].file
= BAD_FILE
;
2526 inst
->insert_before(block
, mul
);
2527 inst
->insert_before(block
, add
);
2528 inst
->remove(block
);
2534 invalidate_live_intervals();
2539 /* The align16 hardware can only do 32-bit swizzle channels, so we need to
2540 * translate the logical 64-bit swizzle channels that we use in the Vec4 IR
2541 * to 32-bit swizzle channels in hardware registers.
2543 * @inst and @arg identify the original vec4 IR source operand we need to
2544 * translate the swizzle for and @hw_reg is the hardware register where we
2545 * will write the hardware swizzle to use.
2547 * This pass assumes that Align16/DF instructions have been fully scalarized
2548 * previously so there is just one 64-bit swizzle channel to deal with for any
2549 * given Vec4 IR source.
2552 vec4_visitor::apply_logical_swizzle(struct brw_reg
*hw_reg
,
2553 vec4_instruction
*inst
, int arg
)
2555 src_reg reg
= inst
->src
[arg
];
2557 if (reg
.file
== BAD_FILE
|| reg
.file
== BRW_IMMEDIATE_VALUE
)
2560 /* If this is not a 64-bit operand or this is a scalar instruction we don't
2561 * need to do anything about the swizzles.
2563 if(type_sz(reg
.type
) < 8 || is_align1_df(inst
)) {
2564 hw_reg
->swizzle
= reg
.swizzle
;
2568 /* Take the 64-bit logical swizzle channel and translate it to 32-bit */
2569 assert(brw_is_single_value_swizzle(reg
.swizzle
) ||
2570 is_supported_64bit_region(inst
, arg
));
2572 /* Apply the region <2, 2, 1> for GRF or <0, 2, 1> for uniforms, as align16
2573 * HW can only do 32-bit swizzle channels.
2575 hw_reg
->width
= BRW_WIDTH_2
;
2577 if (is_supported_64bit_region(inst
, arg
) &&
2578 !is_gen7_supported_64bit_swizzle(inst
, arg
)) {
2579 /* Supported 64-bit swizzles are those such that their first two
2580 * components, when expanded to 32-bit swizzles, match the semantics
2581 * of the original 64-bit swizzle with 2-wide row regioning.
2583 unsigned swizzle0
= BRW_GET_SWZ(reg
.swizzle
, 0);
2584 unsigned swizzle1
= BRW_GET_SWZ(reg
.swizzle
, 1);
2585 hw_reg
->swizzle
= BRW_SWIZZLE4(swizzle0
* 2, swizzle0
* 2 + 1,
2586 swizzle1
* 2, swizzle1
* 2 + 1);
2588 /* If we got here then we have one of the following:
2590 * 1. An unsupported swizzle, which should be single-value thanks to the
2591 * scalarization pass.
2593 * 2. A gen7 supported swizzle. These can be single-value or double-value
2594 * swizzles. If the latter, they are never cross-dvec2 channels. For
2595 * these we always need to activate the gen7 vstride=0 exploit.
2597 unsigned swizzle0
= BRW_GET_SWZ(reg
.swizzle
, 0);
2598 unsigned swizzle1
= BRW_GET_SWZ(reg
.swizzle
, 1);
2599 assert((swizzle0
< 2) == (swizzle1
< 2));
2601 /* To gain access to Z/W components we need to select the second half
2602 * of the register and then use a X/Y swizzle to select Z/W respectively.
2604 if (swizzle0
>= 2) {
2605 *hw_reg
= suboffset(*hw_reg
, 2);
2610 /* All gen7-specific supported swizzles require the vstride=0 exploit */
2611 if (devinfo
->gen
== 7 && is_gen7_supported_64bit_swizzle(inst
, arg
))
2612 hw_reg
->vstride
= BRW_VERTICAL_STRIDE_0
;
2614 /* Any 64-bit source with an offset at 16B is intended to address the
2615 * second half of a register and needs a vertical stride of 0 so we:
2617 * 1. Don't violate register region restrictions.
2618 * 2. Activate the gen7 instruction decompresion bug exploit when
2621 if (hw_reg
->subnr
% REG_SIZE
== 16) {
2622 assert(devinfo
->gen
== 7);
2623 hw_reg
->vstride
= BRW_VERTICAL_STRIDE_0
;
2626 hw_reg
->swizzle
= BRW_SWIZZLE4(swizzle0
* 2, swizzle0
* 2 + 1,
2627 swizzle1
* 2, swizzle1
* 2 + 1);
2634 if (shader_time_index
>= 0)
2635 emit_shader_time_begin();
2648 /* Before any optimization, push array accesses out to scratch
2649 * space where we need them to be. This pass may allocate new
2650 * virtual GRFs, so we want to do it early. It also makes sure
2651 * that we have reladdr computations available for CSE, since we'll
2652 * often do repeated subexpressions for those.
2654 move_grf_array_access_to_scratch();
2655 move_uniform_array_access_to_pull_constants();
2657 pack_uniform_registers();
2658 move_push_constants_to_pull_constants();
2659 split_virtual_grfs();
2661 #define OPT(pass, args...) ({ \
2663 bool this_progress = pass(args); \
2665 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
2666 char filename[64]; \
2667 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
2668 stage_abbrev, nir->info.name, iteration, pass_num); \
2670 backend_shader::dump_instructions(filename); \
2673 progress = progress || this_progress; \
2678 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
2680 snprintf(filename
, 64, "%s-%s-00-00-start",
2681 stage_abbrev
, nir
->info
.name
);
2683 backend_shader::dump_instructions(filename
);
2694 OPT(opt_predicated_break
, this);
2695 OPT(opt_reduce_swizzle
);
2696 OPT(dead_code_eliminate
);
2697 OPT(dead_control_flow_eliminate
, this);
2698 OPT(opt_copy_propagation
);
2699 OPT(opt_cmod_propagation
);
2702 OPT(opt_register_coalesce
);
2703 OPT(eliminate_find_live_channel
);
2708 if (OPT(opt_vector_float
)) {
2710 OPT(opt_copy_propagation
, false);
2711 OPT(opt_copy_propagation
, true);
2712 OPT(dead_code_eliminate
);
2715 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
2716 OPT(opt_cmod_propagation
);
2718 OPT(opt_copy_propagation
);
2719 OPT(dead_code_eliminate
);
2722 if (OPT(lower_simd_width
)) {
2723 OPT(opt_copy_propagation
);
2724 OPT(dead_code_eliminate
);
2730 OPT(lower_64bit_mad_to_mul_add
);
2732 /* Run this before payload setup because tesselation shaders
2733 * rely on it to prevent cross dvec2 regioning on DF attributes
2734 * that are setup so that XY are on the second half of register and
2735 * ZW are in the first half of the next.
2741 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
2742 /* Debug of register spilling: Go spill everything. */
2743 const int grf_count
= alloc
.count
;
2744 float spill_costs
[alloc
.count
];
2745 bool no_spill
[alloc
.count
];
2746 evaluate_spill_costs(spill_costs
, no_spill
);
2747 for (int i
= 0; i
< grf_count
; i
++) {
2753 /* We want to run this after spilling because 64-bit (un)spills need to
2754 * emit code to shuffle 64-bit data for the 32-bit scratch read/write
2755 * messages that can produce unsupported 64-bit swizzle regions.
2760 fixup_3src_null_dest();
2762 bool allocated_without_spills
= reg_allocate();
2764 if (!allocated_without_spills
) {
2765 compiler
->shader_perf_log(log_data
,
2766 "%s shader triggered register spilling. "
2767 "Try reducing the number of live vec4 values "
2768 "to improve performance.\n",
2771 while (!reg_allocate()) {
2776 /* We want to run this after spilling because 64-bit (un)spills need to
2777 * emit code to shuffle 64-bit data for the 32-bit scratch read/write
2778 * messages that can produce unsupported 64-bit swizzle regions.
2783 opt_schedule_instructions();
2785 opt_set_dependency_control();
2787 convert_to_hw_regs();
2789 if (last_scratch
> 0) {
2790 prog_data
->base
.total_scratch
=
2791 brw_get_scratch_size(last_scratch
* REG_SIZE
);
2797 } /* namespace brw */
2802 * Compile a vertex shader.
2804 * Returns the final assembly and the program's size.
2807 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
2809 const struct brw_vs_prog_key
*key
,
2810 struct brw_vs_prog_data
*prog_data
,
2811 const nir_shader
*src_shader
,
2812 int shader_time_index
,
2815 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_VERTEX
];
2816 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
2817 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, is_scalar
);
2819 const unsigned *assembly
= NULL
;
2821 if (prog_data
->base
.vue_map
.varying_to_slot
[VARYING_SLOT_EDGE
] != -1) {
2822 /* If the output VUE map contains VARYING_SLOT_EDGE then we need to copy
2823 * the edge flag from VERT_ATTRIB_EDGEFLAG. This will be done
2824 * automatically by brw_vec4_visitor::emit_urb_slot but we need to
2825 * ensure that prog_data->inputs_read is accurate.
2827 * In order to make late NIR passes aware of the change, we actually
2828 * whack shader->info.inputs_read instead. This is safe because we just
2829 * made a copy of the shader.
2832 assert(key
->copy_edgeflag
);
2833 shader
->info
.inputs_read
|= VERT_BIT_EDGEFLAG
;
2836 prog_data
->inputs_read
= shader
->info
.inputs_read
;
2837 prog_data
->double_inputs_read
= shader
->info
.vs
.double_inputs
;
2839 brw_nir_lower_vs_inputs(shader
, key
->gl_attrib_wa_flags
);
2840 brw_nir_lower_vue_outputs(shader
);
2841 shader
= brw_postprocess_nir(shader
, compiler
, is_scalar
);
2843 prog_data
->base
.clip_distance_mask
=
2844 ((1 << shader
->info
.clip_distance_array_size
) - 1);
2845 prog_data
->base
.cull_distance_mask
=
2846 ((1 << shader
->info
.cull_distance_array_size
) - 1) <<
2847 shader
->info
.clip_distance_array_size
;
2849 unsigned nr_attribute_slots
= util_bitcount64(prog_data
->inputs_read
);
2851 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
2852 * incoming vertex attribute. So, add an extra slot.
2854 if (shader
->info
.system_values_read
&
2855 (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX
) |
2856 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
2857 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
2858 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
2859 nr_attribute_slots
++;
2862 /* gl_DrawID and IsIndexedDraw share its very own vec4 */
2863 if (shader
->info
.system_values_read
&
2864 (BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
) |
2865 BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW
))) {
2866 nr_attribute_slots
++;
2869 if (shader
->info
.system_values_read
&
2870 BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW
))
2871 prog_data
->uses_is_indexed_draw
= true;
2873 if (shader
->info
.system_values_read
&
2874 BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX
))
2875 prog_data
->uses_firstvertex
= true;
2877 if (shader
->info
.system_values_read
&
2878 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
))
2879 prog_data
->uses_baseinstance
= true;
2881 if (shader
->info
.system_values_read
&
2882 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
))
2883 prog_data
->uses_vertexid
= true;
2885 if (shader
->info
.system_values_read
&
2886 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))
2887 prog_data
->uses_instanceid
= true;
2889 if (shader
->info
.system_values_read
&
2890 BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
))
2891 prog_data
->uses_drawid
= true;
2893 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
2894 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
2895 * vec4 mode, the hardware appears to wedge unless we read something.
2898 prog_data
->base
.urb_read_length
=
2899 DIV_ROUND_UP(nr_attribute_slots
, 2);
2901 prog_data
->base
.urb_read_length
=
2902 DIV_ROUND_UP(MAX2(nr_attribute_slots
, 1), 2);
2904 prog_data
->nr_attribute_slots
= nr_attribute_slots
;
2906 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
2907 * (overwriting the original contents), we need to make sure the size is
2908 * the larger of the two.
2910 const unsigned vue_entries
=
2911 MAX2(nr_attribute_slots
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
2913 if (compiler
->devinfo
->gen
== 6) {
2914 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
2916 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
2917 /* On Cannonlake software shall not program an allocation size that
2918 * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
2920 if (compiler
->devinfo
->gen
== 10 &&
2921 prog_data
->base
.urb_entry_size
% 3 == 0)
2922 prog_data
->base
.urb_entry_size
++;
2925 if (INTEL_DEBUG
& DEBUG_VS
) {
2926 fprintf(stderr
, "VS Output ");
2927 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
2931 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
2933 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
2934 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
2935 shader
, 8, shader_time_index
);
2938 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2943 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
2945 fs_generator
g(compiler
, log_data
, mem_ctx
,
2946 &prog_data
->base
.base
, v
.promoted_constants
,
2947 v
.runtime_check_aads_emit
, MESA_SHADER_VERTEX
);
2948 if (INTEL_DEBUG
& DEBUG_VS
) {
2949 const char *debug_name
=
2950 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
2951 shader
->info
.label
? shader
->info
.label
:
2955 g
.enable_debug(debug_name
);
2957 g
.generate_code(v
.cfg
, 8);
2958 assembly
= g
.get_assembly();
2962 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2964 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2965 shader
, mem_ctx
, shader_time_index
);
2968 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2973 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
2974 shader
, &prog_data
->base
, v
.cfg
);