2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_vec4_builder.h"
29 #include "brw_vec4_live_variables.h"
30 #include "brw_vec4_vs.h"
31 #include "brw_dead_control_flow.h"
32 #include "common/gen_debug.h"
33 #include "program/prog_parameter.h"
35 #define MAX_INSTRUCTION (1 << 30)
44 memset(this, 0, sizeof(*this));
45 this->file
= BAD_FILE
;
46 this->type
= BRW_REGISTER_TYPE_UD
;
49 src_reg::src_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
)
55 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
56 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
58 this->swizzle
= BRW_SWIZZLE_XYZW
;
60 this->type
= brw_type_for_base_type(type
);
63 /** Generic unset register constructor. */
69 src_reg::src_reg(struct ::brw_reg reg
) :
76 src_reg::src_reg(const dst_reg
®
) :
79 this->reladdr
= reg
.reladdr
;
80 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
86 memset(this, 0, sizeof(*this));
87 this->file
= BAD_FILE
;
88 this->type
= BRW_REGISTER_TYPE_UD
;
89 this->writemask
= WRITEMASK_XYZW
;
97 dst_reg::dst_reg(enum brw_reg_file file
, int nr
)
105 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
,
112 this->type
= brw_type_for_base_type(type
);
113 this->writemask
= writemask
;
116 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, brw_reg_type type
,
124 this->writemask
= writemask
;
127 dst_reg::dst_reg(struct ::brw_reg reg
) :
131 this->reladdr
= NULL
;
134 dst_reg::dst_reg(const src_reg
®
) :
137 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
138 this->reladdr
= reg
.reladdr
;
142 dst_reg::equals(const dst_reg
&r
) const
144 return (this->backend_reg::equals(r
) &&
145 (reladdr
== r
.reladdr
||
146 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))));
150 vec4_instruction::is_send_from_grf()
153 case SHADER_OPCODE_SHADER_TIME_ADD
:
154 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
155 case SHADER_OPCODE_UNTYPED_ATOMIC
:
156 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
157 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
158 case SHADER_OPCODE_TYPED_ATOMIC
:
159 case SHADER_OPCODE_TYPED_SURFACE_READ
:
160 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
161 case VEC4_OPCODE_URB_READ
:
162 case TCS_OPCODE_URB_WRITE
:
163 case TCS_OPCODE_RELEASE_INPUT
:
164 case SHADER_OPCODE_BARRIER
:
172 * Returns true if this instruction's sources and destinations cannot
173 * safely be the same register.
175 * In most cases, a register can be written over safely by the same
176 * instruction that is its last use. For a single instruction, the
177 * sources are dereferenced before writing of the destination starts
180 * However, there are a few cases where this can be problematic:
182 * - Virtual opcodes that translate to multiple instructions in the
183 * code generator: if src == dst and one instruction writes the
184 * destination before a later instruction reads the source, then
185 * src will have been clobbered.
187 * The register allocator uses this information to set up conflicts between
188 * GRF sources and the destination.
191 vec4_instruction::has_source_and_destination_hazard() const
194 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
195 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
196 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
199 /* 8-wide compressed DF operations are executed as two 4-wide operations,
200 * so we have a src/dst hazard if the first half of the instruction
201 * overwrites the source of the second half. Prevent this by marking
202 * compressed instructions as having src/dst hazards, so the register
203 * allocator assigns safe register regions for dst and srcs.
205 return size_written
> REG_SIZE
;
210 vec4_instruction::size_read(unsigned arg
) const
213 case SHADER_OPCODE_SHADER_TIME_ADD
:
214 case SHADER_OPCODE_UNTYPED_ATOMIC
:
215 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
216 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
217 case SHADER_OPCODE_TYPED_ATOMIC
:
218 case SHADER_OPCODE_TYPED_SURFACE_READ
:
219 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
220 case TCS_OPCODE_URB_WRITE
:
222 return mlen
* REG_SIZE
;
224 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
226 return mlen
* REG_SIZE
;
232 switch (src
[arg
].file
) {
237 return 4 * type_sz(src
[arg
].type
);
239 /* XXX - Represent actual vertical stride. */
240 return exec_size
* type_sz(src
[arg
].type
);
245 vec4_instruction::can_do_source_mods(const struct gen_device_info
*devinfo
)
247 if (devinfo
->gen
== 6 && is_math())
250 if (is_send_from_grf())
253 if (!backend_instruction::can_do_source_mods())
260 vec4_instruction::can_do_writemask(const struct gen_device_info
*devinfo
)
263 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
264 case VEC4_OPCODE_DOUBLE_TO_F32
:
265 case VEC4_OPCODE_DOUBLE_TO_D32
:
266 case VEC4_OPCODE_DOUBLE_TO_U32
:
267 case VEC4_OPCODE_TO_DOUBLE
:
268 case VEC4_OPCODE_PICK_LOW_32BIT
:
269 case VEC4_OPCODE_PICK_HIGH_32BIT
:
270 case VEC4_OPCODE_SET_LOW_32BIT
:
271 case VEC4_OPCODE_SET_HIGH_32BIT
:
272 case VS_OPCODE_PULL_CONSTANT_LOAD
:
273 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
274 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
275 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
276 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
277 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
278 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
279 case VEC4_OPCODE_URB_READ
:
280 case SHADER_OPCODE_MOV_INDIRECT
:
283 /* The MATH instruction on Gen6 only executes in align1 mode, which does
284 * not support writemasking.
286 if (devinfo
->gen
== 6 && is_math())
297 vec4_instruction::can_change_types() const
299 return dst
.type
== src
[0].type
&&
300 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
301 (opcode
== BRW_OPCODE_MOV
||
302 (opcode
== BRW_OPCODE_SEL
&&
303 dst
.type
== src
[1].type
&&
304 predicate
!= BRW_PREDICATE_NONE
&&
305 !src
[1].abs
&& !src
[1].negate
));
309 * Returns how many MRFs an opcode will write over.
311 * Note that this is not the 0 or 1 implied writes in an actual gen
312 * instruction -- the generate_* functions generate additional MOVs
316 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
318 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
321 switch (inst
->opcode
) {
322 case SHADER_OPCODE_RCP
:
323 case SHADER_OPCODE_RSQ
:
324 case SHADER_OPCODE_SQRT
:
325 case SHADER_OPCODE_EXP2
:
326 case SHADER_OPCODE_LOG2
:
327 case SHADER_OPCODE_SIN
:
328 case SHADER_OPCODE_COS
:
330 case SHADER_OPCODE_INT_QUOTIENT
:
331 case SHADER_OPCODE_INT_REMAINDER
:
332 case SHADER_OPCODE_POW
:
333 case TCS_OPCODE_THREAD_END
:
335 case VS_OPCODE_URB_WRITE
:
337 case VS_OPCODE_PULL_CONSTANT_LOAD
:
339 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
341 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
343 case GS_OPCODE_URB_WRITE
:
344 case GS_OPCODE_URB_WRITE_ALLOCATE
:
345 case GS_OPCODE_THREAD_END
:
347 case GS_OPCODE_FF_SYNC
:
349 case TCS_OPCODE_URB_WRITE
:
351 case SHADER_OPCODE_SHADER_TIME_ADD
:
353 case SHADER_OPCODE_TEX
:
354 case SHADER_OPCODE_TXL
:
355 case SHADER_OPCODE_TXD
:
356 case SHADER_OPCODE_TXF
:
357 case SHADER_OPCODE_TXF_CMS
:
358 case SHADER_OPCODE_TXF_CMS_W
:
359 case SHADER_OPCODE_TXF_MCS
:
360 case SHADER_OPCODE_TXS
:
361 case SHADER_OPCODE_TG4
:
362 case SHADER_OPCODE_TG4_OFFSET
:
363 case SHADER_OPCODE_SAMPLEINFO
:
364 case SHADER_OPCODE_GET_BUFFER_SIZE
:
365 return inst
->header_size
;
367 unreachable("not reached");
372 src_reg::equals(const src_reg
&r
) const
374 return (this->backend_reg::equals(r
) &&
375 !reladdr
&& !r
.reladdr
);
379 src_reg::negative_equals(const src_reg
&r
) const
381 return this->backend_reg::negative_equals(r
) &&
382 !reladdr
&& !r
.reladdr
;
386 vec4_visitor::opt_vector_float()
388 bool progress
= false;
390 foreach_block(block
, cfg
) {
391 int last_reg
= -1, last_offset
= -1;
392 enum brw_reg_file last_reg_file
= BAD_FILE
;
394 uint8_t imm
[4] = { 0 };
396 vec4_instruction
*imm_inst
[4];
397 unsigned writemask
= 0;
398 enum brw_reg_type dest_type
= BRW_REGISTER_TYPE_F
;
400 foreach_inst_in_block_safe(vec4_instruction
, inst
, block
) {
402 enum brw_reg_type need_type
;
404 /* Look for unconditional MOVs from an immediate with a partial
405 * writemask. Skip type-conversion MOVs other than integer 0,
406 * where the type doesn't matter. See if the immediate can be
407 * represented as a VF.
409 if (inst
->opcode
== BRW_OPCODE_MOV
&&
410 inst
->src
[0].file
== IMM
&&
411 inst
->predicate
== BRW_PREDICATE_NONE
&&
412 inst
->dst
.writemask
!= WRITEMASK_XYZW
&&
413 type_sz(inst
->src
[0].type
) < 8 &&
414 (inst
->src
[0].type
== inst
->dst
.type
|| inst
->src
[0].d
== 0)) {
416 vf
= brw_float_to_vf(inst
->src
[0].d
);
417 need_type
= BRW_REGISTER_TYPE_D
;
420 vf
= brw_float_to_vf(inst
->src
[0].f
);
421 need_type
= BRW_REGISTER_TYPE_F
;
427 /* If this wasn't a MOV, or the destination register doesn't match,
428 * or we have to switch destination types, then this breaks our
429 * sequence. Combine anything we've accumulated so far.
431 if (last_reg
!= inst
->dst
.nr
||
432 last_offset
!= inst
->dst
.offset
||
433 last_reg_file
!= inst
->dst
.file
||
434 (vf
> 0 && dest_type
!= need_type
)) {
436 if (inst_count
> 1) {
438 memcpy(&vf
, imm
, sizeof(vf
));
439 vec4_instruction
*mov
= MOV(imm_inst
[0]->dst
, brw_imm_vf(vf
));
440 mov
->dst
.type
= dest_type
;
441 mov
->dst
.writemask
= writemask
;
442 inst
->insert_before(block
, mov
);
444 for (int i
= 0; i
< inst_count
; i
++) {
445 imm_inst
[i
]->remove(block
);
454 dest_type
= BRW_REGISTER_TYPE_F
;
456 for (int i
= 0; i
< 4; i
++) {
461 /* Record this instruction's value (if it was representable). */
463 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
465 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
467 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
469 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
472 writemask
|= inst
->dst
.writemask
;
473 imm_inst
[inst_count
++] = inst
;
475 last_reg
= inst
->dst
.nr
;
476 last_offset
= inst
->dst
.offset
;
477 last_reg_file
= inst
->dst
.file
;
479 dest_type
= need_type
;
485 invalidate_live_intervals();
490 /* Replaces unused channels of a swizzle with channels that are used.
492 * For instance, this pass transforms
494 * mov vgrf4.yz, vgrf5.wxzy
498 * mov vgrf4.yz, vgrf5.xxzx
500 * This eliminates false uses of some channels, letting dead code elimination
501 * remove the instructions that wrote them.
504 vec4_visitor::opt_reduce_swizzle()
506 bool progress
= false;
508 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
509 if (inst
->dst
.file
== BAD_FILE
||
510 inst
->dst
.file
== ARF
||
511 inst
->dst
.file
== FIXED_GRF
||
512 inst
->is_send_from_grf())
517 /* Determine which channels of the sources are read. */
518 switch (inst
->opcode
) {
519 case VEC4_OPCODE_PACK_BYTES
:
521 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
522 * but all four of src1.
524 swizzle
= brw_swizzle_for_size(4);
527 swizzle
= brw_swizzle_for_size(3);
530 swizzle
= brw_swizzle_for_size(2);
533 case VEC4_OPCODE_TO_DOUBLE
:
534 case VEC4_OPCODE_DOUBLE_TO_F32
:
535 case VEC4_OPCODE_DOUBLE_TO_D32
:
536 case VEC4_OPCODE_DOUBLE_TO_U32
:
537 case VEC4_OPCODE_PICK_LOW_32BIT
:
538 case VEC4_OPCODE_PICK_HIGH_32BIT
:
539 case VEC4_OPCODE_SET_LOW_32BIT
:
540 case VEC4_OPCODE_SET_HIGH_32BIT
:
541 swizzle
= brw_swizzle_for_size(4);
545 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
549 /* Update sources' swizzles. */
550 for (int i
= 0; i
< 3; i
++) {
551 if (inst
->src
[i
].file
!= VGRF
&&
552 inst
->src
[i
].file
!= ATTR
&&
553 inst
->src
[i
].file
!= UNIFORM
)
556 const unsigned new_swizzle
=
557 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
558 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
559 inst
->src
[i
].swizzle
= new_swizzle
;
566 invalidate_live_intervals();
572 vec4_visitor::split_uniform_registers()
574 /* Prior to this, uniforms have been in an array sized according to
575 * the number of vector uniforms present, sparsely filled (so an
576 * aggregate results in reg indices being skipped over). Now we're
577 * going to cut those aggregates up so each .nr index is one
578 * vector. The goal is to make elimination of unused uniform
579 * components easier later.
581 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
582 for (int i
= 0 ; i
< 3; i
++) {
583 if (inst
->src
[i
].file
!= UNIFORM
)
586 assert(!inst
->src
[i
].reladdr
);
588 inst
->src
[i
].nr
+= inst
->src
[i
].offset
/ 16;
589 inst
->src
[i
].offset
%= 16;
594 /* This function returns the register number where we placed the uniform */
596 set_push_constant_loc(const int nr_uniforms
, int *new_uniform_count
,
597 const int src
, const int size
, const int channel_size
,
598 int *new_loc
, int *new_chan
,
602 /* Find the lowest place we can slot this uniform in. */
603 for (dst
= 0; dst
< nr_uniforms
; dst
++) {
604 if (ALIGN(new_chans_used
[dst
], channel_size
) + size
<= 4)
608 assert(dst
< nr_uniforms
);
611 new_chan
[src
] = ALIGN(new_chans_used
[dst
], channel_size
);
612 new_chans_used
[dst
] = ALIGN(new_chans_used
[dst
], channel_size
) + size
;
614 *new_uniform_count
= MAX2(*new_uniform_count
, dst
+ 1);
619 vec4_visitor::pack_uniform_registers()
621 uint8_t chans_used
[this->uniforms
];
622 int new_loc
[this->uniforms
];
623 int new_chan
[this->uniforms
];
624 bool is_aligned_to_dvec4
[this->uniforms
];
625 int new_chans_used
[this->uniforms
];
626 int channel_sizes
[this->uniforms
];
628 memset(chans_used
, 0, sizeof(chans_used
));
629 memset(new_loc
, 0, sizeof(new_loc
));
630 memset(new_chan
, 0, sizeof(new_chan
));
631 memset(new_chans_used
, 0, sizeof(new_chans_used
));
632 memset(is_aligned_to_dvec4
, 0, sizeof(is_aligned_to_dvec4
));
633 memset(channel_sizes
, 0, sizeof(channel_sizes
));
635 /* Find which uniform vectors are actually used by the program. We
636 * expect unused vector elements when we've moved array access out
637 * to pull constants, and from some GLSL code generators like wine.
639 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
641 switch (inst
->opcode
) {
642 case VEC4_OPCODE_PACK_BYTES
:
654 readmask
= inst
->dst
.writemask
;
658 for (int i
= 0 ; i
< 3; i
++) {
659 if (inst
->src
[i
].file
!= UNIFORM
)
662 assert(type_sz(inst
->src
[i
].type
) % 4 == 0);
663 int channel_size
= type_sz(inst
->src
[i
].type
) / 4;
665 int reg
= inst
->src
[i
].nr
;
666 for (int c
= 0; c
< 4; c
++) {
667 if (!(readmask
& (1 << c
)))
670 unsigned channel
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1;
671 unsigned used
= MAX2(chans_used
[reg
], channel
* channel_size
);
673 chans_used
[reg
] = used
;
674 channel_sizes
[reg
] = MAX2(channel_sizes
[reg
], channel_size
);
676 is_aligned_to_dvec4
[reg
] = true;
677 is_aligned_to_dvec4
[reg
+ 1] = true;
678 chans_used
[reg
+ 1] = used
- 4;
679 channel_sizes
[reg
+ 1] = MAX2(channel_sizes
[reg
+ 1], channel_size
);
684 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
685 inst
->src
[0].file
== UNIFORM
) {
686 assert(inst
->src
[2].file
== BRW_IMMEDIATE_VALUE
);
687 assert(inst
->src
[0].subnr
== 0);
689 unsigned bytes_read
= inst
->src
[2].ud
;
690 assert(bytes_read
% 4 == 0);
691 unsigned vec4s_read
= DIV_ROUND_UP(bytes_read
, 16);
693 /* We just mark every register touched by a MOV_INDIRECT as being
694 * fully used. This ensures that it doesn't broken up piecewise by
695 * the next part of our packing algorithm.
697 int reg
= inst
->src
[0].nr
;
698 for (unsigned i
= 0; i
< vec4s_read
; i
++)
699 chans_used
[reg
+ i
] = 4;
703 int new_uniform_count
= 0;
705 /* As the uniforms are going to be reordered, take the data from a temporary
706 * copy of the original param[].
708 uint32_t *param
= ralloc_array(NULL
, uint32_t, stage_prog_data
->nr_params
);
709 memcpy(param
, stage_prog_data
->param
,
710 sizeof(uint32_t) * stage_prog_data
->nr_params
);
712 /* Now, figure out a packing of the live uniform vectors into our
713 * push constants. Start with dvec{3,4} because they are aligned to
714 * dvec4 size (2 vec4).
716 for (int src
= 0; src
< uniforms
; src
++) {
717 int size
= chans_used
[src
];
719 if (size
== 0 || !is_aligned_to_dvec4
[src
])
722 /* dvec3 are aligned to dvec4 size, apply the alignment of the size
723 * to 4 to avoid moving last component of a dvec3 to the available
724 * location at the end of a previous dvec3. These available locations
725 * could be filled by smaller variables in next loop.
727 size
= ALIGN(size
, 4);
728 int dst
= set_push_constant_loc(uniforms
, &new_uniform_count
,
729 src
, size
, channel_sizes
[src
],
732 /* Move the references to the data */
733 for (int j
= 0; j
< size
; j
++) {
734 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
739 /* Continue with the rest of data, which is aligned to vec4. */
740 for (int src
= 0; src
< uniforms
; src
++) {
741 int size
= chans_used
[src
];
743 if (size
== 0 || is_aligned_to_dvec4
[src
])
746 int dst
= set_push_constant_loc(uniforms
, &new_uniform_count
,
747 src
, size
, channel_sizes
[src
],
750 /* Move the references to the data */
751 for (int j
= 0; j
< size
; j
++) {
752 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
758 this->uniforms
= new_uniform_count
;
760 /* Now, update the instructions for our repacked uniforms. */
761 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
762 for (int i
= 0 ; i
< 3; i
++) {
763 int src
= inst
->src
[i
].nr
;
765 if (inst
->src
[i
].file
!= UNIFORM
)
768 int chan
= new_chan
[src
] / channel_sizes
[src
];
769 inst
->src
[i
].nr
= new_loc
[src
];
770 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(chan
, chan
, chan
, chan
);
776 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
778 * While GLSL IR also performs this optimization, we end up with it in
779 * our instruction stream for a couple of reasons. One is that we
780 * sometimes generate silly instructions, for example in array access
781 * where we'll generate "ADD offset, index, base" even if base is 0.
782 * The other is that GLSL IR's constant propagation doesn't track the
783 * components of aggregates, so some VS patterns (initialize matrix to
784 * 0, accumulate in vertex blending factors) end up breaking down to
785 * instructions involving 0.
788 vec4_visitor::opt_algebraic()
790 bool progress
= false;
792 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
793 switch (inst
->opcode
) {
795 if (inst
->src
[0].file
!= IMM
)
798 if (inst
->saturate
) {
799 if (inst
->dst
.type
!= inst
->src
[0].type
)
800 assert(!"unimplemented: saturate mixed types");
802 if (brw_saturate_immediate(inst
->dst
.type
,
803 &inst
->src
[0].as_brw_reg())) {
804 inst
->saturate
= false;
810 case VEC4_OPCODE_UNPACK_UNIFORM
:
811 if (inst
->src
[0].file
!= UNIFORM
) {
812 inst
->opcode
= BRW_OPCODE_MOV
;
818 if (inst
->src
[1].is_zero()) {
819 inst
->opcode
= BRW_OPCODE_MOV
;
820 inst
->src
[1] = src_reg();
826 if (inst
->src
[1].is_zero()) {
827 inst
->opcode
= BRW_OPCODE_MOV
;
828 switch (inst
->src
[0].type
) {
829 case BRW_REGISTER_TYPE_F
:
830 inst
->src
[0] = brw_imm_f(0.0f
);
832 case BRW_REGISTER_TYPE_D
:
833 inst
->src
[0] = brw_imm_d(0);
835 case BRW_REGISTER_TYPE_UD
:
836 inst
->src
[0] = brw_imm_ud(0u);
839 unreachable("not reached");
841 inst
->src
[1] = src_reg();
843 } else if (inst
->src
[1].is_one()) {
844 inst
->opcode
= BRW_OPCODE_MOV
;
845 inst
->src
[1] = src_reg();
847 } else if (inst
->src
[1].is_negative_one()) {
848 inst
->opcode
= BRW_OPCODE_MOV
;
849 inst
->src
[0].negate
= !inst
->src
[0].negate
;
850 inst
->src
[1] = src_reg();
855 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
857 inst
->src
[0].negate
&&
858 inst
->src
[1].is_zero()) {
859 inst
->src
[0].abs
= false;
860 inst
->src
[0].negate
= false;
861 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
866 case SHADER_OPCODE_BROADCAST
:
867 if (is_uniform(inst
->src
[0]) ||
868 inst
->src
[1].is_zero()) {
869 inst
->opcode
= BRW_OPCODE_MOV
;
870 inst
->src
[1] = src_reg();
871 inst
->force_writemask_all
= true;
882 invalidate_live_intervals();
888 * Only a limited number of hardware registers may be used for push
889 * constants, so this turns access to the overflowed constants into
893 vec4_visitor::move_push_constants_to_pull_constants()
895 int pull_constant_loc
[this->uniforms
];
897 /* Only allow 32 registers (256 uniform components) as push constants,
898 * which is the limit on gen6.
900 * If changing this value, note the limitation about total_regs in
903 int max_uniform_components
= 32 * 8;
904 if (this->uniforms
* 4 <= max_uniform_components
)
907 /* Make some sort of choice as to which uniforms get sent to pull
908 * constants. We could potentially do something clever here like
909 * look for the most infrequently used uniform vec4s, but leave
912 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
913 pull_constant_loc
[i
/ 4] = -1;
915 if (i
>= max_uniform_components
) {
916 uint32_t *values
= &stage_prog_data
->param
[i
];
918 /* Try to find an existing copy of this uniform in the pull
919 * constants if it was part of an array access already.
921 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
924 for (matches
= 0; matches
< 4; matches
++) {
925 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
930 pull_constant_loc
[i
/ 4] = j
/ 4;
935 if (pull_constant_loc
[i
/ 4] == -1) {
936 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
937 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
939 for (int j
= 0; j
< 4; j
++) {
940 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
947 /* Now actually rewrite usage of the things we've moved to pull
950 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
951 for (int i
= 0 ; i
< 3; i
++) {
952 if (inst
->src
[i
].file
!= UNIFORM
||
953 pull_constant_loc
[inst
->src
[i
].nr
] == -1)
956 int uniform
= inst
->src
[i
].nr
;
958 const glsl_type
*temp_type
= type_sz(inst
->src
[i
].type
) == 8 ?
959 glsl_type::dvec4_type
: glsl_type::vec4_type
;
960 dst_reg temp
= dst_reg(this, temp_type
);
962 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
963 pull_constant_loc
[uniform
], src_reg());
965 inst
->src
[i
].file
= temp
.file
;
966 inst
->src
[i
].nr
= temp
.nr
;
967 inst
->src
[i
].offset
%= 16;
968 inst
->src
[i
].reladdr
= NULL
;
972 /* Repack push constants to remove the now-unused ones. */
973 pack_uniform_registers();
976 /* Conditions for which we want to avoid setting the dependency control bits */
978 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
980 #define IS_DWORD(reg) \
981 (reg.type == BRW_REGISTER_TYPE_UD || \
982 reg.type == BRW_REGISTER_TYPE_D)
984 #define IS_64BIT(reg) (reg.file != BAD_FILE && type_sz(reg.type) == 8)
986 /* From the Cherryview and Broadwell PRMs:
988 * "When source or destination datatype is 64b or operation is integer DWord
989 * multiply, DepCtrl must not be used."
991 * SKL PRMs don't include this restriction, however, gen7 seems to be
992 * affected, at least by the 64b restriction, since DepCtrl with double
993 * precision instructions seems to produce GPU hangs in some cases.
995 if (devinfo
->gen
== 8 || gen_device_info_is_9lp(devinfo
)) {
996 if (inst
->opcode
== BRW_OPCODE_MUL
&&
997 IS_DWORD(inst
->src
[0]) &&
998 IS_DWORD(inst
->src
[1]))
1002 if (devinfo
->gen
>= 7 && devinfo
->gen
<= 8) {
1003 if (IS_64BIT(inst
->dst
) || IS_64BIT(inst
->src
[0]) ||
1004 IS_64BIT(inst
->src
[1]) || IS_64BIT(inst
->src
[2]))
1011 if (devinfo
->gen
>= 8) {
1012 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
1018 * In the presence of send messages, totally interrupt dependency
1019 * control. They're long enough that the chance of dependency
1020 * control around them just doesn't matter.
1023 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
1024 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
1025 * completes the scoreboard clear must have a non-zero execution mask. This
1026 * means, if any kind of predication can change the execution mask or channel
1027 * enable of the last instruction, the optimization must be avoided. This is
1028 * to avoid instructions being shot down the pipeline when no writes are
1032 * Dependency control does not work well over math instructions.
1033 * NB: Discovered empirically
1035 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
1039 * Sets the dependency control fields on instructions after register
1040 * allocation and before the generator is run.
1042 * When you have a sequence of instructions like:
1044 * DP4 temp.x vertex uniform[0]
1045 * DP4 temp.y vertex uniform[0]
1046 * DP4 temp.z vertex uniform[0]
1047 * DP4 temp.w vertex uniform[0]
1049 * The hardware doesn't know that it can actually run the later instructions
1050 * while the previous ones are in flight, producing stalls. However, we have
1051 * manual fields we can set in the instructions that let it do so.
1054 vec4_visitor::opt_set_dependency_control()
1056 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
1057 uint8_t grf_channels_written
[BRW_MAX_GRF
];
1058 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
1059 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
1061 assert(prog_data
->total_grf
||
1062 !"Must be called after register allocation");
1064 foreach_block (block
, cfg
) {
1065 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1066 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1068 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
1069 /* If we read from a register that we were doing dependency control
1070 * on, don't do dependency control across the read.
1072 for (int i
= 0; i
< 3; i
++) {
1073 int reg
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ REG_SIZE
;
1074 if (inst
->src
[i
].file
== VGRF
) {
1075 last_grf_write
[reg
] = NULL
;
1076 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1077 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1080 assert(inst
->src
[i
].file
!= MRF
);
1083 if (is_dep_ctrl_unsafe(inst
)) {
1084 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1085 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1089 /* Now, see if we can do dependency control for this instruction
1090 * against a previous one writing to its destination.
1092 int reg
= inst
->dst
.nr
+ inst
->dst
.offset
/ REG_SIZE
;
1093 if (inst
->dst
.file
== VGRF
|| inst
->dst
.file
== FIXED_GRF
) {
1094 if (last_grf_write
[reg
] &&
1095 last_grf_write
[reg
]->dst
.offset
== inst
->dst
.offset
&&
1096 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
1097 last_grf_write
[reg
]->no_dd_clear
= true;
1098 inst
->no_dd_check
= true;
1100 grf_channels_written
[reg
] = 0;
1103 last_grf_write
[reg
] = inst
;
1104 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
1105 } else if (inst
->dst
.file
== MRF
) {
1106 if (last_mrf_write
[reg
] &&
1107 last_mrf_write
[reg
]->dst
.offset
== inst
->dst
.offset
&&
1108 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
1109 last_mrf_write
[reg
]->no_dd_clear
= true;
1110 inst
->no_dd_check
= true;
1112 mrf_channels_written
[reg
] = 0;
1115 last_mrf_write
[reg
] = inst
;
1116 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
1123 vec4_instruction::can_reswizzle(const struct gen_device_info
*devinfo
,
1128 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
1131 if (devinfo
->gen
== 6 && is_math() && swizzle
!= BRW_SWIZZLE_XYZW
)
1134 /* We can't swizzle implicit accumulator access. We'd have to
1135 * reswizzle the producer of the accumulator value in addition
1136 * to the consumer (i.e. both MUL and MACH). Just skip this.
1138 if (reads_accumulator_implicitly())
1141 if (!can_do_writemask(devinfo
) && dst_writemask
!= WRITEMASK_XYZW
)
1144 /* If this instruction sets anything not referenced by swizzle, then we'd
1145 * totally break it when we reswizzle.
1147 if (dst
.writemask
& ~swizzle_mask
)
1153 for (int i
= 0; i
< 3; i
++) {
1154 if (src
[i
].is_accumulator())
1162 * For any channels in the swizzle's source that were populated by this
1163 * instruction, rewrite the instruction to put the appropriate result directly
1164 * in those channels.
1166 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
1169 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
1171 /* Destination write mask doesn't correspond to source swizzle for the dot
1172 * product and pack_bytes instructions.
1174 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
1175 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
1176 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
1177 for (int i
= 0; i
< 3; i
++) {
1178 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
1181 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
1185 /* Apply the specified swizzle and writemask to the original mask of
1186 * written components.
1188 dst
.writemask
= dst_writemask
&
1189 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1193 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1194 * just written and then MOVed into another reg and making the original write
1195 * of the GRF write directly to the final destination instead.
1198 vec4_visitor::opt_register_coalesce()
1200 bool progress
= false;
1203 calculate_live_intervals();
1205 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1209 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1210 (inst
->dst
.file
!= VGRF
&& inst
->dst
.file
!= MRF
) ||
1212 inst
->src
[0].file
!= VGRF
||
1213 inst
->dst
.type
!= inst
->src
[0].type
||
1214 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1217 /* Remove no-op MOVs */
1218 if (inst
->dst
.file
== inst
->src
[0].file
&&
1219 inst
->dst
.nr
== inst
->src
[0].nr
&&
1220 inst
->dst
.offset
== inst
->src
[0].offset
) {
1221 bool is_nop_mov
= true;
1223 for (unsigned c
= 0; c
< 4; c
++) {
1224 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1227 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1234 inst
->remove(block
);
1240 bool to_mrf
= (inst
->dst
.file
== MRF
);
1242 /* Can't coalesce this GRF if someone else was going to
1245 if (var_range_end(var_from_reg(alloc
, dst_reg(inst
->src
[0])), 8) > ip
)
1248 /* We need to check interference with the final destination between this
1249 * instruction and the earliest instruction involved in writing the GRF
1250 * we're eliminating. To do that, keep track of which of our source
1251 * channels we've seen initialized.
1253 const unsigned chans_needed
=
1254 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1255 inst
->dst
.writemask
);
1256 unsigned chans_remaining
= chans_needed
;
1258 /* Now walk up the instruction stream trying to see if we can rewrite
1259 * everything writing to the temporary to write into the destination
1262 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1263 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1265 _scan_inst
= scan_inst
;
1267 if (regions_overlap(inst
->src
[0], inst
->size_read(0),
1268 scan_inst
->dst
, scan_inst
->size_written
)) {
1269 /* Found something writing to the reg we want to coalesce away. */
1271 /* SEND instructions can't have MRF as a destination. */
1272 if (scan_inst
->mlen
)
1275 if (devinfo
->gen
== 6) {
1276 /* gen6 math instructions must have the destination be
1277 * VGRF, so no compute-to-MRF for them.
1279 if (scan_inst
->is_math()) {
1285 /* This doesn't handle saturation on the instruction we
1286 * want to coalesce away if the register types do not match.
1287 * But if scan_inst is a non type-converting 'mov', we can fix
1290 if (inst
->saturate
&&
1291 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1292 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1293 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1296 /* Only allow coalescing between registers of the same type size.
1297 * Otherwise we would need to make the pass aware of the fact that
1298 * channel sizes are different for single and double precision.
1300 if (type_sz(inst
->src
[0].type
) != type_sz(scan_inst
->src
[0].type
))
1303 /* Check that scan_inst writes the same amount of data as the
1304 * instruction, otherwise coalescing would lead to writing a
1305 * different (larger or smaller) region of the destination
1307 if (scan_inst
->size_written
!= inst
->size_written
)
1310 /* If we can't handle the swizzle, bail. */
1311 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1312 inst
->src
[0].swizzle
,
1317 /* This only handles coalescing writes of 8 channels (1 register
1318 * for single-precision and 2 registers for double-precision)
1319 * starting at the source offset of the copy instruction.
1321 if (DIV_ROUND_UP(scan_inst
->size_written
,
1322 type_sz(scan_inst
->dst
.type
)) > 8 ||
1323 scan_inst
->dst
.offset
!= inst
->src
[0].offset
)
1326 /* Mark which channels we found unconditional writes for. */
1327 if (!scan_inst
->predicate
)
1328 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1330 if (chans_remaining
== 0)
1334 /* You can't read from an MRF, so if someone else reads our MRF's
1335 * source GRF that we wanted to rewrite, that stops us. If it's a
1336 * GRF we're trying to coalesce to, we don't actually handle
1337 * rewriting sources so bail in that case as well.
1339 bool interfered
= false;
1340 for (int i
= 0; i
< 3; i
++) {
1341 if (regions_overlap(inst
->src
[0], inst
->size_read(0),
1342 scan_inst
->src
[i
], scan_inst
->size_read(i
)))
1348 /* If somebody else writes the same channels of our destination here,
1349 * we can't coalesce before that.
1351 if (regions_overlap(inst
->dst
, inst
->size_written
,
1352 scan_inst
->dst
, scan_inst
->size_written
) &&
1353 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1357 /* Check for reads of the register we're trying to coalesce into. We
1358 * can't go rewriting instructions above that to put some other value
1359 * in the register instead.
1361 if (to_mrf
&& scan_inst
->mlen
> 0) {
1362 if (inst
->dst
.nr
>= scan_inst
->base_mrf
&&
1363 inst
->dst
.nr
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1367 for (int i
= 0; i
< 3; i
++) {
1368 if (regions_overlap(inst
->dst
, inst
->size_written
,
1369 scan_inst
->src
[i
], scan_inst
->size_read(i
)))
1377 if (chans_remaining
== 0) {
1378 /* If we've made it here, we have an MOV we want to coalesce out, and
1379 * a scan_inst pointing to the earliest instruction involved in
1380 * computing the value. Now go rewrite the instruction stream
1383 vec4_instruction
*scan_inst
= _scan_inst
;
1384 while (scan_inst
!= inst
) {
1385 if (scan_inst
->dst
.file
== VGRF
&&
1386 scan_inst
->dst
.nr
== inst
->src
[0].nr
&&
1387 scan_inst
->dst
.offset
== inst
->src
[0].offset
) {
1388 scan_inst
->reswizzle(inst
->dst
.writemask
,
1389 inst
->src
[0].swizzle
);
1390 scan_inst
->dst
.file
= inst
->dst
.file
;
1391 scan_inst
->dst
.nr
= inst
->dst
.nr
;
1392 scan_inst
->dst
.offset
= inst
->dst
.offset
;
1393 if (inst
->saturate
&&
1394 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1395 /* If we have reached this point, scan_inst is a non
1396 * type-converting 'mov' and we can modify its register types
1397 * to match the ones in inst. Otherwise, we could have an
1398 * incorrect saturation result.
1400 scan_inst
->dst
.type
= inst
->dst
.type
;
1401 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1403 scan_inst
->saturate
|= inst
->saturate
;
1405 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1407 inst
->remove(block
);
1413 invalidate_live_intervals();
1419 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1420 * flow. We could probably do better here with some form of divergence
1424 vec4_visitor::eliminate_find_live_channel()
1426 bool progress
= false;
1429 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
1430 /* The optimization below assumes that channel zero is live on thread
1431 * dispatch, which may not be the case if the fixed function dispatches
1437 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1438 switch (inst
->opcode
) {
1444 case BRW_OPCODE_ENDIF
:
1445 case BRW_OPCODE_WHILE
:
1449 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1451 inst
->opcode
= BRW_OPCODE_MOV
;
1452 inst
->src
[0] = brw_imm_d(0);
1453 inst
->force_writemask_all
= true;
1467 * Splits virtual GRFs requesting more than one contiguous physical register.
1469 * We initially create large virtual GRFs for temporary structures, arrays,
1470 * and matrices, so that the visitor functions can add offsets to work their
1471 * way down to the actual member being accessed. But when it comes to
1472 * optimization, we'd like to treat each register as individual storage if
1475 * So far, the only thing that might prevent splitting is a send message from
1479 vec4_visitor::split_virtual_grfs()
1481 int num_vars
= this->alloc
.count
;
1482 int new_virtual_grf
[num_vars
];
1483 bool split_grf
[num_vars
];
1485 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1487 /* Try to split anything > 0 sized. */
1488 for (int i
= 0; i
< num_vars
; i
++) {
1489 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1492 /* Check that the instructions are compatible with the registers we're trying
1495 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1496 if (inst
->dst
.file
== VGRF
&& regs_written(inst
) > 1)
1497 split_grf
[inst
->dst
.nr
] = false;
1499 for (int i
= 0; i
< 3; i
++) {
1500 if (inst
->src
[i
].file
== VGRF
&& regs_read(inst
, i
) > 1)
1501 split_grf
[inst
->src
[i
].nr
] = false;
1505 /* Allocate new space for split regs. Note that the virtual
1506 * numbers will be contiguous.
1508 for (int i
= 0; i
< num_vars
; i
++) {
1512 new_virtual_grf
[i
] = alloc
.allocate(1);
1513 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1514 unsigned reg
= alloc
.allocate(1);
1515 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1518 this->alloc
.sizes
[i
] = 1;
1521 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1522 if (inst
->dst
.file
== VGRF
&& split_grf
[inst
->dst
.nr
] &&
1523 inst
->dst
.offset
/ REG_SIZE
!= 0) {
1524 inst
->dst
.nr
= (new_virtual_grf
[inst
->dst
.nr
] +
1525 inst
->dst
.offset
/ REG_SIZE
- 1);
1526 inst
->dst
.offset
%= REG_SIZE
;
1528 for (int i
= 0; i
< 3; i
++) {
1529 if (inst
->src
[i
].file
== VGRF
&& split_grf
[inst
->src
[i
].nr
] &&
1530 inst
->src
[i
].offset
/ REG_SIZE
!= 0) {
1531 inst
->src
[i
].nr
= (new_virtual_grf
[inst
->src
[i
].nr
] +
1532 inst
->src
[i
].offset
/ REG_SIZE
- 1);
1533 inst
->src
[i
].offset
%= REG_SIZE
;
1537 invalidate_live_intervals();
1541 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1543 dump_instruction(be_inst
, stderr
);
1547 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1549 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1551 if (inst
->predicate
) {
1552 fprintf(file
, "(%cf%d.%d%s) ",
1553 inst
->predicate_inverse
? '-' : '+',
1554 inst
->flag_subreg
/ 2,
1555 inst
->flag_subreg
% 2,
1556 pred_ctrl_align16
[inst
->predicate
]);
1559 fprintf(file
, "%s(%d)", brw_instruction_name(devinfo
, inst
->opcode
),
1562 fprintf(file
, ".sat");
1563 if (inst
->conditional_mod
) {
1564 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1565 if (!inst
->predicate
&&
1566 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1567 inst
->opcode
!= BRW_OPCODE_CSEL
&&
1568 inst
->opcode
!= BRW_OPCODE_IF
&&
1569 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1570 fprintf(file
, ".f%d.%d", inst
->flag_subreg
/ 2, inst
->flag_subreg
% 2);
1575 switch (inst
->dst
.file
) {
1577 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
1580 fprintf(file
, "g%d", inst
->dst
.nr
);
1583 fprintf(file
, "m%d", inst
->dst
.nr
);
1586 switch (inst
->dst
.nr
) {
1588 fprintf(file
, "null");
1590 case BRW_ARF_ADDRESS
:
1591 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
1593 case BRW_ARF_ACCUMULATOR
:
1594 fprintf(file
, "acc%d", inst
->dst
.subnr
);
1597 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1600 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1605 fprintf(file
, "(null)");
1610 unreachable("not reached");
1612 if (inst
->dst
.offset
||
1613 (inst
->dst
.file
== VGRF
&&
1614 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
1615 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 16 : REG_SIZE
);
1616 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
1617 inst
->dst
.offset
% reg_size
);
1619 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1621 if (inst
->dst
.writemask
& 1)
1623 if (inst
->dst
.writemask
& 2)
1625 if (inst
->dst
.writemask
& 4)
1627 if (inst
->dst
.writemask
& 8)
1630 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->dst
.type
));
1632 if (inst
->src
[0].file
!= BAD_FILE
)
1633 fprintf(file
, ", ");
1635 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1636 if (inst
->src
[i
].negate
)
1638 if (inst
->src
[i
].abs
)
1640 switch (inst
->src
[i
].file
) {
1642 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
1645 fprintf(file
, "g%d.%d", inst
->src
[i
].nr
, inst
->src
[i
].subnr
);
1648 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
1651 fprintf(file
, "u%d", inst
->src
[i
].nr
);
1654 switch (inst
->src
[i
].type
) {
1655 case BRW_REGISTER_TYPE_F
:
1656 fprintf(file
, "%fF", inst
->src
[i
].f
);
1658 case BRW_REGISTER_TYPE_DF
:
1659 fprintf(file
, "%fDF", inst
->src
[i
].df
);
1661 case BRW_REGISTER_TYPE_D
:
1662 fprintf(file
, "%dD", inst
->src
[i
].d
);
1664 case BRW_REGISTER_TYPE_UD
:
1665 fprintf(file
, "%uU", inst
->src
[i
].ud
);
1667 case BRW_REGISTER_TYPE_VF
:
1668 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1669 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
1670 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
1671 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
1672 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
1675 fprintf(file
, "???");
1680 switch (inst
->src
[i
].nr
) {
1682 fprintf(file
, "null");
1684 case BRW_ARF_ADDRESS
:
1685 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
1687 case BRW_ARF_ACCUMULATOR
:
1688 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
1691 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1694 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1699 fprintf(file
, "(null)");
1702 unreachable("not reached");
1705 if (inst
->src
[i
].offset
||
1706 (inst
->src
[i
].file
== VGRF
&&
1707 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
1708 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 16 : REG_SIZE
);
1709 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
1710 inst
->src
[i
].offset
% reg_size
);
1713 if (inst
->src
[i
].file
!= IMM
) {
1714 static const char *chans
[4] = {"x", "y", "z", "w"};
1716 for (int c
= 0; c
< 4; c
++) {
1717 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1721 if (inst
->src
[i
].abs
)
1724 if (inst
->src
[i
].file
!= IMM
) {
1725 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
1728 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1729 fprintf(file
, ", ");
1732 if (inst
->force_writemask_all
)
1733 fprintf(file
, " NoMask");
1735 if (inst
->exec_size
!= 8)
1736 fprintf(file
, " group%d", inst
->group
);
1738 fprintf(file
, "\n");
1743 vec4_vs_visitor::setup_attributes(int payload_reg
)
1745 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1746 for (int i
= 0; i
< 3; i
++) {
1747 if (inst
->src
[i
].file
== ATTR
) {
1748 assert(inst
->src
[i
].offset
% REG_SIZE
== 0);
1749 int grf
= payload_reg
+ inst
->src
[i
].nr
+
1750 inst
->src
[i
].offset
/ REG_SIZE
;
1752 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1753 reg
.swizzle
= inst
->src
[i
].swizzle
;
1754 reg
.type
= inst
->src
[i
].type
;
1755 reg
.abs
= inst
->src
[i
].abs
;
1756 reg
.negate
= inst
->src
[i
].negate
;
1762 return payload_reg
+ vs_prog_data
->nr_attribute_slots
;
1766 vec4_visitor::setup_uniforms(int reg
)
1768 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1770 /* The pre-gen6 VS requires that some push constants get loaded no
1771 * matter what, or the GPU would hang.
1773 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1774 brw_stage_prog_data_add_params(stage_prog_data
, 4);
1775 for (unsigned int i
= 0; i
< 4; i
++) {
1776 unsigned int slot
= this->uniforms
* 4 + i
;
1777 stage_prog_data
->param
[slot
] = BRW_PARAM_BUILTIN_ZERO
;
1783 reg
+= ALIGN(uniforms
, 2) / 2;
1786 for (int i
= 0; i
< 4; i
++)
1787 reg
+= stage_prog_data
->ubo_ranges
[i
].length
;
1789 stage_prog_data
->nr_params
= this->uniforms
* 4;
1791 prog_data
->base
.curb_read_length
=
1792 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1798 vec4_vs_visitor::setup_payload(void)
1802 /* The payload always contains important data in g0, which contains
1803 * the URB handles that are passed on to the URB write at the end
1804 * of the thread. So, we always start push constants at g1.
1808 reg
= setup_uniforms(reg
);
1810 reg
= setup_attributes(reg
);
1812 this->first_non_payload_grf
= reg
;
1816 vec4_visitor::lower_minmax()
1818 assert(devinfo
->gen
< 6);
1820 bool progress
= false;
1822 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1823 const vec4_builder
ibld(this, block
, inst
);
1825 if (inst
->opcode
== BRW_OPCODE_SEL
&&
1826 inst
->predicate
== BRW_PREDICATE_NONE
) {
1827 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
1828 * the original SEL.L/GE instruction
1830 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
1831 inst
->conditional_mod
);
1832 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1833 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
1840 invalidate_live_intervals();
1846 vec4_visitor::get_timestamp()
1848 assert(devinfo
->gen
>= 7);
1850 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1855 BRW_REGISTER_TYPE_UD
,
1856 BRW_VERTICAL_STRIDE_0
,
1858 BRW_HORIZONTAL_STRIDE_4
,
1862 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1864 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1865 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1866 * even if it's not enabled in the dispatch.
1868 mov
->force_writemask_all
= true;
1870 return src_reg(dst
);
1874 vec4_visitor::emit_shader_time_begin()
1876 current_annotation
= "shader time start";
1877 shader_start_time
= get_timestamp();
1881 vec4_visitor::emit_shader_time_end()
1883 current_annotation
= "shader time end";
1884 src_reg shader_end_time
= get_timestamp();
1887 /* Check that there weren't any timestamp reset events (assuming these
1888 * were the only two timestamp reads that happened).
1890 src_reg reset_end
= shader_end_time
;
1891 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1892 vec4_instruction
*test
= emit(AND(dst_null_ud(), reset_end
, brw_imm_ud(1u)));
1893 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1895 emit(IF(BRW_PREDICATE_NORMAL
));
1897 /* Take the current timestamp and get the delta. */
1898 shader_start_time
.negate
= true;
1899 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1900 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1902 /* If there were no instructions between the two timestamp gets, the diff
1903 * is 2 cycles. Remove that overhead, so I can forget about that when
1904 * trying to determine the time taken for single instructions.
1906 emit(ADD(diff
, src_reg(diff
), brw_imm_ud(-2u)));
1908 emit_shader_time_write(0, src_reg(diff
));
1909 emit_shader_time_write(1, brw_imm_ud(1u));
1910 emit(BRW_OPCODE_ELSE
);
1911 emit_shader_time_write(2, brw_imm_ud(1u));
1912 emit(BRW_OPCODE_ENDIF
);
1916 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1919 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1921 dst_reg offset
= dst
;
1923 time
.offset
+= REG_SIZE
;
1925 offset
.type
= BRW_REGISTER_TYPE_UD
;
1926 int index
= shader_time_index
* 3 + shader_time_subindex
;
1927 emit(MOV(offset
, brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
)));
1929 time
.type
= BRW_REGISTER_TYPE_UD
;
1930 emit(MOV(time
, value
));
1932 vec4_instruction
*inst
=
1933 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1938 is_align1_df(vec4_instruction
*inst
)
1940 switch (inst
->opcode
) {
1941 case VEC4_OPCODE_DOUBLE_TO_F32
:
1942 case VEC4_OPCODE_DOUBLE_TO_D32
:
1943 case VEC4_OPCODE_DOUBLE_TO_U32
:
1944 case VEC4_OPCODE_TO_DOUBLE
:
1945 case VEC4_OPCODE_PICK_LOW_32BIT
:
1946 case VEC4_OPCODE_PICK_HIGH_32BIT
:
1947 case VEC4_OPCODE_SET_LOW_32BIT
:
1948 case VEC4_OPCODE_SET_HIGH_32BIT
:
1956 * Three source instruction must have a GRF/MRF destination register.
1957 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
1960 vec4_visitor::fixup_3src_null_dest()
1962 bool progress
= false;
1964 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1965 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
1966 const unsigned size_written
= type_sz(inst
->dst
.type
);
1967 const unsigned num_regs
= DIV_ROUND_UP(size_written
, REG_SIZE
);
1969 inst
->dst
= retype(dst_reg(VGRF
, alloc
.allocate(num_regs
)),
1976 invalidate_live_intervals();
1980 vec4_visitor::convert_to_hw_regs()
1982 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1983 for (int i
= 0; i
< 3; i
++) {
1984 class src_reg
&src
= inst
->src
[i
];
1988 reg
= byte_offset(brw_vecn_grf(4, src
.nr
, 0), src
.offset
);
1989 reg
.type
= src
.type
;
1991 reg
.negate
= src
.negate
;
1996 reg
= stride(byte_offset(brw_vec4_grf(
1997 prog_data
->base
.dispatch_grf_start_reg
+
1998 src
.nr
/ 2, src
.nr
% 2 * 4),
2001 reg
.type
= src
.type
;
2003 reg
.negate
= src
.negate
;
2005 /* This should have been moved to pull constants. */
2006 assert(!src
.reladdr
);
2011 if (type_sz(src
.type
) == 8) {
2012 reg
= src
.as_brw_reg();
2021 /* Probably unused. */
2022 reg
= brw_null_reg();
2023 reg
= retype(reg
, src
.type
);
2028 unreachable("not reached");
2031 apply_logical_swizzle(®
, inst
, i
);
2034 /* From IVB PRM, vol4, part3, "General Restrictions on Regioning
2037 * "If ExecSize = Width and HorzStride ≠ 0, VertStride must be set
2038 * to Width * HorzStride."
2040 * We can break this rule with DF sources on DF align1
2041 * instructions, because the exec_size would be 4 and width is 4.
2042 * As we know we are not accessing to next GRF, it is safe to
2043 * set vstride to the formula given by the rule itself.
2045 if (is_align1_df(inst
) && (cvt(inst
->exec_size
) - 1) == src
.width
)
2046 src
.vstride
= src
.width
+ src
.hstride
;
2049 if (inst
->is_3src(devinfo
)) {
2050 /* 3-src instructions with scalar sources support arbitrary subnr,
2051 * but don't actually use swizzles. Convert swizzle into subnr.
2052 * Skip this for double-precision instructions: RepCtrl=1 is not
2053 * allowed for them and needs special handling.
2055 for (int i
= 0; i
< 3; i
++) {
2056 if (inst
->src
[i
].vstride
== BRW_VERTICAL_STRIDE_0
&&
2057 type_sz(inst
->src
[i
].type
) < 8) {
2058 assert(brw_is_single_value_swizzle(inst
->src
[i
].swizzle
));
2059 inst
->src
[i
].subnr
+= 4 * BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0);
2064 dst_reg
&dst
= inst
->dst
;
2067 switch (inst
->dst
.file
) {
2069 reg
= byte_offset(brw_vec8_grf(dst
.nr
, 0), dst
.offset
);
2070 reg
.type
= dst
.type
;
2071 reg
.writemask
= dst
.writemask
;
2075 reg
= byte_offset(brw_message_reg(dst
.nr
), dst
.offset
);
2076 assert((reg
.nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
2077 reg
.type
= dst
.type
;
2078 reg
.writemask
= dst
.writemask
;
2083 reg
= dst
.as_brw_reg();
2087 reg
= brw_null_reg();
2088 reg
= retype(reg
, dst
.type
);
2094 unreachable("not reached");
2102 stage_uses_interleaved_attributes(unsigned stage
,
2103 enum shader_dispatch_mode dispatch_mode
)
2106 case MESA_SHADER_TESS_EVAL
:
2108 case MESA_SHADER_GEOMETRY
:
2109 return dispatch_mode
!= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2116 * Get the closest native SIMD width supported by the hardware for instruction
2117 * \p inst. The instruction will be left untouched by
2118 * vec4_visitor::lower_simd_width() if the returned value matches the
2119 * instruction's original execution size.
2122 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
2123 enum shader_dispatch_mode dispatch_mode
,
2124 unsigned stage
, const vec4_instruction
*inst
)
2126 /* Do not split some instructions that require special handling */
2127 switch (inst
->opcode
) {
2128 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2129 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2130 return inst
->exec_size
;
2135 unsigned lowered_width
= MIN2(16, inst
->exec_size
);
2137 /* We need to split some cases of double-precision instructions that write
2138 * 2 registers. We only need to care about this in gen7 because that is the
2139 * only hardware that implements fp64 in Align16.
2141 if (devinfo
->gen
== 7 && inst
->size_written
> REG_SIZE
) {
2142 /* Align16 8-wide double-precision SEL does not work well. Verified
2145 if (inst
->opcode
== BRW_OPCODE_SEL
&& type_sz(inst
->dst
.type
) == 8)
2146 lowered_width
= MIN2(lowered_width
, 4);
2148 /* HSW PRM, 3D Media GPGPU Engine, Region Alignment Rules for Direct
2149 * Register Addressing:
2151 * "When destination spans two registers, the source MUST span two
2154 for (unsigned i
= 0; i
< 3; i
++) {
2155 if (inst
->src
[i
].file
== BAD_FILE
)
2157 if (inst
->size_read(i
) <= REG_SIZE
)
2158 lowered_width
= MIN2(lowered_width
, 4);
2160 /* Interleaved attribute setups use a vertical stride of 0, which
2161 * makes them hit the associated instruction decompression bug in gen7.
2162 * Split them to prevent this.
2164 if (inst
->src
[i
].file
== ATTR
&&
2165 stage_uses_interleaved_attributes(stage
, dispatch_mode
))
2166 lowered_width
= MIN2(lowered_width
, 4);
2170 /* IvyBridge can manage a maximum of 4 DFs per SIMD4x2 instruction, since
2171 * it doesn't support compression in Align16 mode, no matter if it has
2172 * force_writemask_all enabled or disabled (the latter is affected by the
2173 * compressed instruction bug in gen7, which is another reason to enforce
2176 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
2177 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8))
2178 lowered_width
= MIN2(lowered_width
, 4);
2180 return lowered_width
;
2184 dst_src_regions_overlap(vec4_instruction
*inst
)
2186 if (inst
->size_written
== 0)
2189 unsigned dst_start
= inst
->dst
.offset
;
2190 unsigned dst_end
= dst_start
+ inst
->size_written
- 1;
2191 for (int i
= 0; i
< 3; i
++) {
2192 if (inst
->src
[i
].file
== BAD_FILE
)
2195 if (inst
->dst
.file
!= inst
->src
[i
].file
||
2196 inst
->dst
.nr
!= inst
->src
[i
].nr
)
2199 unsigned src_start
= inst
->src
[i
].offset
;
2200 unsigned src_end
= src_start
+ inst
->size_read(i
) - 1;
2202 if ((dst_start
>= src_start
&& dst_start
<= src_end
) ||
2203 (dst_end
>= src_start
&& dst_end
<= src_end
) ||
2204 (dst_start
<= src_start
&& dst_end
>= src_end
)) {
2213 vec4_visitor::lower_simd_width()
2215 bool progress
= false;
2217 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
2218 const unsigned lowered_width
=
2219 get_lowered_simd_width(devinfo
, prog_data
->dispatch_mode
, stage
, inst
);
2220 assert(lowered_width
<= inst
->exec_size
);
2221 if (lowered_width
== inst
->exec_size
)
2224 /* We need to deal with source / destination overlaps when splitting.
2225 * The hardware supports reading from and writing to the same register
2226 * in the same instruction, but we need to be careful that each split
2227 * instruction we produce does not corrupt the source of the next.
2229 * The easiest way to handle this is to make the split instructions write
2230 * to temporaries if there is an src/dst overlap and then move from the
2231 * temporaries to the original destination. We also need to consider
2232 * instructions that do partial writes via align1 opcodes, in which case
2233 * we need to make sure that the we initialize the temporary with the
2234 * value of the instruction's dst.
2236 bool needs_temp
= dst_src_regions_overlap(inst
);
2237 for (unsigned n
= 0; n
< inst
->exec_size
/ lowered_width
; n
++) {
2238 unsigned channel_offset
= lowered_width
* n
;
2240 unsigned size_written
= lowered_width
* type_sz(inst
->dst
.type
);
2242 /* Create the split instruction from the original so that we copy all
2243 * relevant instruction fields, then set the width and calculate the
2244 * new dst/src regions.
2246 vec4_instruction
*linst
= new(mem_ctx
) vec4_instruction(*inst
);
2247 linst
->exec_size
= lowered_width
;
2248 linst
->group
= channel_offset
;
2249 linst
->size_written
= size_written
;
2251 /* Compute split dst region */
2254 unsigned num_regs
= DIV_ROUND_UP(size_written
, REG_SIZE
);
2255 dst
= retype(dst_reg(VGRF
, alloc
.allocate(num_regs
)),
2257 if (inst
->is_align1_partial_write()) {
2258 vec4_instruction
*copy
= MOV(dst
, src_reg(inst
->dst
));
2259 copy
->exec_size
= lowered_width
;
2260 copy
->group
= channel_offset
;
2261 copy
->size_written
= size_written
;
2262 inst
->insert_before(block
, copy
);
2265 dst
= horiz_offset(inst
->dst
, channel_offset
);
2269 /* Compute split source regions */
2270 for (int i
= 0; i
< 3; i
++) {
2271 if (linst
->src
[i
].file
== BAD_FILE
)
2274 bool is_interleaved_attr
=
2275 linst
->src
[i
].file
== ATTR
&&
2276 stage_uses_interleaved_attributes(stage
,
2277 prog_data
->dispatch_mode
);
2279 if (!is_uniform(linst
->src
[i
]) && !is_interleaved_attr
)
2280 linst
->src
[i
] = horiz_offset(linst
->src
[i
], channel_offset
);
2283 inst
->insert_before(block
, linst
);
2285 /* If we used a temporary to store the result of the split
2286 * instruction, copy the result to the original destination
2289 vec4_instruction
*mov
=
2290 MOV(offset(inst
->dst
, lowered_width
, n
), src_reg(dst
));
2291 mov
->exec_size
= lowered_width
;
2292 mov
->group
= channel_offset
;
2293 mov
->size_written
= size_written
;
2294 mov
->predicate
= inst
->predicate
;
2295 inst
->insert_before(block
, mov
);
2299 inst
->remove(block
);
2304 invalidate_live_intervals();
2309 static brw_predicate
2310 scalarize_predicate(brw_predicate predicate
, unsigned writemask
)
2312 if (predicate
!= BRW_PREDICATE_NORMAL
)
2315 switch (writemask
) {
2317 return BRW_PREDICATE_ALIGN16_REPLICATE_X
;
2319 return BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
2321 return BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
2323 return BRW_PREDICATE_ALIGN16_REPLICATE_W
;
2325 unreachable("invalid writemask");
2329 /* Gen7 has a hardware decompression bug that we can exploit to represent
2330 * handful of additional swizzles natively.
2333 is_gen7_supported_64bit_swizzle(vec4_instruction
*inst
, unsigned arg
)
2335 switch (inst
->src
[arg
].swizzle
) {
2336 case BRW_SWIZZLE_XXXX
:
2337 case BRW_SWIZZLE_YYYY
:
2338 case BRW_SWIZZLE_ZZZZ
:
2339 case BRW_SWIZZLE_WWWW
:
2340 case BRW_SWIZZLE_XYXY
:
2341 case BRW_SWIZZLE_YXYX
:
2342 case BRW_SWIZZLE_ZWZW
:
2343 case BRW_SWIZZLE_WZWZ
:
2350 /* 64-bit sources use regions with a width of 2. These 2 elements in each row
2351 * can be addressed using 32-bit swizzles (which is what the hardware supports)
2352 * but it also means that the swizzle we apply on the first two components of a
2353 * dvec4 is coupled with the swizzle we use for the last 2. In other words,
2354 * only some specific swizzle combinations can be natively supported.
2356 * FIXME: we can go an step further and implement even more swizzle
2357 * variations using only partial scalarization.
2359 * For more details see:
2360 * https://bugs.freedesktop.org/show_bug.cgi?id=92760#c82
2363 vec4_visitor::is_supported_64bit_region(vec4_instruction
*inst
, unsigned arg
)
2365 const src_reg
&src
= inst
->src
[arg
];
2366 assert(type_sz(src
.type
) == 8);
2368 /* Uniform regions have a vstride=0. Because we use 2-wide rows with
2369 * 64-bit regions it means that we cannot access components Z/W, so
2370 * return false for any such case. Interleaved attributes will also be
2371 * mapped to GRF registers with a vstride of 0, so apply the same
2374 if ((is_uniform(src
) ||
2375 (stage_uses_interleaved_attributes(stage
, prog_data
->dispatch_mode
) &&
2376 src
.file
== ATTR
)) &&
2377 (brw_mask_for_swizzle(src
.swizzle
) & 12))
2380 switch (src
.swizzle
) {
2381 case BRW_SWIZZLE_XYZW
:
2382 case BRW_SWIZZLE_XXZZ
:
2383 case BRW_SWIZZLE_YYWW
:
2384 case BRW_SWIZZLE_YXWZ
:
2387 return devinfo
->gen
== 7 && is_gen7_supported_64bit_swizzle(inst
, arg
);
2392 vec4_visitor::scalarize_df()
2394 bool progress
= false;
2396 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
2397 /* Skip DF instructions that operate in Align1 mode */
2398 if (is_align1_df(inst
))
2401 /* Check if this is a double-precision instruction */
2402 bool is_double
= type_sz(inst
->dst
.type
) == 8;
2403 for (int arg
= 0; !is_double
&& arg
< 3; arg
++) {
2404 is_double
= inst
->src
[arg
].file
!= BAD_FILE
&&
2405 type_sz(inst
->src
[arg
].type
) == 8;
2411 /* Skip the lowering for specific regioning scenarios that we can
2414 bool skip_lowering
= true;
2416 /* XY and ZW writemasks operate in 32-bit, which means that they don't
2417 * have a native 64-bit representation and they should always be split.
2419 if (inst
->dst
.writemask
== WRITEMASK_XY
||
2420 inst
->dst
.writemask
== WRITEMASK_ZW
) {
2421 skip_lowering
= false;
2423 for (unsigned i
= 0; i
< 3; i
++) {
2424 if (inst
->src
[i
].file
== BAD_FILE
|| type_sz(inst
->src
[i
].type
) < 8)
2426 skip_lowering
= skip_lowering
&& is_supported_64bit_region(inst
, i
);
2433 /* Generate scalar instructions for each enabled channel */
2434 for (unsigned chan
= 0; chan
< 4; chan
++) {
2435 unsigned chan_mask
= 1 << chan
;
2436 if (!(inst
->dst
.writemask
& chan_mask
))
2439 vec4_instruction
*scalar_inst
= new(mem_ctx
) vec4_instruction(*inst
);
2441 for (unsigned i
= 0; i
< 3; i
++) {
2442 unsigned swz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, chan
);
2443 scalar_inst
->src
[i
].swizzle
= BRW_SWIZZLE4(swz
, swz
, swz
, swz
);
2446 scalar_inst
->dst
.writemask
= chan_mask
;
2448 if (inst
->predicate
!= BRW_PREDICATE_NONE
) {
2449 scalar_inst
->predicate
=
2450 scalarize_predicate(inst
->predicate
, chan_mask
);
2453 inst
->insert_before(block
, scalar_inst
);
2456 inst
->remove(block
);
2461 invalidate_live_intervals();
2467 vec4_visitor::lower_64bit_mad_to_mul_add()
2469 bool progress
= false;
2471 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
2472 if (inst
->opcode
!= BRW_OPCODE_MAD
)
2475 if (type_sz(inst
->dst
.type
) != 8)
2478 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
2480 /* Use the copy constructor so we copy all relevant instruction fields
2481 * from the original mad into the add and mul instructions
2483 vec4_instruction
*mul
= new(mem_ctx
) vec4_instruction(*inst
);
2484 mul
->opcode
= BRW_OPCODE_MUL
;
2486 mul
->src
[0] = inst
->src
[1];
2487 mul
->src
[1] = inst
->src
[2];
2488 mul
->src
[2].file
= BAD_FILE
;
2490 vec4_instruction
*add
= new(mem_ctx
) vec4_instruction(*inst
);
2491 add
->opcode
= BRW_OPCODE_ADD
;
2492 add
->src
[0] = src_reg(mul_dst
);
2493 add
->src
[1] = inst
->src
[0];
2494 add
->src
[2].file
= BAD_FILE
;
2496 inst
->insert_before(block
, mul
);
2497 inst
->insert_before(block
, add
);
2498 inst
->remove(block
);
2504 invalidate_live_intervals();
2509 /* The align16 hardware can only do 32-bit swizzle channels, so we need to
2510 * translate the logical 64-bit swizzle channels that we use in the Vec4 IR
2511 * to 32-bit swizzle channels in hardware registers.
2513 * @inst and @arg identify the original vec4 IR source operand we need to
2514 * translate the swizzle for and @hw_reg is the hardware register where we
2515 * will write the hardware swizzle to use.
2517 * This pass assumes that Align16/DF instructions have been fully scalarized
2518 * previously so there is just one 64-bit swizzle channel to deal with for any
2519 * given Vec4 IR source.
2522 vec4_visitor::apply_logical_swizzle(struct brw_reg
*hw_reg
,
2523 vec4_instruction
*inst
, int arg
)
2525 src_reg reg
= inst
->src
[arg
];
2527 if (reg
.file
== BAD_FILE
|| reg
.file
== BRW_IMMEDIATE_VALUE
)
2530 /* If this is not a 64-bit operand or this is a scalar instruction we don't
2531 * need to do anything about the swizzles.
2533 if(type_sz(reg
.type
) < 8 || is_align1_df(inst
)) {
2534 hw_reg
->swizzle
= reg
.swizzle
;
2538 /* Take the 64-bit logical swizzle channel and translate it to 32-bit */
2539 assert(brw_is_single_value_swizzle(reg
.swizzle
) ||
2540 is_supported_64bit_region(inst
, arg
));
2542 /* Apply the region <2, 2, 1> for GRF or <0, 2, 1> for uniforms, as align16
2543 * HW can only do 32-bit swizzle channels.
2545 hw_reg
->width
= BRW_WIDTH_2
;
2547 if (is_supported_64bit_region(inst
, arg
) &&
2548 !is_gen7_supported_64bit_swizzle(inst
, arg
)) {
2549 /* Supported 64-bit swizzles are those such that their first two
2550 * components, when expanded to 32-bit swizzles, match the semantics
2551 * of the original 64-bit swizzle with 2-wide row regioning.
2553 unsigned swizzle0
= BRW_GET_SWZ(reg
.swizzle
, 0);
2554 unsigned swizzle1
= BRW_GET_SWZ(reg
.swizzle
, 1);
2555 hw_reg
->swizzle
= BRW_SWIZZLE4(swizzle0
* 2, swizzle0
* 2 + 1,
2556 swizzle1
* 2, swizzle1
* 2 + 1);
2558 /* If we got here then we have one of the following:
2560 * 1. An unsupported swizzle, which should be single-value thanks to the
2561 * scalarization pass.
2563 * 2. A gen7 supported swizzle. These can be single-value or double-value
2564 * swizzles. If the latter, they are never cross-dvec2 channels. For
2565 * these we always need to activate the gen7 vstride=0 exploit.
2567 unsigned swizzle0
= BRW_GET_SWZ(reg
.swizzle
, 0);
2568 unsigned swizzle1
= BRW_GET_SWZ(reg
.swizzle
, 1);
2569 assert((swizzle0
< 2) == (swizzle1
< 2));
2571 /* To gain access to Z/W components we need to select the second half
2572 * of the register and then use a X/Y swizzle to select Z/W respectively.
2574 if (swizzle0
>= 2) {
2575 *hw_reg
= suboffset(*hw_reg
, 2);
2580 /* All gen7-specific supported swizzles require the vstride=0 exploit */
2581 if (devinfo
->gen
== 7 && is_gen7_supported_64bit_swizzle(inst
, arg
))
2582 hw_reg
->vstride
= BRW_VERTICAL_STRIDE_0
;
2584 /* Any 64-bit source with an offset at 16B is intended to address the
2585 * second half of a register and needs a vertical stride of 0 so we:
2587 * 1. Don't violate register region restrictions.
2588 * 2. Activate the gen7 instruction decompresion bug exploit when
2591 if (hw_reg
->subnr
% REG_SIZE
== 16) {
2592 assert(devinfo
->gen
== 7);
2593 hw_reg
->vstride
= BRW_VERTICAL_STRIDE_0
;
2596 hw_reg
->swizzle
= BRW_SWIZZLE4(swizzle0
* 2, swizzle0
* 2 + 1,
2597 swizzle1
* 2, swizzle1
* 2 + 1);
2604 if (shader_time_index
>= 0)
2605 emit_shader_time_begin();
2618 /* Before any optimization, push array accesses out to scratch
2619 * space where we need them to be. This pass may allocate new
2620 * virtual GRFs, so we want to do it early. It also makes sure
2621 * that we have reladdr computations available for CSE, since we'll
2622 * often do repeated subexpressions for those.
2624 move_grf_array_access_to_scratch();
2625 move_uniform_array_access_to_pull_constants();
2627 pack_uniform_registers();
2628 move_push_constants_to_pull_constants();
2629 split_virtual_grfs();
2631 #define OPT(pass, args...) ({ \
2633 bool this_progress = pass(args); \
2635 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
2636 char filename[64]; \
2637 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
2638 stage_abbrev, nir->info.name, iteration, pass_num); \
2640 backend_shader::dump_instructions(filename); \
2643 progress = progress || this_progress; \
2648 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
2650 snprintf(filename
, 64, "%s-%s-00-00-start",
2651 stage_abbrev
, nir
->info
.name
);
2653 backend_shader::dump_instructions(filename
);
2664 OPT(opt_predicated_break
, this);
2665 OPT(opt_reduce_swizzle
);
2666 OPT(dead_code_eliminate
);
2667 OPT(dead_control_flow_eliminate
, this);
2668 OPT(opt_copy_propagation
);
2669 OPT(opt_cmod_propagation
);
2672 OPT(opt_register_coalesce
);
2673 OPT(eliminate_find_live_channel
);
2678 if (OPT(opt_vector_float
)) {
2680 OPT(opt_copy_propagation
, false);
2681 OPT(opt_copy_propagation
, true);
2682 OPT(dead_code_eliminate
);
2685 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
2686 OPT(opt_cmod_propagation
);
2688 OPT(opt_copy_propagation
);
2689 OPT(dead_code_eliminate
);
2692 if (OPT(lower_simd_width
)) {
2693 OPT(opt_copy_propagation
);
2694 OPT(dead_code_eliminate
);
2700 OPT(lower_64bit_mad_to_mul_add
);
2702 /* Run this before payload setup because tesselation shaders
2703 * rely on it to prevent cross dvec2 regioning on DF attributes
2704 * that are setup so that XY are on the second half of register and
2705 * ZW are in the first half of the next.
2711 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
2712 /* Debug of register spilling: Go spill everything. */
2713 const int grf_count
= alloc
.count
;
2714 float spill_costs
[alloc
.count
];
2715 bool no_spill
[alloc
.count
];
2716 evaluate_spill_costs(spill_costs
, no_spill
);
2717 for (int i
= 0; i
< grf_count
; i
++) {
2723 /* We want to run this after spilling because 64-bit (un)spills need to
2724 * emit code to shuffle 64-bit data for the 32-bit scratch read/write
2725 * messages that can produce unsupported 64-bit swizzle regions.
2730 fixup_3src_null_dest();
2732 bool allocated_without_spills
= reg_allocate();
2734 if (!allocated_without_spills
) {
2735 compiler
->shader_perf_log(log_data
,
2736 "%s shader triggered register spilling. "
2737 "Try reducing the number of live vec4 values "
2738 "to improve performance.\n",
2741 while (!reg_allocate()) {
2746 /* We want to run this after spilling because 64-bit (un)spills need to
2747 * emit code to shuffle 64-bit data for the 32-bit scratch read/write
2748 * messages that can produce unsupported 64-bit swizzle regions.
2753 opt_schedule_instructions();
2755 opt_set_dependency_control();
2757 convert_to_hw_regs();
2759 if (last_scratch
> 0) {
2760 prog_data
->base
.total_scratch
=
2761 brw_get_scratch_size(last_scratch
* REG_SIZE
);
2767 } /* namespace brw */
2772 * Compile a vertex shader.
2774 * Returns the final assembly and the program's size.
2777 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
2779 const struct brw_vs_prog_key
*key
,
2780 struct brw_vs_prog_data
*prog_data
,
2781 const nir_shader
*src_shader
,
2782 int shader_time_index
,
2785 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_VERTEX
];
2786 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
2787 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, is_scalar
);
2789 const unsigned *assembly
= NULL
;
2791 if (prog_data
->base
.vue_map
.varying_to_slot
[VARYING_SLOT_EDGE
] != -1) {
2792 /* If the output VUE map contains VARYING_SLOT_EDGE then we need to copy
2793 * the edge flag from VERT_ATTRIB_EDGEFLAG. This will be done
2794 * automatically by brw_vec4_visitor::emit_urb_slot but we need to
2795 * ensure that prog_data->inputs_read is accurate.
2797 * In order to make late NIR passes aware of the change, we actually
2798 * whack shader->info.inputs_read instead. This is safe because we just
2799 * made a copy of the shader.
2802 assert(key
->copy_edgeflag
);
2803 shader
->info
.inputs_read
|= VERT_BIT_EDGEFLAG
;
2806 prog_data
->inputs_read
= shader
->info
.inputs_read
;
2807 prog_data
->double_inputs_read
= shader
->info
.vs
.double_inputs
;
2809 brw_nir_lower_vs_inputs(shader
, key
->gl_attrib_wa_flags
);
2810 brw_nir_lower_vue_outputs(shader
, is_scalar
);
2811 shader
= brw_postprocess_nir(shader
, compiler
, is_scalar
);
2813 prog_data
->base
.clip_distance_mask
=
2814 ((1 << shader
->info
.clip_distance_array_size
) - 1);
2815 prog_data
->base
.cull_distance_mask
=
2816 ((1 << shader
->info
.cull_distance_array_size
) - 1) <<
2817 shader
->info
.clip_distance_array_size
;
2819 unsigned nr_attribute_slots
= _mesa_bitcount_64(prog_data
->inputs_read
);
2821 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
2822 * incoming vertex attribute. So, add an extra slot.
2824 if (shader
->info
.system_values_read
&
2825 (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
) |
2826 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
2827 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
2828 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
2829 nr_attribute_slots
++;
2832 if (shader
->info
.system_values_read
&
2833 BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
))
2834 prog_data
->uses_basevertex
= true;
2836 if (shader
->info
.system_values_read
&
2837 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
))
2838 prog_data
->uses_baseinstance
= true;
2840 if (shader
->info
.system_values_read
&
2841 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
))
2842 prog_data
->uses_vertexid
= true;
2844 if (shader
->info
.system_values_read
&
2845 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))
2846 prog_data
->uses_instanceid
= true;
2848 /* gl_DrawID has its very own vec4 */
2849 if (shader
->info
.system_values_read
&
2850 BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
)) {
2851 prog_data
->uses_drawid
= true;
2852 nr_attribute_slots
++;
2855 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
2856 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
2857 * vec4 mode, the hardware appears to wedge unless we read something.
2860 prog_data
->base
.urb_read_length
=
2861 DIV_ROUND_UP(nr_attribute_slots
, 2);
2863 prog_data
->base
.urb_read_length
=
2864 DIV_ROUND_UP(MAX2(nr_attribute_slots
, 1), 2);
2866 prog_data
->nr_attribute_slots
= nr_attribute_slots
;
2868 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
2869 * (overwriting the original contents), we need to make sure the size is
2870 * the larger of the two.
2872 const unsigned vue_entries
=
2873 MAX2(nr_attribute_slots
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
2875 if (compiler
->devinfo
->gen
== 6) {
2876 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
2878 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
2879 /* On Cannonlake software shall not program an allocation size that
2880 * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
2882 if (compiler
->devinfo
->gen
== 10 &&
2883 prog_data
->base
.urb_entry_size
% 3 == 0)
2884 prog_data
->base
.urb_entry_size
++;
2887 if (INTEL_DEBUG
& DEBUG_VS
) {
2888 fprintf(stderr
, "VS Output ");
2889 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
2893 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
2895 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
2896 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
2897 shader
, 8, shader_time_index
);
2900 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2905 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
2907 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
2908 &prog_data
->base
.base
, v
.promoted_constants
,
2909 v
.runtime_check_aads_emit
, MESA_SHADER_VERTEX
);
2910 if (INTEL_DEBUG
& DEBUG_VS
) {
2911 const char *debug_name
=
2912 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
2913 shader
->info
.label
? shader
->info
.label
:
2917 g
.enable_debug(debug_name
);
2919 g
.generate_code(v
.cfg
, 8);
2920 assembly
= g
.get_assembly();
2924 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2926 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2927 shader
, mem_ctx
, shader_time_index
);
2930 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2935 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
2936 shader
, &prog_data
->base
, v
.cfg
);