src/intel/compiler/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include "brw_shader.h"
  28
  29 #ifdef __cplusplus
  30 #include "brw_ir_vec4.h"
  31 #include "brw_vec4_builder.h"
  32 #include "brw_vec4_live_variables.h"
  33 #endif
  34
  35 #include "compiler/glsl/ir.h"
  36 #include "compiler/nir/nir.h"
  37
  38
  39 #ifdef __cplusplus
  40 extern "C" {
  41 #endif
  42
  43 const unsigned *
  44 brw_vec4_generate_assembly(const struct brw_compiler *compiler,
  45                            void *log_data,
  46                            void *mem_ctx,
  47                            const nir_shader *nir,
  48                            struct brw_vue_prog_data *prog_data,
  49                            const struct cfg_t *cfg,
  50                            struct brw_compile_stats *stats);
  51
  52 #ifdef __cplusplus
  53 } /* extern "C" */
  54
  55 namespace brw {
  56 /**
  57  * The vertex shader front-end.
  58  *
  59  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
  60  * fixed-function) into VS IR.
  61  */
  62 class vec4_visitor : public backend_shader
  63 {
  64 public:
  65    vec4_visitor(const struct brw_compiler *compiler,
  66                 void *log_data,
  67                 const struct brw_sampler_prog_key_data *key,
  68                 struct brw_vue_prog_data *prog_data,
  69                 const nir_shader *shader,
  70                 void *mem_ctx,
  71                 bool no_spills,
  72                 int shader_time_index);
  73
  74    dst_reg dst_null_f()
  75    {
  76       return dst_reg(brw_null_reg());
  77    }
  78
  79    dst_reg dst_null_df()
  80    {
  81       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_DF));
  82    }
  83
  84    dst_reg dst_null_d()
  85    {
  86       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
  87    }
  88
  89    dst_reg dst_null_ud()
  90    {
  91       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
  92    }
  93
  94    const struct brw_sampler_prog_key_data * const key_tex;
  95    struct brw_vue_prog_data * const prog_data;
  96    char *fail_msg;
  97    bool failed;
  98
  99    /**
 100     * GLSL IR currently being processed, which is associated with our
 101     * driver IR instructions for debugging purposes.
 102     */
 103    const void *base_ir;
 104    const char *current_annotation;
 105
 106    int first_non_payload_grf;
 107    unsigned int max_grf;
 108    int *virtual_grf_start;
 109    int *virtual_grf_end;
 110    brw::vec4_live_variables *live_intervals;
 111
 112    bool need_all_constants_in_pull_buffer;
 113
 114    /* Regs for vertex results.  Generated at ir_variable visiting time
 115     * for the ir->location's used.
 116     */
 117    dst_reg output_reg[VARYING_SLOT_TESS_MAX][4];
 118    unsigned output_num_components[VARYING_SLOT_TESS_MAX][4];
 119    const char *output_reg_annotation[VARYING_SLOT_TESS_MAX];
 120    int uniforms;
 121
 122    src_reg shader_start_time;
 123
 124    bool run();
 125    void fail(const char *msg, ...);
 126
 127    int setup_uniforms(int payload_reg);
 128
 129    bool reg_allocate_trivial();
 130    bool reg_allocate();
 131    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 132    int choose_spill_reg(struct ra_graph *g);
 133    void spill_reg(unsigned spill_reg);
 134    void move_grf_array_access_to_scratch();
 135    void move_uniform_array_access_to_pull_constants();
 136    void move_push_constants_to_pull_constants();
 137    void split_uniform_registers();
 138    void pack_uniform_registers();
 139    void calculate_live_intervals();
 140    void invalidate_live_intervals();
 141    void split_virtual_grfs();
 142    bool opt_vector_float();
 143    bool opt_reduce_swizzle();
 144    bool dead_code_eliminate();
 145    int var_range_start(unsigned v, unsigned n) const;
 146    int var_range_end(unsigned v, unsigned n) const;
 147    bool virtual_grf_interferes(int a, int b);
 148    bool opt_cmod_propagation();
 149    bool opt_copy_propagation(bool do_constant_prop = true);
 150    bool opt_cse_local(bblock_t *block);
 151    bool opt_cse();
 152    bool opt_algebraic();
 153    bool opt_register_coalesce();
 154    bool eliminate_find_live_channel();
 155    bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
 156    void opt_set_dependency_control();
 157    void opt_schedule_instructions();
 158    void convert_to_hw_regs();
 159    void fixup_3src_null_dest();
 160
 161    bool is_supported_64bit_region(vec4_instruction *inst, unsigned arg);
 162    bool lower_simd_width();
 163    bool scalarize_df();
 164    bool lower_64bit_mad_to_mul_add();
 165    void apply_logical_swizzle(struct brw_reg *hw_reg,
 166                               vec4_instruction *inst, int arg);
 167
 168    vec4_instruction *emit(vec4_instruction *inst);
 169
 170    vec4_instruction *emit(enum opcode opcode);
 171    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
 172    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 173                           const src_reg &src0);
 174    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 175                           const src_reg &src0, const src_reg &src1);
 176    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 177                           const src_reg &src0, const src_reg &src1,
 178                           const src_reg &src2);
 179
 180    vec4_instruction *emit_before(bblock_t *block,
 181                                  vec4_instruction *inst,
 182                                  vec4_instruction *new_inst);
 183
 184 #define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
 185 #define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
 186 #define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src_reg &);
 187    EMIT1(MOV)
 188    EMIT1(NOT)
 189    EMIT1(RNDD)
 190    EMIT1(RNDE)
 191    EMIT1(RNDZ)
 192    EMIT1(FRC)
 193    EMIT1(F32TO16)
 194    EMIT1(F16TO32)
 195    EMIT2(ADD)
 196    EMIT2(MUL)
 197    EMIT2(MACH)
 198    EMIT2(MAC)
 199    EMIT2(AND)
 200    EMIT2(OR)
 201    EMIT2(XOR)
 202    EMIT2(DP3)
 203    EMIT2(DP4)
 204    EMIT2(DPH)
 205    EMIT2(SHL)
 206    EMIT2(SHR)
 207    EMIT2(ASR)
 208    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 209                          enum brw_conditional_mod condition);
 210    vec4_instruction *IF(src_reg src0, src_reg src1,
 211                         enum brw_conditional_mod condition);
 212    vec4_instruction *IF(enum brw_predicate predicate);
 213    EMIT1(SCRATCH_READ)
 214    EMIT2(SCRATCH_WRITE)
 215    EMIT3(LRP)
 216    EMIT1(BFREV)
 217    EMIT3(BFE)
 218    EMIT2(BFI1)
 219    EMIT3(BFI2)
 220    EMIT1(FBH)
 221    EMIT1(FBL)
 222    EMIT1(CBIT)
 223    EMIT3(MAD)
 224    EMIT2(ADDC)
 225    EMIT2(SUBB)
 226    EMIT1(DIM)
 227
 228 #undef EMIT1
 229 #undef EMIT2
 230 #undef EMIT3
 231
 232    int implied_mrf_writes(vec4_instruction *inst);
 233
 234    vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
 235                                  src_reg src0, src_reg src1);
 236
 237    /**
 238     * Copy any live channel from \p src to the first channel of the
 239     * result.
 240     */
 241    src_reg emit_uniformize(const src_reg &src);
 242
 243    /** Fix all float operands of a 3-source instruction. */
 244    void fix_float_operands(src_reg op[3], nir_alu_instr *instr);
 245
 246    src_reg fix_3src_operand(const src_reg &src);
 247    src_reg resolve_source_modifiers(const src_reg &src);
 248
 249    vec4_instruction *emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
 250                                const src_reg &src1 = src_reg());
 251
 252    src_reg fix_math_operand(const src_reg &src);
 253
 254    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 255    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 256    void emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0);
 257    void emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0);
 258    void emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0);
 259    void emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0);
 260
 261    void emit_texture(ir_texture_opcode op,
 262                      dst_reg dest,
 263                      const glsl_type *dest_type,
 264                      src_reg coordinate,
 265                      int coord_components,
 266                      src_reg shadow_comparator,
 267                      src_reg lod, src_reg lod2,
 268                      src_reg sample_index,
 269                      uint32_t constant_offset,
 270                      src_reg offset_value,
 271                      src_reg mcs,
 272                      uint32_t surface, src_reg surface_reg,
 273                      src_reg sampler_reg);
 274
 275    src_reg emit_mcs_fetch(const glsl_type *coordinate_type, src_reg coordinate,
 276                           src_reg surface);
 277    void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
 278
 279    void emit_ndc_computation();
 280    void emit_psiz_and_flags(dst_reg reg);
 281    vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying, int comp);
 282    virtual void emit_urb_slot(dst_reg reg, int varying);
 283
 284    void emit_shader_time_begin();
 285    void emit_shader_time_end();
 286    void emit_shader_time_write(int shader_time_subindex, src_reg value);
 287
 288    src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
 289                               src_reg *reladdr, int reg_offset);
 290    void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
 291                           dst_reg dst,
 292                           src_reg orig_src,
 293                           int base_offset);
 294    void emit_scratch_write(bblock_t *block, vec4_instruction *inst,
 295                            int base_offset);
 296    void emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
 297                                 dst_reg dst,
 298                                 src_reg orig_src,
 299                                 int base_offset,
 300                                 src_reg indirect);
 301    void emit_pull_constant_load_reg(dst_reg dst,
 302                                     src_reg surf_index,
 303                                     src_reg offset,
 304                                     bblock_t *before_block,
 305                                     vec4_instruction *before_inst);
 306    src_reg emit_resolve_reladdr(int scratch_loc[], bblock_t *block,
 307                                 vec4_instruction *inst, src_reg src);
 308
 309    void resolve_ud_negate(src_reg *reg);
 310
 311    bool lower_minmax();
 312
 313    src_reg get_timestamp();
 314
 315    void dump_instruction(backend_instruction *inst);
 316    void dump_instruction(backend_instruction *inst, FILE *file);
 317
 318    bool is_high_sampler(src_reg sampler);
 319
 320    bool optimize_predicate(nir_alu_instr *instr, enum brw_predicate *predicate);
 321
 322    void emit_conversion_from_double(dst_reg dst, src_reg src, bool saturate);
 323    void emit_conversion_to_double(dst_reg dst, src_reg src, bool saturate);
 324
 325    vec4_instruction *shuffle_64bit_data(dst_reg dst, src_reg src,
 326                                         bool for_write,
 327                                         bblock_t *block = NULL,
 328                                         vec4_instruction *ref = NULL);
 329
 330    virtual void emit_nir_code();
 331    virtual void nir_setup_uniforms();
 332    virtual void nir_emit_impl(nir_function_impl *impl);
 333    virtual void nir_emit_cf_list(exec_list *list);
 334    virtual void nir_emit_if(nir_if *if_stmt);
 335    virtual void nir_emit_loop(nir_loop *loop);
 336    virtual void nir_emit_block(nir_block *block);
 337    virtual void nir_emit_instr(nir_instr *instr);
 338    virtual void nir_emit_load_const(nir_load_const_instr *instr);
 339    src_reg get_nir_ssbo_intrinsic_index(nir_intrinsic_instr *instr);
 340    virtual void nir_emit_intrinsic(nir_intrinsic_instr *instr);
 341    virtual void nir_emit_alu(nir_alu_instr *instr);
 342    virtual void nir_emit_jump(nir_jump_instr *instr);
 343    virtual void nir_emit_texture(nir_tex_instr *instr);
 344    virtual void nir_emit_undef(nir_ssa_undef_instr *instr);
 345    virtual void nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr);
 346
 347    dst_reg get_nir_dest(const nir_dest &dest, enum brw_reg_type type);
 348    dst_reg get_nir_dest(const nir_dest &dest, nir_alu_type type);
 349    dst_reg get_nir_dest(const nir_dest &dest);
 350    src_reg get_nir_src(const nir_src &src, enum brw_reg_type type,
 351                        unsigned num_components = 4);
 352    src_reg get_nir_src(const nir_src &src, nir_alu_type type,
 353                        unsigned num_components = 4);
 354    src_reg get_nir_src(const nir_src &src,
 355                        unsigned num_components = 4);
 356    src_reg get_nir_src_imm(const nir_src &src);
 357    src_reg get_indirect_offset(nir_intrinsic_instr *instr);
 358
 359    dst_reg *nir_locals;
 360    dst_reg *nir_ssa_values;
 361
 362 protected:
 363    void emit_vertex();
 364    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 365                                    int reg_node_count);
 366    virtual void setup_payload() = 0;
 367    virtual void emit_prolog() = 0;
 368    virtual void emit_thread_end() = 0;
 369    virtual void emit_urb_write_header(int mrf) = 0;
 370    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 371    virtual void gs_emit_vertex(int stream_id);
 372    virtual void gs_end_primitive();
 373
 374 private:
 375    /**
 376     * If true, then register allocation should fail instead of spilling.
 377     */
 378    const bool no_spills;
 379
 380    int shader_time_index;
 381
 382    unsigned last_scratch; /**< measured in 32-byte (register size) units */
 383 };
 384
 385 } /* namespace brw */
 386 #endif /* __cplusplus */
 387
 388 #endif /* BRW_VEC4_H */