2 * Copyright © 2014 Intel Corporation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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25 #include "brw_vec4_live_variables.h"
28 /** @file brw_vec4_dead_code_eliminate.cpp
30 * Dataflow-aware dead code elimination.
32 * Walks the instruction list from the bottom, removing instructions that
33 * have results that both aren't used in later blocks and haven't been read
34 * yet in the tail end of this block.
40 vec4_visitor::dead_code_eliminate()
42 bool progress
= false;
44 const vec4_live_variables
&live_vars
= live_analysis
.require();
45 int num_vars
= live_vars
.num_vars
;
46 BITSET_WORD
*live
= rzalloc_array(NULL
, BITSET_WORD
, BITSET_WORDS(num_vars
));
47 BITSET_WORD
*flag_live
= rzalloc_array(NULL
, BITSET_WORD
, 1);
49 foreach_block_reverse_safe(block
, cfg
) {
50 memcpy(live
, live_vars
.block_data
[block
->num
].liveout
,
51 sizeof(BITSET_WORD
) * BITSET_WORDS(num_vars
));
52 memcpy(flag_live
, live_vars
.block_data
[block
->num
].flag_liveout
,
55 foreach_inst_in_block_reverse_safe(vec4_instruction
, inst
, block
) {
56 if ((inst
->dst
.file
== VGRF
&& !inst
->has_side_effects()) ||
57 (inst
->dst
.is_null() && inst
->writes_flag())){
58 bool result_live
[4] = { false };
59 if (inst
->dst
.file
== VGRF
) {
60 for (unsigned i
= 0; i
< DIV_ROUND_UP(inst
->size_written
, 16); i
++) {
61 for (int c
= 0; c
< 4; c
++) {
62 const unsigned v
= var_from_reg(alloc
, inst
->dst
, c
, i
);
63 result_live
[c
] |= BITSET_TEST(live
, v
);
67 for (unsigned c
= 0; c
< 4; c
++)
68 result_live
[c
] = BITSET_TEST(flag_live
, c
);
71 /* If the instruction can't do writemasking, then it's all or
74 if (!inst
->can_do_writemask(devinfo
)) {
75 bool result
= result_live
[0] | result_live
[1] |
76 result_live
[2] | result_live
[3];
77 result_live
[0] = result
;
78 result_live
[1] = result
;
79 result_live
[2] = result
;
80 result_live
[3] = result
;
83 if (inst
->writes_flag()) {
84 /* Independently calculate the usage of the flag components and
85 * the destination value components.
87 uint8_t flag_mask
= inst
->dst
.writemask
;
88 uint8_t dest_mask
= inst
->dst
.writemask
;
90 for (int c
= 0; c
< 4; c
++) {
91 if (!result_live
[c
] && dest_mask
& (1 << c
))
92 dest_mask
&= ~(1 << c
);
94 if (!BITSET_TEST(flag_live
, c
))
95 flag_mask
&= ~(1 << c
);
98 if (inst
->dst
.writemask
!= (flag_mask
| dest_mask
)) {
100 inst
->dst
.writemask
= flag_mask
| dest_mask
;
103 /* If none of the destination components are read, replace the
104 * destination register with the NULL register.
106 if (dest_mask
== 0) {
108 inst
->dst
= dst_reg(retype(brw_null_reg(), inst
->dst
.type
));
111 for (int c
= 0; c
< 4; c
++) {
112 if (!result_live
[c
] && inst
->dst
.writemask
& (1 << c
)) {
113 inst
->dst
.writemask
&= ~(1 << c
);
116 if (inst
->dst
.writemask
== 0) {
117 if (inst
->writes_accumulator
) {
118 inst
->dst
= dst_reg(retype(brw_null_reg(), inst
->dst
.type
));
120 inst
->opcode
= BRW_OPCODE_NOP
;
129 if (inst
->dst
.is_null() && inst
->writes_flag()) {
130 bool combined_live
= false;
131 for (unsigned c
= 0; c
< 4; c
++)
132 combined_live
|= BITSET_TEST(flag_live
, c
);
134 if (!combined_live
) {
135 inst
->opcode
= BRW_OPCODE_NOP
;
140 if (inst
->dst
.file
== VGRF
&& !inst
->predicate
&&
141 !inst
->is_align1_partial_write()) {
142 for (unsigned i
= 0; i
< DIV_ROUND_UP(inst
->size_written
, 16); i
++) {
143 for (int c
= 0; c
< 4; c
++) {
144 if (inst
->dst
.writemask
& (1 << c
)) {
145 const unsigned v
= var_from_reg(alloc
, inst
->dst
, c
, i
);
146 BITSET_CLEAR(live
, v
);
152 if (inst
->writes_flag() && !inst
->predicate
&& inst
->exec_size
== 8) {
153 for (unsigned c
= 0; c
< 4; c
++)
154 BITSET_CLEAR(flag_live
, c
);
157 if (inst
->opcode
== BRW_OPCODE_NOP
) {
162 for (int i
= 0; i
< 3; i
++) {
163 if (inst
->src
[i
].file
== VGRF
) {
164 for (unsigned j
= 0; j
< DIV_ROUND_UP(inst
->size_read(i
), 16); j
++) {
165 for (int c
= 0; c
< 4; c
++) {
166 const unsigned v
= var_from_reg(alloc
, inst
->src
[i
], c
, j
);
173 for (unsigned c
= 0; c
< 4; c
++) {
174 if (inst
->reads_flag(c
)) {
175 BITSET_SET(flag_live
, c
);
182 ralloc_free(flag_live
);
185 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);