src/intel/compiler/brw_vec4_dead_code_eliminate.cpp

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_vec4.h"
  25 #include "brw_vec4_live_variables.h"
  26 #include "brw_cfg.h"
  27
  28 /** @file brw_vec4_dead_code_eliminate.cpp
  29  *
  30  * Dataflow-aware dead code elimination.
  31  *
  32  * Walks the instruction list from the bottom, removing instructions that
  33  * have results that both aren't used in later blocks and haven't been read
  34  * yet in the tail end of this block.
  35  */
  36
  37 using namespace brw;
  38
  39 bool
  40 vec4_visitor::dead_code_eliminate()
  41 {
  42    bool progress = false;
  43
  44    calculate_live_intervals();
  45
  46    int num_vars = live_intervals->num_vars;
  47    BITSET_WORD *live = rzalloc_array(NULL, BITSET_WORD, BITSET_WORDS(num_vars));
  48    BITSET_WORD *flag_live = rzalloc_array(NULL, BITSET_WORD, 1);
  49
  50    foreach_block_reverse_safe(block, cfg) {
  51       memcpy(live, live_intervals->block_data[block->num].liveout,
  52              sizeof(BITSET_WORD) * BITSET_WORDS(num_vars));
  53       memcpy(flag_live, live_intervals->block_data[block->num].flag_liveout,
  54              sizeof(BITSET_WORD));
  55
  56       foreach_inst_in_block_reverse_safe(vec4_instruction, inst, block) {
  57          if ((inst->dst.file == VGRF && !inst->has_side_effects()) ||
  58              (inst->dst.is_null() && inst->writes_flag())){
  59             bool result_live[4] = { false };
  60             if (inst->dst.file == VGRF) {
  61                for (unsigned i = 0; i < DIV_ROUND_UP(inst->size_written, 16); i++) {
  62                   for (int c = 0; c < 4; c++) {
  63                      const unsigned v = var_from_reg(alloc, inst->dst, c, i);
  64                      result_live[c] |= BITSET_TEST(live, v);
  65                   }
  66                }
  67             } else {
  68                for (unsigned c = 0; c < 4; c++)
  69                   result_live[c] = BITSET_TEST(flag_live, c);
  70             }
  71
  72             /* If the instruction can't do writemasking, then it's all or
  73              * nothing.
  74              */
  75             if (!inst->can_do_writemask(devinfo)) {
  76                bool result = result_live[0] | result_live[1] |
  77                              result_live[2] | result_live[3];
  78                result_live[0] = result;
  79                result_live[1] = result;
  80                result_live[2] = result;
  81                result_live[3] = result;
  82             }
  83
  84             if (inst->writes_flag()) {
  85                /* Independently calculate the usage of the flag components and
  86                 * the destination value components.
  87                 */
  88                uint8_t flag_mask = inst->dst.writemask;
  89                uint8_t dest_mask = inst->dst.writemask;
  90
  91                for (int c = 0; c < 4; c++) {
  92                   if (!result_live[c] && dest_mask & (1 << c))
  93                      dest_mask &= ~(1 << c);
  94
  95                   if (!BITSET_TEST(flag_live, c))
  96                      flag_mask &= ~(1 << c);
  97                }
  98
  99                if (inst->dst.writemask != (flag_mask | dest_mask)) {
 100                   progress = true;
 101                   inst->dst.writemask = flag_mask | dest_mask;
 102                }
 103
 104                /* If none of the destination components are read, replace the
 105                 * destination register with the NULL register.
 106                 */
 107                if (dest_mask == 0) {
 108                   progress = true;
 109                   inst->dst = dst_reg(retype(brw_null_reg(), inst->dst.type));
 110                }
 111             } else {
 112                for (int c = 0; c < 4; c++) {
 113                   if (!result_live[c] && inst->dst.writemask & (1 << c)) {
 114                      inst->dst.writemask &= ~(1 << c);
 115                      progress = true;
 116
 117                      if (inst->dst.writemask == 0) {
 118                         if (inst->writes_accumulator) {
 119                            inst->dst = dst_reg(retype(brw_null_reg(), inst->dst.type));
 120                         } else {
 121                            inst->opcode = BRW_OPCODE_NOP;
 122                            break;
 123                         }
 124                      }
 125                   }
 126                }
 127             }
 128          }
 129
 130          if (inst->dst.is_null() && inst->writes_flag()) {
 131             bool combined_live = false;
 132             for (unsigned c = 0; c < 4; c++)
 133                combined_live |= BITSET_TEST(flag_live, c);
 134
 135             if (!combined_live) {
 136                inst->opcode = BRW_OPCODE_NOP;
 137                progress = true;
 138             }
 139          }
 140
 141          if (inst->dst.file == VGRF && !inst->predicate &&
 142              !inst->is_align1_partial_write()) {
 143             for (unsigned i = 0; i < DIV_ROUND_UP(inst->size_written, 16); i++) {
 144                for (int c = 0; c < 4; c++) {
 145                   if (inst->dst.writemask & (1 << c)) {
 146                      const unsigned v = var_from_reg(alloc, inst->dst, c, i);
 147                      BITSET_CLEAR(live, v);
 148                   }
 149                }
 150             }
 151          }
 152
 153          if (inst->writes_flag() && !inst->predicate && inst->exec_size == 8) {
 154             for (unsigned c = 0; c < 4; c++)
 155                BITSET_CLEAR(flag_live, c);
 156          }
 157
 158          if (inst->opcode == BRW_OPCODE_NOP) {
 159             inst->remove(block);
 160             continue;
 161          }
 162
 163          for (int i = 0; i < 3; i++) {
 164             if (inst->src[i].file == VGRF) {
 165                for (unsigned j = 0; j < DIV_ROUND_UP(inst->size_read(i), 16); j++) {
 166                   for (int c = 0; c < 4; c++) {
 167                      const unsigned v = var_from_reg(alloc, inst->src[i], c, j);
 168                      BITSET_SET(live, v);
 169                   }
 170                }
 171             }
 172          }
 173
 174          for (unsigned c = 0; c < 4; c++) {
 175             if (inst->reads_flag(c)) {
 176                BITSET_SET(flag_live, c);
 177             }
 178          }
 179       }
 180    }
 181
 182    ralloc_free(live);
 183    ralloc_free(flag_live);
 184
 185    if (progress)
 186       invalidate_live_intervals();
 187
 188    return progress;
 189 }