1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_debug.h"
31 generate_math1_gen4(struct brw_codegen
*p
,
32 vec4_instruction
*inst
,
38 brw_math_function(inst
->opcode
),
41 BRW_MATH_PRECISION_FULL
);
45 check_gen6_math_src_arg(struct brw_reg src
)
47 /* Source swizzles are ignored. */
50 assert(src
.swizzle
== BRW_SWIZZLE_XYZW
);
54 generate_math_gen6(struct brw_codegen
*p
,
55 vec4_instruction
*inst
,
60 /* Can't do writemask because math can't be align16. */
61 assert(dst
.writemask
== WRITEMASK_XYZW
);
62 /* Source swizzles are ignored. */
63 check_gen6_math_src_arg(src0
);
64 if (src1
.file
== BRW_GENERAL_REGISTER_FILE
)
65 check_gen6_math_src_arg(src1
);
67 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
68 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
69 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
73 generate_math2_gen4(struct brw_codegen
*p
,
74 vec4_instruction
*inst
,
79 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
82 * "Operand0[7]. For the INT DIV functions, this operand is the
85 * "Operand1[7]. For the INT DIV functions, this operand is the
88 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
89 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
90 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
92 brw_push_insn_state(p
);
93 brw_set_default_saturate(p
, false);
94 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
95 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
96 brw_pop_insn_state(p
);
100 brw_math_function(inst
->opcode
),
103 BRW_MATH_PRECISION_FULL
);
107 generate_tex(struct brw_codegen
*p
,
108 struct brw_vue_prog_data
*prog_data
,
109 gl_shader_stage stage
,
110 vec4_instruction
*inst
,
113 struct brw_reg surface_index
,
114 struct brw_reg sampler_index
)
116 const struct gen_device_info
*devinfo
= p
->devinfo
;
119 if (devinfo
->gen
>= 5) {
120 switch (inst
->opcode
) {
121 case SHADER_OPCODE_TEX
:
122 case SHADER_OPCODE_TXL
:
123 if (inst
->shadow_compare
) {
124 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
126 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
129 case SHADER_OPCODE_TXD
:
130 if (inst
->shadow_compare
) {
131 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
132 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
133 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
135 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
138 case SHADER_OPCODE_TXF
:
139 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
141 case SHADER_OPCODE_TXF_CMS_W
:
142 assert(devinfo
->gen
>= 9);
143 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
145 case SHADER_OPCODE_TXF_CMS
:
146 if (devinfo
->gen
>= 7)
147 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
149 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
151 case SHADER_OPCODE_TXF_MCS
:
152 assert(devinfo
->gen
>= 7);
153 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
155 case SHADER_OPCODE_TXS
:
156 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
158 case SHADER_OPCODE_TG4
:
159 if (inst
->shadow_compare
) {
160 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
162 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
165 case SHADER_OPCODE_TG4_OFFSET
:
166 if (inst
->shadow_compare
) {
167 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
169 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
172 case SHADER_OPCODE_SAMPLEINFO
:
173 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
176 unreachable("should not get here: invalid vec4 texture opcode");
179 switch (inst
->opcode
) {
180 case SHADER_OPCODE_TEX
:
181 case SHADER_OPCODE_TXL
:
182 if (inst
->shadow_compare
) {
183 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
184 assert(inst
->mlen
== 3);
186 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
187 assert(inst
->mlen
== 2);
190 case SHADER_OPCODE_TXD
:
191 /* There is no sample_d_c message; comparisons are done manually. */
192 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
193 assert(inst
->mlen
== 4);
195 case SHADER_OPCODE_TXF
:
196 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
197 assert(inst
->mlen
== 2);
199 case SHADER_OPCODE_TXS
:
200 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
201 assert(inst
->mlen
== 2);
204 unreachable("should not get here: invalid vec4 texture opcode");
208 assert(msg_type
!= -1);
210 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
212 /* Load the message header if present. If there's a texture offset, we need
213 * to set it up explicitly and load the offset bitfield. Otherwise, we can
214 * use an implied move from g0 to the first message register.
216 if (inst
->header_size
!= 0) {
217 if (devinfo
->gen
< 6 && !inst
->offset
) {
218 /* Set up an implied move from g0 to the MRF. */
219 src
= brw_vec8_grf(0, 0);
221 struct brw_reg header
=
222 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
225 /* Explicitly set up the message header by copying g0 to the MRF. */
226 brw_push_insn_state(p
);
227 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
228 brw_MOV(p
, header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
230 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
233 /* Set the texel offset bits in DWord 2. */
236 if (devinfo
->gen
>= 9)
237 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
238 * based on bit 22 in the header.
240 dw2
|= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
;
242 /* The VS, DS, and FS stages have the g0.2 payload delivered as 0,
243 * so header0.2 is 0 when g0 is copied. The HS and GS stages do
244 * not, so we must set to to 0 to avoid setting undesirable bits
245 * in the message header.
248 stage
== MESA_SHADER_TESS_CTRL
||
249 stage
== MESA_SHADER_GEOMETRY
) {
250 brw_MOV(p
, get_element_ud(header
, 2), brw_imm_ud(dw2
));
253 brw_adjust_sampler_state_pointer(p
, header
, sampler_index
);
254 brw_pop_insn_state(p
);
258 uint32_t return_format
;
261 case BRW_REGISTER_TYPE_D
:
262 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
264 case BRW_REGISTER_TYPE_UD
:
265 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
268 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
272 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
273 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
274 ? prog_data
->base
.binding_table
.gather_texture_start
275 : prog_data
->base
.binding_table
.texture_start
;
277 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
278 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
279 uint32_t surface
= surface_index
.ud
;
280 uint32_t sampler
= sampler_index
.ud
;
286 surface
+ base_binding_table_index
,
289 1, /* response length */
291 inst
->header_size
!= 0,
292 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
295 brw_mark_surface_used(&prog_data
->base
, sampler
+ base_binding_table_index
);
297 /* Non-constant sampler index. */
299 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
300 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
301 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
303 brw_push_insn_state(p
);
304 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
305 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
307 if (brw_regs_equal(&surface_reg
, &sampler_reg
)) {
308 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
310 if (sampler_reg
.file
== BRW_IMMEDIATE_VALUE
) {
311 brw_OR(p
, addr
, surface_reg
, brw_imm_ud(sampler_reg
.ud
<< 8));
313 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
314 brw_OR(p
, addr
, addr
, surface_reg
);
317 if (base_binding_table_index
)
318 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
319 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
321 brw_pop_insn_state(p
);
323 if (inst
->base_mrf
!= -1)
324 gen6_resolve_implied_move(p
, &src
, inst
->base_mrf
);
326 /* dst = send(offset, a0.0 | <descriptor>) */
327 brw_inst
*insn
= brw_send_indirect_message(
328 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
329 brw_set_sampler_message(p
, insn
,
334 inst
->mlen
/* mlen */,
335 inst
->header_size
!= 0 /* header */,
336 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
339 /* visitor knows more than we do about the surface limit required,
340 * so has already done marking.
346 generate_vs_urb_write(struct brw_codegen
*p
, vec4_instruction
*inst
)
349 brw_null_reg(), /* dest */
350 inst
->base_mrf
, /* starting mrf reg nr */
351 brw_vec8_grf(0, 0), /* src */
352 inst
->urb_write_flags
,
354 0, /* response len */
355 inst
->offset
, /* urb destination offset */
356 BRW_URB_SWIZZLE_INTERLEAVE
);
360 generate_gs_urb_write(struct brw_codegen
*p
, vec4_instruction
*inst
)
362 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
364 brw_null_reg(), /* dest */
365 inst
->base_mrf
, /* starting mrf reg nr */
367 inst
->urb_write_flags
,
369 0, /* response len */
370 inst
->offset
, /* urb destination offset */
371 BRW_URB_SWIZZLE_INTERLEAVE
);
375 generate_gs_urb_write_allocate(struct brw_codegen
*p
, vec4_instruction
*inst
)
377 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
379 /* We pass the temporary passed in src0 as the writeback register */
381 inst
->src
[0].as_brw_reg(), /* dest */
382 inst
->base_mrf
, /* starting mrf reg nr */
384 BRW_URB_WRITE_ALLOCATE_COMPLETE
,
386 1, /* response len */
387 inst
->offset
, /* urb destination offset */
388 BRW_URB_SWIZZLE_INTERLEAVE
);
390 /* Now put allocated urb handle in dst.0 */
391 brw_push_insn_state(p
);
392 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
393 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
394 brw_MOV(p
, get_element_ud(inst
->dst
.as_brw_reg(), 0),
395 get_element_ud(inst
->src
[0].as_brw_reg(), 0));
396 brw_pop_insn_state(p
);
400 generate_gs_thread_end(struct brw_codegen
*p
, vec4_instruction
*inst
)
402 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
404 brw_null_reg(), /* dest */
405 inst
->base_mrf
, /* starting mrf reg nr */
407 BRW_URB_WRITE_EOT
| inst
->urb_write_flags
,
409 0, /* response len */
410 0, /* urb destination offset */
411 BRW_URB_SWIZZLE_INTERLEAVE
);
415 generate_gs_set_write_offset(struct brw_codegen
*p
,
420 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
423 * Slot 0 Offset. This field, after adding to the Global Offset field
424 * in the message descriptor, specifies the offset (in 256-bit units)
425 * from the start of the URB entry, as referenced by URB Handle 0, at
426 * which the data will be accessed.
428 * Similar text describes DWORD M0.4, which is slot 1 offset.
430 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
431 * of the register for geometry shader invocations 0 and 1) by the
432 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
434 * We can do this with the following EU instruction:
436 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
438 brw_push_insn_state(p
);
439 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
440 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
441 assert(p
->devinfo
->gen
>= 7 &&
442 src1
.file
== BRW_IMMEDIATE_VALUE
&&
443 src1
.type
== BRW_REGISTER_TYPE_UD
&&
444 src1
.ud
<= USHRT_MAX
);
445 if (src0
.file
== BRW_IMMEDIATE_VALUE
) {
446 brw_MOV(p
, suboffset(stride(dst
, 2, 2, 1), 3),
447 brw_imm_ud(src0
.ud
* src1
.ud
));
449 brw_MUL(p
, suboffset(stride(dst
, 2, 2, 1), 3), stride(src0
, 8, 2, 4),
450 retype(src1
, BRW_REGISTER_TYPE_UW
));
452 brw_pop_insn_state(p
);
456 generate_gs_set_vertex_count(struct brw_codegen
*p
,
460 brw_push_insn_state(p
);
461 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
463 if (p
->devinfo
->gen
>= 8) {
464 /* Move the vertex count into the second MRF for the EOT write. */
465 brw_MOV(p
, retype(brw_message_reg(dst
.nr
+ 1), BRW_REGISTER_TYPE_UD
),
468 /* If we think of the src and dst registers as composed of 8 DWORDs each,
469 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
470 * them to WORDs, and then pack them into DWORD 2 of dst.
472 * It's easier to get the EU to do this if we think of the src and dst
473 * registers as composed of 16 WORDS each; then, we want to pick up the
474 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
477 * We can do that by the following EU instruction:
479 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
481 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
483 suboffset(stride(retype(dst
, BRW_REGISTER_TYPE_UW
), 2, 2, 1), 4),
484 stride(retype(src
, BRW_REGISTER_TYPE_UW
), 8, 1, 0));
486 brw_pop_insn_state(p
);
490 generate_gs_svb_write(struct brw_codegen
*p
,
491 struct brw_vue_prog_data
*prog_data
,
492 vec4_instruction
*inst
,
497 int binding
= inst
->sol_binding
;
498 bool final_write
= inst
->sol_final_write
;
500 brw_push_insn_state(p
);
501 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
502 /* Copy Vertex data into M0.x */
503 brw_MOV(p
, stride(dst
, 4, 4, 1),
504 stride(retype(src0
, BRW_REGISTER_TYPE_UD
), 4, 4, 1));
505 brw_pop_insn_state(p
);
507 brw_push_insn_state(p
);
510 final_write
? src1
: brw_null_reg(), /* dest == src1 */
512 dst
, /* src0 == previous dst */
513 BRW_GEN6_SOL_BINDING_START
+ binding
, /* binding_table_index */
514 final_write
); /* send_commit_msg */
516 /* Finally, wait for the write commit to occur so that we can proceed to
517 * other things safely.
519 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
521 * The write commit does not modify the destination register, but
522 * merely clears the dependency associated with the destination
523 * register. Thus, a simple “mov” instruction using the register as a
524 * source is sufficient to wait for the write commit to occur.
527 brw_MOV(p
, src1
, src1
);
529 brw_pop_insn_state(p
);
533 generate_gs_svb_set_destination_index(struct brw_codegen
*p
,
534 vec4_instruction
*inst
,
538 int vertex
= inst
->sol_vertex
;
539 brw_push_insn_state(p
);
540 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
541 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
542 brw_MOV(p
, get_element_ud(dst
, 5), get_element_ud(src
, vertex
));
543 brw_pop_insn_state(p
);
547 generate_gs_set_dword_2(struct brw_codegen
*p
,
551 brw_push_insn_state(p
);
552 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
553 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
554 brw_MOV(p
, suboffset(vec1(dst
), 2), suboffset(vec1(src
), 0));
555 brw_pop_insn_state(p
);
559 generate_gs_prepare_channel_masks(struct brw_codegen
*p
,
562 /* We want to left shift just DWORD 4 (the x component belonging to the
563 * second geometry shader invocation) by 4 bits. So generate the
566 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
568 dst
= suboffset(vec1(dst
), 4);
569 brw_push_insn_state(p
);
570 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
571 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
572 brw_SHL(p
, dst
, dst
, brw_imm_ud(4));
573 brw_pop_insn_state(p
);
577 generate_gs_set_channel_masks(struct brw_codegen
*p
,
581 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
584 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
586 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
587 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
588 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
589 * channel enable to determine the final channel enable. For the
590 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
591 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
592 * in the writeback message. For the URB_WRITE_OWORD &
593 * URB_WRITE_HWORD messages, when final channel enable is 1 it
594 * indicates that Vertex 1 DATA [3] will be written to the surface.
596 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
597 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
599 * 14 Vertex 1 DATA [2] Channel Mask
600 * 13 Vertex 1 DATA [1] Channel Mask
601 * 12 Vertex 1 DATA [0] Channel Mask
602 * 11 Vertex 0 DATA [3] Channel Mask
603 * 10 Vertex 0 DATA [2] Channel Mask
604 * 9 Vertex 0 DATA [1] Channel Mask
605 * 8 Vertex 0 DATA [0] Channel Mask
607 * (This is from a section of the PRM that is agnostic to the particular
608 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
609 * geometry shader invocations 0 and 1, respectively). Since we have the
610 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
611 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
612 * DWORD 4, we just need to OR them together and store the result in bits
615 * It's easier to get the EU to do this if we think of the src and dst
616 * registers as composed of 32 bytes each; then, we want to pick up the
617 * contents of bytes 0 and 16 from src, OR them together, and store them in
620 * We can do that by the following EU instruction:
622 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
624 * Note: this relies on the source register having zeros in (a) bits 7:4 of
625 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
626 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
627 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
628 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
629 * contain valid channel mask values (which are in the range 0x0-0xf).
631 dst
= retype(dst
, BRW_REGISTER_TYPE_UB
);
632 src
= retype(src
, BRW_REGISTER_TYPE_UB
);
633 brw_push_insn_state(p
);
634 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
635 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
636 brw_OR(p
, suboffset(vec1(dst
), 21), vec1(src
), suboffset(vec1(src
), 16));
637 brw_pop_insn_state(p
);
641 generate_gs_get_instance_id(struct brw_codegen
*p
,
644 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
645 * and store into dst.0 & dst.4. So generate the instruction:
647 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
649 brw_push_insn_state(p
);
650 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
651 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
652 struct brw_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
653 brw_SHR(p
, dst
, stride(r0
, 1, 4, 0),
654 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
));
655 brw_pop_insn_state(p
);
659 generate_gs_ff_sync_set_primitives(struct brw_codegen
*p
,
665 brw_push_insn_state(p
);
666 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
667 /* Save src0 data in 16:31 bits of dst.0 */
668 brw_AND(p
, suboffset(vec1(dst
), 0), suboffset(vec1(src0
), 0),
669 brw_imm_ud(0xffffu
));
670 brw_SHL(p
, suboffset(vec1(dst
), 0), suboffset(vec1(dst
), 0), brw_imm_ud(16));
671 /* Save src1 data in 0:15 bits of dst.0 */
672 brw_AND(p
, suboffset(vec1(src2
), 0), suboffset(vec1(src1
), 0),
673 brw_imm_ud(0xffffu
));
674 brw_OR(p
, suboffset(vec1(dst
), 0),
675 suboffset(vec1(dst
), 0),
676 suboffset(vec1(src2
), 0));
677 brw_pop_insn_state(p
);
681 generate_gs_ff_sync(struct brw_codegen
*p
,
682 vec4_instruction
*inst
,
687 /* This opcode uses an implied MRF register for:
688 * - the header of the ff_sync message. And as such it is expected to be
689 * initialized to r0 before calling here.
690 * - the destination where we will write the allocated URB handle.
692 struct brw_reg header
=
693 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
695 /* Overwrite dword 0 of the header (SO vertices to write) and
696 * dword 1 (number of primitives written).
698 brw_push_insn_state(p
);
699 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
700 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
701 brw_MOV(p
, get_element_ud(header
, 0), get_element_ud(src1
, 0));
702 brw_MOV(p
, get_element_ud(header
, 1), get_element_ud(src0
, 0));
703 brw_pop_insn_state(p
);
705 /* Allocate URB handle in dst */
711 1, /* response length */
714 /* Now put allocated urb handle in header.0 */
715 brw_push_insn_state(p
);
716 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
717 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
718 brw_MOV(p
, get_element_ud(header
, 0), get_element_ud(dst
, 0));
720 /* src1 is not an immediate when we use transform feedback */
721 if (src1
.file
!= BRW_IMMEDIATE_VALUE
) {
722 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
723 brw_MOV(p
, brw_vec4_grf(src1
.nr
, 0), brw_vec4_grf(dst
.nr
, 1));
726 brw_pop_insn_state(p
);
730 generate_gs_set_primitive_id(struct brw_codegen
*p
, struct brw_reg dst
)
732 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
733 struct brw_reg src
= brw_vec8_grf(0, 0);
734 brw_push_insn_state(p
);
735 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
736 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
737 brw_MOV(p
, get_element_ud(dst
, 0), get_element_ud(src
, 1));
738 brw_pop_insn_state(p
);
742 generate_tcs_get_instance_id(struct brw_codegen
*p
, struct brw_reg dst
)
744 const struct gen_device_info
*devinfo
= p
->devinfo
;
745 const bool ivb
= devinfo
->is_ivybridge
|| devinfo
->is_baytrail
;
747 /* "Instance Count" comes as part of the payload in r0.2 bits 23:17.
749 * Since we operate in SIMD4x2 mode, we need run half as many threads
750 * as necessary. So we assign (2i + 1, 2i) as the thread counts. We
751 * shift right by one less to accomplish the multiplication by two.
753 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
754 struct brw_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
756 brw_push_insn_state(p
);
757 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
759 const int mask
= ivb
? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
760 const int shift
= ivb
? 16 : 17;
762 brw_AND(p
, get_element_ud(dst
, 0), get_element_ud(r0
, 2), brw_imm_ud(mask
));
763 brw_SHR(p
, get_element_ud(dst
, 0), get_element_ud(dst
, 0),
764 brw_imm_ud(shift
- 1));
765 brw_ADD(p
, get_element_ud(dst
, 4), get_element_ud(dst
, 0), brw_imm_ud(1));
767 brw_pop_insn_state(p
);
771 generate_tcs_urb_write(struct brw_codegen
*p
,
772 vec4_instruction
*inst
,
773 struct brw_reg urb_header
)
775 const struct gen_device_info
*devinfo
= p
->devinfo
;
777 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
778 brw_set_dest(p
, send
, brw_null_reg());
779 brw_set_src0(p
, send
, urb_header
);
781 brw_set_message_descriptor(p
, send
, BRW_SFID_URB
,
782 inst
->mlen
/* mlen */, 0 /* rlen */,
783 true /* header */, false /* eot */);
784 brw_inst_set_urb_opcode(devinfo
, send
, BRW_URB_OPCODE_WRITE_OWORD
);
785 brw_inst_set_urb_global_offset(devinfo
, send
, inst
->offset
);
786 if (inst
->urb_write_flags
& BRW_URB_WRITE_EOT
) {
787 brw_inst_set_eot(devinfo
, send
, 1);
789 brw_inst_set_urb_per_slot_offset(devinfo
, send
, 1);
790 brw_inst_set_urb_swizzle_control(devinfo
, send
, BRW_URB_SWIZZLE_INTERLEAVE
);
793 /* what happens to swizzles? */
798 generate_tcs_input_urb_offsets(struct brw_codegen
*p
,
800 struct brw_reg vertex
,
801 struct brw_reg offset
)
803 /* Generates an URB read/write message header for HS/DS operation.
804 * Inputs are a vertex index, and a byte offset from the beginning of
807 /* If `vertex` is not an immediate, we clobber a0.0 */
809 assert(vertex
.file
== BRW_IMMEDIATE_VALUE
|| vertex
.file
== BRW_GENERAL_REGISTER_FILE
);
810 assert(vertex
.type
== BRW_REGISTER_TYPE_UD
|| vertex
.type
== BRW_REGISTER_TYPE_D
);
812 assert(dst
.file
== BRW_GENERAL_REGISTER_FILE
);
814 brw_push_insn_state(p
);
815 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
816 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
817 brw_MOV(p
, dst
, brw_imm_ud(0));
819 /* m0.5 bits 8-15 are channel enables */
820 brw_MOV(p
, get_element_ud(dst
, 5), brw_imm_ud(0xff00));
822 /* m0.0-0.1: URB handles */
823 if (vertex
.file
== BRW_IMMEDIATE_VALUE
) {
824 uint32_t vertex_index
= vertex
.ud
;
825 struct brw_reg index_reg
= brw_vec1_grf(
826 1 + (vertex_index
>> 3), vertex_index
& 7);
828 brw_MOV(p
, vec2(get_element_ud(dst
, 0)),
829 retype(index_reg
, BRW_REGISTER_TYPE_UD
));
831 /* Use indirect addressing. ICP Handles are DWords (single channels
832 * of a register) and start at g1.0.
834 * In order to start our region at g1.0, we add 8 to the vertex index,
835 * effectively skipping over the 8 channels in g0.0. This gives us a
836 * DWord offset to the ICP Handle.
838 * Indirect addressing works in terms of bytes, so we then multiply
839 * the DWord offset by 4 (by shifting left by 2).
841 struct brw_reg addr
= brw_address_reg(0);
843 /* bottom half: m0.0 = g[1.0 + vertex.0]UD */
844 brw_ADD(p
, addr
, retype(get_element_ud(vertex
, 0), BRW_REGISTER_TYPE_UW
),
846 brw_SHL(p
, addr
, addr
, brw_imm_uw(2));
847 brw_MOV(p
, get_element_ud(dst
, 0), deref_1ud(brw_indirect(0, 0), 0));
849 /* top half: m0.1 = g[1.0 + vertex.4]UD */
850 brw_ADD(p
, addr
, retype(get_element_ud(vertex
, 4), BRW_REGISTER_TYPE_UW
),
852 brw_SHL(p
, addr
, addr
, brw_imm_uw(2));
853 brw_MOV(p
, get_element_ud(dst
, 1), deref_1ud(brw_indirect(0, 0), 0));
856 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
857 if (offset
.file
!= ARF
)
858 brw_MOV(p
, vec2(get_element_ud(dst
, 3)), stride(offset
, 4, 1, 0));
860 brw_pop_insn_state(p
);
865 generate_tcs_output_urb_offsets(struct brw_codegen
*p
,
867 struct brw_reg write_mask
,
868 struct brw_reg offset
)
870 /* Generates an URB read/write message header for HS/DS operation, for the patch URB entry. */
871 assert(dst
.file
== BRW_GENERAL_REGISTER_FILE
|| dst
.file
== BRW_MESSAGE_REGISTER_FILE
);
873 assert(write_mask
.file
== BRW_IMMEDIATE_VALUE
);
874 assert(write_mask
.type
== BRW_REGISTER_TYPE_UD
);
876 brw_push_insn_state(p
);
878 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
879 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
880 brw_MOV(p
, dst
, brw_imm_ud(0));
882 unsigned mask
= write_mask
.ud
;
884 /* m0.5 bits 15:12 and 11:8 are channel enables */
885 brw_MOV(p
, get_element_ud(dst
, 5), brw_imm_ud((mask
<< 8) | (mask
<< 12)));
887 /* HS patch URB handle is delivered in r0.0 */
888 struct brw_reg urb_handle
= brw_vec1_grf(0, 0);
890 /* m0.0-0.1: URB handles */
891 brw_MOV(p
, vec2(get_element_ud(dst
, 0)),
892 retype(urb_handle
, BRW_REGISTER_TYPE_UD
));
894 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
895 if (offset
.file
!= ARF
)
896 brw_MOV(p
, vec2(get_element_ud(dst
, 3)), stride(offset
, 4, 1, 0));
898 brw_pop_insn_state(p
);
902 generate_tes_create_input_read_header(struct brw_codegen
*p
,
905 brw_push_insn_state(p
);
906 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
907 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
909 /* Initialize the register to 0 */
910 brw_MOV(p
, dst
, brw_imm_ud(0));
912 /* Enable all the channels in m0.5 bits 15:8 */
913 brw_MOV(p
, get_element_ud(dst
, 5), brw_imm_ud(0xff00));
915 /* Copy g1.3 (the patch URB handle) to m0.0 and m0.1. For safety,
916 * mask out irrelevant "Reserved" bits, as they're not marked MBZ.
918 brw_AND(p
, vec2(get_element_ud(dst
, 0)),
919 retype(brw_vec1_grf(1, 3), BRW_REGISTER_TYPE_UD
),
921 brw_pop_insn_state(p
);
925 generate_tes_add_indirect_urb_offset(struct brw_codegen
*p
,
927 struct brw_reg header
,
928 struct brw_reg offset
)
930 brw_push_insn_state(p
);
931 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
932 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
934 brw_MOV(p
, dst
, header
);
935 /* m0.3-0.4: 128-bit-granular offsets into the URB from the handles */
936 brw_MOV(p
, vec2(get_element_ud(dst
, 3)), stride(offset
, 4, 1, 0));
938 brw_pop_insn_state(p
);
942 generate_vec4_urb_read(struct brw_codegen
*p
,
943 vec4_instruction
*inst
,
945 struct brw_reg header
)
947 const struct gen_device_info
*devinfo
= p
->devinfo
;
949 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
950 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
952 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
953 brw_set_dest(p
, send
, dst
);
954 brw_set_src0(p
, send
, header
);
956 brw_set_message_descriptor(p
, send
, BRW_SFID_URB
,
957 1 /* mlen */, 1 /* rlen */,
958 true /* header */, false /* eot */);
959 brw_inst_set_urb_opcode(devinfo
, send
, BRW_URB_OPCODE_READ_OWORD
);
960 brw_inst_set_urb_swizzle_control(devinfo
, send
, BRW_URB_SWIZZLE_INTERLEAVE
);
961 brw_inst_set_urb_per_slot_offset(devinfo
, send
, 1);
963 brw_inst_set_urb_global_offset(devinfo
, send
, inst
->offset
);
967 generate_tcs_release_input(struct brw_codegen
*p
,
968 struct brw_reg header
,
969 struct brw_reg vertex
,
970 struct brw_reg is_unpaired
)
972 const struct gen_device_info
*devinfo
= p
->devinfo
;
974 assert(vertex
.file
== BRW_IMMEDIATE_VALUE
);
975 assert(vertex
.type
== BRW_REGISTER_TYPE_UD
);
977 /* m0.0-0.1: URB handles */
978 struct brw_reg urb_handles
=
979 retype(brw_vec2_grf(1 + (vertex
.ud
>> 3), vertex
.ud
& 7),
980 BRW_REGISTER_TYPE_UD
);
982 brw_push_insn_state(p
);
983 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
984 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
985 brw_MOV(p
, header
, brw_imm_ud(0));
986 brw_MOV(p
, vec2(get_element_ud(header
, 0)), urb_handles
);
987 brw_pop_insn_state(p
);
989 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
990 brw_set_dest(p
, send
, brw_null_reg());
991 brw_set_src0(p
, send
, header
);
992 brw_set_message_descriptor(p
, send
, BRW_SFID_URB
,
993 1 /* mlen */, 0 /* rlen */,
994 true /* header */, false /* eot */);
995 brw_inst_set_urb_opcode(devinfo
, send
, BRW_URB_OPCODE_READ_OWORD
);
996 brw_inst_set_urb_complete(devinfo
, send
, 1);
997 brw_inst_set_urb_swizzle_control(devinfo
, send
, is_unpaired
.ud
?
998 BRW_URB_SWIZZLE_NONE
:
999 BRW_URB_SWIZZLE_INTERLEAVE
);
1003 generate_tcs_thread_end(struct brw_codegen
*p
, vec4_instruction
*inst
)
1005 struct brw_reg header
= brw_message_reg(inst
->base_mrf
);
1007 brw_push_insn_state(p
);
1008 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1009 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1010 brw_MOV(p
, header
, brw_imm_ud(0));
1011 brw_MOV(p
, get_element_ud(header
, 5), brw_imm_ud(WRITEMASK_X
<< 8));
1012 brw_MOV(p
, get_element_ud(header
, 0),
1013 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1014 brw_MOV(p
, brw_message_reg(inst
->base_mrf
+ 1), brw_imm_ud(0u));
1015 brw_pop_insn_state(p
);
1018 brw_null_reg(), /* dest */
1019 inst
->base_mrf
, /* starting mrf reg nr */
1021 BRW_URB_WRITE_EOT
| BRW_URB_WRITE_OWORD
|
1022 BRW_URB_WRITE_USE_CHANNEL_MASKS
,
1024 0, /* response len */
1025 0, /* urb destination offset */
1030 generate_tes_get_primitive_id(struct brw_codegen
*p
, struct brw_reg dst
)
1032 brw_push_insn_state(p
);
1033 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1034 brw_MOV(p
, dst
, retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_D
));
1035 brw_pop_insn_state(p
);
1039 generate_tcs_get_primitive_id(struct brw_codegen
*p
, struct brw_reg dst
)
1041 brw_push_insn_state(p
);
1042 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1043 brw_MOV(p
, dst
, retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
1044 brw_pop_insn_state(p
);
1048 generate_tcs_create_barrier_header(struct brw_codegen
*p
,
1049 struct brw_vue_prog_data
*prog_data
,
1052 const struct gen_device_info
*devinfo
= p
->devinfo
;
1053 const bool ivb
= devinfo
->is_ivybridge
|| devinfo
->is_baytrail
;
1054 struct brw_reg m0_2
= get_element_ud(dst
, 2);
1055 unsigned instances
= ((struct brw_tcs_prog_data
*) prog_data
)->instances
;
1057 brw_push_insn_state(p
);
1058 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1059 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1061 /* Zero the message header */
1062 brw_MOV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
1064 /* Copy "Barrier ID" from r0.2, bits 16:13 (Gen7.5+) or 15:12 (Gen7) */
1066 retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
1067 brw_imm_ud(ivb
? INTEL_MASK(15, 12) : INTEL_MASK(16, 13)));
1069 /* Shift it up to bits 27:24. */
1070 brw_SHL(p
, m0_2
, get_element_ud(dst
, 2), brw_imm_ud(ivb
? 12 : 11));
1072 /* Set the Barrier Count and the enable bit */
1073 brw_OR(p
, m0_2
, m0_2
, brw_imm_ud(instances
<< 9 | (1 << 15)));
1075 brw_pop_insn_state(p
);
1079 generate_oword_dual_block_offsets(struct brw_codegen
*p
,
1081 struct brw_reg index
)
1083 int second_vertex_offset
;
1085 if (p
->devinfo
->gen
>= 6)
1086 second_vertex_offset
= 1;
1088 second_vertex_offset
= 16;
1090 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
1092 /* Set up M1 (message payload). Only the block offsets in M1.0 and
1093 * M1.4 are used, and the rest are ignored.
1095 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
1096 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
1097 struct brw_reg index_0
= suboffset(vec1(index
), 0);
1098 struct brw_reg index_4
= suboffset(vec1(index
), 4);
1100 brw_push_insn_state(p
);
1101 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1102 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1104 brw_MOV(p
, m1_0
, index_0
);
1106 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1107 index_4
.ud
+= second_vertex_offset
;
1108 brw_MOV(p
, m1_4
, index_4
);
1110 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
1113 brw_pop_insn_state(p
);
1117 generate_unpack_flags(struct brw_codegen
*p
,
1120 brw_push_insn_state(p
);
1121 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1122 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1124 struct brw_reg flags
= brw_flag_reg(0, 0);
1125 struct brw_reg dst_0
= suboffset(vec1(dst
), 0);
1126 struct brw_reg dst_4
= suboffset(vec1(dst
), 4);
1128 brw_AND(p
, dst_0
, flags
, brw_imm_ud(0x0f));
1129 brw_AND(p
, dst_4
, flags
, brw_imm_ud(0xf0));
1130 brw_SHR(p
, dst_4
, dst_4
, brw_imm_ud(4));
1132 brw_pop_insn_state(p
);
1136 generate_scratch_read(struct brw_codegen
*p
,
1137 vec4_instruction
*inst
,
1139 struct brw_reg index
)
1141 const struct gen_device_info
*devinfo
= p
->devinfo
;
1142 struct brw_reg header
= brw_vec8_grf(0, 0);
1144 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1146 generate_oword_dual_block_offsets(p
, brw_message_reg(inst
->base_mrf
+ 1),
1151 if (devinfo
->gen
>= 6)
1152 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1153 else if (devinfo
->gen
== 5 || devinfo
->is_g4x
)
1154 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1156 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1158 const unsigned target_cache
=
1159 devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
1160 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
1161 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
;
1163 /* Each of the 8 channel enables is considered for whether each
1166 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1167 brw_set_dest(p
, send
, dst
);
1168 brw_set_src0(p
, send
, header
);
1169 if (devinfo
->gen
< 6)
1170 brw_inst_set_cond_modifier(devinfo
, send
, inst
->base_mrf
);
1171 brw_set_dp_read_message(p
, send
,
1172 brw_scratch_surface_idx(p
),
1173 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
1174 msg_type
, target_cache
,
1176 true, /* header_present */
1181 generate_scratch_write(struct brw_codegen
*p
,
1182 vec4_instruction
*inst
,
1185 struct brw_reg index
)
1187 const struct gen_device_info
*devinfo
= p
->devinfo
;
1188 const unsigned target_cache
=
1189 (devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
1190 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
1191 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
);
1192 struct brw_reg header
= brw_vec8_grf(0, 0);
1195 /* If the instruction is predicated, we'll predicate the send, not
1198 brw_set_default_predicate_control(p
, false);
1200 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1202 generate_oword_dual_block_offsets(p
, brw_message_reg(inst
->base_mrf
+ 1),
1206 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
1207 retype(src
, BRW_REGISTER_TYPE_D
));
1211 if (devinfo
->gen
>= 7)
1212 msg_type
= GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE
;
1213 else if (devinfo
->gen
== 6)
1214 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
1216 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
1218 brw_set_default_predicate_control(p
, inst
->predicate
);
1220 /* Pre-gen6, we have to specify write commits to ensure ordering
1221 * between reads and writes within a thread. Afterwards, that's
1222 * guaranteed and write commits only matter for inter-thread
1225 if (devinfo
->gen
>= 6) {
1226 write_commit
= false;
1228 /* The visitor set up our destination register to be g0. This
1229 * means that when the next read comes along, we will end up
1230 * reading from g0 and causing a block on the write commit. For
1231 * write-after-read, we are relying on the value of the previous
1232 * read being used (and thus blocking on completion) before our
1233 * write is executed. This means we have to be careful in
1234 * instruction scheduling to not violate this assumption.
1236 write_commit
= true;
1239 /* Each of the 8 channel enables is considered for whether each
1242 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1243 brw_set_dest(p
, send
, dst
);
1244 brw_set_src0(p
, send
, header
);
1245 if (devinfo
->gen
< 6)
1246 brw_inst_set_cond_modifier(p
->devinfo
, send
, inst
->base_mrf
);
1247 brw_set_dp_write_message(p
, send
,
1248 brw_scratch_surface_idx(p
),
1249 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
1253 true, /* header present */
1254 false, /* not a render target write */
1255 write_commit
, /* rlen */
1261 generate_pull_constant_load(struct brw_codegen
*p
,
1262 struct brw_vue_prog_data
*prog_data
,
1263 vec4_instruction
*inst
,
1265 struct brw_reg index
,
1266 struct brw_reg offset
)
1268 const struct gen_device_info
*devinfo
= p
->devinfo
;
1269 const unsigned target_cache
=
1270 (devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_SAMPLER_CACHE
:
1271 BRW_DATAPORT_READ_TARGET_DATA_CACHE
);
1272 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1273 index
.type
== BRW_REGISTER_TYPE_UD
);
1274 uint32_t surf_index
= index
.ud
;
1276 struct brw_reg header
= brw_vec8_grf(0, 0);
1278 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1280 if (devinfo
->gen
>= 6) {
1281 if (offset
.file
== BRW_IMMEDIATE_VALUE
) {
1282 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1),
1283 BRW_REGISTER_TYPE_D
),
1284 brw_imm_d(offset
.ud
>> 4));
1286 brw_SHR(p
, retype(brw_message_reg(inst
->base_mrf
+ 1),
1287 BRW_REGISTER_TYPE_D
),
1288 offset
, brw_imm_d(4));
1291 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1),
1292 BRW_REGISTER_TYPE_D
),
1298 if (devinfo
->gen
>= 6)
1299 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1300 else if (devinfo
->gen
== 5 || devinfo
->is_g4x
)
1301 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1303 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1305 /* Each of the 8 channel enables is considered for whether each
1308 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1309 brw_set_dest(p
, send
, dst
);
1310 brw_set_src0(p
, send
, header
);
1311 if (devinfo
->gen
< 6)
1312 brw_inst_set_cond_modifier(p
->devinfo
, send
, inst
->base_mrf
);
1313 brw_set_dp_read_message(p
, send
,
1315 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
1319 true, /* header_present */
1324 generate_get_buffer_size(struct brw_codegen
*p
,
1325 struct brw_vue_prog_data
*prog_data
,
1326 vec4_instruction
*inst
,
1329 struct brw_reg surf_index
)
1331 assert(p
->devinfo
->gen
>= 7);
1332 assert(surf_index
.type
== BRW_REGISTER_TYPE_UD
&&
1333 surf_index
.file
== BRW_IMMEDIATE_VALUE
);
1341 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
1342 1, /* response length */
1344 inst
->header_size
> 0,
1345 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1346 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
1348 brw_mark_surface_used(&prog_data
->base
, surf_index
.ud
);
1352 generate_pull_constant_load_gen7(struct brw_codegen
*p
,
1353 struct brw_vue_prog_data
*prog_data
,
1354 vec4_instruction
*inst
,
1356 struct brw_reg surf_index
,
1357 struct brw_reg offset
)
1359 assert(surf_index
.type
== BRW_REGISTER_TYPE_UD
);
1361 if (surf_index
.file
== BRW_IMMEDIATE_VALUE
) {
1363 brw_inst
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1364 brw_set_dest(p
, insn
, dst
);
1365 brw_set_src0(p
, insn
, offset
);
1366 brw_set_sampler_message(p
, insn
,
1368 0, /* LD message ignores sampler unit */
1369 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1372 inst
->header_size
!= 0,
1373 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1376 brw_mark_surface_used(&prog_data
->base
, surf_index
.ud
);
1380 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1382 brw_push_insn_state(p
);
1383 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1384 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1386 /* a0.0 = surf_index & 0xff */
1387 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1388 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1389 brw_set_dest(p
, insn_and
, addr
);
1390 brw_set_src0(p
, insn_and
, vec1(retype(surf_index
, BRW_REGISTER_TYPE_UD
)));
1391 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1393 brw_pop_insn_state(p
);
1395 /* dst = send(offset, a0.0 | <descriptor>) */
1396 brw_inst
*insn
= brw_send_indirect_message(
1397 p
, BRW_SFID_SAMPLER
, dst
, offset
, addr
);
1398 brw_set_sampler_message(p
, insn
,
1401 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1404 inst
->header_size
!= 0,
1405 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1411 generate_set_simd4x2_header_gen9(struct brw_codegen
*p
,
1415 brw_push_insn_state(p
);
1416 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1418 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1419 brw_MOV(p
, vec8(dst
), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1421 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1422 brw_MOV(p
, get_element_ud(dst
, 2),
1423 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
));
1425 brw_pop_insn_state(p
);
1429 generate_mov_indirect(struct brw_codegen
*p
,
1431 struct brw_reg dst
, struct brw_reg reg
,
1432 struct brw_reg indirect
)
1434 assert(indirect
.type
== BRW_REGISTER_TYPE_UD
);
1435 assert(p
->devinfo
->gen
>= 6);
1437 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
* (REG_SIZE
/ 2);
1439 /* This instruction acts in align1 mode */
1440 assert(dst
.writemask
== WRITEMASK_XYZW
);
1442 if (indirect
.file
== BRW_IMMEDIATE_VALUE
) {
1443 imm_byte_offset
+= indirect
.ud
;
1445 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
1446 reg
.subnr
= (imm_byte_offset
/ (REG_SIZE
/ 2)) % 2;
1447 unsigned shift
= (imm_byte_offset
/ 4) % 4;
1448 reg
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
1450 brw_MOV(p
, dst
, reg
);
1452 brw_push_insn_state(p
);
1453 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1454 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1456 struct brw_reg addr
= vec8(brw_address_reg(0));
1458 /* We need to move the indirect value into the address register. In
1459 * order to make things make some sense, we want to respect at least the
1460 * X component of the swizzle. In order to do that, we need to convert
1461 * the subnr (probably 0) to an align1 subnr and add in the swizzle.
1463 assert(brw_is_single_value_swizzle(indirect
.swizzle
));
1464 indirect
.subnr
= (indirect
.subnr
* 4 + BRW_GET_SWZ(indirect
.swizzle
, 0));
1466 /* We then use a region of <8,4,0>:uw to pick off the first 2 bytes of
1467 * the indirect and splat it out to all four channels of the given half
1470 indirect
.subnr
*= 2;
1471 indirect
= stride(retype(indirect
, BRW_REGISTER_TYPE_UW
), 8, 4, 0);
1472 brw_ADD(p
, addr
, indirect
, brw_imm_uw(imm_byte_offset
));
1474 /* Now we need to incorporate the swizzle from the source register */
1475 if (reg
.swizzle
!= BRW_SWIZZLE_XXXX
) {
1476 uint32_t uv_swiz
= BRW_GET_SWZ(reg
.swizzle
, 0) << 2 |
1477 BRW_GET_SWZ(reg
.swizzle
, 1) << 6 |
1478 BRW_GET_SWZ(reg
.swizzle
, 2) << 10 |
1479 BRW_GET_SWZ(reg
.swizzle
, 3) << 14;
1480 uv_swiz
|= uv_swiz
<< 16;
1482 brw_ADD(p
, addr
, addr
, brw_imm_uv(uv_swiz
));
1485 brw_MOV(p
, dst
, retype(brw_VxH_indirect(0, 0), reg
.type
));
1487 brw_pop_insn_state(p
);
1492 generate_code(struct brw_codegen
*p
,
1493 const struct brw_compiler
*compiler
,
1495 const nir_shader
*nir
,
1496 struct brw_vue_prog_data
*prog_data
,
1497 const struct cfg_t
*cfg
)
1499 const struct gen_device_info
*devinfo
= p
->devinfo
;
1500 const char *stage_abbrev
= _mesa_shader_stage_to_abbrev(nir
->info
.stage
);
1501 bool debug_flag
= INTEL_DEBUG
&
1502 intel_debug_flag_for_shader_stage(nir
->info
.stage
);
1503 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1504 int spill_count
= 0, fill_count
= 0;
1507 foreach_block_and_inst (block
, vec4_instruction
, inst
, cfg
) {
1508 struct brw_reg src
[3], dst
;
1510 if (unlikely(debug_flag
))
1511 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1513 for (unsigned int i
= 0; i
< 3; i
++) {
1514 src
[i
] = inst
->src
[i
].as_brw_reg();
1516 dst
= inst
->dst
.as_brw_reg();
1518 brw_set_default_predicate_control(p
, inst
->predicate
);
1519 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1520 brw_set_default_flag_reg(p
, inst
->flag_subreg
/ 2, inst
->flag_subreg
% 2);
1521 brw_set_default_saturate(p
, inst
->saturate
);
1522 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1523 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1525 assert(inst
->group
% inst
->exec_size
== 0);
1526 assert(inst
->group
% 4 == 0);
1528 /* There are some instructions where the destination is 64-bit
1529 * but we retype it to a smaller type. In that case, we cannot
1530 * double the exec_size.
1532 const bool is_df
= (get_exec_type_size(inst
) == 8 ||
1533 inst
->dst
.type
== BRW_REGISTER_TYPE_DF
) &&
1534 inst
->opcode
!= VEC4_OPCODE_PICK_LOW_32BIT
&&
1535 inst
->opcode
!= VEC4_OPCODE_PICK_HIGH_32BIT
&&
1536 inst
->opcode
!= VEC4_OPCODE_SET_LOW_32BIT
&&
1537 inst
->opcode
!= VEC4_OPCODE_SET_HIGH_32BIT
;
1539 unsigned exec_size
= inst
->exec_size
;
1540 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&& is_df
)
1543 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1545 if (!inst
->force_writemask_all
)
1546 brw_set_default_group(p
, inst
->group
);
1548 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1549 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1551 unsigned pre_emit_nr_insn
= p
->nr_insn
;
1553 switch (inst
->opcode
) {
1554 case VEC4_OPCODE_UNPACK_UNIFORM
:
1555 case BRW_OPCODE_MOV
:
1556 brw_MOV(p
, dst
, src
[0]);
1558 case BRW_OPCODE_ADD
:
1559 brw_ADD(p
, dst
, src
[0], src
[1]);
1561 case BRW_OPCODE_MUL
:
1562 brw_MUL(p
, dst
, src
[0], src
[1]);
1564 case BRW_OPCODE_MACH
:
1565 brw_MACH(p
, dst
, src
[0], src
[1]);
1568 case BRW_OPCODE_MAD
:
1569 assert(devinfo
->gen
>= 6);
1570 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1573 case BRW_OPCODE_FRC
:
1574 brw_FRC(p
, dst
, src
[0]);
1576 case BRW_OPCODE_RNDD
:
1577 brw_RNDD(p
, dst
, src
[0]);
1579 case BRW_OPCODE_RNDE
:
1580 brw_RNDE(p
, dst
, src
[0]);
1582 case BRW_OPCODE_RNDZ
:
1583 brw_RNDZ(p
, dst
, src
[0]);
1586 case BRW_OPCODE_AND
:
1587 brw_AND(p
, dst
, src
[0], src
[1]);
1590 brw_OR(p
, dst
, src
[0], src
[1]);
1592 case BRW_OPCODE_XOR
:
1593 brw_XOR(p
, dst
, src
[0], src
[1]);
1595 case BRW_OPCODE_NOT
:
1596 brw_NOT(p
, dst
, src
[0]);
1598 case BRW_OPCODE_ASR
:
1599 brw_ASR(p
, dst
, src
[0], src
[1]);
1601 case BRW_OPCODE_SHR
:
1602 brw_SHR(p
, dst
, src
[0], src
[1]);
1604 case BRW_OPCODE_SHL
:
1605 brw_SHL(p
, dst
, src
[0], src
[1]);
1608 case BRW_OPCODE_CMP
:
1609 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1611 case BRW_OPCODE_SEL
:
1612 brw_SEL(p
, dst
, src
[0], src
[1]);
1615 case BRW_OPCODE_DPH
:
1616 brw_DPH(p
, dst
, src
[0], src
[1]);
1619 case BRW_OPCODE_DP4
:
1620 brw_DP4(p
, dst
, src
[0], src
[1]);
1623 case BRW_OPCODE_DP3
:
1624 brw_DP3(p
, dst
, src
[0], src
[1]);
1627 case BRW_OPCODE_DP2
:
1628 brw_DP2(p
, dst
, src
[0], src
[1]);
1631 case BRW_OPCODE_F32TO16
:
1632 assert(devinfo
->gen
>= 7);
1633 brw_F32TO16(p
, dst
, src
[0]);
1636 case BRW_OPCODE_F16TO32
:
1637 assert(devinfo
->gen
>= 7);
1638 brw_F16TO32(p
, dst
, src
[0]);
1641 case BRW_OPCODE_LRP
:
1642 assert(devinfo
->gen
>= 6);
1643 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1646 case BRW_OPCODE_BFREV
:
1647 assert(devinfo
->gen
>= 7);
1648 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1649 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1651 case BRW_OPCODE_FBH
:
1652 assert(devinfo
->gen
>= 7);
1653 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1655 case BRW_OPCODE_FBL
:
1656 assert(devinfo
->gen
>= 7);
1657 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1658 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1660 case BRW_OPCODE_LZD
:
1661 brw_LZD(p
, dst
, src
[0]);
1663 case BRW_OPCODE_CBIT
:
1664 assert(devinfo
->gen
>= 7);
1665 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1666 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1668 case BRW_OPCODE_ADDC
:
1669 assert(devinfo
->gen
>= 7);
1670 brw_ADDC(p
, dst
, src
[0], src
[1]);
1672 case BRW_OPCODE_SUBB
:
1673 assert(devinfo
->gen
>= 7);
1674 brw_SUBB(p
, dst
, src
[0], src
[1]);
1676 case BRW_OPCODE_MAC
:
1677 brw_MAC(p
, dst
, src
[0], src
[1]);
1680 case BRW_OPCODE_BFE
:
1681 assert(devinfo
->gen
>= 7);
1682 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1685 case BRW_OPCODE_BFI1
:
1686 assert(devinfo
->gen
>= 7);
1687 brw_BFI1(p
, dst
, src
[0], src
[1]);
1689 case BRW_OPCODE_BFI2
:
1690 assert(devinfo
->gen
>= 7);
1691 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1695 if (!inst
->src
[0].is_null()) {
1696 /* The instruction has an embedded compare (only allowed on gen6) */
1697 assert(devinfo
->gen
== 6);
1698 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1700 brw_inst
*if_inst
= brw_IF(p
, BRW_EXECUTE_8
);
1701 brw_inst_set_pred_control(p
->devinfo
, if_inst
, inst
->predicate
);
1705 case BRW_OPCODE_ELSE
:
1708 case BRW_OPCODE_ENDIF
:
1713 brw_DO(p
, BRW_EXECUTE_8
);
1716 case BRW_OPCODE_BREAK
:
1718 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1720 case BRW_OPCODE_CONTINUE
:
1722 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1725 case BRW_OPCODE_WHILE
:
1730 case SHADER_OPCODE_RCP
:
1731 case SHADER_OPCODE_RSQ
:
1732 case SHADER_OPCODE_SQRT
:
1733 case SHADER_OPCODE_EXP2
:
1734 case SHADER_OPCODE_LOG2
:
1735 case SHADER_OPCODE_SIN
:
1736 case SHADER_OPCODE_COS
:
1737 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1738 if (devinfo
->gen
>= 7) {
1739 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1741 } else if (devinfo
->gen
== 6) {
1742 generate_math_gen6(p
, inst
, dst
, src
[0], brw_null_reg());
1744 generate_math1_gen4(p
, inst
, dst
, src
[0]);
1748 case SHADER_OPCODE_POW
:
1749 case SHADER_OPCODE_INT_QUOTIENT
:
1750 case SHADER_OPCODE_INT_REMAINDER
:
1751 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1752 if (devinfo
->gen
>= 7) {
1753 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1754 } else if (devinfo
->gen
== 6) {
1755 generate_math_gen6(p
, inst
, dst
, src
[0], src
[1]);
1757 generate_math2_gen4(p
, inst
, dst
, src
[0], src
[1]);
1761 case SHADER_OPCODE_TEX
:
1762 case SHADER_OPCODE_TXD
:
1763 case SHADER_OPCODE_TXF
:
1764 case SHADER_OPCODE_TXF_CMS
:
1765 case SHADER_OPCODE_TXF_CMS_W
:
1766 case SHADER_OPCODE_TXF_MCS
:
1767 case SHADER_OPCODE_TXL
:
1768 case SHADER_OPCODE_TXS
:
1769 case SHADER_OPCODE_TG4
:
1770 case SHADER_OPCODE_TG4_OFFSET
:
1771 case SHADER_OPCODE_SAMPLEINFO
:
1772 generate_tex(p
, prog_data
, nir
->info
.stage
,
1773 inst
, dst
, src
[0], src
[1], src
[2]);
1776 case SHADER_OPCODE_GET_BUFFER_SIZE
:
1777 generate_get_buffer_size(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1780 case VS_OPCODE_URB_WRITE
:
1781 generate_vs_urb_write(p
, inst
);
1784 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1785 generate_scratch_read(p
, inst
, dst
, src
[0]);
1789 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1790 generate_scratch_write(p
, inst
, dst
, src
[0], src
[1]);
1794 case VS_OPCODE_PULL_CONSTANT_LOAD
:
1795 generate_pull_constant_load(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1798 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
1799 generate_pull_constant_load_gen7(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1802 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
1803 generate_set_simd4x2_header_gen9(p
, inst
, dst
);
1806 case GS_OPCODE_URB_WRITE
:
1807 generate_gs_urb_write(p
, inst
);
1810 case GS_OPCODE_URB_WRITE_ALLOCATE
:
1811 generate_gs_urb_write_allocate(p
, inst
);
1814 case GS_OPCODE_SVB_WRITE
:
1815 generate_gs_svb_write(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1818 case GS_OPCODE_SVB_SET_DST_INDEX
:
1819 generate_gs_svb_set_destination_index(p
, inst
, dst
, src
[0]);
1822 case GS_OPCODE_THREAD_END
:
1823 generate_gs_thread_end(p
, inst
);
1826 case GS_OPCODE_SET_WRITE_OFFSET
:
1827 generate_gs_set_write_offset(p
, dst
, src
[0], src
[1]);
1830 case GS_OPCODE_SET_VERTEX_COUNT
:
1831 generate_gs_set_vertex_count(p
, dst
, src
[0]);
1834 case GS_OPCODE_FF_SYNC
:
1835 generate_gs_ff_sync(p
, inst
, dst
, src
[0], src
[1]);
1838 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
1839 generate_gs_ff_sync_set_primitives(p
, dst
, src
[0], src
[1], src
[2]);
1842 case GS_OPCODE_SET_PRIMITIVE_ID
:
1843 generate_gs_set_primitive_id(p
, dst
);
1846 case GS_OPCODE_SET_DWORD_2
:
1847 generate_gs_set_dword_2(p
, dst
, src
[0]);
1850 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
1851 generate_gs_prepare_channel_masks(p
, dst
);
1854 case GS_OPCODE_SET_CHANNEL_MASKS
:
1855 generate_gs_set_channel_masks(p
, dst
, src
[0]);
1858 case GS_OPCODE_GET_INSTANCE_ID
:
1859 generate_gs_get_instance_id(p
, dst
);
1862 case SHADER_OPCODE_SHADER_TIME_ADD
:
1863 brw_shader_time_add(p
, src
[0],
1864 prog_data
->base
.binding_table
.shader_time_start
);
1865 brw_mark_surface_used(&prog_data
->base
,
1866 prog_data
->base
.binding_table
.shader_time_start
);
1869 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1870 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1871 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
, inst
->mlen
,
1872 !inst
->dst
.is_null(), inst
->header_size
);
1875 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1876 assert(!inst
->header_size
);
1877 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1878 brw_untyped_surface_read(p
, dst
, src
[0], src
[1], inst
->mlen
,
1882 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1883 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1884 brw_untyped_surface_write(p
, src
[0], src
[1], inst
->mlen
,
1885 src
[2].ud
, inst
->header_size
);
1888 case SHADER_OPCODE_TYPED_ATOMIC
:
1889 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1890 brw_typed_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
, inst
->mlen
,
1891 !inst
->dst
.is_null(), inst
->header_size
);
1894 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1895 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1896 brw_typed_surface_read(p
, dst
, src
[0], src
[1], inst
->mlen
,
1897 src
[2].ud
, inst
->header_size
);
1900 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1901 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1902 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
,
1903 src
[2].ud
, inst
->header_size
);
1906 case SHADER_OPCODE_MEMORY_FENCE
:
1907 brw_memory_fence(p
, dst
);
1910 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
1911 const struct brw_reg mask
=
1912 brw_stage_has_packed_dispatch(devinfo
, nir
->info
.stage
,
1913 &prog_data
->base
) ? brw_imm_ud(~0u) :
1915 brw_find_live_channel(p
, dst
, mask
);
1919 case SHADER_OPCODE_BROADCAST
:
1920 assert(inst
->force_writemask_all
);
1921 brw_broadcast(p
, dst
, src
[0], src
[1]);
1924 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
1925 generate_unpack_flags(p
, dst
);
1928 case VEC4_OPCODE_MOV_BYTES
: {
1929 /* Moves the low byte from each channel, using an Align1 access mode
1930 * and a <4,1,0> source region.
1932 assert(src
[0].type
== BRW_REGISTER_TYPE_UB
||
1933 src
[0].type
== BRW_REGISTER_TYPE_B
);
1935 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1936 src
[0].vstride
= BRW_VERTICAL_STRIDE_4
;
1937 src
[0].width
= BRW_WIDTH_1
;
1938 src
[0].hstride
= BRW_HORIZONTAL_STRIDE_0
;
1939 brw_MOV(p
, dst
, src
[0]);
1940 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1944 case VEC4_OPCODE_DOUBLE_TO_F32
:
1945 case VEC4_OPCODE_DOUBLE_TO_D32
:
1946 case VEC4_OPCODE_DOUBLE_TO_U32
: {
1947 assert(type_sz(src
[0].type
) == 8);
1948 assert(type_sz(dst
.type
) == 8);
1950 brw_reg_type dst_type
;
1952 switch (inst
->opcode
) {
1953 case VEC4_OPCODE_DOUBLE_TO_F32
:
1954 dst_type
= BRW_REGISTER_TYPE_F
;
1956 case VEC4_OPCODE_DOUBLE_TO_D32
:
1957 dst_type
= BRW_REGISTER_TYPE_D
;
1959 case VEC4_OPCODE_DOUBLE_TO_U32
:
1960 dst_type
= BRW_REGISTER_TYPE_UD
;
1963 unreachable("Not supported conversion");
1965 dst
= retype(dst
, dst_type
);
1967 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1969 /* When converting from DF->F, we set destination's stride as 2 as an
1970 * aligment requirement. But in IVB/BYT, each DF implicitly writes
1971 * two floats, being the first one the converted value. So we don't
1972 * need to explicitly set stride 2, but 1.
1974 struct brw_reg spread_dst
;
1975 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
)
1976 spread_dst
= stride(dst
, 8, 4, 1);
1978 spread_dst
= stride(dst
, 8, 4, 2);
1980 brw_MOV(p
, spread_dst
, src
[0]);
1982 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1986 case VEC4_OPCODE_TO_DOUBLE
: {
1987 assert(type_sz(src
[0].type
) == 4);
1988 assert(type_sz(dst
.type
) == 8);
1990 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1992 brw_MOV(p
, dst
, src
[0]);
1994 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1998 case VEC4_OPCODE_PICK_LOW_32BIT
:
1999 case VEC4_OPCODE_PICK_HIGH_32BIT
: {
2000 /* Stores the low/high 32-bit of each 64-bit element in src[0] into
2001 * dst using ALIGN1 mode and a <8,4,2>:UD region on the source.
2003 assert(type_sz(src
[0].type
) == 8);
2004 assert(type_sz(dst
.type
) == 4);
2006 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
2008 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
2009 dst
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
2011 src
[0] = retype(src
[0], BRW_REGISTER_TYPE_UD
);
2012 if (inst
->opcode
== VEC4_OPCODE_PICK_HIGH_32BIT
)
2013 src
[0] = suboffset(src
[0], 1);
2014 src
[0] = spread(src
[0], 2);
2015 brw_MOV(p
, dst
, src
[0]);
2017 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2021 case VEC4_OPCODE_SET_LOW_32BIT
:
2022 case VEC4_OPCODE_SET_HIGH_32BIT
: {
2023 /* Reads consecutive 32-bit elements from src[0] and writes
2024 * them to the low/high 32-bit of each 64-bit element in dst.
2026 assert(type_sz(src
[0].type
) == 4);
2027 assert(type_sz(dst
.type
) == 8);
2029 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
2031 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
2032 if (inst
->opcode
== VEC4_OPCODE_SET_HIGH_32BIT
)
2033 dst
= suboffset(dst
, 1);
2034 dst
.hstride
= BRW_HORIZONTAL_STRIDE_2
;
2036 src
[0] = retype(src
[0], BRW_REGISTER_TYPE_UD
);
2037 brw_MOV(p
, dst
, src
[0]);
2039 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2043 case VEC4_OPCODE_PACK_BYTES
: {
2046 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
2048 * but destinations' only regioning is horizontal stride, so instead we
2049 * have to use two instructions:
2051 * mov(4) dst<1>:UB src<4,1,0>:UB
2052 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
2054 * where they pack the four bytes from the low and high four DW.
2056 assert(_mesa_is_pow_two(dst
.writemask
) &&
2057 dst
.writemask
!= 0);
2058 unsigned offset
= __builtin_ctz(dst
.writemask
);
2060 dst
.type
= BRW_REGISTER_TYPE_UB
;
2062 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
2064 src
[0].type
= BRW_REGISTER_TYPE_UB
;
2065 src
[0].vstride
= BRW_VERTICAL_STRIDE_4
;
2066 src
[0].width
= BRW_WIDTH_1
;
2067 src
[0].hstride
= BRW_HORIZONTAL_STRIDE_0
;
2068 dst
.subnr
= offset
* 4;
2069 struct brw_inst
*insn
= brw_MOV(p
, dst
, src
[0]);
2070 brw_inst_set_exec_size(p
->devinfo
, insn
, BRW_EXECUTE_4
);
2071 brw_inst_set_no_dd_clear(p
->devinfo
, insn
, true);
2072 brw_inst_set_no_dd_check(p
->devinfo
, insn
, inst
->no_dd_check
);
2075 dst
.subnr
= 16 + offset
* 4;
2076 insn
= brw_MOV(p
, dst
, src
[0]);
2077 brw_inst_set_exec_size(p
->devinfo
, insn
, BRW_EXECUTE_4
);
2078 brw_inst_set_no_dd_clear(p
->devinfo
, insn
, inst
->no_dd_clear
);
2079 brw_inst_set_no_dd_check(p
->devinfo
, insn
, true);
2081 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2085 case TCS_OPCODE_URB_WRITE
:
2086 generate_tcs_urb_write(p
, inst
, src
[0]);
2089 case VEC4_OPCODE_URB_READ
:
2090 generate_vec4_urb_read(p
, inst
, dst
, src
[0]);
2093 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
2094 generate_tcs_input_urb_offsets(p
, dst
, src
[0], src
[1]);
2097 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
2098 generate_tcs_output_urb_offsets(p
, dst
, src
[0], src
[1]);
2101 case TCS_OPCODE_GET_INSTANCE_ID
:
2102 generate_tcs_get_instance_id(p
, dst
);
2105 case TCS_OPCODE_GET_PRIMITIVE_ID
:
2106 generate_tcs_get_primitive_id(p
, dst
);
2109 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
2110 generate_tcs_create_barrier_header(p
, prog_data
, dst
);
2113 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
2114 generate_tes_create_input_read_header(p
, dst
);
2117 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
2118 generate_tes_add_indirect_urb_offset(p
, dst
, src
[0], src
[1]);
2121 case TES_OPCODE_GET_PRIMITIVE_ID
:
2122 generate_tes_get_primitive_id(p
, dst
);
2125 case TCS_OPCODE_SRC0_010_IS_ZERO
:
2126 /* If src_reg had stride like fs_reg, we wouldn't need this. */
2127 brw_MOV(p
, brw_null_reg(), stride(src
[0], 0, 1, 0));
2130 case TCS_OPCODE_RELEASE_INPUT
:
2131 generate_tcs_release_input(p
, dst
, src
[0], src
[1]);
2134 case TCS_OPCODE_THREAD_END
:
2135 generate_tcs_thread_end(p
, inst
);
2138 case SHADER_OPCODE_BARRIER
:
2139 brw_barrier(p
, src
[0]);
2143 case SHADER_OPCODE_MOV_INDIRECT
:
2144 generate_mov_indirect(p
, inst
, dst
, src
[0], src
[1]);
2147 case BRW_OPCODE_DIM
:
2148 assert(devinfo
->is_haswell
);
2149 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2150 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2151 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2155 unreachable("Unsupported opcode");
2158 if (inst
->opcode
== VEC4_OPCODE_PACK_BYTES
) {
2159 /* Handled dependency hints in the generator. */
2161 assert(!inst
->conditional_mod
);
2162 } else if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2163 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
2164 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2165 "emitting more than 1 instruction");
2167 brw_inst
*last
= &p
->store
[pre_emit_nr_insn
];
2169 if (inst
->conditional_mod
)
2170 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2171 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2172 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2176 brw_set_uip_jip(p
, 0);
2178 /* end of program sentinel */
2179 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2184 if (unlikely(debug_flag
))
2186 brw_validate_instructions(devinfo
, p
->store
,
2187 0, p
->next_insn_offset
,
2190 int before_size
= p
->next_insn_offset
;
2191 brw_compact_instructions(p
, 0, disasm_info
);
2192 int after_size
= p
->next_insn_offset
;
2194 if (unlikely(debug_flag
)) {
2195 fprintf(stderr
, "Native code for %s %s shader %s:\n",
2196 nir
->info
.label
? nir
->info
.label
: "unnamed",
2197 _mesa_shader_stage_to_string(nir
->info
.stage
), nir
->info
.name
);
2199 fprintf(stderr
, "%s vec4 shader: %d instructions. %d loops. %u cycles. %d:%d "
2200 "spills:fills. Compacted %d to %d bytes (%.0f%%)\n",
2201 stage_abbrev
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2202 spill_count
, fill_count
, before_size
, after_size
,
2203 100.0f
* (before_size
- after_size
) / before_size
);
2205 dump_assembly(p
->store
, disasm_info
);
2207 ralloc_free(disasm_info
);
2210 compiler
->shader_debug_log(log_data
,
2211 "%s vec4 shader: %d inst, %d loops, %u cycles, "
2212 "%d:%d spills:fills, compacted %d to %d bytes.",
2213 stage_abbrev
, before_size
/ 16,
2214 loop_count
, cfg
->cycle_count
, spill_count
,
2215 fill_count
, before_size
, after_size
);
2219 extern "C" const unsigned *
2220 brw_vec4_generate_assembly(const struct brw_compiler
*compiler
,
2223 const nir_shader
*nir
,
2224 struct brw_vue_prog_data
*prog_data
,
2225 const struct cfg_t
*cfg
)
2227 struct brw_codegen
*p
= rzalloc(mem_ctx
, struct brw_codegen
);
2228 brw_init_codegen(compiler
->devinfo
, p
, mem_ctx
);
2229 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2231 generate_code(p
, compiler
, log_data
, nir
, prog_data
, cfg
);
2233 return brw_get_program(p
, &prog_data
->base
.program_size
);