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25 * \file brw_vec4_gs_visitor.cpp
27 * Geometry-shader-specific code derived from the vec4_visitor class.
30 #include "brw_vec4_gs_visitor.h"
31 #include "gen6_gs_visitor.h"
35 #include "common/gen_debug.h"
39 vec4_gs_visitor::vec4_gs_visitor(const struct brw_compiler
*compiler
,
41 struct brw_gs_compile
*c
,
42 struct brw_gs_prog_data
*prog_data
,
43 const nir_shader
*shader
,
46 int shader_time_index
)
47 : vec4_visitor(compiler
, log_data
, &c
->key
.tex
,
48 &prog_data
->base
, shader
, mem_ctx
,
49 no_spills
, shader_time_index
),
51 gs_prog_data(prog_data
)
57 vec4_gs_visitor::make_reg_for_system_value(int location
)
59 dst_reg
*reg
= new(mem_ctx
) dst_reg(this, glsl_type::int_type
);
62 case SYSTEM_VALUE_INVOCATION_ID
:
63 this->current_annotation
= "initialize gl_InvocationID";
64 if (gs_prog_data
->invocations
> 1)
65 emit(GS_OPCODE_GET_INSTANCE_ID
, *reg
);
67 emit(MOV(*reg
, brw_imm_ud(0)));
70 unreachable("not reached");
76 static inline struct brw_reg
77 attribute_to_hw_reg(int attr
, brw_reg_type type
, bool interleaved
)
81 unsigned width
= REG_SIZE
/ 2 / MAX2(4, type_sz(type
));
83 reg
= stride(brw_vecn_grf(width
, attr
/ 2, (attr
% 2) * 4), 0, width
, 1);
85 reg
= brw_vecn_grf(width
, attr
, 0);
93 * Replace each register of type ATTR in this->instructions with a reference
94 * to a fixed HW register.
96 * If interleaved is true, then each attribute takes up half a register, with
97 * register N containing attribute 2*N in its first half and attribute 2*N+1
98 * in its second half (this corresponds to the payload setup used by geometry
99 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
100 * false, then each attribute takes up a whole register, with register N
101 * containing attribute N (this corresponds to the payload setup used by
102 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
105 vec4_gs_visitor::setup_varying_inputs(int payload_reg
,
106 int attributes_per_reg
)
108 /* For geometry shaders there are N copies of the input attributes, where N
109 * is the number of input vertices. attribute_map[BRW_VARYING_SLOT_COUNT *
110 * i + j] represents attribute j for vertex i.
112 * Note that GS inputs are read from the VUE 256 bits (2 vec4's) at a time,
113 * so the total number of input slots that will be delivered to the GS (and
114 * thus the stride of the input arrays) is urb_read_length * 2.
116 const unsigned num_input_vertices
= nir
->info
.gs
.vertices_in
;
117 assert(num_input_vertices
<= MAX_GS_INPUT_VERTICES
);
118 unsigned input_array_stride
= prog_data
->urb_read_length
* 2;
120 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
121 for (int i
= 0; i
< 3; i
++) {
122 if (inst
->src
[i
].file
!= ATTR
)
125 assert(inst
->src
[i
].offset
% REG_SIZE
== 0);
126 int grf
= payload_reg
* attributes_per_reg
+
127 inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ REG_SIZE
;
130 attribute_to_hw_reg(grf
, inst
->src
[i
].type
, attributes_per_reg
> 1);
131 reg
.swizzle
= inst
->src
[i
].swizzle
;
132 if (inst
->src
[i
].abs
)
134 if (inst
->src
[i
].negate
)
141 int regs_used
= ALIGN(input_array_stride
* num_input_vertices
,
142 attributes_per_reg
) / attributes_per_reg
;
143 return payload_reg
+ regs_used
;
147 vec4_gs_visitor::setup_payload()
149 /* If we are in dual instanced or single mode, then attributes are going
150 * to be interleaved, so one register contains two attribute slots.
152 int attributes_per_reg
=
153 prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
? 1 : 2;
157 /* The payload always contains important data in r0, which contains
158 * the URB handles that are passed on to the URB write at the end
163 /* If the shader uses gl_PrimitiveIDIn, that goes in r1. */
164 if (gs_prog_data
->include_primitive_id
)
167 reg
= setup_uniforms(reg
);
169 reg
= setup_varying_inputs(reg
, attributes_per_reg
);
171 this->first_non_payload_grf
= reg
;
176 vec4_gs_visitor::emit_prolog()
178 /* In vertex shaders, r0.2 is guaranteed to be initialized to zero. In
179 * geometry shaders, it isn't (it contains a bunch of information we don't
180 * need, like the input primitive type). We need r0.2 to be zero in order
181 * to build scratch read/write messages correctly (otherwise this value
182 * will be interpreted as a global offset, causing us to do our scratch
183 * reads/writes to garbage memory). So just set it to zero at the top of
186 this->current_annotation
= "clear r0.2";
187 dst_reg
r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD
));
188 vec4_instruction
*inst
= emit(GS_OPCODE_SET_DWORD_2
, r0
, brw_imm_ud(0u));
189 inst
->force_writemask_all
= true;
191 /* Create a virtual register to hold the vertex count */
192 this->vertex_count
= src_reg(this, glsl_type::uint_type
);
194 /* Initialize the vertex_count register to 0 */
195 this->current_annotation
= "initialize vertex_count";
196 inst
= emit(MOV(dst_reg(this->vertex_count
), brw_imm_ud(0u)));
197 inst
->force_writemask_all
= true;
199 if (c
->control_data_header_size_bits
> 0) {
200 /* Create a virtual register to hold the current set of control data
203 this->control_data_bits
= src_reg(this, glsl_type::uint_type
);
205 /* If we're outputting more than 32 control data bits, then EmitVertex()
206 * will set control_data_bits to 0 after emitting the first vertex.
207 * Otherwise, we need to initialize it to 0 here.
209 if (c
->control_data_header_size_bits
<= 32) {
210 this->current_annotation
= "initialize control data bits";
211 inst
= emit(MOV(dst_reg(this->control_data_bits
), brw_imm_ud(0u)));
212 inst
->force_writemask_all
= true;
216 this->current_annotation
= NULL
;
220 vec4_gs_visitor::emit_thread_end()
222 if (c
->control_data_header_size_bits
> 0) {
223 /* During shader execution, we only ever call emit_control_data_bits()
224 * just prior to outputting a vertex. Therefore, the control data bits
225 * corresponding to the most recently output vertex still need to be
228 current_annotation
= "thread end: emit control data bits";
229 emit_control_data_bits();
232 /* MRF 0 is reserved for the debugger, so start with message header
237 bool static_vertex_count
= gs_prog_data
->static_vertex_count
!= -1;
239 /* If the previous instruction was a URB write, we don't need to issue
240 * a second one - we can just set the EOT bit on the previous write.
242 * Skip this on Gen8+ unless there's a static vertex count, as we also
243 * need to write the vertex count out, and combining the two may not be
244 * possible (or at least not straightforward).
246 vec4_instruction
*last
= (vec4_instruction
*) instructions
.get_tail();
247 if (last
&& last
->opcode
== GS_OPCODE_URB_WRITE
&&
248 !(INTEL_DEBUG
& DEBUG_SHADER_TIME
) &&
249 devinfo
->gen
>= 8 && static_vertex_count
) {
250 last
->urb_write_flags
= BRW_URB_WRITE_EOT
| last
->urb_write_flags
;
254 current_annotation
= "thread end";
255 dst_reg
mrf_reg(MRF
, base_mrf
);
256 src_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
257 vec4_instruction
*inst
= emit(MOV(mrf_reg
, r0
));
258 inst
->force_writemask_all
= true;
259 if (devinfo
->gen
< 8 || !static_vertex_count
)
260 emit(GS_OPCODE_SET_VERTEX_COUNT
, mrf_reg
, this->vertex_count
);
261 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
262 emit_shader_time_end();
263 inst
= emit(GS_OPCODE_THREAD_END
);
264 inst
->base_mrf
= base_mrf
;
265 inst
->mlen
= devinfo
->gen
>= 8 && !static_vertex_count
? 2 : 1;
270 vec4_gs_visitor::emit_urb_write_header(int mrf
)
272 /* The SEND instruction that writes the vertex data to the VUE will use
273 * per_slot_offset=true, which means that DWORDs 3 and 4 of the message
274 * header specify an offset (in multiples of 256 bits) into the URB entry
275 * at which the write should take place.
277 * So we have to prepare a message header with the appropriate offset
280 dst_reg
mrf_reg(MRF
, mrf
);
281 src_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
282 this->current_annotation
= "URB write header";
283 vec4_instruction
*inst
= emit(MOV(mrf_reg
, r0
));
284 inst
->force_writemask_all
= true;
285 emit(GS_OPCODE_SET_WRITE_OFFSET
, mrf_reg
, this->vertex_count
,
286 brw_imm_ud(gs_prog_data
->output_vertex_size_hwords
));
291 vec4_gs_visitor::emit_urb_write_opcode(bool complete
)
293 /* We don't care whether the vertex is complete, because in general
294 * geometry shaders output multiple vertices, and we don't terminate the
295 * thread until all vertices are complete.
299 vec4_instruction
*inst
= emit(GS_OPCODE_URB_WRITE
);
300 inst
->offset
= gs_prog_data
->control_data_header_size_hwords
;
302 /* We need to increment Global Offset by 1 to make room for Broadwell's
303 * extra "Vertex Count" payload at the beginning of the URB entry.
305 if (devinfo
->gen
>= 8 && gs_prog_data
->static_vertex_count
== -1)
308 inst
->urb_write_flags
= BRW_URB_WRITE_PER_SLOT_OFFSET
;
314 * Write out a batch of 32 control data bits from the control_data_bits
315 * register to the URB.
317 * The current value of the vertex_count register determines which DWORD in
318 * the URB receives the control data bits. The control_data_bits register is
319 * assumed to contain the correct data for the vertex that was most recently
320 * output, and all previous vertices that share the same DWORD.
322 * This function takes care of ensuring that if no vertices have been output
323 * yet, no control bits are emitted.
326 vec4_gs_visitor::emit_control_data_bits()
328 assert(c
->control_data_bits_per_vertex
!= 0);
330 /* Since the URB_WRITE_OWORD message operates with 128-bit (vec4 sized)
331 * granularity, we need to use two tricks to ensure that the batch of 32
332 * control data bits is written to the appropriate DWORD in the URB. To
333 * select which vec4 we are writing to, we use the "slot {0,1} offset"
334 * fields of the message header. To select which DWORD in the vec4 we are
335 * writing to, we use the channel mask fields of the message header. To
336 * avoid penalizing geometry shaders that emit a small number of vertices
337 * with extra bookkeeping, we only do each of these tricks when
338 * c->prog_data.control_data_header_size_bits is large enough to make it
341 * Note: this means that if we're outputting just a single DWORD of control
342 * data bits, we'll actually replicate it four times since we won't do any
343 * channel masking. But that's not a problem since in this case the
344 * hardware only pays attention to the first DWORD.
346 enum brw_urb_write_flags urb_write_flags
= BRW_URB_WRITE_OWORD
;
347 if (c
->control_data_header_size_bits
> 32)
348 urb_write_flags
= urb_write_flags
| BRW_URB_WRITE_USE_CHANNEL_MASKS
;
349 if (c
->control_data_header_size_bits
> 128)
350 urb_write_flags
= urb_write_flags
| BRW_URB_WRITE_PER_SLOT_OFFSET
;
352 /* If we are using either channel masks or a per-slot offset, then we
353 * need to figure out which DWORD we are trying to write to, using the
356 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
358 * Since bits_per_vertex is a power of two, and is known at compile
359 * time, this can be optimized to:
361 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
363 src_reg
dword_index(this, glsl_type::uint_type
);
364 if (urb_write_flags
) {
365 src_reg
prev_count(this, glsl_type::uint_type
);
366 emit(ADD(dst_reg(prev_count
), this->vertex_count
,
367 brw_imm_ud(0xffffffffu
)));
368 unsigned log2_bits_per_vertex
=
369 util_last_bit(c
->control_data_bits_per_vertex
);
370 emit(SHR(dst_reg(dword_index
), prev_count
,
371 brw_imm_ud(6 - log2_bits_per_vertex
)));
374 /* Start building the URB write message. The first MRF gets a copy of
378 dst_reg
mrf_reg(MRF
, base_mrf
);
379 src_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
380 vec4_instruction
*inst
= emit(MOV(mrf_reg
, r0
));
381 inst
->force_writemask_all
= true;
383 if (urb_write_flags
& BRW_URB_WRITE_PER_SLOT_OFFSET
) {
384 /* Set the per-slot offset to dword_index / 4, to that we'll write to
385 * the appropriate OWORD within the control data header.
387 src_reg
per_slot_offset(this, glsl_type::uint_type
);
388 emit(SHR(dst_reg(per_slot_offset
), dword_index
, brw_imm_ud(2u)));
389 emit(GS_OPCODE_SET_WRITE_OFFSET
, mrf_reg
, per_slot_offset
,
393 if (urb_write_flags
& BRW_URB_WRITE_USE_CHANNEL_MASKS
) {
394 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
395 * write to the appropriate DWORD within the OWORD. We need to do
396 * this computation with force_writemask_all, otherwise garbage data
397 * from invocation 0 might clobber the mask for invocation 1 when
398 * GS_OPCODE_PREPARE_CHANNEL_MASKS tries to OR the two masks
401 src_reg
channel(this, glsl_type::uint_type
);
402 inst
= emit(AND(dst_reg(channel
), dword_index
, brw_imm_ud(3u)));
403 inst
->force_writemask_all
= true;
404 src_reg
one(this, glsl_type::uint_type
);
405 inst
= emit(MOV(dst_reg(one
), brw_imm_ud(1u)));
406 inst
->force_writemask_all
= true;
407 src_reg
channel_mask(this, glsl_type::uint_type
);
408 inst
= emit(SHL(dst_reg(channel_mask
), one
, channel
));
409 inst
->force_writemask_all
= true;
410 emit(GS_OPCODE_PREPARE_CHANNEL_MASKS
, dst_reg(channel_mask
),
412 emit(GS_OPCODE_SET_CHANNEL_MASKS
, mrf_reg
, channel_mask
);
415 /* Store the control data bits in the message payload and send it. */
416 dst_reg
mrf_reg2(MRF
, base_mrf
+ 1);
417 inst
= emit(MOV(mrf_reg2
, this->control_data_bits
));
418 inst
->force_writemask_all
= true;
419 inst
= emit(GS_OPCODE_URB_WRITE
);
420 inst
->urb_write_flags
= urb_write_flags
;
421 /* We need to increment Global Offset by 256-bits to make room for
422 * Broadwell's extra "Vertex Count" payload at the beginning of the
423 * URB entry. Since this is an OWord message, Global Offset is counted
424 * in 128-bit units, so we must set it to 2.
426 if (devinfo
->gen
>= 8 && gs_prog_data
->static_vertex_count
== -1)
428 inst
->base_mrf
= base_mrf
;
433 vec4_gs_visitor::set_stream_control_data_bits(unsigned stream_id
)
435 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
437 /* Note: we are calling this *before* increasing vertex_count, so
438 * this->vertex_count == vertex_count - 1 in the formula above.
441 /* Stream mode uses 2 bits per vertex */
442 assert(c
->control_data_bits_per_vertex
== 2);
444 /* Must be a valid stream */
445 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
447 /* Control data bits are initialized to 0 so we don't have to set any
448 * bits when sending vertices to stream 0.
453 /* reg::sid = stream_id */
454 src_reg
sid(this, glsl_type::uint_type
);
455 emit(MOV(dst_reg(sid
), brw_imm_ud(stream_id
)));
457 /* reg:shift_count = 2 * (vertex_count - 1) */
458 src_reg
shift_count(this, glsl_type::uint_type
);
459 emit(SHL(dst_reg(shift_count
), this->vertex_count
, brw_imm_ud(1u)));
461 /* Note: we're relying on the fact that the GEN SHL instruction only pays
462 * attention to the lower 5 bits of its second source argument, so on this
463 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
464 * stream_id << ((2 * (vertex_count - 1)) % 32).
466 src_reg
mask(this, glsl_type::uint_type
);
467 emit(SHL(dst_reg(mask
), sid
, shift_count
));
468 emit(OR(dst_reg(this->control_data_bits
), this->control_data_bits
, mask
));
472 vec4_gs_visitor::gs_emit_vertex(int stream_id
)
474 this->current_annotation
= "emit vertex: safety check";
476 /* Haswell and later hardware ignores the "Render Stream Select" bits
477 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
478 * and instead sends all primitives down the pipeline for rasterization.
479 * If the SOL stage is enabled, "Render Stream Select" is honored and
480 * primitives bound to non-zero streams are discarded after stream output.
482 * Since the only purpose of primives sent to non-zero streams is to
483 * be recorded by transform feedback, we can simply discard all geometry
484 * bound to these streams when transform feedback is disabled.
486 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
489 /* If we're outputting 32 control data bits or less, then we can wait
490 * until the shader is over to output them all. Otherwise we need to
491 * output them as we go. Now is the time to do it, since we're about to
492 * output the vertex_count'th vertex, so it's guaranteed that the
493 * control data bits associated with the (vertex_count - 1)th vertex are
496 if (c
->control_data_header_size_bits
> 32) {
497 this->current_annotation
= "emit vertex: emit control data bits";
498 /* Only emit control data bits if we've finished accumulating a batch
499 * of 32 bits. This is the case when:
501 * (vertex_count * bits_per_vertex) % 32 == 0
503 * (in other words, when the last 5 bits of vertex_count *
504 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
505 * integer n (which is always the case, since bits_per_vertex is
506 * always 1 or 2), this is equivalent to requiring that the last 5-n
507 * bits of vertex_count are 0:
509 * vertex_count & (2^(5-n) - 1) == 0
511 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
514 * vertex_count & (32 / bits_per_vertex - 1) == 0
516 vec4_instruction
*inst
=
517 emit(AND(dst_null_ud(), this->vertex_count
,
518 brw_imm_ud(32 / c
->control_data_bits_per_vertex
- 1)));
519 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
521 emit(IF(BRW_PREDICATE_NORMAL
));
523 /* If vertex_count is 0, then no control data bits have been
524 * accumulated yet, so we skip emitting them.
526 emit(CMP(dst_null_ud(), this->vertex_count
, brw_imm_ud(0u),
527 BRW_CONDITIONAL_NEQ
));
528 emit(IF(BRW_PREDICATE_NORMAL
));
529 emit_control_data_bits();
530 emit(BRW_OPCODE_ENDIF
);
532 /* Reset control_data_bits to 0 so we can start accumulating a new
535 * Note: in the case where vertex_count == 0, this neutralizes the
536 * effect of any call to EndPrimitive() that the shader may have
537 * made before outputting its first vertex.
539 inst
= emit(MOV(dst_reg(this->control_data_bits
), brw_imm_ud(0u)));
540 inst
->force_writemask_all
= true;
542 emit(BRW_OPCODE_ENDIF
);
545 this->current_annotation
= "emit vertex: vertex data";
548 /* In stream mode we have to set control data bits for all vertices
549 * unless we have disabled control data bits completely (which we do
550 * do for GL_POINTS outputs that don't use streams).
552 if (c
->control_data_header_size_bits
> 0 &&
553 gs_prog_data
->control_data_format
==
554 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
555 this->current_annotation
= "emit vertex: Stream control data bits";
556 set_stream_control_data_bits(stream_id
);
559 this->current_annotation
= NULL
;
563 vec4_gs_visitor::gs_end_primitive()
565 /* We can only do EndPrimitive() functionality when the control data
566 * consists of cut bits. Fortunately, the only time it isn't is when the
567 * output type is points, in which case EndPrimitive() is a no-op.
569 if (gs_prog_data
->control_data_format
!=
570 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
574 if (c
->control_data_header_size_bits
== 0)
577 /* Cut bits use one bit per vertex. */
578 assert(c
->control_data_bits_per_vertex
== 1);
580 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
581 * vertex n, 0 otherwise. So all we need to do here is mark bit
582 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
583 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
584 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
586 * Note that if EndPrimitve() is called before emitting any vertices, this
587 * will cause us to set bit 31 of the control_data_bits register to 1.
588 * That's fine because:
590 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
591 * output, so the hardware will ignore cut bit 31.
593 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
594 * last vertex, so setting cut bit 31 has no effect (since the primitive
595 * is automatically ended when the GS terminates).
597 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
598 * control_data_bits register to 0 when the first vertex is emitted.
601 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
602 src_reg
one(this, glsl_type::uint_type
);
603 emit(MOV(dst_reg(one
), brw_imm_ud(1u)));
604 src_reg
prev_count(this, glsl_type::uint_type
);
605 emit(ADD(dst_reg(prev_count
), this->vertex_count
, brw_imm_ud(0xffffffffu
)));
606 src_reg
mask(this, glsl_type::uint_type
);
607 /* Note: we're relying on the fact that the GEN SHL instruction only pays
608 * attention to the lower 5 bits of its second source argument, so on this
609 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
610 * ((vertex_count - 1) % 32).
612 emit(SHL(dst_reg(mask
), one
, prev_count
));
613 emit(OR(dst_reg(this->control_data_bits
), this->control_data_bits
, mask
));
616 static const GLuint gl_prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1] = {
617 [GL_POINTS
] =_3DPRIM_POINTLIST
,
618 [GL_LINES
] = _3DPRIM_LINELIST
,
619 [GL_LINE_LOOP
] = _3DPRIM_LINELOOP
,
620 [GL_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
621 [GL_TRIANGLES
] = _3DPRIM_TRILIST
,
622 [GL_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
623 [GL_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
624 [GL_QUADS
] = _3DPRIM_QUADLIST
,
625 [GL_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
626 [GL_POLYGON
] = _3DPRIM_POLYGON
,
627 [GL_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
628 [GL_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
629 [GL_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
630 [GL_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
633 extern "C" const unsigned *
634 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
636 const struct brw_gs_prog_key
*key
,
637 struct brw_gs_prog_data
*prog_data
,
638 const nir_shader
*src_shader
,
639 struct gl_program
*prog
,
640 int shader_time_index
,
641 unsigned *final_assembly_size
,
644 struct brw_gs_compile c
;
645 memset(&c
, 0, sizeof(c
));
648 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
];
649 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
651 /* The GLSL linker will have already matched up GS inputs and the outputs
652 * of prior stages. The driver does extend VS outputs in some cases, but
653 * only for legacy OpenGL or Gen4-5 hardware, neither of which offer
654 * geometry shader support. So we can safely ignore that.
656 * For SSO pipelines, we use a fixed VUE map layout based on variable
657 * locations, so we can rely on rendezvous-by-location making this work.
659 GLbitfield64 inputs_read
= shader
->info
.inputs_read
;
660 brw_compute_vue_map(compiler
->devinfo
,
661 &c
.input_vue_map
, inputs_read
,
662 shader
->info
.separate_shader
);
664 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, is_scalar
);
665 brw_nir_lower_vue_inputs(shader
, &c
.input_vue_map
);
666 brw_nir_lower_vue_outputs(shader
, is_scalar
);
667 shader
= brw_postprocess_nir(shader
, compiler
, is_scalar
);
669 prog_data
->base
.clip_distance_mask
=
670 ((1 << shader
->info
.clip_distance_array_size
) - 1);
671 prog_data
->base
.cull_distance_mask
=
672 ((1 << shader
->info
.cull_distance_array_size
) - 1) <<
673 shader
->info
.clip_distance_array_size
;
675 prog_data
->include_primitive_id
=
676 (shader
->info
.system_values_read
& (1 << SYSTEM_VALUE_PRIMITIVE_ID
)) != 0;
678 prog_data
->invocations
= shader
->info
.gs
.invocations
;
680 if (compiler
->devinfo
->gen
>= 8)
681 prog_data
->static_vertex_count
= nir_gs_count_vertices(shader
);
683 if (compiler
->devinfo
->gen
>= 7) {
684 if (shader
->info
.gs
.output_primitive
== GL_POINTS
) {
685 /* When the output type is points, the geometry shader may output data
686 * to multiple streams, and EndPrimitive() has no effect. So we
687 * configure the hardware to interpret the control data as stream ID.
689 prog_data
->control_data_format
= GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
;
691 /* We only have to emit control bits if we are using streams */
692 if (prog
&& prog
->info
.gs
.uses_streams
)
693 c
.control_data_bits_per_vertex
= 2;
695 c
.control_data_bits_per_vertex
= 0;
697 /* When the output type is triangle_strip or line_strip, EndPrimitive()
698 * may be used to terminate the current strip and start a new one
699 * (similar to primitive restart), and outputting data to multiple
700 * streams is not supported. So we configure the hardware to interpret
701 * the control data as EndPrimitive information (a.k.a. "cut bits").
703 prog_data
->control_data_format
= GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
;
705 /* We only need to output control data if the shader actually calls
708 c
.control_data_bits_per_vertex
=
709 shader
->info
.gs
.uses_end_primitive
? 1 : 0;
712 /* There are no control data bits in gen6. */
713 c
.control_data_bits_per_vertex
= 0;
715 c
.control_data_header_size_bits
=
716 shader
->info
.gs
.vertices_out
* c
.control_data_bits_per_vertex
;
718 /* 1 HWORD = 32 bytes = 256 bits */
719 prog_data
->control_data_header_size_hwords
=
720 ALIGN(c
.control_data_header_size_bits
, 256) / 256;
722 /* Compute the output vertex size.
724 * From the Ivy Bridge PRM, Vol2 Part1 7.2.1.1 STATE_GS - Output Vertex
727 * [0,62] indicating [1,63] 16B units
729 * Specifies the size of each vertex stored in the GS output entry
730 * (following any Control Header data) as a number of 128-bit units
733 * Programming Restrictions: The vertex size must be programmed as a
734 * multiple of 32B units with the following exception: Rendering is
735 * disabled (as per SOL stage state) and the vertex size output by the
738 * If rendering is enabled (as per SOL state) the vertex size must be
739 * programmed as a multiple of 32B units. In other words, the only time
740 * software can program a vertex size with an odd number of 16B units
741 * is when rendering is disabled.
743 * Note: B=bytes in the above text.
745 * It doesn't seem worth the extra trouble to optimize the case where the
746 * vertex size is 16B (especially since this would require special-casing
747 * the GEN assembly that writes to the URB). So we just set the vertex
748 * size to a multiple of 32B (2 vec4's) in all cases.
750 * The maximum output vertex size is 62*16 = 992 bytes (31 hwords). We
751 * budget that as follows:
753 * 512 bytes for varyings (a varying component is 4 bytes and
754 * gl_MaxGeometryOutputComponents = 128)
755 * 16 bytes overhead for VARYING_SLOT_PSIZ (each varying slot is 16
757 * 16 bytes overhead for gl_Position (we allocate it a slot in the VUE
758 * even if it's not used)
759 * 32 bytes overhead for gl_ClipDistance (we allocate it 2 VUE slots
760 * whenever clip planes are enabled, even if the shader doesn't
761 * write to gl_ClipDistance)
762 * 16 bytes overhead since the VUE size must be a multiple of 32 bytes
763 * (see below)--this causes up to 1 VUE slot to be wasted
764 * 400 bytes available for varying packing overhead
766 * Worst-case varying packing overhead is 3/4 of a varying slot (12 bytes)
767 * per interpolation type, so this is plenty.
770 unsigned output_vertex_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 16;
771 assert(compiler
->devinfo
->gen
== 6 ||
772 output_vertex_size_bytes
<= GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES
);
773 prog_data
->output_vertex_size_hwords
=
774 ALIGN(output_vertex_size_bytes
, 32) / 32;
776 /* Compute URB entry size. The maximum allowed URB entry size is 32k.
777 * That divides up as follows:
779 * 64 bytes for the control data header (cut indices or StreamID bits)
780 * 4096 bytes for varyings (a varying component is 4 bytes and
781 * gl_MaxGeometryTotalOutputComponents = 1024)
782 * 4096 bytes overhead for VARYING_SLOT_PSIZ (each varying slot is 16
783 * bytes/vertex and gl_MaxGeometryOutputVertices is 256)
784 * 4096 bytes overhead for gl_Position (we allocate it a slot in the VUE
785 * even if it's not used)
786 * 8192 bytes overhead for gl_ClipDistance (we allocate it 2 VUE slots
787 * whenever clip planes are enabled, even if the shader doesn't
788 * write to gl_ClipDistance)
789 * 4096 bytes overhead since the VUE size must be a multiple of 32
790 * bytes (see above)--this causes up to 1 VUE slot to be wasted
791 * 8128 bytes available for varying packing overhead
793 * Worst-case varying packing overhead is 3/4 of a varying slot per
794 * interpolation type, which works out to 3072 bytes, so this would allow
795 * us to accommodate 2 interpolation types without any danger of running
798 * In practice, the risk of running out of URB space is very small, since
799 * the above figures are all worst-case, and most of them scale with the
800 * number of output vertices. So we'll just calculate the amount of space
801 * we need, and if it's too large, fail to compile.
803 * The above is for gen7+ where we have a single URB entry that will hold
804 * all the output. In gen6, we will have to allocate URB entries for every
805 * vertex we emit, so our URB entries only need to be large enough to hold
806 * a single vertex. Also, gen6 does not have a control data header.
808 unsigned output_size_bytes
;
809 if (compiler
->devinfo
->gen
>= 7) {
811 prog_data
->output_vertex_size_hwords
* 32 * shader
->info
.gs
.vertices_out
;
812 output_size_bytes
+= 32 * prog_data
->control_data_header_size_hwords
;
814 output_size_bytes
= prog_data
->output_vertex_size_hwords
* 32;
817 /* Broadwell stores "Vertex Count" as a full 8 DWord (32 byte) URB output,
818 * which comes before the control header.
820 if (compiler
->devinfo
->gen
>= 8)
821 output_size_bytes
+= 32;
823 /* Shaders can technically set max_vertices = 0, at which point we
824 * may have a URB size of 0 bytes. Nothing good can come from that,
825 * so enforce a minimum size.
827 if (output_size_bytes
== 0)
828 output_size_bytes
= 1;
830 unsigned max_output_size_bytes
= GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES
;
831 if (compiler
->devinfo
->gen
== 6)
832 max_output_size_bytes
= GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES
;
833 if (output_size_bytes
> max_output_size_bytes
)
837 /* URB entry sizes are stored as a multiple of 64 bytes in gen7+ and
838 * a multiple of 128 bytes in gen6.
840 if (compiler
->devinfo
->gen
>= 7)
841 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
843 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 128) / 128;
845 assert(shader
->info
.gs
.output_primitive
< ARRAY_SIZE(gl_prim_to_hw_prim
));
846 prog_data
->output_topology
=
847 gl_prim_to_hw_prim
[shader
->info
.gs
.output_primitive
];
849 prog_data
->vertices_in
= shader
->info
.gs
.vertices_in
;
851 /* GS inputs are read from the VUE 256 bits (2 vec4's) at a time, so we
852 * need to program a URB read length of ceiling(num_slots / 2).
854 prog_data
->base
.urb_read_length
= (c
.input_vue_map
.num_slots
+ 1) / 2;
856 /* Now that prog_data setup is done, we are ready to actually compile the
859 if (unlikely(INTEL_DEBUG
& DEBUG_GS
)) {
860 fprintf(stderr
, "GS Input ");
861 brw_print_vue_map(stderr
, &c
.input_vue_map
);
862 fprintf(stderr
, "GS Output ");
863 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
867 fs_visitor
v(compiler
, log_data
, mem_ctx
, &c
, prog_data
, shader
,
870 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
871 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
873 fs_generator
g(compiler
, log_data
, mem_ctx
, &c
.key
,
874 &prog_data
->base
.base
, v
.promoted_constants
,
875 false, MESA_SHADER_GEOMETRY
);
876 if (unlikely(INTEL_DEBUG
& DEBUG_GS
)) {
878 shader
->info
.label
? shader
->info
.label
: "unnamed";
879 char *name
= ralloc_asprintf(mem_ctx
, "%s geometry shader %s",
880 label
, shader
->info
.name
);
881 g
.enable_debug(name
);
883 g
.generate_code(v
.cfg
, 8);
884 return g
.get_assembly(final_assembly_size
);
888 if (compiler
->devinfo
->gen
>= 7) {
889 /* Compile the geometry shader in DUAL_OBJECT dispatch mode, if we can do
890 * so without spilling. If the GS invocations count > 1, then we can't use
893 if (prog_data
->invocations
<= 1 &&
894 likely(!(INTEL_DEBUG
& DEBUG_NO_DUAL_OBJECT_GS
))) {
895 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
897 vec4_gs_visitor
v(compiler
, log_data
, &c
, prog_data
, shader
,
898 mem_ctx
, true /* no_spills */, shader_time_index
);
900 return brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
901 shader
, &prog_data
->base
, v
.cfg
,
902 final_assembly_size
);
907 /* Either we failed to compile in DUAL_OBJECT mode (probably because it
908 * would have required spilling) or DUAL_OBJECT mode is disabled. So fall
909 * back to DUAL_INSTANCED or SINGLE mode, which consumes fewer registers.
911 * FIXME: Single dispatch mode requires that the driver can handle
912 * interleaving of input registers, but this is already supported (dual
913 * instance mode has the same requirement). However, to take full advantage
914 * of single dispatch mode to reduce register pressure we would also need to
915 * do interleaved outputs, but currently, the vec4 visitor and generator
916 * classes do not support this, so at the moment register pressure in
917 * single and dual instance modes is the same.
919 * From the Ivy Bridge PRM, Vol2 Part1 7.2.1.1 "3DSTATE_GS"
920 * "If InstanceCount>1, DUAL_OBJECT mode is invalid. Software will likely
921 * want to use DUAL_INSTANCE mode for higher performance, but SINGLE mode
922 * is also supported. When InstanceCount=1 (one instance per object) software
923 * can decide which dispatch mode to use. DUAL_OBJECT mode would likely be
924 * the best choice for performance, followed by SINGLE mode."
926 * So SINGLE mode is more performant when invocations == 1 and DUAL_INSTANCE
927 * mode is more performant when invocations > 1. Gen6 only supports
930 if (prog_data
->invocations
<= 1 || compiler
->devinfo
->gen
< 7)
931 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X1_SINGLE
;
933 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_INSTANCE
;
935 vec4_gs_visitor
*gs
= NULL
;
936 const unsigned *ret
= NULL
;
938 if (compiler
->devinfo
->gen
>= 7)
939 gs
= new vec4_gs_visitor(compiler
, log_data
, &c
, prog_data
,
940 shader
, mem_ctx
, false /* no_spills */,
943 gs
= new gen6_gs_visitor(compiler
, log_data
, &c
, prog_data
, prog
,
944 shader
, mem_ctx
, false /* no_spills */,
949 *error_str
= ralloc_strdup(mem_ctx
, gs
->fail_msg
);
951 ret
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, shader
,
952 &prog_data
->base
, gs
->cfg
,
953 final_assembly_size
);
961 } /* namespace brw */