2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
30 using namespace brw::surface_access
;
35 vec4_visitor::emit_nir_code()
37 if (nir
->num_uniforms
> 0)
40 /* get the main function and emit it */
41 nir_foreach_function(function
, nir
) {
42 assert(strcmp(function
->name
, "main") == 0);
43 assert(function
->impl
);
44 nir_emit_impl(function
->impl
);
49 vec4_visitor::nir_setup_uniforms()
51 uniforms
= nir
->num_uniforms
/ 16;
55 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
57 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
58 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
59 nir_locals
[i
] = dst_reg();
62 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
63 unsigned array_elems
=
64 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
65 const unsigned num_regs
= array_elems
* DIV_ROUND_UP(reg
->bit_size
, 32);
66 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(num_regs
));
68 if (reg
->bit_size
== 64)
69 nir_locals
[reg
->index
].type
= BRW_REGISTER_TYPE_DF
;
72 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
74 nir_emit_cf_list(&impl
->body
);
78 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
80 exec_list_validate(list
);
81 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
84 nir_emit_if(nir_cf_node_as_if(node
));
87 case nir_cf_node_loop
:
88 nir_emit_loop(nir_cf_node_as_loop(node
));
91 case nir_cf_node_block
:
92 nir_emit_block(nir_cf_node_as_block(node
));
96 unreachable("Invalid CFG node block");
102 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
104 /* First, put the condition in f0 */
105 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
106 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
107 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
109 /* We can just predicate based on the X channel, as the condition only
110 * goes on its own line */
111 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
113 nir_emit_cf_list(&if_stmt
->then_list
);
115 /* note: if the else is empty, dead CF elimination will remove it */
116 emit(BRW_OPCODE_ELSE
);
118 nir_emit_cf_list(&if_stmt
->else_list
);
120 emit(BRW_OPCODE_ENDIF
);
124 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
128 nir_emit_cf_list(&loop
->body
);
130 emit(BRW_OPCODE_WHILE
);
134 vec4_visitor::nir_emit_block(nir_block
*block
)
136 nir_foreach_instr(instr
, block
) {
137 nir_emit_instr(instr
);
142 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
146 switch (instr
->type
) {
147 case nir_instr_type_load_const
:
148 nir_emit_load_const(nir_instr_as_load_const(instr
));
151 case nir_instr_type_intrinsic
:
152 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
155 case nir_instr_type_alu
:
156 nir_emit_alu(nir_instr_as_alu(instr
));
159 case nir_instr_type_jump
:
160 nir_emit_jump(nir_instr_as_jump(instr
));
163 case nir_instr_type_tex
:
164 nir_emit_texture(nir_instr_as_tex(instr
));
167 case nir_instr_type_ssa_undef
:
168 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
172 fprintf(stderr
, "VS instruction not yet implemented by NIR->vec4\n");
178 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
179 unsigned base_offset
, nir_src
*indirect
)
183 reg
= v
->nir_locals
[nir_reg
->index
];
184 if (nir_reg
->bit_size
== 64)
185 reg
.type
= BRW_REGISTER_TYPE_DF
;
186 reg
= offset(reg
, 8, base_offset
);
189 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
197 vec4_visitor::get_nir_dest(const nir_dest
&dest
)
201 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(dest
.ssa
.bit_size
, 32)));
202 if (dest
.ssa
.bit_size
== 64)
203 dst
.type
= BRW_REGISTER_TYPE_DF
;
204 nir_ssa_values
[dest
.ssa
.index
] = dst
;
207 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
213 vec4_visitor::get_nir_dest(const nir_dest
&dest
, enum brw_reg_type type
)
215 return retype(get_nir_dest(dest
), type
);
219 vec4_visitor::get_nir_dest(const nir_dest
&dest
, nir_alu_type type
)
221 return get_nir_dest(dest
, brw_type_for_nir_type(devinfo
, type
));
225 vec4_visitor::get_nir_src(const nir_src
&src
, enum brw_reg_type type
,
226 unsigned num_components
)
231 assert(src
.ssa
!= NULL
);
232 reg
= nir_ssa_values
[src
.ssa
->index
];
235 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
239 reg
= retype(reg
, type
);
241 src_reg reg_as_src
= src_reg(reg
);
242 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
247 vec4_visitor::get_nir_src(const nir_src
&src
, nir_alu_type type
,
248 unsigned num_components
)
250 return get_nir_src(src
, brw_type_for_nir_type(devinfo
, type
),
255 vec4_visitor::get_nir_src(const nir_src
&src
, unsigned num_components
)
257 /* if type is not specified, default to signed int */
258 return get_nir_src(src
, nir_type_int32
, num_components
);
262 vec4_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
264 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
265 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
268 /* The only constant offset we should find is 0. brw_nir.c's
269 * add_const_offset_to_base() will fold other constant offsets
270 * into instr->const_index[0].
272 assert(const_value
->u32
[0] == 0);
276 return get_nir_src(*offset_src
, BRW_REGISTER_TYPE_UD
, 1);
280 setup_imm_df(const vec4_builder
&bld
, double v
)
282 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
283 assert(devinfo
->gen
>= 7);
285 if (devinfo
->gen
>= 8)
286 return brw_imm_df(v
);
288 /* gen7.5 does not support DF immediates straighforward but the DIM
289 * instruction allows to set the 64-bit immediate value.
291 if (devinfo
->is_haswell
) {
292 const vec4_builder ubld
= bld
.exec_all();
293 const dst_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_DF
);
294 ubld
.DIM(dst
, brw_imm_df(v
));
295 return swizzle(src_reg(dst
), BRW_SWIZZLE_XXXX
);
298 /* gen7 does not support DF immediates */
309 /* Write the low 32-bit of the constant to the X:UD channel and the
310 * high 32-bit to the Y:UD channel to build the constant in a VGRF.
311 * We have to do this twice (offset 0 and offset 1), since a DF VGRF takes
312 * two SIMD8 registers in SIMD4x2 execution. Finally, return a swizzle
313 * XXXX so any access to the VGRF only reads the constant data in these
316 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
317 for (unsigned n
= 0; n
< 2; n
++) {
318 const vec4_builder ubld
= bld
.exec_all().group(4, n
);
319 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_X
), brw_imm_ud(di
.i1
));
320 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_Y
), brw_imm_ud(di
.i2
));
323 return swizzle(src_reg(retype(tmp
, BRW_REGISTER_TYPE_DF
)), BRW_SWIZZLE_XXXX
);
327 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
331 if (instr
->def
.bit_size
== 64) {
332 reg
= dst_reg(VGRF
, alloc
.allocate(2));
333 reg
.type
= BRW_REGISTER_TYPE_DF
;
335 reg
= dst_reg(VGRF
, alloc
.allocate(1));
336 reg
.type
= BRW_REGISTER_TYPE_D
;
339 const vec4_builder ibld
= vec4_builder(this).at_end();
340 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
342 /* @FIXME: consider emitting vector operations to save some MOVs in
343 * cases where the components are representable in 8 bits.
344 * For now, we emit a MOV for each distinct value.
346 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
347 unsigned writemask
= 1 << i
;
349 if ((remaining
& writemask
) == 0)
352 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
353 if ((instr
->def
.bit_size
== 32 &&
354 instr
->value
.u32
[i
] == instr
->value
.u32
[j
]) ||
355 (instr
->def
.bit_size
== 64 &&
356 instr
->value
.f64
[i
] == instr
->value
.f64
[j
])) {
361 reg
.writemask
= writemask
;
362 if (instr
->def
.bit_size
== 64) {
363 emit(MOV(reg
, setup_imm_df(ibld
, instr
->value
.f64
[i
])));
365 emit(MOV(reg
, brw_imm_d(instr
->value
.i32
[i
])));
368 remaining
&= ~writemask
;
371 /* Set final writemask */
372 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
374 nir_ssa_values
[instr
->def
.index
] = reg
;
378 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
383 switch (instr
->intrinsic
) {
385 case nir_intrinsic_load_input
: {
386 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
388 /* We set EmitNoIndirectInput for VS */
389 assert(const_offset
);
391 dest
= get_nir_dest(instr
->dest
);
392 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
394 src
= src_reg(ATTR
, instr
->const_index
[0] + const_offset
->u32
[0],
395 glsl_type::uvec4_type
);
396 src
= retype(src
, dest
.type
);
398 bool is_64bit
= nir_dest_bit_size(instr
->dest
) == 64;
400 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
401 src
.swizzle
= BRW_SWIZZLE_XYZW
;
402 shuffle_64bit_data(tmp
, src
, false);
403 emit(MOV(dest
, src_reg(tmp
)));
405 /* Swizzle source based on component layout qualifier */
406 src
.swizzle
= BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr
));
407 emit(MOV(dest
, src
));
412 case nir_intrinsic_store_output
: {
413 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
414 assert(const_offset
);
416 int varying
= instr
->const_index
[0] + const_offset
->u32
[0];
418 bool is_64bit
= nir_src_bit_size(instr
->src
[0]) == 64;
421 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_DF
,
422 instr
->num_components
);
423 data
= src_reg(this, glsl_type::dvec4_type
);
424 shuffle_64bit_data(dst_reg(data
), src
, true);
425 src
= retype(data
, BRW_REGISTER_TYPE_F
);
427 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
428 instr
->num_components
);
431 unsigned c
= nir_intrinsic_component(instr
);
432 output_reg
[varying
][c
] = dst_reg(src
);
433 output_num_components
[varying
][c
] = instr
->num_components
;
435 unsigned num_components
= instr
->num_components
;
439 output_reg
[varying
][c
] = dst_reg(src
);
440 output_num_components
[varying
][c
] = MIN2(4, num_components
);
442 if (is_64bit
&& num_components
> 4) {
443 assert(num_components
<= 8);
444 output_reg
[varying
+ 1][c
] = byte_offset(dst_reg(src
), REG_SIZE
);
445 output_num_components
[varying
+ 1][c
] = num_components
- 4;
450 case nir_intrinsic_get_buffer_size
: {
451 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
452 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
454 const unsigned index
=
455 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
456 dst_reg result_dst
= get_nir_dest(instr
->dest
);
457 vec4_instruction
*inst
= new(mem_ctx
)
458 vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE
, result_dst
);
461 inst
->mlen
= 1; /* always at least one */
462 inst
->src
[1] = brw_imm_ud(index
);
464 /* MRF for the first parameter */
465 src_reg lod
= brw_imm_d(0);
466 int param_base
= inst
->base_mrf
;
467 int writemask
= WRITEMASK_X
;
468 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
472 brw_mark_surface_used(&prog_data
->base
, index
);
476 case nir_intrinsic_store_ssbo
: {
477 assert(devinfo
->gen
>= 7);
481 nir_const_value
*const_uniform_block
=
482 nir_src_as_const_value(instr
->src
[1]);
483 if (const_uniform_block
) {
484 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
485 const_uniform_block
->u32
[0];
486 surf_index
= brw_imm_ud(index
);
487 brw_mark_surface_used(&prog_data
->base
, index
);
489 surf_index
= src_reg(this, glsl_type::uint_type
);
490 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
491 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
492 surf_index
= emit_uniformize(surf_index
);
494 brw_mark_surface_used(&prog_data
->base
,
495 prog_data
->base
.binding_table
.ssbo_start
+
496 nir
->info
.num_ssbos
- 1);
501 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
503 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
505 offset_reg
= get_nir_src(instr
->src
[2], 1);
509 src_reg val_reg
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
, 4);
512 unsigned write_mask
= instr
->const_index
[0];
514 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
515 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
516 * typed and untyped messages and across hardware platforms, the
517 * current implementation of the untyped messages will transparently convert
518 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
519 * and enabling only channel X on the SEND instruction.
521 * The above, works well for full vector writes, but not for partial writes
522 * where we want to write some channels and not others, like when we have
523 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
524 * quite restrictive with regards to the channel enables we can configure in
525 * the message descriptor (not all combinations are allowed) we cannot simply
526 * implement these scenarios with a single message while keeping the
527 * aforementioned symmetry in the implementation. For now we de decided that
528 * it is better to keep the symmetry to reduce complexity, so in situations
529 * such as the one described we end up emitting two untyped write messages
530 * (one for xy and another for w).
532 * The code below packs consecutive channels into a single write message,
533 * detects gaps in the vector write and if needed, sends a second message
534 * with the remaining channels. If in the future we decide that we want to
535 * emit a single message at the expense of losing the symmetry in the
536 * implementation we can:
538 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
539 * message payload. In this mode we can write up to 8 offsets and dwords
540 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
541 * and select which of the 8 channels carry data to write by setting the
542 * appropriate writemask in the dst register of the SEND instruction.
543 * It would require to write a new generator opcode specifically for
544 * IvyBridge since we would need to prepare a SIMD8 payload that could
545 * use any channel, not just X.
547 * 2) For Haswell+: Simply send a single write message but set the writemask
548 * on the dst of the SEND instruction to select the channels we want to
549 * write. It would require to modify the current messages to receive
550 * and honor the writemask provided.
552 const vec4_builder bld
= vec4_builder(this).at_end()
553 .annotate(current_annotation
, base_ir
);
555 unsigned type_slots
= nir_src_bit_size(instr
->src
[0]) / 32;
556 if (type_slots
== 2) {
557 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
558 shuffle_64bit_data(tmp
, retype(val_reg
, tmp
.type
), true);
559 val_reg
= src_reg(retype(tmp
, BRW_REGISTER_TYPE_F
));
562 uint8_t swizzle
[4] = { 0, 0, 0, 0};
563 int num_channels
= 0;
564 unsigned skipped_channels
= 0;
565 int num_components
= instr
->num_components
;
566 for (int i
= 0; i
< num_components
; i
++) {
567 /* Read components Z/W of a dvec from the appropriate place. We will
568 * also have to adjust the swizzle (we do that with the '% 4' below)
570 if (i
== 2 && type_slots
== 2)
571 val_reg
= byte_offset(val_reg
, REG_SIZE
);
573 /* Check if this channel needs to be written. If so, record the
574 * channel we need to take the data from in the swizzle array
576 int component_mask
= 1 << i
;
577 int write_test
= write_mask
& component_mask
;
579 /* If we are writing doubles we have to write 2 channels worth of
580 * of data (64 bits) for each double component.
582 swizzle
[num_channels
++] = (i
* type_slots
) % 4;
584 swizzle
[num_channels
++] = (i
* type_slots
+ 1) % 4;
587 /* If we don't have to write this channel it means we have a gap in the
588 * vector, so write the channels we accumulated until now, if any. Do
589 * the same if this was the last component in the vector, if we have
590 * enough channels for a full vec4 write or if we have processed
591 * components XY of a dvec (since components ZW are not in the same
594 if (!write_test
|| i
== num_components
- 1 || num_channels
== 4 ||
595 (i
== 1 && type_slots
== 2)) {
596 if (num_channels
> 0) {
597 /* We have channels to write, so update the offset we need to
598 * write at to skip the channels we skipped, if any.
600 if (skipped_channels
> 0) {
601 if (offset_reg
.file
== IMM
) {
602 offset_reg
.ud
+= 4 * skipped_channels
;
604 emit(ADD(dst_reg(offset_reg
), offset_reg
,
605 brw_imm_ud(4 * skipped_channels
)));
609 /* Swizzle the data register so we take the data from the channels
610 * we need to write and send the write message. This will write
611 * num_channels consecutive dwords starting at offset.
614 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
615 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
616 1 /* dims */, num_channels
/* size */,
619 /* If we have to do a second write we will have to update the
620 * offset so that we jump over the channels we have just written
623 skipped_channels
= num_channels
;
625 /* Restart the count for the next write message */
629 /* If we didn't write the channel, increase skipped count */
631 skipped_channels
+= type_slots
;
638 case nir_intrinsic_load_ssbo
: {
639 assert(devinfo
->gen
>= 7);
641 nir_const_value
*const_uniform_block
=
642 nir_src_as_const_value(instr
->src
[0]);
645 if (const_uniform_block
) {
646 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
647 const_uniform_block
->u32
[0];
648 surf_index
= brw_imm_ud(index
);
650 brw_mark_surface_used(&prog_data
->base
, index
);
652 surf_index
= src_reg(this, glsl_type::uint_type
);
653 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
654 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
655 surf_index
= emit_uniformize(surf_index
);
657 /* Assume this may touch any UBO. It would be nice to provide
658 * a tighter bound, but the array information is already lowered away.
660 brw_mark_surface_used(&prog_data
->base
,
661 prog_data
->base
.binding_table
.ssbo_start
+
662 nir
->info
.num_ssbos
- 1);
666 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
668 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
670 offset_reg
= get_nir_src(instr
->src
[1], 1);
673 /* Read the vector */
674 const vec4_builder bld
= vec4_builder(this).at_end()
675 .annotate(current_annotation
, base_ir
);
678 dst_reg dest
= get_nir_dest(instr
->dest
);
679 if (type_sz(dest
.type
) < 8) {
680 read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
681 1 /* dims */, 4 /* size*/,
684 src_reg shuffled
= src_reg(this, glsl_type::dvec4_type
);
687 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
688 1 /* dims */, 4 /* size*/,
690 emit(MOV(dst_reg(retype(shuffled
, temp
.type
)), temp
));
692 if (offset_reg
.file
== IMM
)
695 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16)));
697 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
698 1 /* dims */, 4 /* size*/,
700 emit(MOV(dst_reg(retype(byte_offset(shuffled
, REG_SIZE
), temp
.type
)),
703 read_result
= src_reg(this, glsl_type::dvec4_type
);
704 shuffle_64bit_data(dst_reg(read_result
), shuffled
, false);
707 read_result
.type
= dest
.type
;
708 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
709 emit(MOV(dest
, read_result
));
713 case nir_intrinsic_ssbo_atomic_add
:
714 nir_emit_ssbo_atomic(BRW_AOP_ADD
, instr
);
716 case nir_intrinsic_ssbo_atomic_imin
:
717 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
719 case nir_intrinsic_ssbo_atomic_umin
:
720 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
722 case nir_intrinsic_ssbo_atomic_imax
:
723 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
725 case nir_intrinsic_ssbo_atomic_umax
:
726 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
728 case nir_intrinsic_ssbo_atomic_and
:
729 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
731 case nir_intrinsic_ssbo_atomic_or
:
732 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
734 case nir_intrinsic_ssbo_atomic_xor
:
735 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
737 case nir_intrinsic_ssbo_atomic_exchange
:
738 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
740 case nir_intrinsic_ssbo_atomic_comp_swap
:
741 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
744 case nir_intrinsic_load_vertex_id
:
745 unreachable("should be lowered by lower_vertex_id()");
747 case nir_intrinsic_load_vertex_id_zero_base
:
748 case nir_intrinsic_load_base_vertex
:
749 case nir_intrinsic_load_instance_id
:
750 case nir_intrinsic_load_base_instance
:
751 case nir_intrinsic_load_draw_id
:
752 case nir_intrinsic_load_invocation_id
:
753 unreachable("should be lowered by brw_nir_lower_vs_inputs()");
755 case nir_intrinsic_load_uniform
: {
756 /* Offsets are in bytes but they should always be multiples of 4 */
757 assert(nir_intrinsic_base(instr
) % 4 == 0);
759 dest
= get_nir_dest(instr
->dest
);
761 src
= src_reg(dst_reg(UNIFORM
, nir_intrinsic_base(instr
) / 16));
762 src
.type
= dest
.type
;
764 /* Uniforms don't actually have to be vec4 aligned. In the case that
765 * it isn't, we have to use a swizzle to shift things around. They
766 * do still have the std140 alignment requirement that vec2's have to
767 * be vec2-aligned and vec3's and vec4's have to be vec4-aligned.
769 * The swizzle also works in the indirect case as the generator adds
770 * the swizzle to the offset for us.
772 unsigned shift
= (nir_intrinsic_base(instr
) % 16) / 4;
773 assert(shift
+ instr
->num_components
<= 4);
775 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
777 /* Offsets are in bytes but they should always be multiples of 4 */
778 assert(const_offset
->u32
[0] % 4 == 0);
780 unsigned offset
= const_offset
->u32
[0] + shift
* 4;
781 src
.offset
= ROUND_DOWN_TO(offset
, 16);
782 shift
= (offset
% 16) / 4;
783 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
785 emit(MOV(dest
, src
));
787 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
789 src_reg indirect
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
791 /* MOV_INDIRECT is going to stomp the whole thing anyway */
792 dest
.writemask
= WRITEMASK_XYZW
;
794 emit(SHADER_OPCODE_MOV_INDIRECT
, dest
, src
,
795 indirect
, brw_imm_ud(instr
->const_index
[1]));
800 case nir_intrinsic_atomic_counter_read
:
801 case nir_intrinsic_atomic_counter_inc
:
802 case nir_intrinsic_atomic_counter_dec
: {
803 unsigned surf_index
= prog_data
->base
.binding_table
.abo_start
+
804 (unsigned) instr
->const_index
[0];
805 const vec4_builder bld
=
806 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
808 /* Get some metadata from the image intrinsic. */
809 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
811 /* Get the arguments of the atomic intrinsic. */
812 src_reg offset
= get_nir_src(instr
->src
[0], nir_type_int32
,
813 instr
->num_components
);
814 const src_reg surface
= brw_imm_ud(surf_index
);
815 const src_reg src0
= (info
->num_srcs
>= 2
816 ? get_nir_src(instr
->src
[1]) : src_reg());
817 const src_reg src1
= (info
->num_srcs
>= 3
818 ? get_nir_src(instr
->src
[2]) : src_reg());
822 dest
= get_nir_dest(instr
->dest
);
824 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
825 tmp
= emit_untyped_read(bld
, surface
, offset
, 1, 1);
827 tmp
= emit_untyped_atomic(bld
, surface
, offset
,
830 get_atomic_counter_op(instr
->intrinsic
));
833 bld
.MOV(retype(dest
, tmp
.type
), tmp
);
834 brw_mark_surface_used(stage_prog_data
, surf_index
);
838 case nir_intrinsic_load_ubo
: {
839 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
842 dest
= get_nir_dest(instr
->dest
);
844 if (const_block_index
) {
845 /* The block index is a constant, so just emit the binding table entry
848 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
849 const_block_index
->u32
[0];
850 surf_index
= brw_imm_ud(index
);
851 brw_mark_surface_used(&prog_data
->base
, index
);
853 /* The block index is not a constant. Evaluate the index expression
854 * per-channel and add the base UBO index; we have to select a value
855 * from any live channel.
857 surf_index
= src_reg(this, glsl_type::uint_type
);
858 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int32
,
859 instr
->num_components
),
860 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
861 surf_index
= emit_uniformize(surf_index
);
863 /* Assume this may touch any UBO. It would be nice to provide
864 * a tighter bound, but the array information is already lowered away.
866 brw_mark_surface_used(&prog_data
->base
,
867 prog_data
->base
.binding_table
.ubo_start
+
868 nir
->info
.num_ubos
- 1);
872 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
874 offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
876 offset_reg
= get_nir_src(instr
->src
[1], nir_type_uint32
, 1);
879 src_reg packed_consts
;
880 if (nir_dest_bit_size(instr
->dest
) == 32) {
881 packed_consts
= src_reg(this, glsl_type::vec4_type
);
882 emit_pull_constant_load_reg(dst_reg(packed_consts
),
885 NULL
, NULL
/* before_block/inst */);
887 src_reg temp
= src_reg(this, glsl_type::dvec4_type
);
888 src_reg temp_float
= retype(temp
, BRW_REGISTER_TYPE_F
);
890 emit_pull_constant_load_reg(dst_reg(temp_float
),
891 surf_index
, offset_reg
, NULL
, NULL
);
892 if (offset_reg
.file
== IMM
)
895 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16u)));
896 emit_pull_constant_load_reg(dst_reg(byte_offset(temp_float
, REG_SIZE
)),
897 surf_index
, offset_reg
, NULL
, NULL
);
899 packed_consts
= src_reg(this, glsl_type::dvec4_type
);
900 shuffle_64bit_data(dst_reg(packed_consts
), temp
, false);
903 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
905 unsigned type_size
= type_sz(dest
.type
);
906 packed_consts
.swizzle
+=
907 BRW_SWIZZLE4(const_offset
->u32
[0] % 16 / type_size
,
908 const_offset
->u32
[0] % 16 / type_size
,
909 const_offset
->u32
[0] % 16 / type_size
,
910 const_offset
->u32
[0] % 16 / type_size
);
913 emit(MOV(dest
, retype(packed_consts
, dest
.type
)));
918 case nir_intrinsic_memory_barrier
: {
919 const vec4_builder bld
=
920 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
921 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
922 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
923 ->size_written
= 2 * REG_SIZE
;
927 case nir_intrinsic_shader_clock
: {
928 /* We cannot do anything if there is an event, so ignore it for now */
929 const src_reg shader_clock
= get_timestamp();
930 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
932 dest
= get_nir_dest(instr
->dest
, type
);
933 emit(MOV(dest
, shader_clock
));
938 unreachable("Unknown intrinsic");
943 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
946 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
947 dest
= get_nir_dest(instr
->dest
);
950 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
952 unsigned surf_index
= prog_data
->base
.binding_table
.ssbo_start
+
953 const_surface
->u32
[0];
954 surface
= brw_imm_ud(surf_index
);
955 brw_mark_surface_used(&prog_data
->base
, surf_index
);
957 surface
= src_reg(this, glsl_type::uint_type
);
958 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
959 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
961 /* Assume this may touch any UBO. This is the same we do for other
962 * UBO/SSBO accesses with non-constant surface.
964 brw_mark_surface_used(&prog_data
->base
,
965 prog_data
->base
.binding_table
.ssbo_start
+
966 nir
->info
.num_ssbos
- 1);
969 src_reg offset
= get_nir_src(instr
->src
[1], 1);
970 src_reg data1
= get_nir_src(instr
->src
[2], 1);
972 if (op
== BRW_AOP_CMPWR
)
973 data2
= get_nir_src(instr
->src
[3], 1);
975 /* Emit the actual atomic operation operation */
976 const vec4_builder bld
=
977 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
979 src_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
981 1 /* dims */, 1 /* rsize */,
984 dest
.type
= atomic_result
.type
;
985 bld
.MOV(dest
, atomic_result
);
989 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
991 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
994 static enum brw_conditional_mod
995 brw_conditional_for_nir_comparison(nir_op op
)
1001 return BRW_CONDITIONAL_L
;
1006 return BRW_CONDITIONAL_GE
;
1010 case nir_op_ball_fequal2
:
1011 case nir_op_ball_iequal2
:
1012 case nir_op_ball_fequal3
:
1013 case nir_op_ball_iequal3
:
1014 case nir_op_ball_fequal4
:
1015 case nir_op_ball_iequal4
:
1016 return BRW_CONDITIONAL_Z
;
1020 case nir_op_bany_fnequal2
:
1021 case nir_op_bany_inequal2
:
1022 case nir_op_bany_fnequal3
:
1023 case nir_op_bany_inequal3
:
1024 case nir_op_bany_fnequal4
:
1025 case nir_op_bany_inequal4
:
1026 return BRW_CONDITIONAL_NZ
;
1029 unreachable("not reached: bad operation for comparison");
1034 vec4_visitor::optimize_predicate(nir_alu_instr
*instr
,
1035 enum brw_predicate
*predicate
)
1037 if (!instr
->src
[0].src
.is_ssa
||
1038 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
1041 nir_alu_instr
*cmp_instr
=
1042 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
1044 switch (cmp_instr
->op
) {
1045 case nir_op_bany_fnequal2
:
1046 case nir_op_bany_inequal2
:
1047 case nir_op_bany_fnequal3
:
1048 case nir_op_bany_inequal3
:
1049 case nir_op_bany_fnequal4
:
1050 case nir_op_bany_inequal4
:
1051 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1053 case nir_op_ball_fequal2
:
1054 case nir_op_ball_iequal2
:
1055 case nir_op_ball_fequal3
:
1056 case nir_op_ball_iequal3
:
1057 case nir_op_ball_fequal4
:
1058 case nir_op_ball_iequal4
:
1059 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1065 unsigned size_swizzle
=
1066 brw_swizzle_for_size(nir_op_infos
[cmp_instr
->op
].input_sizes
[0]);
1069 assert(nir_op_infos
[cmp_instr
->op
].num_inputs
== 2);
1070 for (unsigned i
= 0; i
< 2; i
++) {
1071 nir_alu_type type
= nir_op_infos
[cmp_instr
->op
].input_types
[i
];
1072 unsigned bit_size
= nir_src_bit_size(cmp_instr
->src
[i
].src
);
1073 type
= (nir_alu_type
) (((unsigned) type
) | bit_size
);
1074 op
[i
] = get_nir_src(cmp_instr
->src
[i
].src
, type
, 4);
1075 unsigned base_swizzle
=
1076 brw_swizzle_for_nir_swizzle(cmp_instr
->src
[i
].swizzle
);
1077 op
[i
].swizzle
= brw_compose_swizzle(size_swizzle
, base_swizzle
);
1078 op
[i
].abs
= cmp_instr
->src
[i
].abs
;
1079 op
[i
].negate
= cmp_instr
->src
[i
].negate
;
1082 emit(CMP(dst_null_d(), op
[0], op
[1],
1083 brw_conditional_for_nir_comparison(cmp_instr
->op
)));
1089 emit_find_msb_using_lzd(const vec4_builder
&bld
,
1094 vec4_instruction
*inst
;
1098 /* LZD of an absolute value source almost always does the right
1099 * thing. There are two problem values:
1101 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
1102 * 0. However, findMSB(int(0x80000000)) == 30.
1104 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
1105 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
1107 * For a value of zero or negative one, -1 will be returned.
1109 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
1110 * findMSB(-(1<<x)) should return x-1.
1112 * For all negative number cases, including 0x80000000 and
1113 * 0xffffffff, the correct value is obtained from LZD if instead of
1114 * negating the (already negative) value the logical-not is used. A
1115 * conditonal logical-not can be achieved in two instructions.
1117 temp
= src_reg(bld
.vgrf(BRW_REGISTER_TYPE_D
));
1119 bld
.ASR(dst_reg(temp
), src
, brw_imm_d(31));
1120 bld
.XOR(dst_reg(temp
), temp
, src
);
1123 bld
.LZD(retype(dst
, BRW_REGISTER_TYPE_UD
),
1124 retype(temp
, BRW_REGISTER_TYPE_UD
));
1126 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
1127 * from the LSB side. Subtract the result from 31 to convert the MSB count
1128 * into an LSB count. If no bits are set, LZD will return 32. 31-32 = -1,
1129 * which is exactly what findMSB() is supposed to return.
1131 inst
= bld
.ADD(dst
, retype(src_reg(dst
), BRW_REGISTER_TYPE_D
),
1133 inst
->src
[0].negate
= true;
1137 vec4_visitor::emit_conversion_from_double(dst_reg dst
, src_reg src
,
1140 /* BDW PRM vol 15 - workarounds:
1141 * DF->f format conversion for Align16 has wrong emask calculation when
1142 * source is immediate.
1144 if (devinfo
->gen
== 8 && dst
.type
== BRW_REGISTER_TYPE_F
&&
1145 src
.file
== BRW_IMMEDIATE_VALUE
) {
1146 vec4_instruction
*inst
= emit(MOV(dst
, brw_imm_f(src
.df
)));
1147 inst
->saturate
= saturate
;
1153 case BRW_REGISTER_TYPE_D
:
1154 op
= VEC4_OPCODE_DOUBLE_TO_D32
;
1156 case BRW_REGISTER_TYPE_UD
:
1157 op
= VEC4_OPCODE_DOUBLE_TO_U32
;
1159 case BRW_REGISTER_TYPE_F
:
1160 op
= VEC4_OPCODE_DOUBLE_TO_F32
;
1163 unreachable("Unknown conversion");
1166 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1167 emit(MOV(temp
, src
));
1168 dst_reg temp2
= dst_reg(this, glsl_type::dvec4_type
);
1169 emit(op
, temp2
, src_reg(temp
));
1171 emit(VEC4_OPCODE_PICK_LOW_32BIT
, retype(temp2
, dst
.type
), src_reg(temp2
));
1172 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(retype(temp2
, dst
.type
))));
1173 inst
->saturate
= saturate
;
1177 vec4_visitor::emit_conversion_to_double(dst_reg dst
, src_reg src
,
1180 dst_reg tmp_dst
= dst_reg(src_reg(this, glsl_type::dvec4_type
));
1181 src_reg tmp_src
= retype(src_reg(this, glsl_type::vec4_type
), src
.type
);
1182 emit(MOV(dst_reg(tmp_src
), src
));
1183 emit(VEC4_OPCODE_TO_DOUBLE
, tmp_dst
, tmp_src
);
1184 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(tmp_dst
)));
1185 inst
->saturate
= saturate
;
1189 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
1191 vec4_instruction
*inst
;
1193 nir_alu_type dst_type
= (nir_alu_type
) (nir_op_infos
[instr
->op
].output_type
|
1194 nir_dest_bit_size(instr
->dest
.dest
));
1195 dst_reg dst
= get_nir_dest(instr
->dest
.dest
, dst_type
);
1196 dst
.writemask
= instr
->dest
.write_mask
;
1199 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1200 nir_alu_type src_type
= (nir_alu_type
)
1201 (nir_op_infos
[instr
->op
].input_types
[i
] |
1202 nir_src_bit_size(instr
->src
[i
].src
));
1203 op
[i
] = get_nir_src(instr
->src
[i
].src
, src_type
, 4);
1204 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
1205 op
[i
].abs
= instr
->src
[i
].abs
;
1206 op
[i
].negate
= instr
->src
[i
].negate
;
1209 switch (instr
->op
) {
1212 inst
= emit(MOV(dst
, op
[0]));
1213 inst
->saturate
= instr
->dest
.saturate
;
1219 unreachable("not reached: should be handled by lower_vec_to_movs()");
1223 inst
= emit(MOV(dst
, op
[0]));
1224 inst
->saturate
= instr
->dest
.saturate
;
1230 if (nir_src_bit_size(instr
->src
[0].src
) == 64)
1231 emit_conversion_from_double(dst
, op
[0], instr
->dest
.saturate
);
1233 inst
= emit(MOV(dst
, op
[0]));
1239 emit_conversion_to_double(dst
, op
[0], instr
->dest
.saturate
);
1243 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1246 inst
= emit(ADD(dst
, op
[0], op
[1]));
1247 inst
->saturate
= instr
->dest
.saturate
;
1251 inst
= emit(MUL(dst
, op
[0], op
[1]));
1252 inst
->saturate
= instr
->dest
.saturate
;
1256 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1257 if (devinfo
->gen
< 8) {
1258 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
1259 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
1261 /* For integer multiplication, the MUL uses the low 16 bits of one of
1262 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1263 * accumulates in the contribution of the upper 16 bits of that
1264 * operand. If we can determine that one of the args is in the low
1265 * 16 bits, though, we can just emit a single MUL.
1267 if (value0
&& value0
->u32
[0] < (1 << 16)) {
1268 if (devinfo
->gen
< 7)
1269 emit(MUL(dst
, op
[0], op
[1]));
1271 emit(MUL(dst
, op
[1], op
[0]));
1272 } else if (value1
&& value1
->u32
[0] < (1 << 16)) {
1273 if (devinfo
->gen
< 7)
1274 emit(MUL(dst
, op
[1], op
[0]));
1276 emit(MUL(dst
, op
[0], op
[1]));
1278 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1280 emit(MUL(acc
, op
[0], op
[1]));
1281 emit(MACH(dst_null_d(), op
[0], op
[1]));
1282 emit(MOV(dst
, src_reg(acc
)));
1285 emit(MUL(dst
, op
[0], op
[1]));
1290 case nir_op_imul_high
:
1291 case nir_op_umul_high
: {
1292 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1293 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1295 if (devinfo
->gen
>= 8)
1296 emit(MUL(acc
, op
[0], retype(op
[1], BRW_REGISTER_TYPE_UW
)));
1298 emit(MUL(acc
, op
[0], op
[1]));
1300 emit(MACH(dst
, op
[0], op
[1]));
1305 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1306 inst
->saturate
= instr
->dest
.saturate
;
1310 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1311 inst
->saturate
= instr
->dest
.saturate
;
1315 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1316 inst
->saturate
= instr
->dest
.saturate
;
1320 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1321 inst
->saturate
= instr
->dest
.saturate
;
1325 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1326 inst
->saturate
= instr
->dest
.saturate
;
1331 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1332 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1337 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1338 * appears that our hardware just does the right thing for signed
1341 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1342 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1346 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1347 inst
= emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1349 /* Math instructions don't support conditional mod */
1350 inst
= emit(MOV(dst_null_d(), src_reg(dst
)));
1351 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1353 /* Now, we need to determine if signs of the sources are different.
1354 * When we XOR the sources, the top bit is 0 if they are the same and 1
1355 * if they are different. We can then use a conditional modifier to
1356 * turn that into a predicate. This leads us to an XOR.l instruction.
1358 * Technically, according to the PRM, you're not allowed to use .l on a
1359 * XOR instruction. However, emperical experiments and Curro's reading
1360 * of the simulator source both indicate that it's safe.
1362 src_reg tmp
= src_reg(this, glsl_type::ivec4_type
);
1363 inst
= emit(XOR(dst_reg(tmp
), op
[0], op
[1]));
1364 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1365 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1367 /* If the result of the initial remainder operation is non-zero and the
1368 * two sources have different signs, add in a copy of op[1] to get the
1369 * final integer modulus value.
1371 inst
= emit(ADD(dst
, src_reg(dst
), op
[1]));
1372 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1377 unreachable("not reached: should be handled by ldexp_to_arith()");
1380 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1381 inst
->saturate
= instr
->dest
.saturate
;
1385 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1386 inst
->saturate
= instr
->dest
.saturate
;
1390 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1391 inst
->saturate
= instr
->dest
.saturate
;
1394 case nir_op_uadd_carry
: {
1395 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1396 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1398 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1399 emit(MOV(dst
, src_reg(acc
)));
1403 case nir_op_usub_borrow
: {
1404 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1405 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1407 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1408 emit(MOV(dst
, src_reg(acc
)));
1413 inst
= emit(RNDZ(dst
, op
[0]));
1414 inst
->saturate
= instr
->dest
.saturate
;
1417 case nir_op_fceil
: {
1418 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1420 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1421 instr
->src
[0].src
.ssa
->num_components
:
1422 instr
->src
[0].src
.reg
.reg
->num_components
);
1424 op
[0].negate
= !op
[0].negate
;
1425 emit(RNDD(dst_reg(tmp
), op
[0]));
1427 inst
= emit(MOV(dst
, tmp
));
1428 inst
->saturate
= instr
->dest
.saturate
;
1433 inst
= emit(RNDD(dst
, op
[0]));
1434 inst
->saturate
= instr
->dest
.saturate
;
1438 inst
= emit(FRC(dst
, op
[0]));
1439 inst
->saturate
= instr
->dest
.saturate
;
1442 case nir_op_fround_even
:
1443 inst
= emit(RNDE(dst
, op
[0]));
1444 inst
->saturate
= instr
->dest
.saturate
;
1447 case nir_op_fquantize2f16
: {
1448 /* See also vec4_visitor::emit_pack_half_2x16() */
1449 src_reg tmp16
= src_reg(this, glsl_type::uvec4_type
);
1450 src_reg tmp32
= src_reg(this, glsl_type::vec4_type
);
1451 src_reg zero
= src_reg(this, glsl_type::vec4_type
);
1453 /* Check for denormal */
1454 src_reg abs_src0
= op
[0];
1455 abs_src0
.abs
= true;
1456 emit(CMP(dst_null_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1457 BRW_CONDITIONAL_L
));
1458 /* Get the appropriately signed zero */
1459 emit(AND(retype(dst_reg(zero
), BRW_REGISTER_TYPE_UD
),
1460 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1461 brw_imm_ud(0x80000000)));
1462 /* Do the actual F32 -> F16 -> F32 conversion */
1463 emit(F32TO16(dst_reg(tmp16
), op
[0]));
1464 emit(F16TO32(dst_reg(tmp32
), tmp16
));
1465 /* Select that or zero based on normal status */
1466 inst
= emit(BRW_OPCODE_SEL
, dst
, zero
, tmp32
);
1467 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1468 inst
->saturate
= instr
->dest
.saturate
;
1474 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1477 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1478 inst
->saturate
= instr
->dest
.saturate
;
1483 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1486 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1487 inst
->saturate
= instr
->dest
.saturate
;
1491 case nir_op_fddx_coarse
:
1492 case nir_op_fddx_fine
:
1494 case nir_op_fddy_coarse
:
1495 case nir_op_fddy_fine
:
1496 unreachable("derivatives are not valid in vertex shaders");
1504 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1510 enum brw_conditional_mod conditional_mod
=
1511 brw_conditional_for_nir_comparison(instr
->op
);
1513 if (nir_src_bit_size(instr
->src
[0].src
) < 64) {
1514 emit(CMP(dst
, op
[0], op
[1], conditional_mod
));
1516 /* Produce a 32-bit boolean result from the DF comparison by selecting
1517 * only the low 32-bit in each DF produced. Do this in a temporary
1518 * so we can then move from there to the result using align16 again
1519 * to honor the original writemask.
1521 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1522 emit(CMP(temp
, op
[0], op
[1], conditional_mod
));
1523 dst_reg result
= dst_reg(this, glsl_type::bvec4_type
);
1524 emit(VEC4_OPCODE_PICK_LOW_32BIT
, result
, src_reg(temp
));
1525 emit(MOV(dst
, src_reg(result
)));
1530 case nir_op_ball_iequal2
:
1531 case nir_op_ball_iequal3
:
1532 case nir_op_ball_iequal4
:
1533 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1535 case nir_op_ball_fequal2
:
1536 case nir_op_ball_fequal3
:
1537 case nir_op_ball_fequal4
: {
1539 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1541 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1542 brw_conditional_for_nir_comparison(instr
->op
)));
1543 emit(MOV(dst
, brw_imm_d(0)));
1544 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1545 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1549 case nir_op_bany_inequal2
:
1550 case nir_op_bany_inequal3
:
1551 case nir_op_bany_inequal4
:
1552 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1554 case nir_op_bany_fnequal2
:
1555 case nir_op_bany_fnequal3
:
1556 case nir_op_bany_fnequal4
: {
1558 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1560 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1561 brw_conditional_for_nir_comparison(instr
->op
)));
1563 emit(MOV(dst
, brw_imm_d(0)));
1564 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1565 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1570 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1571 if (devinfo
->gen
>= 8) {
1572 op
[0] = resolve_source_modifiers(op
[0]);
1574 emit(NOT(dst
, op
[0]));
1578 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1579 if (devinfo
->gen
>= 8) {
1580 op
[0] = resolve_source_modifiers(op
[0]);
1581 op
[1] = resolve_source_modifiers(op
[1]);
1583 emit(XOR(dst
, op
[0], op
[1]));
1587 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1588 if (devinfo
->gen
>= 8) {
1589 op
[0] = resolve_source_modifiers(op
[0]);
1590 op
[1] = resolve_source_modifiers(op
[1]);
1592 emit(OR(dst
, op
[0], op
[1]));
1596 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1597 if (devinfo
->gen
>= 8) {
1598 op
[0] = resolve_source_modifiers(op
[0]);
1599 op
[1] = resolve_source_modifiers(op
[1]);
1601 emit(AND(dst
, op
[0], op
[1]));
1606 emit(MOV(dst
, negate(op
[0])));
1610 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1611 /* We use a MOV with conditional_mod to check if the provided value is
1612 * 0.0. We want this to flush denormalized numbers to zero, so we set a
1613 * source modifier on the source operand to trigger this, as source
1614 * modifiers don't affect the result of the testing against 0.0.
1616 src_reg value
= op
[0];
1618 vec4_instruction
*inst
= emit(MOV(dst_null_df(), value
));
1619 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1621 src_reg one
= src_reg(this, glsl_type::ivec4_type
);
1622 emit(MOV(dst_reg(one
), brw_imm_d(~0)));
1623 inst
= emit(BRW_OPCODE_SEL
, dst
, one
, brw_imm_d(0));
1624 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1626 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1631 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1634 case nir_op_fnoise1_1
:
1635 case nir_op_fnoise1_2
:
1636 case nir_op_fnoise1_3
:
1637 case nir_op_fnoise1_4
:
1638 case nir_op_fnoise2_1
:
1639 case nir_op_fnoise2_2
:
1640 case nir_op_fnoise2_3
:
1641 case nir_op_fnoise2_4
:
1642 case nir_op_fnoise3_1
:
1643 case nir_op_fnoise3_2
:
1644 case nir_op_fnoise3_3
:
1645 case nir_op_fnoise3_4
:
1646 case nir_op_fnoise4_1
:
1647 case nir_op_fnoise4_2
:
1648 case nir_op_fnoise4_3
:
1649 case nir_op_fnoise4_4
:
1650 unreachable("not reached: should be handled by lower_noise");
1652 case nir_op_unpack_half_2x16_split_x
:
1653 case nir_op_unpack_half_2x16_split_y
:
1654 case nir_op_pack_half_2x16_split
:
1655 unreachable("not reached: should not occur in vertex shader");
1657 case nir_op_unpack_snorm_2x16
:
1658 case nir_op_unpack_unorm_2x16
:
1659 case nir_op_pack_snorm_2x16
:
1660 case nir_op_pack_unorm_2x16
:
1661 unreachable("not reached: should be handled by lower_packing_builtins");
1663 case nir_op_pack_uvec4_to_uint
:
1664 unreachable("not reached");
1666 case nir_op_pack_uvec2_to_uint
: {
1667 dst_reg tmp1
= dst_reg(this, glsl_type::uint_type
);
1668 tmp1
.writemask
= WRITEMASK_X
;
1669 op
[0].swizzle
= BRW_SWIZZLE_YYYY
;
1670 emit(SHL(tmp1
, op
[0], src_reg(brw_imm_ud(16u))));
1672 dst_reg tmp2
= dst_reg(this, glsl_type::uint_type
);
1673 tmp2
.writemask
= WRITEMASK_X
;
1674 op
[0].swizzle
= BRW_SWIZZLE_XXXX
;
1675 emit(AND(tmp2
, op
[0], src_reg(brw_imm_ud(0xffffu
))));
1677 emit(OR(dst
, src_reg(tmp1
), src_reg(tmp2
)));
1681 case nir_op_pack_64_2x32_split
: {
1682 dst_reg result
= dst_reg(this, glsl_type::dvec4_type
);
1683 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1684 emit(MOV(tmp
, retype(op
[0], BRW_REGISTER_TYPE_UD
)));
1685 emit(VEC4_OPCODE_SET_LOW_32BIT
, result
, src_reg(tmp
));
1686 emit(MOV(tmp
, retype(op
[1], BRW_REGISTER_TYPE_UD
)));
1687 emit(VEC4_OPCODE_SET_HIGH_32BIT
, result
, src_reg(tmp
));
1688 emit(MOV(dst
, src_reg(result
)));
1692 case nir_op_unpack_64_2x32_split_x
:
1693 case nir_op_unpack_64_2x32_split_y
: {
1694 enum opcode oper
= (instr
->op
== nir_op_unpack_64_2x32_split_x
) ?
1695 VEC4_OPCODE_PICK_LOW_32BIT
: VEC4_OPCODE_PICK_HIGH_32BIT
;
1696 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
1697 emit(MOV(tmp
, op
[0]));
1698 dst_reg tmp2
= dst_reg(this, glsl_type::uvec4_type
);
1699 emit(oper
, tmp2
, src_reg(tmp
));
1700 emit(MOV(dst
, src_reg(tmp2
)));
1704 case nir_op_unpack_half_2x16
:
1705 /* As NIR does not guarantee that we have a correct swizzle outside the
1706 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1707 * uses the source operand in an operation with WRITEMASK_Y while our
1708 * source operand has only size 1, it accessed incorrect data producing
1709 * regressions in Piglit. We repeat the swizzle of the first component on the
1710 * rest of components to avoid regressions. In the vec4_visitor IR code path
1711 * this is not needed because the operand has already the correct swizzle.
1713 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1714 emit_unpack_half_2x16(dst
, op
[0]);
1717 case nir_op_pack_half_2x16
:
1718 emit_pack_half_2x16(dst
, op
[0]);
1721 case nir_op_unpack_unorm_4x8
:
1722 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1723 emit_unpack_unorm_4x8(dst
, op
[0]);
1726 case nir_op_pack_unorm_4x8
:
1727 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1728 emit_pack_unorm_4x8(dst
, op
[0]);
1731 case nir_op_unpack_snorm_4x8
:
1732 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1733 emit_unpack_snorm_4x8(dst
, op
[0]);
1736 case nir_op_pack_snorm_4x8
:
1737 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1738 emit_pack_snorm_4x8(dst
, op
[0]);
1741 case nir_op_bitfield_reverse
:
1742 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1743 emit(BFREV(dst
, op
[0]));
1746 case nir_op_bit_count
:
1747 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1748 emit(CBIT(dst
, op
[0]));
1751 case nir_op_ufind_msb
:
1752 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1753 emit_find_msb_using_lzd(vec4_builder(this).at_end(), dst
, op
[0], false);
1756 case nir_op_ifind_msb
: {
1757 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1758 vec4_builder bld
= vec4_builder(this).at_end();
1761 if (devinfo
->gen
< 7) {
1762 emit_find_msb_using_lzd(bld
, dst
, op
[0], true);
1764 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1766 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1767 * count from the LSB side. If FBH didn't return an error
1768 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1769 * count into an LSB count.
1771 bld
.CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1773 inst
= bld
.ADD(dst
, src
, brw_imm_d(31));
1774 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1775 inst
->src
[0].negate
= true;
1780 case nir_op_find_lsb
: {
1781 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1782 vec4_builder bld
= vec4_builder(this).at_end();
1784 if (devinfo
->gen
< 7) {
1785 dst_reg temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1787 /* (x & -x) generates a value that consists of only the LSB of x.
1788 * For all powers of 2, findMSB(y) == findLSB(y).
1790 src_reg src
= src_reg(retype(op
[0], BRW_REGISTER_TYPE_D
));
1791 src_reg negated_src
= src
;
1793 /* One must be negated, and the other must be non-negated. It
1794 * doesn't matter which is which.
1796 negated_src
.negate
= true;
1799 bld
.AND(temp
, src
, negated_src
);
1800 emit_find_msb_using_lzd(bld
, dst
, src_reg(temp
), false);
1802 bld
.FBL(dst
, op
[0]);
1807 case nir_op_ubitfield_extract
:
1808 case nir_op_ibitfield_extract
:
1809 unreachable("should have been lowered");
1812 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1813 op
[0] = fix_3src_operand(op
[0]);
1814 op
[1] = fix_3src_operand(op
[1]);
1815 op
[2] = fix_3src_operand(op
[2]);
1817 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1821 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1822 emit(BFI1(dst
, op
[0], op
[1]));
1826 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1827 op
[0] = fix_3src_operand(op
[0]);
1828 op
[1] = fix_3src_operand(op
[1]);
1829 op
[2] = fix_3src_operand(op
[2]);
1831 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1834 case nir_op_bitfield_insert
:
1835 unreachable("not reached: should have been lowered");
1838 if (type_sz(op
[0].type
) < 8) {
1839 /* AND(val, 0x80000000) gives the sign bit.
1841 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1844 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1846 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1847 dst
.type
= BRW_REGISTER_TYPE_UD
;
1848 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1850 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1851 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1852 dst
.type
= BRW_REGISTER_TYPE_F
;
1854 if (instr
->dest
.saturate
) {
1855 inst
= emit(MOV(dst
, src_reg(dst
)));
1856 inst
->saturate
= true;
1859 /* For doubles we do the same but we need to consider:
1861 * - We use a MOV with conditional_mod instead of a CMP so that we can
1862 * skip loading a 0.0 immediate. We use a source modifier on the
1863 * source of the MOV so that we flush denormalized values to 0.
1864 * Since we want to compare against 0, this won't alter the result.
1865 * - We need to extract the high 32-bit of each DF where the sign
1867 * - We need to produce a DF result.
1870 /* Check for zero */
1871 src_reg value
= op
[0];
1873 inst
= emit(MOV(dst_null_df(), value
));
1874 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1876 /* AND each high 32-bit channel with 0x80000000u */
1877 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1878 emit(VEC4_OPCODE_PICK_HIGH_32BIT
, tmp
, op
[0]);
1879 emit(AND(tmp
, src_reg(tmp
), brw_imm_ud(0x80000000u
)));
1881 /* Add 1.0 to each channel, predicated to skip the cases where the
1882 * channel's value was 0
1884 inst
= emit(OR(tmp
, src_reg(tmp
), brw_imm_ud(0x3f800000u
)));
1885 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1887 /* Now convert the result from float to double */
1888 emit_conversion_to_double(dst
, retype(src_reg(tmp
),
1889 BRW_REGISTER_TYPE_F
),
1890 instr
->dest
.saturate
);
1895 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1896 * -> non-negative val generates 0x00000000.
1897 * Predicated OR sets 1 if val is positive.
1899 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1900 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1901 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1902 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1903 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1907 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1908 emit(SHL(dst
, op
[0], op
[1]));
1912 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1913 emit(ASR(dst
, op
[0], op
[1]));
1917 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1918 emit(SHR(dst
, op
[0], op
[1]));
1922 if (type_sz(dst
.type
) == 8) {
1923 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
1924 emit(MUL(mul_dst
, op
[1], op
[0]));
1925 inst
= emit(ADD(dst
, src_reg(mul_dst
), op
[2]));
1926 inst
->saturate
= instr
->dest
.saturate
;
1928 op
[0] = fix_3src_operand(op
[0]);
1929 op
[1] = fix_3src_operand(op
[1]);
1930 op
[2] = fix_3src_operand(op
[2]);
1932 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1933 inst
->saturate
= instr
->dest
.saturate
;
1938 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1939 inst
->saturate
= instr
->dest
.saturate
;
1943 enum brw_predicate predicate
;
1944 if (!optimize_predicate(instr
, &predicate
)) {
1945 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1946 switch (dst
.writemask
) {
1948 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1951 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1954 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1957 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1960 predicate
= BRW_PREDICATE_NORMAL
;
1964 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1965 inst
->predicate
= predicate
;
1968 case nir_op_fdot_replicated2
:
1969 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1970 inst
->saturate
= instr
->dest
.saturate
;
1973 case nir_op_fdot_replicated3
:
1974 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1975 inst
->saturate
= instr
->dest
.saturate
;
1978 case nir_op_fdot_replicated4
:
1979 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1980 inst
->saturate
= instr
->dest
.saturate
;
1983 case nir_op_fdph_replicated
:
1984 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1985 inst
->saturate
= instr
->dest
.saturate
;
1990 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1995 unreachable("not reached: should be lowered by lower_source mods");
1998 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
2001 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
2005 unreachable("not reached: should be handled by ir_sub_to_add_neg");
2008 unreachable("Unimplemented ALU operation");
2011 /* If we need to do a boolean resolve, replace the result with -(x & 1)
2012 * to sign extend the low bit to 0/~0
2014 if (devinfo
->gen
<= 5 &&
2015 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
2016 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
2017 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
2018 masked
.writemask
= dst
.writemask
;
2019 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
2020 src_reg masked_neg
= src_reg(masked
);
2021 masked_neg
.negate
= true;
2022 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
2027 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
2029 switch (instr
->type
) {
2030 case nir_jump_break
:
2031 emit(BRW_OPCODE_BREAK
);
2034 case nir_jump_continue
:
2035 emit(BRW_OPCODE_CONTINUE
);
2038 case nir_jump_return
:
2041 unreachable("unknown jump");
2045 enum ir_texture_opcode
2046 ir_texture_opcode_for_nir_texop(nir_texop texop
)
2048 enum ir_texture_opcode op
;
2051 case nir_texop_lod
: op
= ir_lod
; break;
2052 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2053 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
2054 case nir_texop_tex
: op
= ir_tex
; break;
2055 case nir_texop_tg4
: op
= ir_tg4
; break;
2056 case nir_texop_txb
: op
= ir_txb
; break;
2057 case nir_texop_txd
: op
= ir_txd
; break;
2058 case nir_texop_txf
: op
= ir_txf
; break;
2059 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2060 case nir_texop_txl
: op
= ir_txl
; break;
2061 case nir_texop_txs
: op
= ir_txs
; break;
2062 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2064 unreachable("unknown texture opcode");
2070 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
2071 unsigned components
)
2073 return glsl_type::get_instance(brw_glsl_base_type_for_nir_type(alu_type
),
2078 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
2080 unsigned texture
= instr
->texture_index
;
2081 unsigned sampler
= instr
->sampler_index
;
2082 src_reg texture_reg
= brw_imm_ud(texture
);
2083 src_reg sampler_reg
= brw_imm_ud(sampler
);
2085 const glsl_type
*coord_type
= NULL
;
2086 src_reg shadow_comparator
;
2087 src_reg offset_value
;
2089 src_reg sample_index
;
2092 const glsl_type
*dest_type
=
2093 glsl_type_for_nir_alu_type(instr
->dest_type
,
2094 nir_tex_instr_dest_size(instr
));
2095 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
2097 /* The hardware requires a LOD for buffer textures */
2098 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
2101 /* Load the texture operation sources */
2102 uint32_t constant_offset
= 0;
2103 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2104 switch (instr
->src
[i
].src_type
) {
2105 case nir_tex_src_comparator
:
2106 shadow_comparator
= get_nir_src(instr
->src
[i
].src
,
2107 BRW_REGISTER_TYPE_F
, 1);
2110 case nir_tex_src_coord
: {
2111 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
2113 switch (instr
->op
) {
2115 case nir_texop_txf_ms
:
2116 case nir_texop_samples_identical
:
2117 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
2119 coord_type
= glsl_type::ivec(src_size
);
2123 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2125 coord_type
= glsl_type::vec(src_size
);
2131 case nir_tex_src_ddx
:
2132 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2133 nir_tex_instr_src_size(instr
, i
));
2136 case nir_tex_src_ddy
:
2137 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2138 nir_tex_instr_src_size(instr
, i
));
2141 case nir_tex_src_lod
:
2142 switch (instr
->op
) {
2145 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2149 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
2154 case nir_tex_src_ms_index
: {
2155 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2159 case nir_tex_src_offset
: {
2160 nir_const_value
*const_offset
=
2161 nir_src_as_const_value(instr
->src
[i
].src
);
2162 if (!const_offset
||
2163 !brw_texture_offset(const_offset
->i32
,
2164 nir_tex_instr_src_size(instr
, i
),
2165 &constant_offset
)) {
2167 get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
2172 case nir_tex_src_texture_offset
: {
2173 /* The highest texture which may be used by this operation is
2174 * the last element of the array. Mark it here, because the generator
2175 * doesn't have enough information to determine the bound.
2177 uint32_t array_size
= instr
->texture_array_size
;
2178 uint32_t max_used
= texture
+ array_size
- 1;
2179 if (instr
->op
== nir_texop_tg4
) {
2180 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2182 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2185 brw_mark_surface_used(&prog_data
->base
, max_used
);
2187 /* Emit code to evaluate the actual indexing expression */
2188 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2189 src_reg
temp(this, glsl_type::uint_type
);
2190 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(texture
)));
2191 texture_reg
= emit_uniformize(temp
);
2195 case nir_tex_src_sampler_offset
: {
2196 /* Emit code to evaluate the actual indexing expression */
2197 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2198 src_reg
temp(this, glsl_type::uint_type
);
2199 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
2200 sampler_reg
= emit_uniformize(temp
);
2204 case nir_tex_src_projector
:
2205 unreachable("Should be lowered by do_lower_texture_projection");
2207 case nir_tex_src_bias
:
2208 unreachable("LOD bias is not valid for vertex shaders.\n");
2211 unreachable("unknown texture source");
2215 if (instr
->op
== nir_texop_txf_ms
||
2216 instr
->op
== nir_texop_samples_identical
) {
2217 assert(coord_type
!= NULL
);
2218 if (devinfo
->gen
>= 7 &&
2219 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
2220 mcs
= emit_mcs_fetch(coord_type
, coordinate
, texture_reg
);
2222 mcs
= brw_imm_ud(0u);
2226 /* Stuff the channel select bits in the top of the texture offset */
2227 if (instr
->op
== nir_texop_tg4
) {
2228 if (instr
->component
== 1 &&
2229 (key_tex
->gather_channel_quirk_mask
& (1 << texture
))) {
2230 /* gather4 sampler is broken for green channel on RG32F --
2231 * we must ask for blue instead.
2233 constant_offset
|= 2 << 16;
2235 constant_offset
|= instr
->component
<< 16;
2239 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
2241 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
2243 lod
, lod2
, sample_index
,
2244 constant_offset
, offset_value
, mcs
,
2245 texture
, texture_reg
, sampler_reg
);
2249 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
2251 nir_ssa_values
[instr
->def
.index
] =
2252 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(instr
->def
.bit_size
, 32)));
2255 /* SIMD4x2 64bit data is stored in register space like this:
2257 * r0.0:DF x0 y0 z0 w0
2258 * r1.0:DF x1 y1 z1 w1
2260 * When we need to write data such as this to memory using 32-bit write
2261 * messages we need to shuffle it in this fashion:
2263 * r0.0:DF x0 y0 x1 y1 (to be written at base offset)
2264 * r0.0:DF z0 w0 z1 w1 (to be written at base offset + 16)
2266 * We need to do the inverse operation when we read using 32-bit messages,
2267 * which we can do by applying the same exact shuffling on the 64-bit data
2268 * read, only that because the data for each vertex is positioned differently
2269 * we need to apply different channel enables.
2271 * This function takes 64bit data and shuffles it as explained above.
2273 * The @for_write parameter is used to specify if the shuffling is being done
2274 * for proper SIMD4x2 64-bit data that needs to be shuffled prior to a 32-bit
2275 * write message (for_write = true), or instead we are doing the inverse
2276 * operation and we have just read 64-bit data using a 32-bit messages that we
2277 * need to shuffle to create valid SIMD4x2 64-bit data (for_write = false).
2279 * If @block and @ref are non-NULL, then the shuffling is done after @ref,
2280 * otherwise the instructions are emitted normally at the end. The function
2281 * returns the last instruction inserted.
2283 * Notice that @src and @dst cannot be the same register.
2286 vec4_visitor::shuffle_64bit_data(dst_reg dst
, src_reg src
, bool for_write
,
2287 bblock_t
*block
, vec4_instruction
*ref
)
2289 assert(type_sz(src
.type
) == 8);
2290 assert(type_sz(dst
.type
) == 8);
2291 assert(!regions_overlap(dst
, 2 * REG_SIZE
, src
, 2 * REG_SIZE
));
2292 assert(!ref
== !block
);
2294 const vec4_builder bld
= !ref
? vec4_builder(this).at_end() :
2295 vec4_builder(this).at(block
, ref
->next
);
2297 /* Resolve swizzle in src */
2298 vec4_instruction
*inst
;
2299 if (src
.swizzle
!= BRW_SWIZZLE_XYZW
) {
2300 dst_reg data
= dst_reg(this, glsl_type::dvec4_type
);
2301 inst
= bld
.MOV(data
, src
);
2302 src
= src_reg(data
);
2305 /* dst+0.XY = src+0.XY */
2306 inst
= bld
.group(4, 0).MOV(writemask(dst
, WRITEMASK_XY
), src
);
2308 /* dst+0.ZW = src+1.XY */
2309 inst
= bld
.group(4, for_write
? 1 : 0)
2310 .MOV(writemask(dst
, WRITEMASK_ZW
),
2311 swizzle(byte_offset(src
, REG_SIZE
), BRW_SWIZZLE_XYXY
));
2313 /* dst+1.XY = src+0.ZW */
2314 inst
= bld
.group(4, for_write
? 0 : 1)
2315 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_XY
),
2316 swizzle(src
, BRW_SWIZZLE_ZWZW
));
2318 /* dst+1.ZW = src+1.ZW */
2319 inst
= bld
.group(4, 1)
2320 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_ZW
),
2321 byte_offset(src
, REG_SIZE
));