2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
30 using namespace brw::surface_access
;
35 vec4_visitor::emit_nir_code()
37 if (nir
->num_uniforms
> 0)
40 nir_setup_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 vec4_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
56 setup_system_values_block(nir_block
*block
, vec4_visitor
*v
)
58 nir_foreach_instr(instr
, block
) {
59 if (instr
->type
!= nir_instr_type_intrinsic
)
62 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
63 v
->nir_setup_system_value_intrinsic(intrin
);
70 vec4_visitor::nir_setup_system_values()
72 nir_system_values
= ralloc_array(mem_ctx
, dst_reg
, SYSTEM_VALUE_MAX
);
73 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
74 nir_system_values
[i
] = dst_reg();
77 nir_foreach_function(function
, nir
) {
78 assert(strcmp(function
->name
, "main") == 0);
79 assert(function
->impl
);
80 nir_foreach_block(block
, function
->impl
) {
81 setup_system_values_block(block
, this);
87 vec4_visitor::nir_setup_uniforms()
89 uniforms
= nir
->num_uniforms
/ 16;
93 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
95 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
96 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
97 nir_locals
[i
] = dst_reg();
100 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
101 unsigned array_elems
=
102 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
103 const unsigned num_regs
= array_elems
* DIV_ROUND_UP(reg
->bit_size
, 32);
104 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(num_regs
));
106 if (reg
->bit_size
== 64)
107 nir_locals
[reg
->index
].type
= BRW_REGISTER_TYPE_DF
;
110 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
112 nir_emit_cf_list(&impl
->body
);
116 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
118 exec_list_validate(list
);
119 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
120 switch (node
->type
) {
122 nir_emit_if(nir_cf_node_as_if(node
));
125 case nir_cf_node_loop
:
126 nir_emit_loop(nir_cf_node_as_loop(node
));
129 case nir_cf_node_block
:
130 nir_emit_block(nir_cf_node_as_block(node
));
134 unreachable("Invalid CFG node block");
140 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
142 /* First, put the condition in f0 */
143 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
144 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
145 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
147 /* We can just predicate based on the X channel, as the condition only
148 * goes on its own line */
149 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
151 nir_emit_cf_list(&if_stmt
->then_list
);
153 /* note: if the else is empty, dead CF elimination will remove it */
154 emit(BRW_OPCODE_ELSE
);
156 nir_emit_cf_list(&if_stmt
->else_list
);
158 emit(BRW_OPCODE_ENDIF
);
162 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
166 nir_emit_cf_list(&loop
->body
);
168 emit(BRW_OPCODE_WHILE
);
172 vec4_visitor::nir_emit_block(nir_block
*block
)
174 nir_foreach_instr(instr
, block
) {
175 nir_emit_instr(instr
);
180 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
184 switch (instr
->type
) {
185 case nir_instr_type_load_const
:
186 nir_emit_load_const(nir_instr_as_load_const(instr
));
189 case nir_instr_type_intrinsic
:
190 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
193 case nir_instr_type_alu
:
194 nir_emit_alu(nir_instr_as_alu(instr
));
197 case nir_instr_type_jump
:
198 nir_emit_jump(nir_instr_as_jump(instr
));
201 case nir_instr_type_tex
:
202 nir_emit_texture(nir_instr_as_tex(instr
));
205 case nir_instr_type_ssa_undef
:
206 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
210 fprintf(stderr
, "VS instruction not yet implemented by NIR->vec4\n");
216 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
217 unsigned base_offset
, nir_src
*indirect
)
221 reg
= v
->nir_locals
[nir_reg
->index
];
222 if (nir_reg
->bit_size
== 64)
223 reg
.type
= BRW_REGISTER_TYPE_DF
;
224 reg
= offset(reg
, 8, base_offset
);
227 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
235 vec4_visitor::get_nir_dest(const nir_dest
&dest
)
239 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(dest
.ssa
.bit_size
, 32)));
240 if (dest
.ssa
.bit_size
== 64)
241 dst
.type
= BRW_REGISTER_TYPE_DF
;
242 nir_ssa_values
[dest
.ssa
.index
] = dst
;
245 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
251 vec4_visitor::get_nir_dest(const nir_dest
&dest
, enum brw_reg_type type
)
253 return retype(get_nir_dest(dest
), type
);
257 vec4_visitor::get_nir_dest(const nir_dest
&dest
, nir_alu_type type
)
259 return get_nir_dest(dest
, brw_type_for_nir_type(devinfo
, type
));
263 vec4_visitor::get_nir_src(const nir_src
&src
, enum brw_reg_type type
,
264 unsigned num_components
)
269 assert(src
.ssa
!= NULL
);
270 reg
= nir_ssa_values
[src
.ssa
->index
];
273 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
277 reg
= retype(reg
, type
);
279 src_reg reg_as_src
= src_reg(reg
);
280 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
285 vec4_visitor::get_nir_src(const nir_src
&src
, nir_alu_type type
,
286 unsigned num_components
)
288 return get_nir_src(src
, brw_type_for_nir_type(devinfo
, type
),
293 vec4_visitor::get_nir_src(const nir_src
&src
, unsigned num_components
)
295 /* if type is not specified, default to signed int */
296 return get_nir_src(src
, nir_type_int32
, num_components
);
300 vec4_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
302 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
303 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
306 /* The only constant offset we should find is 0. brw_nir.c's
307 * add_const_offset_to_base() will fold other constant offsets
308 * into instr->const_index[0].
310 assert(const_value
->u32
[0] == 0);
314 return get_nir_src(*offset_src
, BRW_REGISTER_TYPE_UD
, 1);
318 setup_imm_df(const vec4_builder
&bld
, double v
)
320 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
321 assert(devinfo
->gen
>= 7);
323 if (devinfo
->gen
>= 8)
324 return brw_imm_df(v
);
326 /* gen7.5 does not support DF immediates straighforward but the DIM
327 * instruction allows to set the 64-bit immediate value.
329 if (devinfo
->is_haswell
) {
330 const vec4_builder ubld
= bld
.exec_all();
331 const dst_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_DF
);
332 ubld
.DIM(dst
, brw_imm_df(v
));
333 return swizzle(src_reg(dst
), BRW_SWIZZLE_XXXX
);
336 /* gen7 does not support DF immediates */
347 /* Write the low 32-bit of the constant to the X:UD channel and the
348 * high 32-bit to the Y:UD channel to build the constant in a VGRF.
349 * We have to do this twice (offset 0 and offset 1), since a DF VGRF takes
350 * two SIMD8 registers in SIMD4x2 execution. Finally, return a swizzle
351 * XXXX so any access to the VGRF only reads the constant data in these
354 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
355 for (unsigned n
= 0; n
< 2; n
++) {
356 const vec4_builder ubld
= bld
.exec_all().group(4, n
);
357 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_X
), brw_imm_ud(di
.i1
));
358 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_Y
), brw_imm_ud(di
.i2
));
361 return swizzle(src_reg(retype(tmp
, BRW_REGISTER_TYPE_DF
)), BRW_SWIZZLE_XXXX
);
365 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
369 if (instr
->def
.bit_size
== 64) {
370 reg
= dst_reg(VGRF
, alloc
.allocate(2));
371 reg
.type
= BRW_REGISTER_TYPE_DF
;
373 reg
= dst_reg(VGRF
, alloc
.allocate(1));
374 reg
.type
= BRW_REGISTER_TYPE_D
;
377 const vec4_builder ibld
= vec4_builder(this).at_end();
378 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
380 /* @FIXME: consider emitting vector operations to save some MOVs in
381 * cases where the components are representable in 8 bits.
382 * For now, we emit a MOV for each distinct value.
384 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
385 unsigned writemask
= 1 << i
;
387 if ((remaining
& writemask
) == 0)
390 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
391 if ((instr
->def
.bit_size
== 32 &&
392 instr
->value
.u32
[i
] == instr
->value
.u32
[j
]) ||
393 (instr
->def
.bit_size
== 64 &&
394 instr
->value
.f64
[i
] == instr
->value
.f64
[j
])) {
399 reg
.writemask
= writemask
;
400 if (instr
->def
.bit_size
== 64) {
401 emit(MOV(reg
, setup_imm_df(ibld
, instr
->value
.f64
[i
])));
403 emit(MOV(reg
, brw_imm_d(instr
->value
.i32
[i
])));
406 remaining
&= ~writemask
;
409 /* Set final writemask */
410 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
412 nir_ssa_values
[instr
->def
.index
] = reg
;
416 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
421 switch (instr
->intrinsic
) {
423 case nir_intrinsic_load_input
: {
424 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
426 /* We set EmitNoIndirectInput for VS */
427 assert(const_offset
);
429 dest
= get_nir_dest(instr
->dest
);
430 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
432 src
= src_reg(ATTR
, instr
->const_index
[0] + const_offset
->u32
[0],
433 glsl_type::uvec4_type
);
434 src
= retype(src
, dest
.type
);
436 bool is_64bit
= nir_dest_bit_size(instr
->dest
) == 64;
438 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
439 src
.swizzle
= BRW_SWIZZLE_XYZW
;
440 shuffle_64bit_data(tmp
, src
, false);
441 emit(MOV(dest
, src_reg(tmp
)));
443 /* Swizzle source based on component layout qualifier */
444 src
.swizzle
= BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr
));
445 emit(MOV(dest
, src
));
450 case nir_intrinsic_store_output
: {
451 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
452 assert(const_offset
);
454 int varying
= instr
->const_index
[0] + const_offset
->u32
[0];
456 bool is_64bit
= nir_src_bit_size(instr
->src
[0]) == 64;
459 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_DF
,
460 instr
->num_components
);
461 data
= src_reg(this, glsl_type::dvec4_type
);
462 shuffle_64bit_data(dst_reg(data
), src
, true);
463 src
= retype(data
, BRW_REGISTER_TYPE_F
);
465 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
466 instr
->num_components
);
469 unsigned c
= nir_intrinsic_component(instr
);
470 output_reg
[varying
][c
] = dst_reg(src
);
471 output_num_components
[varying
][c
] = instr
->num_components
;
473 unsigned num_components
= instr
->num_components
;
477 output_reg
[varying
][c
] = dst_reg(src
);
478 output_num_components
[varying
][c
] = MIN2(4, num_components
);
480 if (is_64bit
&& num_components
> 4) {
481 assert(num_components
<= 8);
482 output_reg
[varying
+ 1][c
] = byte_offset(dst_reg(src
), REG_SIZE
);
483 output_num_components
[varying
+ 1][c
] = num_components
- 4;
488 case nir_intrinsic_get_buffer_size
: {
489 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
490 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
492 const unsigned index
=
493 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
494 dst_reg result_dst
= get_nir_dest(instr
->dest
);
495 vec4_instruction
*inst
= new(mem_ctx
)
496 vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE
, result_dst
);
499 inst
->mlen
= 1; /* always at least one */
500 inst
->src
[1] = brw_imm_ud(index
);
502 /* MRF for the first parameter */
503 src_reg lod
= brw_imm_d(0);
504 int param_base
= inst
->base_mrf
;
505 int writemask
= WRITEMASK_X
;
506 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
510 brw_mark_surface_used(&prog_data
->base
, index
);
514 case nir_intrinsic_store_ssbo
: {
515 assert(devinfo
->gen
>= 7);
519 nir_const_value
*const_uniform_block
=
520 nir_src_as_const_value(instr
->src
[1]);
521 if (const_uniform_block
) {
522 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
523 const_uniform_block
->u32
[0];
524 surf_index
= brw_imm_ud(index
);
525 brw_mark_surface_used(&prog_data
->base
, index
);
527 surf_index
= src_reg(this, glsl_type::uint_type
);
528 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
529 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
530 surf_index
= emit_uniformize(surf_index
);
532 brw_mark_surface_used(&prog_data
->base
,
533 prog_data
->base
.binding_table
.ssbo_start
+
534 nir
->info
.num_ssbos
- 1);
539 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
541 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
543 offset_reg
= get_nir_src(instr
->src
[2], 1);
547 src_reg val_reg
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
, 4);
550 unsigned write_mask
= instr
->const_index
[0];
552 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
553 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
554 * typed and untyped messages and across hardware platforms, the
555 * current implementation of the untyped messages will transparently convert
556 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
557 * and enabling only channel X on the SEND instruction.
559 * The above, works well for full vector writes, but not for partial writes
560 * where we want to write some channels and not others, like when we have
561 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
562 * quite restrictive with regards to the channel enables we can configure in
563 * the message descriptor (not all combinations are allowed) we cannot simply
564 * implement these scenarios with a single message while keeping the
565 * aforementioned symmetry in the implementation. For now we de decided that
566 * it is better to keep the symmetry to reduce complexity, so in situations
567 * such as the one described we end up emitting two untyped write messages
568 * (one for xy and another for w).
570 * The code below packs consecutive channels into a single write message,
571 * detects gaps in the vector write and if needed, sends a second message
572 * with the remaining channels. If in the future we decide that we want to
573 * emit a single message at the expense of losing the symmetry in the
574 * implementation we can:
576 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
577 * message payload. In this mode we can write up to 8 offsets and dwords
578 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
579 * and select which of the 8 channels carry data to write by setting the
580 * appropriate writemask in the dst register of the SEND instruction.
581 * It would require to write a new generator opcode specifically for
582 * IvyBridge since we would need to prepare a SIMD8 payload that could
583 * use any channel, not just X.
585 * 2) For Haswell+: Simply send a single write message but set the writemask
586 * on the dst of the SEND instruction to select the channels we want to
587 * write. It would require to modify the current messages to receive
588 * and honor the writemask provided.
590 const vec4_builder bld
= vec4_builder(this).at_end()
591 .annotate(current_annotation
, base_ir
);
593 unsigned type_slots
= nir_src_bit_size(instr
->src
[0]) / 32;
594 if (type_slots
== 2) {
595 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
596 shuffle_64bit_data(tmp
, retype(val_reg
, tmp
.type
), true);
597 val_reg
= src_reg(retype(tmp
, BRW_REGISTER_TYPE_F
));
600 uint8_t swizzle
[4] = { 0, 0, 0, 0};
601 int num_channels
= 0;
602 unsigned skipped_channels
= 0;
603 int num_components
= instr
->num_components
;
604 for (int i
= 0; i
< num_components
; i
++) {
605 /* Read components Z/W of a dvec from the appropriate place. We will
606 * also have to adjust the swizzle (we do that with the '% 4' below)
608 if (i
== 2 && type_slots
== 2)
609 val_reg
= byte_offset(val_reg
, REG_SIZE
);
611 /* Check if this channel needs to be written. If so, record the
612 * channel we need to take the data from in the swizzle array
614 int component_mask
= 1 << i
;
615 int write_test
= write_mask
& component_mask
;
617 /* If we are writing doubles we have to write 2 channels worth of
618 * of data (64 bits) for each double component.
620 swizzle
[num_channels
++] = (i
* type_slots
) % 4;
622 swizzle
[num_channels
++] = (i
* type_slots
+ 1) % 4;
625 /* If we don't have to write this channel it means we have a gap in the
626 * vector, so write the channels we accumulated until now, if any. Do
627 * the same if this was the last component in the vector, if we have
628 * enough channels for a full vec4 write or if we have processed
629 * components XY of a dvec (since components ZW are not in the same
632 if (!write_test
|| i
== num_components
- 1 || num_channels
== 4 ||
633 (i
== 1 && type_slots
== 2)) {
634 if (num_channels
> 0) {
635 /* We have channels to write, so update the offset we need to
636 * write at to skip the channels we skipped, if any.
638 if (skipped_channels
> 0) {
639 if (offset_reg
.file
== IMM
) {
640 offset_reg
.ud
+= 4 * skipped_channels
;
642 emit(ADD(dst_reg(offset_reg
), offset_reg
,
643 brw_imm_ud(4 * skipped_channels
)));
647 /* Swizzle the data register so we take the data from the channels
648 * we need to write and send the write message. This will write
649 * num_channels consecutive dwords starting at offset.
652 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
653 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
654 1 /* dims */, num_channels
/* size */,
657 /* If we have to do a second write we will have to update the
658 * offset so that we jump over the channels we have just written
661 skipped_channels
= num_channels
;
663 /* Restart the count for the next write message */
667 /* If we didn't write the channel, increase skipped count */
669 skipped_channels
+= type_slots
;
676 case nir_intrinsic_load_ssbo
: {
677 assert(devinfo
->gen
>= 7);
679 nir_const_value
*const_uniform_block
=
680 nir_src_as_const_value(instr
->src
[0]);
683 if (const_uniform_block
) {
684 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
685 const_uniform_block
->u32
[0];
686 surf_index
= brw_imm_ud(index
);
688 brw_mark_surface_used(&prog_data
->base
, index
);
690 surf_index
= src_reg(this, glsl_type::uint_type
);
691 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
692 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
693 surf_index
= emit_uniformize(surf_index
);
695 /* Assume this may touch any UBO. It would be nice to provide
696 * a tighter bound, but the array information is already lowered away.
698 brw_mark_surface_used(&prog_data
->base
,
699 prog_data
->base
.binding_table
.ssbo_start
+
700 nir
->info
.num_ssbos
- 1);
704 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
706 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
708 offset_reg
= get_nir_src(instr
->src
[1], 1);
711 /* Read the vector */
712 const vec4_builder bld
= vec4_builder(this).at_end()
713 .annotate(current_annotation
, base_ir
);
716 dst_reg dest
= get_nir_dest(instr
->dest
);
717 if (type_sz(dest
.type
) < 8) {
718 read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
719 1 /* dims */, 4 /* size*/,
722 src_reg shuffled
= src_reg(this, glsl_type::dvec4_type
);
725 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
726 1 /* dims */, 4 /* size*/,
728 emit(MOV(dst_reg(retype(shuffled
, temp
.type
)), temp
));
730 if (offset_reg
.file
== IMM
)
733 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16)));
735 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
736 1 /* dims */, 4 /* size*/,
738 emit(MOV(dst_reg(retype(byte_offset(shuffled
, REG_SIZE
), temp
.type
)),
741 read_result
= src_reg(this, glsl_type::dvec4_type
);
742 shuffle_64bit_data(dst_reg(read_result
), shuffled
, false);
745 read_result
.type
= dest
.type
;
746 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
747 emit(MOV(dest
, read_result
));
751 case nir_intrinsic_ssbo_atomic_add
:
752 nir_emit_ssbo_atomic(BRW_AOP_ADD
, instr
);
754 case nir_intrinsic_ssbo_atomic_imin
:
755 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
757 case nir_intrinsic_ssbo_atomic_umin
:
758 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
760 case nir_intrinsic_ssbo_atomic_imax
:
761 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
763 case nir_intrinsic_ssbo_atomic_umax
:
764 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
766 case nir_intrinsic_ssbo_atomic_and
:
767 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
769 case nir_intrinsic_ssbo_atomic_or
:
770 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
772 case nir_intrinsic_ssbo_atomic_xor
:
773 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
775 case nir_intrinsic_ssbo_atomic_exchange
:
776 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
778 case nir_intrinsic_ssbo_atomic_comp_swap
:
779 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
782 case nir_intrinsic_load_vertex_id
:
783 unreachable("should be lowered by lower_vertex_id()");
785 case nir_intrinsic_load_vertex_id_zero_base
:
786 case nir_intrinsic_load_base_vertex
:
787 case nir_intrinsic_load_instance_id
:
788 case nir_intrinsic_load_base_instance
:
789 case nir_intrinsic_load_draw_id
:
790 case nir_intrinsic_load_invocation_id
:
791 unreachable("should be lowered by brw_nir_lower_vs_inputs()");
793 case nir_intrinsic_load_uniform
: {
794 /* Offsets are in bytes but they should always be multiples of 4 */
795 assert(nir_intrinsic_base(instr
) % 4 == 0);
797 dest
= get_nir_dest(instr
->dest
);
799 src
= src_reg(dst_reg(UNIFORM
, nir_intrinsic_base(instr
) / 16));
800 src
.type
= dest
.type
;
802 /* Uniforms don't actually have to be vec4 aligned. In the case that
803 * it isn't, we have to use a swizzle to shift things around. They
804 * do still have the std140 alignment requirement that vec2's have to
805 * be vec2-aligned and vec3's and vec4's have to be vec4-aligned.
807 * The swizzle also works in the indirect case as the generator adds
808 * the swizzle to the offset for us.
810 unsigned shift
= (nir_intrinsic_base(instr
) % 16) / 4;
811 assert(shift
+ instr
->num_components
<= 4);
813 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
815 /* Offsets are in bytes but they should always be multiples of 4 */
816 assert(const_offset
->u32
[0] % 4 == 0);
818 unsigned offset
= const_offset
->u32
[0] + shift
* 4;
819 src
.offset
= ROUND_DOWN_TO(offset
, 16);
820 shift
= (offset
% 16) / 4;
821 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
823 emit(MOV(dest
, src
));
825 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
827 src_reg indirect
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
829 /* MOV_INDIRECT is going to stomp the whole thing anyway */
830 dest
.writemask
= WRITEMASK_XYZW
;
832 emit(SHADER_OPCODE_MOV_INDIRECT
, dest
, src
,
833 indirect
, brw_imm_ud(instr
->const_index
[1]));
838 case nir_intrinsic_atomic_counter_read
:
839 case nir_intrinsic_atomic_counter_inc
:
840 case nir_intrinsic_atomic_counter_dec
: {
841 unsigned surf_index
= prog_data
->base
.binding_table
.abo_start
+
842 (unsigned) instr
->const_index
[0];
843 const vec4_builder bld
=
844 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
846 /* Get some metadata from the image intrinsic. */
847 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
849 /* Get the arguments of the atomic intrinsic. */
850 src_reg offset
= get_nir_src(instr
->src
[0], nir_type_int32
,
851 instr
->num_components
);
852 const src_reg surface
= brw_imm_ud(surf_index
);
853 const src_reg src0
= (info
->num_srcs
>= 2
854 ? get_nir_src(instr
->src
[1]) : src_reg());
855 const src_reg src1
= (info
->num_srcs
>= 3
856 ? get_nir_src(instr
->src
[2]) : src_reg());
860 dest
= get_nir_dest(instr
->dest
);
862 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
863 tmp
= emit_untyped_read(bld
, surface
, offset
, 1, 1);
865 tmp
= emit_untyped_atomic(bld
, surface
, offset
,
868 get_atomic_counter_op(instr
->intrinsic
));
871 bld
.MOV(retype(dest
, tmp
.type
), tmp
);
872 brw_mark_surface_used(stage_prog_data
, surf_index
);
876 case nir_intrinsic_load_ubo
: {
877 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
880 dest
= get_nir_dest(instr
->dest
);
882 if (const_block_index
) {
883 /* The block index is a constant, so just emit the binding table entry
886 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
887 const_block_index
->u32
[0];
888 surf_index
= brw_imm_ud(index
);
889 brw_mark_surface_used(&prog_data
->base
, index
);
891 /* The block index is not a constant. Evaluate the index expression
892 * per-channel and add the base UBO index; we have to select a value
893 * from any live channel.
895 surf_index
= src_reg(this, glsl_type::uint_type
);
896 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int32
,
897 instr
->num_components
),
898 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
899 surf_index
= emit_uniformize(surf_index
);
901 /* Assume this may touch any UBO. It would be nice to provide
902 * a tighter bound, but the array information is already lowered away.
904 brw_mark_surface_used(&prog_data
->base
,
905 prog_data
->base
.binding_table
.ubo_start
+
906 nir
->info
.num_ubos
- 1);
910 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
912 offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
914 offset_reg
= get_nir_src(instr
->src
[1], nir_type_uint32
, 1);
917 src_reg packed_consts
;
918 if (nir_dest_bit_size(instr
->dest
) == 32) {
919 packed_consts
= src_reg(this, glsl_type::vec4_type
);
920 emit_pull_constant_load_reg(dst_reg(packed_consts
),
923 NULL
, NULL
/* before_block/inst */);
925 src_reg temp
= src_reg(this, glsl_type::dvec4_type
);
926 src_reg temp_float
= retype(temp
, BRW_REGISTER_TYPE_F
);
928 emit_pull_constant_load_reg(dst_reg(temp_float
),
929 surf_index
, offset_reg
, NULL
, NULL
);
930 if (offset_reg
.file
== IMM
)
933 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16u)));
934 emit_pull_constant_load_reg(dst_reg(byte_offset(temp_float
, REG_SIZE
)),
935 surf_index
, offset_reg
, NULL
, NULL
);
937 packed_consts
= src_reg(this, glsl_type::dvec4_type
);
938 shuffle_64bit_data(dst_reg(packed_consts
), temp
, false);
941 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
943 unsigned type_size
= type_sz(dest
.type
);
944 packed_consts
.swizzle
+=
945 BRW_SWIZZLE4(const_offset
->u32
[0] % 16 / type_size
,
946 const_offset
->u32
[0] % 16 / type_size
,
947 const_offset
->u32
[0] % 16 / type_size
,
948 const_offset
->u32
[0] % 16 / type_size
);
951 emit(MOV(dest
, retype(packed_consts
, dest
.type
)));
956 case nir_intrinsic_memory_barrier
: {
957 const vec4_builder bld
=
958 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
959 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
960 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
961 ->size_written
= 2 * REG_SIZE
;
965 case nir_intrinsic_shader_clock
: {
966 /* We cannot do anything if there is an event, so ignore it for now */
967 const src_reg shader_clock
= get_timestamp();
968 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
970 dest
= get_nir_dest(instr
->dest
, type
);
971 emit(MOV(dest
, shader_clock
));
976 unreachable("Unknown intrinsic");
981 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
984 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
985 dest
= get_nir_dest(instr
->dest
);
988 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
990 unsigned surf_index
= prog_data
->base
.binding_table
.ssbo_start
+
991 const_surface
->u32
[0];
992 surface
= brw_imm_ud(surf_index
);
993 brw_mark_surface_used(&prog_data
->base
, surf_index
);
995 surface
= src_reg(this, glsl_type::uint_type
);
996 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
997 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
999 /* Assume this may touch any UBO. This is the same we do for other
1000 * UBO/SSBO accesses with non-constant surface.
1002 brw_mark_surface_used(&prog_data
->base
,
1003 prog_data
->base
.binding_table
.ssbo_start
+
1004 nir
->info
.num_ssbos
- 1);
1007 src_reg offset
= get_nir_src(instr
->src
[1], 1);
1008 src_reg data1
= get_nir_src(instr
->src
[2], 1);
1010 if (op
== BRW_AOP_CMPWR
)
1011 data2
= get_nir_src(instr
->src
[3], 1);
1013 /* Emit the actual atomic operation operation */
1014 const vec4_builder bld
=
1015 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
1017 src_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
1019 1 /* dims */, 1 /* rsize */,
1021 BRW_PREDICATE_NONE
);
1022 dest
.type
= atomic_result
.type
;
1023 bld
.MOV(dest
, atomic_result
);
1027 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
1029 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1032 static enum brw_conditional_mod
1033 brw_conditional_for_nir_comparison(nir_op op
)
1039 return BRW_CONDITIONAL_L
;
1044 return BRW_CONDITIONAL_GE
;
1048 case nir_op_ball_fequal2
:
1049 case nir_op_ball_iequal2
:
1050 case nir_op_ball_fequal3
:
1051 case nir_op_ball_iequal3
:
1052 case nir_op_ball_fequal4
:
1053 case nir_op_ball_iequal4
:
1054 return BRW_CONDITIONAL_Z
;
1058 case nir_op_bany_fnequal2
:
1059 case nir_op_bany_inequal2
:
1060 case nir_op_bany_fnequal3
:
1061 case nir_op_bany_inequal3
:
1062 case nir_op_bany_fnequal4
:
1063 case nir_op_bany_inequal4
:
1064 return BRW_CONDITIONAL_NZ
;
1067 unreachable("not reached: bad operation for comparison");
1072 vec4_visitor::optimize_predicate(nir_alu_instr
*instr
,
1073 enum brw_predicate
*predicate
)
1075 if (!instr
->src
[0].src
.is_ssa
||
1076 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
1079 nir_alu_instr
*cmp_instr
=
1080 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
1082 switch (cmp_instr
->op
) {
1083 case nir_op_bany_fnequal2
:
1084 case nir_op_bany_inequal2
:
1085 case nir_op_bany_fnequal3
:
1086 case nir_op_bany_inequal3
:
1087 case nir_op_bany_fnequal4
:
1088 case nir_op_bany_inequal4
:
1089 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1091 case nir_op_ball_fequal2
:
1092 case nir_op_ball_iequal2
:
1093 case nir_op_ball_fequal3
:
1094 case nir_op_ball_iequal3
:
1095 case nir_op_ball_fequal4
:
1096 case nir_op_ball_iequal4
:
1097 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1103 unsigned size_swizzle
=
1104 brw_swizzle_for_size(nir_op_infos
[cmp_instr
->op
].input_sizes
[0]);
1107 assert(nir_op_infos
[cmp_instr
->op
].num_inputs
== 2);
1108 for (unsigned i
= 0; i
< 2; i
++) {
1109 nir_alu_type type
= nir_op_infos
[cmp_instr
->op
].input_types
[i
];
1110 unsigned bit_size
= nir_src_bit_size(cmp_instr
->src
[i
].src
);
1111 type
= (nir_alu_type
) (((unsigned) type
) | bit_size
);
1112 op
[i
] = get_nir_src(cmp_instr
->src
[i
].src
, type
, 4);
1113 unsigned base_swizzle
=
1114 brw_swizzle_for_nir_swizzle(cmp_instr
->src
[i
].swizzle
);
1115 op
[i
].swizzle
= brw_compose_swizzle(size_swizzle
, base_swizzle
);
1116 op
[i
].abs
= cmp_instr
->src
[i
].abs
;
1117 op
[i
].negate
= cmp_instr
->src
[i
].negate
;
1120 emit(CMP(dst_null_d(), op
[0], op
[1],
1121 brw_conditional_for_nir_comparison(cmp_instr
->op
)));
1127 emit_find_msb_using_lzd(const vec4_builder
&bld
,
1132 vec4_instruction
*inst
;
1136 /* LZD of an absolute value source almost always does the right
1137 * thing. There are two problem values:
1139 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
1140 * 0. However, findMSB(int(0x80000000)) == 30.
1142 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
1143 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
1145 * For a value of zero or negative one, -1 will be returned.
1147 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
1148 * findMSB(-(1<<x)) should return x-1.
1150 * For all negative number cases, including 0x80000000 and
1151 * 0xffffffff, the correct value is obtained from LZD if instead of
1152 * negating the (already negative) value the logical-not is used. A
1153 * conditonal logical-not can be achieved in two instructions.
1155 temp
= src_reg(bld
.vgrf(BRW_REGISTER_TYPE_D
));
1157 bld
.ASR(dst_reg(temp
), src
, brw_imm_d(31));
1158 bld
.XOR(dst_reg(temp
), temp
, src
);
1161 bld
.LZD(retype(dst
, BRW_REGISTER_TYPE_UD
),
1162 retype(temp
, BRW_REGISTER_TYPE_UD
));
1164 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
1165 * from the LSB side. Subtract the result from 31 to convert the MSB count
1166 * into an LSB count. If no bits are set, LZD will return 32. 31-32 = -1,
1167 * which is exactly what findMSB() is supposed to return.
1169 inst
= bld
.ADD(dst
, retype(src_reg(dst
), BRW_REGISTER_TYPE_D
),
1171 inst
->src
[0].negate
= true;
1175 vec4_visitor::emit_conversion_from_double(dst_reg dst
, src_reg src
,
1178 /* BDW PRM vol 15 - workarounds:
1179 * DF->f format conversion for Align16 has wrong emask calculation when
1180 * source is immediate.
1182 if (devinfo
->gen
== 8 && dst
.type
== BRW_REGISTER_TYPE_F
&&
1183 src
.file
== BRW_IMMEDIATE_VALUE
) {
1184 vec4_instruction
*inst
= emit(MOV(dst
, brw_imm_f(src
.df
)));
1185 inst
->saturate
= saturate
;
1191 case BRW_REGISTER_TYPE_D
:
1192 op
= VEC4_OPCODE_DOUBLE_TO_D32
;
1194 case BRW_REGISTER_TYPE_UD
:
1195 op
= VEC4_OPCODE_DOUBLE_TO_U32
;
1197 case BRW_REGISTER_TYPE_F
:
1198 op
= VEC4_OPCODE_DOUBLE_TO_F32
;
1201 unreachable("Unknown conversion");
1204 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1205 emit(MOV(temp
, src
));
1206 dst_reg temp2
= dst_reg(this, glsl_type::dvec4_type
);
1207 emit(op
, temp2
, src_reg(temp
));
1209 emit(VEC4_OPCODE_PICK_LOW_32BIT
, retype(temp2
, dst
.type
), src_reg(temp2
));
1210 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(retype(temp2
, dst
.type
))));
1211 inst
->saturate
= saturate
;
1215 vec4_visitor::emit_conversion_to_double(dst_reg dst
, src_reg src
,
1218 dst_reg tmp_dst
= dst_reg(src_reg(this, glsl_type::dvec4_type
));
1219 src_reg tmp_src
= retype(src_reg(this, glsl_type::vec4_type
), src
.type
);
1220 emit(MOV(dst_reg(tmp_src
), src
));
1221 emit(VEC4_OPCODE_TO_DOUBLE
, tmp_dst
, tmp_src
);
1222 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(tmp_dst
)));
1223 inst
->saturate
= saturate
;
1227 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
1229 vec4_instruction
*inst
;
1231 nir_alu_type dst_type
= (nir_alu_type
) (nir_op_infos
[instr
->op
].output_type
|
1232 nir_dest_bit_size(instr
->dest
.dest
));
1233 dst_reg dst
= get_nir_dest(instr
->dest
.dest
, dst_type
);
1234 dst
.writemask
= instr
->dest
.write_mask
;
1237 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1238 nir_alu_type src_type
= (nir_alu_type
)
1239 (nir_op_infos
[instr
->op
].input_types
[i
] |
1240 nir_src_bit_size(instr
->src
[i
].src
));
1241 op
[i
] = get_nir_src(instr
->src
[i
].src
, src_type
, 4);
1242 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
1243 op
[i
].abs
= instr
->src
[i
].abs
;
1244 op
[i
].negate
= instr
->src
[i
].negate
;
1247 switch (instr
->op
) {
1250 inst
= emit(MOV(dst
, op
[0]));
1251 inst
->saturate
= instr
->dest
.saturate
;
1257 unreachable("not reached: should be handled by lower_vec_to_movs()");
1261 inst
= emit(MOV(dst
, op
[0]));
1262 inst
->saturate
= instr
->dest
.saturate
;
1268 if (nir_src_bit_size(instr
->src
[0].src
) == 64)
1269 emit_conversion_from_double(dst
, op
[0], instr
->dest
.saturate
);
1271 inst
= emit(MOV(dst
, op
[0]));
1277 emit_conversion_to_double(dst
, op
[0], instr
->dest
.saturate
);
1281 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1284 inst
= emit(ADD(dst
, op
[0], op
[1]));
1285 inst
->saturate
= instr
->dest
.saturate
;
1289 inst
= emit(MUL(dst
, op
[0], op
[1]));
1290 inst
->saturate
= instr
->dest
.saturate
;
1294 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1295 if (devinfo
->gen
< 8) {
1296 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
1297 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
1299 /* For integer multiplication, the MUL uses the low 16 bits of one of
1300 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1301 * accumulates in the contribution of the upper 16 bits of that
1302 * operand. If we can determine that one of the args is in the low
1303 * 16 bits, though, we can just emit a single MUL.
1305 if (value0
&& value0
->u32
[0] < (1 << 16)) {
1306 if (devinfo
->gen
< 7)
1307 emit(MUL(dst
, op
[0], op
[1]));
1309 emit(MUL(dst
, op
[1], op
[0]));
1310 } else if (value1
&& value1
->u32
[0] < (1 << 16)) {
1311 if (devinfo
->gen
< 7)
1312 emit(MUL(dst
, op
[1], op
[0]));
1314 emit(MUL(dst
, op
[0], op
[1]));
1316 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1318 emit(MUL(acc
, op
[0], op
[1]));
1319 emit(MACH(dst_null_d(), op
[0], op
[1]));
1320 emit(MOV(dst
, src_reg(acc
)));
1323 emit(MUL(dst
, op
[0], op
[1]));
1328 case nir_op_imul_high
:
1329 case nir_op_umul_high
: {
1330 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1331 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1333 if (devinfo
->gen
>= 8)
1334 emit(MUL(acc
, op
[0], retype(op
[1], BRW_REGISTER_TYPE_UW
)));
1336 emit(MUL(acc
, op
[0], op
[1]));
1338 emit(MACH(dst
, op
[0], op
[1]));
1343 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1344 inst
->saturate
= instr
->dest
.saturate
;
1348 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1349 inst
->saturate
= instr
->dest
.saturate
;
1353 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1354 inst
->saturate
= instr
->dest
.saturate
;
1358 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1359 inst
->saturate
= instr
->dest
.saturate
;
1363 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1364 inst
->saturate
= instr
->dest
.saturate
;
1369 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1370 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1375 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1376 * appears that our hardware just does the right thing for signed
1379 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1380 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1384 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1385 inst
= emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1387 /* Math instructions don't support conditional mod */
1388 inst
= emit(MOV(dst_null_d(), src_reg(dst
)));
1389 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1391 /* Now, we need to determine if signs of the sources are different.
1392 * When we XOR the sources, the top bit is 0 if they are the same and 1
1393 * if they are different. We can then use a conditional modifier to
1394 * turn that into a predicate. This leads us to an XOR.l instruction.
1396 * Technically, according to the PRM, you're not allowed to use .l on a
1397 * XOR instruction. However, emperical experiments and Curro's reading
1398 * of the simulator source both indicate that it's safe.
1400 src_reg tmp
= src_reg(this, glsl_type::ivec4_type
);
1401 inst
= emit(XOR(dst_reg(tmp
), op
[0], op
[1]));
1402 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1403 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1405 /* If the result of the initial remainder operation is non-zero and the
1406 * two sources have different signs, add in a copy of op[1] to get the
1407 * final integer modulus value.
1409 inst
= emit(ADD(dst
, src_reg(dst
), op
[1]));
1410 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1415 unreachable("not reached: should be handled by ldexp_to_arith()");
1418 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1419 inst
->saturate
= instr
->dest
.saturate
;
1423 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1424 inst
->saturate
= instr
->dest
.saturate
;
1428 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1429 inst
->saturate
= instr
->dest
.saturate
;
1432 case nir_op_uadd_carry
: {
1433 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1434 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1436 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1437 emit(MOV(dst
, src_reg(acc
)));
1441 case nir_op_usub_borrow
: {
1442 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1443 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1445 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1446 emit(MOV(dst
, src_reg(acc
)));
1451 inst
= emit(RNDZ(dst
, op
[0]));
1452 inst
->saturate
= instr
->dest
.saturate
;
1455 case nir_op_fceil
: {
1456 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1458 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1459 instr
->src
[0].src
.ssa
->num_components
:
1460 instr
->src
[0].src
.reg
.reg
->num_components
);
1462 op
[0].negate
= !op
[0].negate
;
1463 emit(RNDD(dst_reg(tmp
), op
[0]));
1465 inst
= emit(MOV(dst
, tmp
));
1466 inst
->saturate
= instr
->dest
.saturate
;
1471 inst
= emit(RNDD(dst
, op
[0]));
1472 inst
->saturate
= instr
->dest
.saturate
;
1476 inst
= emit(FRC(dst
, op
[0]));
1477 inst
->saturate
= instr
->dest
.saturate
;
1480 case nir_op_fround_even
:
1481 inst
= emit(RNDE(dst
, op
[0]));
1482 inst
->saturate
= instr
->dest
.saturate
;
1485 case nir_op_fquantize2f16
: {
1486 /* See also vec4_visitor::emit_pack_half_2x16() */
1487 src_reg tmp16
= src_reg(this, glsl_type::uvec4_type
);
1488 src_reg tmp32
= src_reg(this, glsl_type::vec4_type
);
1489 src_reg zero
= src_reg(this, glsl_type::vec4_type
);
1491 /* Check for denormal */
1492 src_reg abs_src0
= op
[0];
1493 abs_src0
.abs
= true;
1494 emit(CMP(dst_null_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1495 BRW_CONDITIONAL_L
));
1496 /* Get the appropriately signed zero */
1497 emit(AND(retype(dst_reg(zero
), BRW_REGISTER_TYPE_UD
),
1498 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1499 brw_imm_ud(0x80000000)));
1500 /* Do the actual F32 -> F16 -> F32 conversion */
1501 emit(F32TO16(dst_reg(tmp16
), op
[0]));
1502 emit(F16TO32(dst_reg(tmp32
), tmp16
));
1503 /* Select that or zero based on normal status */
1504 inst
= emit(BRW_OPCODE_SEL
, dst
, zero
, tmp32
);
1505 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1506 inst
->saturate
= instr
->dest
.saturate
;
1512 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1515 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1516 inst
->saturate
= instr
->dest
.saturate
;
1521 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1524 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1525 inst
->saturate
= instr
->dest
.saturate
;
1529 case nir_op_fddx_coarse
:
1530 case nir_op_fddx_fine
:
1532 case nir_op_fddy_coarse
:
1533 case nir_op_fddy_fine
:
1534 unreachable("derivatives are not valid in vertex shaders");
1542 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1548 enum brw_conditional_mod conditional_mod
=
1549 brw_conditional_for_nir_comparison(instr
->op
);
1551 if (nir_src_bit_size(instr
->src
[0].src
) < 64) {
1552 emit(CMP(dst
, op
[0], op
[1], conditional_mod
));
1554 /* Produce a 32-bit boolean result from the DF comparison by selecting
1555 * only the low 32-bit in each DF produced. Do this in a temporary
1556 * so we can then move from there to the result using align16 again
1557 * to honor the original writemask.
1559 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1560 emit(CMP(temp
, op
[0], op
[1], conditional_mod
));
1561 dst_reg result
= dst_reg(this, glsl_type::bvec4_type
);
1562 emit(VEC4_OPCODE_PICK_LOW_32BIT
, result
, src_reg(temp
));
1563 emit(MOV(dst
, src_reg(result
)));
1568 case nir_op_ball_iequal2
:
1569 case nir_op_ball_iequal3
:
1570 case nir_op_ball_iequal4
:
1571 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1573 case nir_op_ball_fequal2
:
1574 case nir_op_ball_fequal3
:
1575 case nir_op_ball_fequal4
: {
1577 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1579 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1580 brw_conditional_for_nir_comparison(instr
->op
)));
1581 emit(MOV(dst
, brw_imm_d(0)));
1582 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1583 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1587 case nir_op_bany_inequal2
:
1588 case nir_op_bany_inequal3
:
1589 case nir_op_bany_inequal4
:
1590 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1592 case nir_op_bany_fnequal2
:
1593 case nir_op_bany_fnequal3
:
1594 case nir_op_bany_fnequal4
: {
1596 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1598 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1599 brw_conditional_for_nir_comparison(instr
->op
)));
1601 emit(MOV(dst
, brw_imm_d(0)));
1602 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1603 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1608 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1609 if (devinfo
->gen
>= 8) {
1610 op
[0] = resolve_source_modifiers(op
[0]);
1612 emit(NOT(dst
, op
[0]));
1616 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1617 if (devinfo
->gen
>= 8) {
1618 op
[0] = resolve_source_modifiers(op
[0]);
1619 op
[1] = resolve_source_modifiers(op
[1]);
1621 emit(XOR(dst
, op
[0], op
[1]));
1625 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1626 if (devinfo
->gen
>= 8) {
1627 op
[0] = resolve_source_modifiers(op
[0]);
1628 op
[1] = resolve_source_modifiers(op
[1]);
1630 emit(OR(dst
, op
[0], op
[1]));
1634 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1635 if (devinfo
->gen
>= 8) {
1636 op
[0] = resolve_source_modifiers(op
[0]);
1637 op
[1] = resolve_source_modifiers(op
[1]);
1639 emit(AND(dst
, op
[0], op
[1]));
1644 emit(MOV(dst
, negate(op
[0])));
1648 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1649 /* We use a MOV with conditional_mod to check if the provided value is
1650 * 0.0. We want this to flush denormalized numbers to zero, so we set a
1651 * source modifier on the source operand to trigger this, as source
1652 * modifiers don't affect the result of the testing against 0.0.
1654 src_reg value
= op
[0];
1656 vec4_instruction
*inst
= emit(MOV(dst_null_df(), value
));
1657 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1659 src_reg one
= src_reg(this, glsl_type::ivec4_type
);
1660 emit(MOV(dst_reg(one
), brw_imm_d(~0)));
1661 inst
= emit(BRW_OPCODE_SEL
, dst
, one
, brw_imm_d(0));
1662 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1664 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1669 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1672 case nir_op_fnoise1_1
:
1673 case nir_op_fnoise1_2
:
1674 case nir_op_fnoise1_3
:
1675 case nir_op_fnoise1_4
:
1676 case nir_op_fnoise2_1
:
1677 case nir_op_fnoise2_2
:
1678 case nir_op_fnoise2_3
:
1679 case nir_op_fnoise2_4
:
1680 case nir_op_fnoise3_1
:
1681 case nir_op_fnoise3_2
:
1682 case nir_op_fnoise3_3
:
1683 case nir_op_fnoise3_4
:
1684 case nir_op_fnoise4_1
:
1685 case nir_op_fnoise4_2
:
1686 case nir_op_fnoise4_3
:
1687 case nir_op_fnoise4_4
:
1688 unreachable("not reached: should be handled by lower_noise");
1690 case nir_op_unpack_half_2x16_split_x
:
1691 case nir_op_unpack_half_2x16_split_y
:
1692 case nir_op_pack_half_2x16_split
:
1693 unreachable("not reached: should not occur in vertex shader");
1695 case nir_op_unpack_snorm_2x16
:
1696 case nir_op_unpack_unorm_2x16
:
1697 case nir_op_pack_snorm_2x16
:
1698 case nir_op_pack_unorm_2x16
:
1699 unreachable("not reached: should be handled by lower_packing_builtins");
1701 case nir_op_pack_uvec4_to_uint
:
1702 unreachable("not reached");
1704 case nir_op_pack_uvec2_to_uint
: {
1705 dst_reg tmp1
= dst_reg(this, glsl_type::uint_type
);
1706 tmp1
.writemask
= WRITEMASK_X
;
1707 op
[0].swizzle
= BRW_SWIZZLE_YYYY
;
1708 emit(SHL(tmp1
, op
[0], src_reg(brw_imm_ud(16u))));
1710 dst_reg tmp2
= dst_reg(this, glsl_type::uint_type
);
1711 tmp2
.writemask
= WRITEMASK_X
;
1712 op
[0].swizzle
= BRW_SWIZZLE_XXXX
;
1713 emit(AND(tmp2
, op
[0], src_reg(brw_imm_ud(0xffffu
))));
1715 emit(OR(dst
, src_reg(tmp1
), src_reg(tmp2
)));
1719 case nir_op_pack_64_2x32_split
: {
1720 dst_reg result
= dst_reg(this, glsl_type::dvec4_type
);
1721 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1722 emit(MOV(tmp
, retype(op
[0], BRW_REGISTER_TYPE_UD
)));
1723 emit(VEC4_OPCODE_SET_LOW_32BIT
, result
, src_reg(tmp
));
1724 emit(MOV(tmp
, retype(op
[1], BRW_REGISTER_TYPE_UD
)));
1725 emit(VEC4_OPCODE_SET_HIGH_32BIT
, result
, src_reg(tmp
));
1726 emit(MOV(dst
, src_reg(result
)));
1730 case nir_op_unpack_64_2x32_split_x
:
1731 case nir_op_unpack_64_2x32_split_y
: {
1732 enum opcode oper
= (instr
->op
== nir_op_unpack_64_2x32_split_x
) ?
1733 VEC4_OPCODE_PICK_LOW_32BIT
: VEC4_OPCODE_PICK_HIGH_32BIT
;
1734 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
1735 emit(MOV(tmp
, op
[0]));
1736 dst_reg tmp2
= dst_reg(this, glsl_type::uvec4_type
);
1737 emit(oper
, tmp2
, src_reg(tmp
));
1738 emit(MOV(dst
, src_reg(tmp2
)));
1742 case nir_op_unpack_half_2x16
:
1743 /* As NIR does not guarantee that we have a correct swizzle outside the
1744 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1745 * uses the source operand in an operation with WRITEMASK_Y while our
1746 * source operand has only size 1, it accessed incorrect data producing
1747 * regressions in Piglit. We repeat the swizzle of the first component on the
1748 * rest of components to avoid regressions. In the vec4_visitor IR code path
1749 * this is not needed because the operand has already the correct swizzle.
1751 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1752 emit_unpack_half_2x16(dst
, op
[0]);
1755 case nir_op_pack_half_2x16
:
1756 emit_pack_half_2x16(dst
, op
[0]);
1759 case nir_op_unpack_unorm_4x8
:
1760 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1761 emit_unpack_unorm_4x8(dst
, op
[0]);
1764 case nir_op_pack_unorm_4x8
:
1765 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1766 emit_pack_unorm_4x8(dst
, op
[0]);
1769 case nir_op_unpack_snorm_4x8
:
1770 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1771 emit_unpack_snorm_4x8(dst
, op
[0]);
1774 case nir_op_pack_snorm_4x8
:
1775 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1776 emit_pack_snorm_4x8(dst
, op
[0]);
1779 case nir_op_bitfield_reverse
:
1780 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1781 emit(BFREV(dst
, op
[0]));
1784 case nir_op_bit_count
:
1785 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1786 emit(CBIT(dst
, op
[0]));
1789 case nir_op_ufind_msb
:
1790 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1791 emit_find_msb_using_lzd(vec4_builder(this).at_end(), dst
, op
[0], false);
1794 case nir_op_ifind_msb
: {
1795 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1796 vec4_builder bld
= vec4_builder(this).at_end();
1799 if (devinfo
->gen
< 7) {
1800 emit_find_msb_using_lzd(bld
, dst
, op
[0], true);
1802 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1804 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1805 * count from the LSB side. If FBH didn't return an error
1806 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1807 * count into an LSB count.
1809 bld
.CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1811 inst
= bld
.ADD(dst
, src
, brw_imm_d(31));
1812 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1813 inst
->src
[0].negate
= true;
1818 case nir_op_find_lsb
: {
1819 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1820 vec4_builder bld
= vec4_builder(this).at_end();
1822 if (devinfo
->gen
< 7) {
1823 dst_reg temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1825 /* (x & -x) generates a value that consists of only the LSB of x.
1826 * For all powers of 2, findMSB(y) == findLSB(y).
1828 src_reg src
= src_reg(retype(op
[0], BRW_REGISTER_TYPE_D
));
1829 src_reg negated_src
= src
;
1831 /* One must be negated, and the other must be non-negated. It
1832 * doesn't matter which is which.
1834 negated_src
.negate
= true;
1837 bld
.AND(temp
, src
, negated_src
);
1838 emit_find_msb_using_lzd(bld
, dst
, src_reg(temp
), false);
1840 bld
.FBL(dst
, op
[0]);
1845 case nir_op_ubitfield_extract
:
1846 case nir_op_ibitfield_extract
:
1847 unreachable("should have been lowered");
1850 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1851 op
[0] = fix_3src_operand(op
[0]);
1852 op
[1] = fix_3src_operand(op
[1]);
1853 op
[2] = fix_3src_operand(op
[2]);
1855 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1859 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1860 emit(BFI1(dst
, op
[0], op
[1]));
1864 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1865 op
[0] = fix_3src_operand(op
[0]);
1866 op
[1] = fix_3src_operand(op
[1]);
1867 op
[2] = fix_3src_operand(op
[2]);
1869 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1872 case nir_op_bitfield_insert
:
1873 unreachable("not reached: should have been lowered");
1876 if (type_sz(op
[0].type
) < 8) {
1877 /* AND(val, 0x80000000) gives the sign bit.
1879 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1882 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1884 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1885 dst
.type
= BRW_REGISTER_TYPE_UD
;
1886 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1888 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1889 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1890 dst
.type
= BRW_REGISTER_TYPE_F
;
1892 if (instr
->dest
.saturate
) {
1893 inst
= emit(MOV(dst
, src_reg(dst
)));
1894 inst
->saturate
= true;
1897 /* For doubles we do the same but we need to consider:
1899 * - We use a MOV with conditional_mod instead of a CMP so that we can
1900 * skip loading a 0.0 immediate. We use a source modifier on the
1901 * source of the MOV so that we flush denormalized values to 0.
1902 * Since we want to compare against 0, this won't alter the result.
1903 * - We need to extract the high 32-bit of each DF where the sign
1905 * - We need to produce a DF result.
1908 /* Check for zero */
1909 src_reg value
= op
[0];
1911 inst
= emit(MOV(dst_null_df(), value
));
1912 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1914 /* AND each high 32-bit channel with 0x80000000u */
1915 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1916 emit(VEC4_OPCODE_PICK_HIGH_32BIT
, tmp
, op
[0]);
1917 emit(AND(tmp
, src_reg(tmp
), brw_imm_ud(0x80000000u
)));
1919 /* Add 1.0 to each channel, predicated to skip the cases where the
1920 * channel's value was 0
1922 inst
= emit(OR(tmp
, src_reg(tmp
), brw_imm_ud(0x3f800000u
)));
1923 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1925 /* Now convert the result from float to double */
1926 emit_conversion_to_double(dst
, retype(src_reg(tmp
),
1927 BRW_REGISTER_TYPE_F
),
1928 instr
->dest
.saturate
);
1933 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1934 * -> non-negative val generates 0x00000000.
1935 * Predicated OR sets 1 if val is positive.
1937 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1938 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1939 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1940 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1941 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1945 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1946 emit(SHL(dst
, op
[0], op
[1]));
1950 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1951 emit(ASR(dst
, op
[0], op
[1]));
1955 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1956 emit(SHR(dst
, op
[0], op
[1]));
1960 if (type_sz(dst
.type
) == 8) {
1961 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
1962 emit(MUL(mul_dst
, op
[1], op
[0]));
1963 inst
= emit(ADD(dst
, src_reg(mul_dst
), op
[2]));
1964 inst
->saturate
= instr
->dest
.saturate
;
1966 op
[0] = fix_3src_operand(op
[0]);
1967 op
[1] = fix_3src_operand(op
[1]);
1968 op
[2] = fix_3src_operand(op
[2]);
1970 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1971 inst
->saturate
= instr
->dest
.saturate
;
1976 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1977 inst
->saturate
= instr
->dest
.saturate
;
1981 enum brw_predicate predicate
;
1982 if (!optimize_predicate(instr
, &predicate
)) {
1983 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1984 switch (dst
.writemask
) {
1986 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1989 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1992 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1995 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1998 predicate
= BRW_PREDICATE_NORMAL
;
2002 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
2003 inst
->predicate
= predicate
;
2006 case nir_op_fdot_replicated2
:
2007 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
2008 inst
->saturate
= instr
->dest
.saturate
;
2011 case nir_op_fdot_replicated3
:
2012 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
2013 inst
->saturate
= instr
->dest
.saturate
;
2016 case nir_op_fdot_replicated4
:
2017 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
2018 inst
->saturate
= instr
->dest
.saturate
;
2021 case nir_op_fdph_replicated
:
2022 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
2023 inst
->saturate
= instr
->dest
.saturate
;
2028 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
2033 unreachable("not reached: should be lowered by lower_source mods");
2036 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
2039 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
2043 unreachable("not reached: should be handled by ir_sub_to_add_neg");
2046 unreachable("Unimplemented ALU operation");
2049 /* If we need to do a boolean resolve, replace the result with -(x & 1)
2050 * to sign extend the low bit to 0/~0
2052 if (devinfo
->gen
<= 5 &&
2053 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
2054 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
2055 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
2056 masked
.writemask
= dst
.writemask
;
2057 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
2058 src_reg masked_neg
= src_reg(masked
);
2059 masked_neg
.negate
= true;
2060 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
2065 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
2067 switch (instr
->type
) {
2068 case nir_jump_break
:
2069 emit(BRW_OPCODE_BREAK
);
2072 case nir_jump_continue
:
2073 emit(BRW_OPCODE_CONTINUE
);
2076 case nir_jump_return
:
2079 unreachable("unknown jump");
2083 enum ir_texture_opcode
2084 ir_texture_opcode_for_nir_texop(nir_texop texop
)
2086 enum ir_texture_opcode op
;
2089 case nir_texop_lod
: op
= ir_lod
; break;
2090 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2091 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
2092 case nir_texop_tex
: op
= ir_tex
; break;
2093 case nir_texop_tg4
: op
= ir_tg4
; break;
2094 case nir_texop_txb
: op
= ir_txb
; break;
2095 case nir_texop_txd
: op
= ir_txd
; break;
2096 case nir_texop_txf
: op
= ir_txf
; break;
2097 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2098 case nir_texop_txl
: op
= ir_txl
; break;
2099 case nir_texop_txs
: op
= ir_txs
; break;
2100 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2102 unreachable("unknown texture opcode");
2108 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
2109 unsigned components
)
2111 return glsl_type::get_instance(brw_glsl_base_type_for_nir_type(alu_type
),
2116 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
2118 unsigned texture
= instr
->texture_index
;
2119 unsigned sampler
= instr
->sampler_index
;
2120 src_reg texture_reg
= brw_imm_ud(texture
);
2121 src_reg sampler_reg
= brw_imm_ud(sampler
);
2123 const glsl_type
*coord_type
= NULL
;
2124 src_reg shadow_comparator
;
2125 src_reg offset_value
;
2127 src_reg sample_index
;
2130 const glsl_type
*dest_type
=
2131 glsl_type_for_nir_alu_type(instr
->dest_type
,
2132 nir_tex_instr_dest_size(instr
));
2133 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
2135 /* The hardware requires a LOD for buffer textures */
2136 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
2139 /* Load the texture operation sources */
2140 uint32_t constant_offset
= 0;
2141 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2142 switch (instr
->src
[i
].src_type
) {
2143 case nir_tex_src_comparator
:
2144 shadow_comparator
= get_nir_src(instr
->src
[i
].src
,
2145 BRW_REGISTER_TYPE_F
, 1);
2148 case nir_tex_src_coord
: {
2149 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
2151 switch (instr
->op
) {
2153 case nir_texop_txf_ms
:
2154 case nir_texop_samples_identical
:
2155 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
2157 coord_type
= glsl_type::ivec(src_size
);
2161 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2163 coord_type
= glsl_type::vec(src_size
);
2169 case nir_tex_src_ddx
:
2170 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2171 nir_tex_instr_src_size(instr
, i
));
2174 case nir_tex_src_ddy
:
2175 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2176 nir_tex_instr_src_size(instr
, i
));
2179 case nir_tex_src_lod
:
2180 switch (instr
->op
) {
2183 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2187 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
2192 case nir_tex_src_ms_index
: {
2193 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2197 case nir_tex_src_offset
: {
2198 nir_const_value
*const_offset
=
2199 nir_src_as_const_value(instr
->src
[i
].src
);
2200 if (!const_offset
||
2201 !brw_texture_offset(const_offset
->i32
,
2202 nir_tex_instr_src_size(instr
, i
),
2203 &constant_offset
)) {
2205 get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
2210 case nir_tex_src_texture_offset
: {
2211 /* The highest texture which may be used by this operation is
2212 * the last element of the array. Mark it here, because the generator
2213 * doesn't have enough information to determine the bound.
2215 uint32_t array_size
= instr
->texture_array_size
;
2216 uint32_t max_used
= texture
+ array_size
- 1;
2217 if (instr
->op
== nir_texop_tg4
) {
2218 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2220 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2223 brw_mark_surface_used(&prog_data
->base
, max_used
);
2225 /* Emit code to evaluate the actual indexing expression */
2226 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2227 src_reg
temp(this, glsl_type::uint_type
);
2228 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(texture
)));
2229 texture_reg
= emit_uniformize(temp
);
2233 case nir_tex_src_sampler_offset
: {
2234 /* Emit code to evaluate the actual indexing expression */
2235 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2236 src_reg
temp(this, glsl_type::uint_type
);
2237 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
2238 sampler_reg
= emit_uniformize(temp
);
2242 case nir_tex_src_projector
:
2243 unreachable("Should be lowered by do_lower_texture_projection");
2245 case nir_tex_src_bias
:
2246 unreachable("LOD bias is not valid for vertex shaders.\n");
2249 unreachable("unknown texture source");
2253 if (instr
->op
== nir_texop_txf_ms
||
2254 instr
->op
== nir_texop_samples_identical
) {
2255 assert(coord_type
!= NULL
);
2256 if (devinfo
->gen
>= 7 &&
2257 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
2258 mcs
= emit_mcs_fetch(coord_type
, coordinate
, texture_reg
);
2260 mcs
= brw_imm_ud(0u);
2264 /* Stuff the channel select bits in the top of the texture offset */
2265 if (instr
->op
== nir_texop_tg4
) {
2266 if (instr
->component
== 1 &&
2267 (key_tex
->gather_channel_quirk_mask
& (1 << texture
))) {
2268 /* gather4 sampler is broken for green channel on RG32F --
2269 * we must ask for blue instead.
2271 constant_offset
|= 2 << 16;
2273 constant_offset
|= instr
->component
<< 16;
2277 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
2279 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
2281 lod
, lod2
, sample_index
,
2282 constant_offset
, offset_value
, mcs
,
2283 texture
, texture_reg
, sampler_reg
);
2287 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
2289 nir_ssa_values
[instr
->def
.index
] =
2290 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(instr
->def
.bit_size
, 32)));
2293 /* SIMD4x2 64bit data is stored in register space like this:
2295 * r0.0:DF x0 y0 z0 w0
2296 * r1.0:DF x1 y1 z1 w1
2298 * When we need to write data such as this to memory using 32-bit write
2299 * messages we need to shuffle it in this fashion:
2301 * r0.0:DF x0 y0 x1 y1 (to be written at base offset)
2302 * r0.0:DF z0 w0 z1 w1 (to be written at base offset + 16)
2304 * We need to do the inverse operation when we read using 32-bit messages,
2305 * which we can do by applying the same exact shuffling on the 64-bit data
2306 * read, only that because the data for each vertex is positioned differently
2307 * we need to apply different channel enables.
2309 * This function takes 64bit data and shuffles it as explained above.
2311 * The @for_write parameter is used to specify if the shuffling is being done
2312 * for proper SIMD4x2 64-bit data that needs to be shuffled prior to a 32-bit
2313 * write message (for_write = true), or instead we are doing the inverse
2314 * operation and we have just read 64-bit data using a 32-bit messages that we
2315 * need to shuffle to create valid SIMD4x2 64-bit data (for_write = false).
2317 * If @block and @ref are non-NULL, then the shuffling is done after @ref,
2318 * otherwise the instructions are emitted normally at the end. The function
2319 * returns the last instruction inserted.
2321 * Notice that @src and @dst cannot be the same register.
2324 vec4_visitor::shuffle_64bit_data(dst_reg dst
, src_reg src
, bool for_write
,
2325 bblock_t
*block
, vec4_instruction
*ref
)
2327 assert(type_sz(src
.type
) == 8);
2328 assert(type_sz(dst
.type
) == 8);
2329 assert(!regions_overlap(dst
, 2 * REG_SIZE
, src
, 2 * REG_SIZE
));
2330 assert(!ref
== !block
);
2332 const vec4_builder bld
= !ref
? vec4_builder(this).at_end() :
2333 vec4_builder(this).at(block
, ref
->next
);
2335 /* Resolve swizzle in src */
2336 vec4_instruction
*inst
;
2337 if (src
.swizzle
!= BRW_SWIZZLE_XYZW
) {
2338 dst_reg data
= dst_reg(this, glsl_type::dvec4_type
);
2339 inst
= bld
.MOV(data
, src
);
2340 src
= src_reg(data
);
2343 /* dst+0.XY = src+0.XY */
2344 inst
= bld
.group(4, 0).MOV(writemask(dst
, WRITEMASK_XY
), src
);
2346 /* dst+0.ZW = src+1.XY */
2347 inst
= bld
.group(4, for_write
? 1 : 0)
2348 .MOV(writemask(dst
, WRITEMASK_ZW
),
2349 swizzle(byte_offset(src
, REG_SIZE
), BRW_SWIZZLE_XYXY
));
2351 /* dst+1.XY = src+0.ZW */
2352 inst
= bld
.group(4, for_write
? 0 : 1)
2353 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_XY
),
2354 swizzle(src
, BRW_SWIZZLE_ZWZW
));
2356 /* dst+1.ZW = src+1.ZW */
2357 inst
= bld
.group(4, 1)
2358 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_ZW
),
2359 byte_offset(src
, REG_SIZE
));