2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
30 using namespace brw::surface_access
;
35 vec4_visitor::emit_nir_code()
37 if (nir
->num_uniforms
> 0)
40 /* get the main function and emit it */
41 nir_foreach_function(function
, nir
) {
42 assert(strcmp(function
->name
, "main") == 0);
43 assert(function
->impl
);
44 nir_emit_impl(function
->impl
);
49 vec4_visitor::nir_setup_uniforms()
51 uniforms
= nir
->num_uniforms
/ 16;
55 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
57 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
58 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
59 nir_locals
[i
] = dst_reg();
62 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
63 unsigned array_elems
=
64 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
65 const unsigned num_regs
= array_elems
* DIV_ROUND_UP(reg
->bit_size
, 32);
66 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(num_regs
));
68 if (reg
->bit_size
== 64)
69 nir_locals
[reg
->index
].type
= BRW_REGISTER_TYPE_DF
;
72 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
74 nir_emit_cf_list(&impl
->body
);
78 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
80 exec_list_validate(list
);
81 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
84 nir_emit_if(nir_cf_node_as_if(node
));
87 case nir_cf_node_loop
:
88 nir_emit_loop(nir_cf_node_as_loop(node
));
91 case nir_cf_node_block
:
92 nir_emit_block(nir_cf_node_as_block(node
));
96 unreachable("Invalid CFG node block");
102 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
104 /* First, put the condition in f0 */
105 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
106 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
107 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
109 /* We can just predicate based on the X channel, as the condition only
110 * goes on its own line */
111 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
113 nir_emit_cf_list(&if_stmt
->then_list
);
115 /* note: if the else is empty, dead CF elimination will remove it */
116 emit(BRW_OPCODE_ELSE
);
118 nir_emit_cf_list(&if_stmt
->else_list
);
120 emit(BRW_OPCODE_ENDIF
);
124 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
128 nir_emit_cf_list(&loop
->body
);
130 emit(BRW_OPCODE_WHILE
);
134 vec4_visitor::nir_emit_block(nir_block
*block
)
136 nir_foreach_instr(instr
, block
) {
137 nir_emit_instr(instr
);
142 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
146 switch (instr
->type
) {
147 case nir_instr_type_load_const
:
148 nir_emit_load_const(nir_instr_as_load_const(instr
));
151 case nir_instr_type_intrinsic
:
152 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
155 case nir_instr_type_alu
:
156 nir_emit_alu(nir_instr_as_alu(instr
));
159 case nir_instr_type_jump
:
160 nir_emit_jump(nir_instr_as_jump(instr
));
163 case nir_instr_type_tex
:
164 nir_emit_texture(nir_instr_as_tex(instr
));
167 case nir_instr_type_ssa_undef
:
168 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
172 fprintf(stderr
, "VS instruction not yet implemented by NIR->vec4\n");
178 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
179 unsigned base_offset
, nir_src
*indirect
)
183 reg
= v
->nir_locals
[nir_reg
->index
];
184 if (nir_reg
->bit_size
== 64)
185 reg
.type
= BRW_REGISTER_TYPE_DF
;
186 reg
= offset(reg
, 8, base_offset
);
189 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
197 vec4_visitor::get_nir_dest(const nir_dest
&dest
)
201 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(dest
.ssa
.bit_size
, 32)));
202 if (dest
.ssa
.bit_size
== 64)
203 dst
.type
= BRW_REGISTER_TYPE_DF
;
204 nir_ssa_values
[dest
.ssa
.index
] = dst
;
207 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
213 vec4_visitor::get_nir_dest(const nir_dest
&dest
, enum brw_reg_type type
)
215 return retype(get_nir_dest(dest
), type
);
219 vec4_visitor::get_nir_dest(const nir_dest
&dest
, nir_alu_type type
)
221 return get_nir_dest(dest
, brw_type_for_nir_type(devinfo
, type
));
225 vec4_visitor::get_nir_src(const nir_src
&src
, enum brw_reg_type type
,
226 unsigned num_components
)
231 assert(src
.ssa
!= NULL
);
232 reg
= nir_ssa_values
[src
.ssa
->index
];
235 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
239 reg
= retype(reg
, type
);
241 src_reg reg_as_src
= src_reg(reg
);
242 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
247 vec4_visitor::get_nir_src(const nir_src
&src
, nir_alu_type type
,
248 unsigned num_components
)
250 return get_nir_src(src
, brw_type_for_nir_type(devinfo
, type
),
255 vec4_visitor::get_nir_src(const nir_src
&src
, unsigned num_components
)
257 /* if type is not specified, default to signed int */
258 return get_nir_src(src
, nir_type_int32
, num_components
);
262 vec4_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
264 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
265 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
268 /* The only constant offset we should find is 0. brw_nir.c's
269 * add_const_offset_to_base() will fold other constant offsets
270 * into instr->const_index[0].
272 assert(const_value
->u32
[0] == 0);
276 return get_nir_src(*offset_src
, BRW_REGISTER_TYPE_UD
, 1);
280 setup_imm_df(const vec4_builder
&bld
, double v
)
282 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
283 assert(devinfo
->gen
>= 7);
285 if (devinfo
->gen
>= 8)
286 return brw_imm_df(v
);
288 /* gen7.5 does not support DF immediates straighforward but the DIM
289 * instruction allows to set the 64-bit immediate value.
291 if (devinfo
->is_haswell
) {
292 const vec4_builder ubld
= bld
.exec_all();
293 const dst_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_DF
);
294 ubld
.DIM(dst
, brw_imm_df(v
));
295 return swizzle(src_reg(dst
), BRW_SWIZZLE_XXXX
);
298 /* gen7 does not support DF immediates */
309 /* Write the low 32-bit of the constant to the X:UD channel and the
310 * high 32-bit to the Y:UD channel to build the constant in a VGRF.
311 * We have to do this twice (offset 0 and offset 1), since a DF VGRF takes
312 * two SIMD8 registers in SIMD4x2 execution. Finally, return a swizzle
313 * XXXX so any access to the VGRF only reads the constant data in these
316 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
317 for (unsigned n
= 0; n
< 2; n
++) {
318 const vec4_builder ubld
= bld
.exec_all().group(4, n
);
319 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_X
), brw_imm_ud(di
.i1
));
320 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_Y
), brw_imm_ud(di
.i2
));
323 return swizzle(src_reg(retype(tmp
, BRW_REGISTER_TYPE_DF
)), BRW_SWIZZLE_XXXX
);
327 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
331 if (instr
->def
.bit_size
== 64) {
332 reg
= dst_reg(VGRF
, alloc
.allocate(2));
333 reg
.type
= BRW_REGISTER_TYPE_DF
;
335 reg
= dst_reg(VGRF
, alloc
.allocate(1));
336 reg
.type
= BRW_REGISTER_TYPE_D
;
339 const vec4_builder ibld
= vec4_builder(this).at_end();
340 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
342 /* @FIXME: consider emitting vector operations to save some MOVs in
343 * cases where the components are representable in 8 bits.
344 * For now, we emit a MOV for each distinct value.
346 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
347 unsigned writemask
= 1 << i
;
349 if ((remaining
& writemask
) == 0)
352 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
353 if ((instr
->def
.bit_size
== 32 &&
354 instr
->value
.u32
[i
] == instr
->value
.u32
[j
]) ||
355 (instr
->def
.bit_size
== 64 &&
356 instr
->value
.f64
[i
] == instr
->value
.f64
[j
])) {
361 reg
.writemask
= writemask
;
362 if (instr
->def
.bit_size
== 64) {
363 emit(MOV(reg
, setup_imm_df(ibld
, instr
->value
.f64
[i
])));
365 emit(MOV(reg
, brw_imm_d(instr
->value
.i32
[i
])));
368 remaining
&= ~writemask
;
371 /* Set final writemask */
372 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
374 nir_ssa_values
[instr
->def
.index
] = reg
;
378 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
383 switch (instr
->intrinsic
) {
385 case nir_intrinsic_load_input
: {
386 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
388 /* We set EmitNoIndirectInput for VS */
389 assert(const_offset
);
391 dest
= get_nir_dest(instr
->dest
);
392 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
394 src
= src_reg(ATTR
, instr
->const_index
[0] + const_offset
->u32
[0],
395 glsl_type::uvec4_type
);
396 src
= retype(src
, dest
.type
);
398 bool is_64bit
= nir_dest_bit_size(instr
->dest
) == 64;
400 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
401 src
.swizzle
= BRW_SWIZZLE_XYZW
;
402 shuffle_64bit_data(tmp
, src
, false);
403 emit(MOV(dest
, src_reg(tmp
)));
405 /* Swizzle source based on component layout qualifier */
406 src
.swizzle
= BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr
));
407 emit(MOV(dest
, src
));
412 case nir_intrinsic_store_output
: {
413 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
414 assert(const_offset
);
416 int varying
= instr
->const_index
[0] + const_offset
->u32
[0];
418 bool is_64bit
= nir_src_bit_size(instr
->src
[0]) == 64;
421 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_DF
,
422 instr
->num_components
);
423 data
= src_reg(this, glsl_type::dvec4_type
);
424 shuffle_64bit_data(dst_reg(data
), src
, true);
425 src
= retype(data
, BRW_REGISTER_TYPE_F
);
427 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
428 instr
->num_components
);
431 unsigned c
= nir_intrinsic_component(instr
);
432 output_reg
[varying
][c
] = dst_reg(src
);
433 output_num_components
[varying
][c
] = instr
->num_components
;
435 unsigned num_components
= instr
->num_components
;
439 output_reg
[varying
][c
] = dst_reg(src
);
440 output_num_components
[varying
][c
] = MIN2(4, num_components
);
442 if (is_64bit
&& num_components
> 4) {
443 assert(num_components
<= 8);
444 output_reg
[varying
+ 1][c
] = byte_offset(dst_reg(src
), REG_SIZE
);
445 output_num_components
[varying
+ 1][c
] = num_components
- 4;
450 case nir_intrinsic_get_buffer_size
: {
451 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
452 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
454 const unsigned index
=
455 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
456 dst_reg result_dst
= get_nir_dest(instr
->dest
);
457 vec4_instruction
*inst
= new(mem_ctx
)
458 vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE
, result_dst
);
461 inst
->mlen
= 1; /* always at least one */
462 inst
->src
[1] = brw_imm_ud(index
);
464 /* MRF for the first parameter */
465 src_reg lod
= brw_imm_d(0);
466 int param_base
= inst
->base_mrf
;
467 int writemask
= WRITEMASK_X
;
468 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
472 brw_mark_surface_used(&prog_data
->base
, index
);
476 case nir_intrinsic_store_ssbo
: {
477 assert(devinfo
->gen
>= 7);
481 nir_const_value
*const_uniform_block
=
482 nir_src_as_const_value(instr
->src
[1]);
483 if (const_uniform_block
) {
484 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
485 const_uniform_block
->u32
[0];
486 surf_index
= brw_imm_ud(index
);
487 brw_mark_surface_used(&prog_data
->base
, index
);
489 surf_index
= src_reg(this, glsl_type::uint_type
);
490 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
491 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
492 surf_index
= emit_uniformize(surf_index
);
494 brw_mark_surface_used(&prog_data
->base
,
495 prog_data
->base
.binding_table
.ssbo_start
+
496 nir
->info
.num_ssbos
- 1);
501 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
503 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
505 offset_reg
= get_nir_src(instr
->src
[2], 1);
509 src_reg val_reg
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
, 4);
512 unsigned write_mask
= instr
->const_index
[0];
514 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
515 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
516 * typed and untyped messages and across hardware platforms, the
517 * current implementation of the untyped messages will transparently convert
518 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
519 * and enabling only channel X on the SEND instruction.
521 * The above, works well for full vector writes, but not for partial writes
522 * where we want to write some channels and not others, like when we have
523 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
524 * quite restrictive with regards to the channel enables we can configure in
525 * the message descriptor (not all combinations are allowed) we cannot simply
526 * implement these scenarios with a single message while keeping the
527 * aforementioned symmetry in the implementation. For now we de decided that
528 * it is better to keep the symmetry to reduce complexity, so in situations
529 * such as the one described we end up emitting two untyped write messages
530 * (one for xy and another for w).
532 * The code below packs consecutive channels into a single write message,
533 * detects gaps in the vector write and if needed, sends a second message
534 * with the remaining channels. If in the future we decide that we want to
535 * emit a single message at the expense of losing the symmetry in the
536 * implementation we can:
538 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
539 * message payload. In this mode we can write up to 8 offsets and dwords
540 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
541 * and select which of the 8 channels carry data to write by setting the
542 * appropriate writemask in the dst register of the SEND instruction.
543 * It would require to write a new generator opcode specifically for
544 * IvyBridge since we would need to prepare a SIMD8 payload that could
545 * use any channel, not just X.
547 * 2) For Haswell+: Simply send a single write message but set the writemask
548 * on the dst of the SEND instruction to select the channels we want to
549 * write. It would require to modify the current messages to receive
550 * and honor the writemask provided.
552 const vec4_builder bld
= vec4_builder(this).at_end()
553 .annotate(current_annotation
, base_ir
);
555 unsigned type_slots
= nir_src_bit_size(instr
->src
[0]) / 32;
556 if (type_slots
== 2) {
557 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
558 shuffle_64bit_data(tmp
, retype(val_reg
, tmp
.type
), true);
559 val_reg
= src_reg(retype(tmp
, BRW_REGISTER_TYPE_F
));
562 uint8_t swizzle
[4] = { 0, 0, 0, 0};
563 int num_channels
= 0;
564 unsigned skipped_channels
= 0;
565 int num_components
= instr
->num_components
;
566 for (int i
= 0; i
< num_components
; i
++) {
567 /* Read components Z/W of a dvec from the appropriate place. We will
568 * also have to adjust the swizzle (we do that with the '% 4' below)
570 if (i
== 2 && type_slots
== 2)
571 val_reg
= byte_offset(val_reg
, REG_SIZE
);
573 /* Check if this channel needs to be written. If so, record the
574 * channel we need to take the data from in the swizzle array
576 int component_mask
= 1 << i
;
577 int write_test
= write_mask
& component_mask
;
579 /* If we are writing doubles we have to write 2 channels worth of
580 * of data (64 bits) for each double component.
582 swizzle
[num_channels
++] = (i
* type_slots
) % 4;
584 swizzle
[num_channels
++] = (i
* type_slots
+ 1) % 4;
587 /* If we don't have to write this channel it means we have a gap in the
588 * vector, so write the channels we accumulated until now, if any. Do
589 * the same if this was the last component in the vector, if we have
590 * enough channels for a full vec4 write or if we have processed
591 * components XY of a dvec (since components ZW are not in the same
594 if (!write_test
|| i
== num_components
- 1 || num_channels
== 4 ||
595 (i
== 1 && type_slots
== 2)) {
596 if (num_channels
> 0) {
597 /* We have channels to write, so update the offset we need to
598 * write at to skip the channels we skipped, if any.
600 if (skipped_channels
> 0) {
601 if (offset_reg
.file
== IMM
) {
602 offset_reg
.ud
+= 4 * skipped_channels
;
604 emit(ADD(dst_reg(offset_reg
), offset_reg
,
605 brw_imm_ud(4 * skipped_channels
)));
609 /* Swizzle the data register so we take the data from the channels
610 * we need to write and send the write message. This will write
611 * num_channels consecutive dwords starting at offset.
614 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
615 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
616 1 /* dims */, num_channels
/* size */,
619 /* If we have to do a second write we will have to update the
620 * offset so that we jump over the channels we have just written
623 skipped_channels
= num_channels
;
625 /* Restart the count for the next write message */
629 /* If we didn't write the channel, increase skipped count */
631 skipped_channels
+= type_slots
;
638 case nir_intrinsic_load_ssbo
: {
639 assert(devinfo
->gen
>= 7);
641 nir_const_value
*const_uniform_block
=
642 nir_src_as_const_value(instr
->src
[0]);
645 if (const_uniform_block
) {
646 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
647 const_uniform_block
->u32
[0];
648 surf_index
= brw_imm_ud(index
);
650 brw_mark_surface_used(&prog_data
->base
, index
);
652 surf_index
= src_reg(this, glsl_type::uint_type
);
653 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
654 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
655 surf_index
= emit_uniformize(surf_index
);
657 /* Assume this may touch any UBO. It would be nice to provide
658 * a tighter bound, but the array information is already lowered away.
660 brw_mark_surface_used(&prog_data
->base
,
661 prog_data
->base
.binding_table
.ssbo_start
+
662 nir
->info
.num_ssbos
- 1);
666 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
668 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
670 offset_reg
= get_nir_src(instr
->src
[1], 1);
673 /* Read the vector */
674 const vec4_builder bld
= vec4_builder(this).at_end()
675 .annotate(current_annotation
, base_ir
);
678 dst_reg dest
= get_nir_dest(instr
->dest
);
679 if (type_sz(dest
.type
) < 8) {
680 read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
681 1 /* dims */, 4 /* size*/,
684 src_reg shuffled
= src_reg(this, glsl_type::dvec4_type
);
687 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
688 1 /* dims */, 4 /* size*/,
690 emit(MOV(dst_reg(retype(shuffled
, temp
.type
)), temp
));
692 if (offset_reg
.file
== IMM
)
695 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16)));
697 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
698 1 /* dims */, 4 /* size*/,
700 emit(MOV(dst_reg(retype(byte_offset(shuffled
, REG_SIZE
), temp
.type
)),
703 read_result
= src_reg(this, glsl_type::dvec4_type
);
704 shuffle_64bit_data(dst_reg(read_result
), shuffled
, false);
707 read_result
.type
= dest
.type
;
708 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
709 emit(MOV(dest
, read_result
));
713 case nir_intrinsic_ssbo_atomic_add
:
714 nir_emit_ssbo_atomic(BRW_AOP_ADD
, instr
);
716 case nir_intrinsic_ssbo_atomic_imin
:
717 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
719 case nir_intrinsic_ssbo_atomic_umin
:
720 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
722 case nir_intrinsic_ssbo_atomic_imax
:
723 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
725 case nir_intrinsic_ssbo_atomic_umax
:
726 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
728 case nir_intrinsic_ssbo_atomic_and
:
729 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
731 case nir_intrinsic_ssbo_atomic_or
:
732 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
734 case nir_intrinsic_ssbo_atomic_xor
:
735 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
737 case nir_intrinsic_ssbo_atomic_exchange
:
738 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
740 case nir_intrinsic_ssbo_atomic_comp_swap
:
741 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
744 case nir_intrinsic_load_vertex_id
:
745 unreachable("should be lowered by lower_vertex_id()");
747 case nir_intrinsic_load_vertex_id_zero_base
:
748 case nir_intrinsic_load_base_vertex
:
749 case nir_intrinsic_load_instance_id
:
750 case nir_intrinsic_load_base_instance
:
751 case nir_intrinsic_load_draw_id
:
752 case nir_intrinsic_load_invocation_id
:
753 unreachable("should be lowered by brw_nir_lower_vs_inputs()");
755 case nir_intrinsic_load_uniform
: {
756 /* Offsets are in bytes but they should always be multiples of 4 */
757 assert(nir_intrinsic_base(instr
) % 4 == 0);
759 dest
= get_nir_dest(instr
->dest
);
761 src
= src_reg(dst_reg(UNIFORM
, nir_intrinsic_base(instr
) / 16));
762 src
.type
= dest
.type
;
764 /* Uniforms don't actually have to be vec4 aligned. In the case that
765 * it isn't, we have to use a swizzle to shift things around. They
766 * do still have the std140 alignment requirement that vec2's have to
767 * be vec2-aligned and vec3's and vec4's have to be vec4-aligned.
769 * The swizzle also works in the indirect case as the generator adds
770 * the swizzle to the offset for us.
772 const int type_size
= type_sz(src
.type
);
773 unsigned shift
= (nir_intrinsic_base(instr
) % 16) / type_size
;
774 assert(shift
+ instr
->num_components
<= 4);
776 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
778 /* Offsets are in bytes but they should always be multiples of 4 */
779 assert(const_offset
->u32
[0] % 4 == 0);
781 src
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
782 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
783 unsigned offset
= const_offset
->u32
[0] + shift
* type_size
;
784 src
.offset
= ROUND_DOWN_TO(offset
, 16);
785 shift
= (offset
% 16) / type_size
;
786 assert(shift
+ instr
->num_components
<= 4);
787 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
789 emit(MOV(dest
, src
));
791 /* Uniform arrays are vec4 aligned, because of std140 alignment
796 src_reg indirect
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
798 /* MOV_INDIRECT is going to stomp the whole thing anyway */
799 dest
.writemask
= WRITEMASK_XYZW
;
801 emit(SHADER_OPCODE_MOV_INDIRECT
, dest
, src
,
802 indirect
, brw_imm_ud(instr
->const_index
[1]));
807 case nir_intrinsic_atomic_counter_read
:
808 case nir_intrinsic_atomic_counter_inc
:
809 case nir_intrinsic_atomic_counter_dec
: {
810 unsigned surf_index
= prog_data
->base
.binding_table
.abo_start
+
811 (unsigned) instr
->const_index
[0];
812 const vec4_builder bld
=
813 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
815 /* Get some metadata from the image intrinsic. */
816 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
818 /* Get the arguments of the atomic intrinsic. */
819 src_reg offset
= get_nir_src(instr
->src
[0], nir_type_int32
,
820 instr
->num_components
);
821 const src_reg surface
= brw_imm_ud(surf_index
);
822 const src_reg src0
= (info
->num_srcs
>= 2
823 ? get_nir_src(instr
->src
[1]) : src_reg());
824 const src_reg src1
= (info
->num_srcs
>= 3
825 ? get_nir_src(instr
->src
[2]) : src_reg());
829 dest
= get_nir_dest(instr
->dest
);
831 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
832 tmp
= emit_untyped_read(bld
, surface
, offset
, 1, 1);
834 tmp
= emit_untyped_atomic(bld
, surface
, offset
,
837 get_atomic_counter_op(instr
->intrinsic
));
840 bld
.MOV(retype(dest
, tmp
.type
), tmp
);
841 brw_mark_surface_used(stage_prog_data
, surf_index
);
845 case nir_intrinsic_load_ubo
: {
846 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
849 dest
= get_nir_dest(instr
->dest
);
851 if (const_block_index
) {
852 /* The block index is a constant, so just emit the binding table entry
855 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
856 const_block_index
->u32
[0];
857 surf_index
= brw_imm_ud(index
);
858 brw_mark_surface_used(&prog_data
->base
, index
);
860 /* The block index is not a constant. Evaluate the index expression
861 * per-channel and add the base UBO index; we have to select a value
862 * from any live channel.
864 surf_index
= src_reg(this, glsl_type::uint_type
);
865 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int32
,
866 instr
->num_components
),
867 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
868 surf_index
= emit_uniformize(surf_index
);
870 /* Assume this may touch any UBO. It would be nice to provide
871 * a tighter bound, but the array information is already lowered away.
873 brw_mark_surface_used(&prog_data
->base
,
874 prog_data
->base
.binding_table
.ubo_start
+
875 nir
->info
.num_ubos
- 1);
879 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
881 offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
883 offset_reg
= get_nir_src(instr
->src
[1], nir_type_uint32
, 1);
886 src_reg packed_consts
;
887 if (nir_dest_bit_size(instr
->dest
) == 32) {
888 packed_consts
= src_reg(this, glsl_type::vec4_type
);
889 emit_pull_constant_load_reg(dst_reg(packed_consts
),
892 NULL
, NULL
/* before_block/inst */);
894 src_reg temp
= src_reg(this, glsl_type::dvec4_type
);
895 src_reg temp_float
= retype(temp
, BRW_REGISTER_TYPE_F
);
897 emit_pull_constant_load_reg(dst_reg(temp_float
),
898 surf_index
, offset_reg
, NULL
, NULL
);
899 if (offset_reg
.file
== IMM
)
902 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16u)));
903 emit_pull_constant_load_reg(dst_reg(byte_offset(temp_float
, REG_SIZE
)),
904 surf_index
, offset_reg
, NULL
, NULL
);
906 packed_consts
= src_reg(this, glsl_type::dvec4_type
);
907 shuffle_64bit_data(dst_reg(packed_consts
), temp
, false);
910 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
912 unsigned type_size
= type_sz(dest
.type
);
913 packed_consts
.swizzle
+=
914 BRW_SWIZZLE4(const_offset
->u32
[0] % 16 / type_size
,
915 const_offset
->u32
[0] % 16 / type_size
,
916 const_offset
->u32
[0] % 16 / type_size
,
917 const_offset
->u32
[0] % 16 / type_size
);
920 emit(MOV(dest
, retype(packed_consts
, dest
.type
)));
925 case nir_intrinsic_memory_barrier
: {
926 const vec4_builder bld
=
927 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
928 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
929 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
930 ->size_written
= 2 * REG_SIZE
;
934 case nir_intrinsic_shader_clock
: {
935 /* We cannot do anything if there is an event, so ignore it for now */
936 const src_reg shader_clock
= get_timestamp();
937 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
939 dest
= get_nir_dest(instr
->dest
, type
);
940 emit(MOV(dest
, shader_clock
));
945 unreachable("Unknown intrinsic");
950 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
953 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
954 dest
= get_nir_dest(instr
->dest
);
957 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
959 unsigned surf_index
= prog_data
->base
.binding_table
.ssbo_start
+
960 const_surface
->u32
[0];
961 surface
= brw_imm_ud(surf_index
);
962 brw_mark_surface_used(&prog_data
->base
, surf_index
);
964 surface
= src_reg(this, glsl_type::uint_type
);
965 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
966 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
968 /* Assume this may touch any UBO. This is the same we do for other
969 * UBO/SSBO accesses with non-constant surface.
971 brw_mark_surface_used(&prog_data
->base
,
972 prog_data
->base
.binding_table
.ssbo_start
+
973 nir
->info
.num_ssbos
- 1);
976 src_reg offset
= get_nir_src(instr
->src
[1], 1);
977 src_reg data1
= get_nir_src(instr
->src
[2], 1);
979 if (op
== BRW_AOP_CMPWR
)
980 data2
= get_nir_src(instr
->src
[3], 1);
982 /* Emit the actual atomic operation operation */
983 const vec4_builder bld
=
984 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
986 src_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
988 1 /* dims */, 1 /* rsize */,
991 dest
.type
= atomic_result
.type
;
992 bld
.MOV(dest
, atomic_result
);
996 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
998 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1001 static enum brw_conditional_mod
1002 brw_conditional_for_nir_comparison(nir_op op
)
1008 return BRW_CONDITIONAL_L
;
1013 return BRW_CONDITIONAL_GE
;
1017 case nir_op_ball_fequal2
:
1018 case nir_op_ball_iequal2
:
1019 case nir_op_ball_fequal3
:
1020 case nir_op_ball_iequal3
:
1021 case nir_op_ball_fequal4
:
1022 case nir_op_ball_iequal4
:
1023 return BRW_CONDITIONAL_Z
;
1027 case nir_op_bany_fnequal2
:
1028 case nir_op_bany_inequal2
:
1029 case nir_op_bany_fnequal3
:
1030 case nir_op_bany_inequal3
:
1031 case nir_op_bany_fnequal4
:
1032 case nir_op_bany_inequal4
:
1033 return BRW_CONDITIONAL_NZ
;
1036 unreachable("not reached: bad operation for comparison");
1041 vec4_visitor::optimize_predicate(nir_alu_instr
*instr
,
1042 enum brw_predicate
*predicate
)
1044 if (!instr
->src
[0].src
.is_ssa
||
1045 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
1048 nir_alu_instr
*cmp_instr
=
1049 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
1051 switch (cmp_instr
->op
) {
1052 case nir_op_bany_fnequal2
:
1053 case nir_op_bany_inequal2
:
1054 case nir_op_bany_fnequal3
:
1055 case nir_op_bany_inequal3
:
1056 case nir_op_bany_fnequal4
:
1057 case nir_op_bany_inequal4
:
1058 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1060 case nir_op_ball_fequal2
:
1061 case nir_op_ball_iequal2
:
1062 case nir_op_ball_fequal3
:
1063 case nir_op_ball_iequal3
:
1064 case nir_op_ball_fequal4
:
1065 case nir_op_ball_iequal4
:
1066 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1072 unsigned size_swizzle
=
1073 brw_swizzle_for_size(nir_op_infos
[cmp_instr
->op
].input_sizes
[0]);
1076 assert(nir_op_infos
[cmp_instr
->op
].num_inputs
== 2);
1077 for (unsigned i
= 0; i
< 2; i
++) {
1078 nir_alu_type type
= nir_op_infos
[cmp_instr
->op
].input_types
[i
];
1079 unsigned bit_size
= nir_src_bit_size(cmp_instr
->src
[i
].src
);
1080 type
= (nir_alu_type
) (((unsigned) type
) | bit_size
);
1081 op
[i
] = get_nir_src(cmp_instr
->src
[i
].src
, type
, 4);
1082 unsigned base_swizzle
=
1083 brw_swizzle_for_nir_swizzle(cmp_instr
->src
[i
].swizzle
);
1084 op
[i
].swizzle
= brw_compose_swizzle(size_swizzle
, base_swizzle
);
1085 op
[i
].abs
= cmp_instr
->src
[i
].abs
;
1086 op
[i
].negate
= cmp_instr
->src
[i
].negate
;
1089 emit(CMP(dst_null_d(), op
[0], op
[1],
1090 brw_conditional_for_nir_comparison(cmp_instr
->op
)));
1096 emit_find_msb_using_lzd(const vec4_builder
&bld
,
1101 vec4_instruction
*inst
;
1105 /* LZD of an absolute value source almost always does the right
1106 * thing. There are two problem values:
1108 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
1109 * 0. However, findMSB(int(0x80000000)) == 30.
1111 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
1112 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
1114 * For a value of zero or negative one, -1 will be returned.
1116 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
1117 * findMSB(-(1<<x)) should return x-1.
1119 * For all negative number cases, including 0x80000000 and
1120 * 0xffffffff, the correct value is obtained from LZD if instead of
1121 * negating the (already negative) value the logical-not is used. A
1122 * conditonal logical-not can be achieved in two instructions.
1124 temp
= src_reg(bld
.vgrf(BRW_REGISTER_TYPE_D
));
1126 bld
.ASR(dst_reg(temp
), src
, brw_imm_d(31));
1127 bld
.XOR(dst_reg(temp
), temp
, src
);
1130 bld
.LZD(retype(dst
, BRW_REGISTER_TYPE_UD
),
1131 retype(temp
, BRW_REGISTER_TYPE_UD
));
1133 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
1134 * from the LSB side. Subtract the result from 31 to convert the MSB count
1135 * into an LSB count. If no bits are set, LZD will return 32. 31-32 = -1,
1136 * which is exactly what findMSB() is supposed to return.
1138 inst
= bld
.ADD(dst
, retype(src_reg(dst
), BRW_REGISTER_TYPE_D
),
1140 inst
->src
[0].negate
= true;
1144 vec4_visitor::emit_conversion_from_double(dst_reg dst
, src_reg src
,
1147 /* BDW PRM vol 15 - workarounds:
1148 * DF->f format conversion for Align16 has wrong emask calculation when
1149 * source is immediate.
1151 if (devinfo
->gen
== 8 && dst
.type
== BRW_REGISTER_TYPE_F
&&
1152 src
.file
== BRW_IMMEDIATE_VALUE
) {
1153 vec4_instruction
*inst
= emit(MOV(dst
, brw_imm_f(src
.df
)));
1154 inst
->saturate
= saturate
;
1160 case BRW_REGISTER_TYPE_D
:
1161 op
= VEC4_OPCODE_DOUBLE_TO_D32
;
1163 case BRW_REGISTER_TYPE_UD
:
1164 op
= VEC4_OPCODE_DOUBLE_TO_U32
;
1166 case BRW_REGISTER_TYPE_F
:
1167 op
= VEC4_OPCODE_DOUBLE_TO_F32
;
1170 unreachable("Unknown conversion");
1173 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1174 emit(MOV(temp
, src
));
1175 dst_reg temp2
= dst_reg(this, glsl_type::dvec4_type
);
1176 emit(op
, temp2
, src_reg(temp
));
1178 emit(VEC4_OPCODE_PICK_LOW_32BIT
, retype(temp2
, dst
.type
), src_reg(temp2
));
1179 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(retype(temp2
, dst
.type
))));
1180 inst
->saturate
= saturate
;
1184 vec4_visitor::emit_conversion_to_double(dst_reg dst
, src_reg src
,
1187 dst_reg tmp_dst
= dst_reg(src_reg(this, glsl_type::dvec4_type
));
1188 src_reg tmp_src
= retype(src_reg(this, glsl_type::vec4_type
), src
.type
);
1189 emit(MOV(dst_reg(tmp_src
), src
));
1190 emit(VEC4_OPCODE_TO_DOUBLE
, tmp_dst
, tmp_src
);
1191 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(tmp_dst
)));
1192 inst
->saturate
= saturate
;
1196 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
1198 vec4_instruction
*inst
;
1200 nir_alu_type dst_type
= (nir_alu_type
) (nir_op_infos
[instr
->op
].output_type
|
1201 nir_dest_bit_size(instr
->dest
.dest
));
1202 dst_reg dst
= get_nir_dest(instr
->dest
.dest
, dst_type
);
1203 dst
.writemask
= instr
->dest
.write_mask
;
1206 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1207 nir_alu_type src_type
= (nir_alu_type
)
1208 (nir_op_infos
[instr
->op
].input_types
[i
] |
1209 nir_src_bit_size(instr
->src
[i
].src
));
1210 op
[i
] = get_nir_src(instr
->src
[i
].src
, src_type
, 4);
1211 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
1212 op
[i
].abs
= instr
->src
[i
].abs
;
1213 op
[i
].negate
= instr
->src
[i
].negate
;
1216 switch (instr
->op
) {
1219 inst
= emit(MOV(dst
, op
[0]));
1220 inst
->saturate
= instr
->dest
.saturate
;
1226 unreachable("not reached: should be handled by lower_vec_to_movs()");
1230 inst
= emit(MOV(dst
, op
[0]));
1231 inst
->saturate
= instr
->dest
.saturate
;
1237 if (nir_src_bit_size(instr
->src
[0].src
) == 64)
1238 emit_conversion_from_double(dst
, op
[0], instr
->dest
.saturate
);
1240 inst
= emit(MOV(dst
, op
[0]));
1246 emit_conversion_to_double(dst
, op
[0], instr
->dest
.saturate
);
1250 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1253 inst
= emit(ADD(dst
, op
[0], op
[1]));
1254 inst
->saturate
= instr
->dest
.saturate
;
1258 inst
= emit(MUL(dst
, op
[0], op
[1]));
1259 inst
->saturate
= instr
->dest
.saturate
;
1263 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1264 if (devinfo
->gen
< 8) {
1265 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
1266 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
1268 /* For integer multiplication, the MUL uses the low 16 bits of one of
1269 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1270 * accumulates in the contribution of the upper 16 bits of that
1271 * operand. If we can determine that one of the args is in the low
1272 * 16 bits, though, we can just emit a single MUL.
1274 if (value0
&& value0
->u32
[0] < (1 << 16)) {
1275 if (devinfo
->gen
< 7)
1276 emit(MUL(dst
, op
[0], op
[1]));
1278 emit(MUL(dst
, op
[1], op
[0]));
1279 } else if (value1
&& value1
->u32
[0] < (1 << 16)) {
1280 if (devinfo
->gen
< 7)
1281 emit(MUL(dst
, op
[1], op
[0]));
1283 emit(MUL(dst
, op
[0], op
[1]));
1285 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1287 emit(MUL(acc
, op
[0], op
[1]));
1288 emit(MACH(dst_null_d(), op
[0], op
[1]));
1289 emit(MOV(dst
, src_reg(acc
)));
1292 emit(MUL(dst
, op
[0], op
[1]));
1297 case nir_op_imul_high
:
1298 case nir_op_umul_high
: {
1299 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1300 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1302 if (devinfo
->gen
>= 8)
1303 emit(MUL(acc
, op
[0], retype(op
[1], BRW_REGISTER_TYPE_UW
)));
1305 emit(MUL(acc
, op
[0], op
[1]));
1307 emit(MACH(dst
, op
[0], op
[1]));
1312 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1313 inst
->saturate
= instr
->dest
.saturate
;
1317 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1318 inst
->saturate
= instr
->dest
.saturate
;
1322 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1323 inst
->saturate
= instr
->dest
.saturate
;
1327 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1328 inst
->saturate
= instr
->dest
.saturate
;
1332 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1333 inst
->saturate
= instr
->dest
.saturate
;
1338 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1339 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1344 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1345 * appears that our hardware just does the right thing for signed
1348 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1349 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1353 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1354 inst
= emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1356 /* Math instructions don't support conditional mod */
1357 inst
= emit(MOV(dst_null_d(), src_reg(dst
)));
1358 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1360 /* Now, we need to determine if signs of the sources are different.
1361 * When we XOR the sources, the top bit is 0 if they are the same and 1
1362 * if they are different. We can then use a conditional modifier to
1363 * turn that into a predicate. This leads us to an XOR.l instruction.
1365 * Technically, according to the PRM, you're not allowed to use .l on a
1366 * XOR instruction. However, emperical experiments and Curro's reading
1367 * of the simulator source both indicate that it's safe.
1369 src_reg tmp
= src_reg(this, glsl_type::ivec4_type
);
1370 inst
= emit(XOR(dst_reg(tmp
), op
[0], op
[1]));
1371 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1372 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1374 /* If the result of the initial remainder operation is non-zero and the
1375 * two sources have different signs, add in a copy of op[1] to get the
1376 * final integer modulus value.
1378 inst
= emit(ADD(dst
, src_reg(dst
), op
[1]));
1379 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1384 unreachable("not reached: should be handled by ldexp_to_arith()");
1387 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1388 inst
->saturate
= instr
->dest
.saturate
;
1392 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1393 inst
->saturate
= instr
->dest
.saturate
;
1397 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1398 inst
->saturate
= instr
->dest
.saturate
;
1401 case nir_op_uadd_carry
: {
1402 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1403 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1405 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1406 emit(MOV(dst
, src_reg(acc
)));
1410 case nir_op_usub_borrow
: {
1411 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1412 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1414 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1415 emit(MOV(dst
, src_reg(acc
)));
1420 inst
= emit(RNDZ(dst
, op
[0]));
1421 inst
->saturate
= instr
->dest
.saturate
;
1424 case nir_op_fceil
: {
1425 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1427 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1428 instr
->src
[0].src
.ssa
->num_components
:
1429 instr
->src
[0].src
.reg
.reg
->num_components
);
1431 op
[0].negate
= !op
[0].negate
;
1432 emit(RNDD(dst_reg(tmp
), op
[0]));
1434 inst
= emit(MOV(dst
, tmp
));
1435 inst
->saturate
= instr
->dest
.saturate
;
1440 inst
= emit(RNDD(dst
, op
[0]));
1441 inst
->saturate
= instr
->dest
.saturate
;
1445 inst
= emit(FRC(dst
, op
[0]));
1446 inst
->saturate
= instr
->dest
.saturate
;
1449 case nir_op_fround_even
:
1450 inst
= emit(RNDE(dst
, op
[0]));
1451 inst
->saturate
= instr
->dest
.saturate
;
1454 case nir_op_fquantize2f16
: {
1455 /* See also vec4_visitor::emit_pack_half_2x16() */
1456 src_reg tmp16
= src_reg(this, glsl_type::uvec4_type
);
1457 src_reg tmp32
= src_reg(this, glsl_type::vec4_type
);
1458 src_reg zero
= src_reg(this, glsl_type::vec4_type
);
1460 /* Check for denormal */
1461 src_reg abs_src0
= op
[0];
1462 abs_src0
.abs
= true;
1463 emit(CMP(dst_null_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1464 BRW_CONDITIONAL_L
));
1465 /* Get the appropriately signed zero */
1466 emit(AND(retype(dst_reg(zero
), BRW_REGISTER_TYPE_UD
),
1467 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1468 brw_imm_ud(0x80000000)));
1469 /* Do the actual F32 -> F16 -> F32 conversion */
1470 emit(F32TO16(dst_reg(tmp16
), op
[0]));
1471 emit(F16TO32(dst_reg(tmp32
), tmp16
));
1472 /* Select that or zero based on normal status */
1473 inst
= emit(BRW_OPCODE_SEL
, dst
, zero
, tmp32
);
1474 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1475 inst
->saturate
= instr
->dest
.saturate
;
1481 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1484 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1485 inst
->saturate
= instr
->dest
.saturate
;
1490 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1493 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1494 inst
->saturate
= instr
->dest
.saturate
;
1498 case nir_op_fddx_coarse
:
1499 case nir_op_fddx_fine
:
1501 case nir_op_fddy_coarse
:
1502 case nir_op_fddy_fine
:
1503 unreachable("derivatives are not valid in vertex shaders");
1511 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1517 enum brw_conditional_mod conditional_mod
=
1518 brw_conditional_for_nir_comparison(instr
->op
);
1520 if (nir_src_bit_size(instr
->src
[0].src
) < 64) {
1521 emit(CMP(dst
, op
[0], op
[1], conditional_mod
));
1523 /* Produce a 32-bit boolean result from the DF comparison by selecting
1524 * only the low 32-bit in each DF produced. Do this in a temporary
1525 * so we can then move from there to the result using align16 again
1526 * to honor the original writemask.
1528 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1529 emit(CMP(temp
, op
[0], op
[1], conditional_mod
));
1530 dst_reg result
= dst_reg(this, glsl_type::bvec4_type
);
1531 emit(VEC4_OPCODE_PICK_LOW_32BIT
, result
, src_reg(temp
));
1532 emit(MOV(dst
, src_reg(result
)));
1537 case nir_op_ball_iequal2
:
1538 case nir_op_ball_iequal3
:
1539 case nir_op_ball_iequal4
:
1540 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1542 case nir_op_ball_fequal2
:
1543 case nir_op_ball_fequal3
:
1544 case nir_op_ball_fequal4
: {
1546 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1548 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1549 brw_conditional_for_nir_comparison(instr
->op
)));
1550 emit(MOV(dst
, brw_imm_d(0)));
1551 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1552 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1556 case nir_op_bany_inequal2
:
1557 case nir_op_bany_inequal3
:
1558 case nir_op_bany_inequal4
:
1559 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1561 case nir_op_bany_fnequal2
:
1562 case nir_op_bany_fnequal3
:
1563 case nir_op_bany_fnequal4
: {
1565 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1567 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1568 brw_conditional_for_nir_comparison(instr
->op
)));
1570 emit(MOV(dst
, brw_imm_d(0)));
1571 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1572 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1577 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1578 if (devinfo
->gen
>= 8) {
1579 op
[0] = resolve_source_modifiers(op
[0]);
1581 emit(NOT(dst
, op
[0]));
1585 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1586 if (devinfo
->gen
>= 8) {
1587 op
[0] = resolve_source_modifiers(op
[0]);
1588 op
[1] = resolve_source_modifiers(op
[1]);
1590 emit(XOR(dst
, op
[0], op
[1]));
1594 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1595 if (devinfo
->gen
>= 8) {
1596 op
[0] = resolve_source_modifiers(op
[0]);
1597 op
[1] = resolve_source_modifiers(op
[1]);
1599 emit(OR(dst
, op
[0], op
[1]));
1603 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1604 if (devinfo
->gen
>= 8) {
1605 op
[0] = resolve_source_modifiers(op
[0]);
1606 op
[1] = resolve_source_modifiers(op
[1]);
1608 emit(AND(dst
, op
[0], op
[1]));
1613 emit(MOV(dst
, negate(op
[0])));
1617 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1618 /* We use a MOV with conditional_mod to check if the provided value is
1619 * 0.0. We want this to flush denormalized numbers to zero, so we set a
1620 * source modifier on the source operand to trigger this, as source
1621 * modifiers don't affect the result of the testing against 0.0.
1623 src_reg value
= op
[0];
1625 vec4_instruction
*inst
= emit(MOV(dst_null_df(), value
));
1626 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1628 src_reg one
= src_reg(this, glsl_type::ivec4_type
);
1629 emit(MOV(dst_reg(one
), brw_imm_d(~0)));
1630 inst
= emit(BRW_OPCODE_SEL
, dst
, one
, brw_imm_d(0));
1631 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1633 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1638 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1641 case nir_op_fnoise1_1
:
1642 case nir_op_fnoise1_2
:
1643 case nir_op_fnoise1_3
:
1644 case nir_op_fnoise1_4
:
1645 case nir_op_fnoise2_1
:
1646 case nir_op_fnoise2_2
:
1647 case nir_op_fnoise2_3
:
1648 case nir_op_fnoise2_4
:
1649 case nir_op_fnoise3_1
:
1650 case nir_op_fnoise3_2
:
1651 case nir_op_fnoise3_3
:
1652 case nir_op_fnoise3_4
:
1653 case nir_op_fnoise4_1
:
1654 case nir_op_fnoise4_2
:
1655 case nir_op_fnoise4_3
:
1656 case nir_op_fnoise4_4
:
1657 unreachable("not reached: should be handled by lower_noise");
1659 case nir_op_unpack_half_2x16_split_x
:
1660 case nir_op_unpack_half_2x16_split_y
:
1661 case nir_op_pack_half_2x16_split
:
1662 unreachable("not reached: should not occur in vertex shader");
1664 case nir_op_unpack_snorm_2x16
:
1665 case nir_op_unpack_unorm_2x16
:
1666 case nir_op_pack_snorm_2x16
:
1667 case nir_op_pack_unorm_2x16
:
1668 unreachable("not reached: should be handled by lower_packing_builtins");
1670 case nir_op_pack_uvec4_to_uint
:
1671 unreachable("not reached");
1673 case nir_op_pack_uvec2_to_uint
: {
1674 dst_reg tmp1
= dst_reg(this, glsl_type::uint_type
);
1675 tmp1
.writemask
= WRITEMASK_X
;
1676 op
[0].swizzle
= BRW_SWIZZLE_YYYY
;
1677 emit(SHL(tmp1
, op
[0], src_reg(brw_imm_ud(16u))));
1679 dst_reg tmp2
= dst_reg(this, glsl_type::uint_type
);
1680 tmp2
.writemask
= WRITEMASK_X
;
1681 op
[0].swizzle
= BRW_SWIZZLE_XXXX
;
1682 emit(AND(tmp2
, op
[0], src_reg(brw_imm_ud(0xffffu
))));
1684 emit(OR(dst
, src_reg(tmp1
), src_reg(tmp2
)));
1688 case nir_op_pack_64_2x32_split
: {
1689 dst_reg result
= dst_reg(this, glsl_type::dvec4_type
);
1690 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1691 emit(MOV(tmp
, retype(op
[0], BRW_REGISTER_TYPE_UD
)));
1692 emit(VEC4_OPCODE_SET_LOW_32BIT
, result
, src_reg(tmp
));
1693 emit(MOV(tmp
, retype(op
[1], BRW_REGISTER_TYPE_UD
)));
1694 emit(VEC4_OPCODE_SET_HIGH_32BIT
, result
, src_reg(tmp
));
1695 emit(MOV(dst
, src_reg(result
)));
1699 case nir_op_unpack_64_2x32_split_x
:
1700 case nir_op_unpack_64_2x32_split_y
: {
1701 enum opcode oper
= (instr
->op
== nir_op_unpack_64_2x32_split_x
) ?
1702 VEC4_OPCODE_PICK_LOW_32BIT
: VEC4_OPCODE_PICK_HIGH_32BIT
;
1703 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
1704 emit(MOV(tmp
, op
[0]));
1705 dst_reg tmp2
= dst_reg(this, glsl_type::uvec4_type
);
1706 emit(oper
, tmp2
, src_reg(tmp
));
1707 emit(MOV(dst
, src_reg(tmp2
)));
1711 case nir_op_unpack_half_2x16
:
1712 /* As NIR does not guarantee that we have a correct swizzle outside the
1713 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1714 * uses the source operand in an operation with WRITEMASK_Y while our
1715 * source operand has only size 1, it accessed incorrect data producing
1716 * regressions in Piglit. We repeat the swizzle of the first component on the
1717 * rest of components to avoid regressions. In the vec4_visitor IR code path
1718 * this is not needed because the operand has already the correct swizzle.
1720 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1721 emit_unpack_half_2x16(dst
, op
[0]);
1724 case nir_op_pack_half_2x16
:
1725 emit_pack_half_2x16(dst
, op
[0]);
1728 case nir_op_unpack_unorm_4x8
:
1729 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1730 emit_unpack_unorm_4x8(dst
, op
[0]);
1733 case nir_op_pack_unorm_4x8
:
1734 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1735 emit_pack_unorm_4x8(dst
, op
[0]);
1738 case nir_op_unpack_snorm_4x8
:
1739 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1740 emit_unpack_snorm_4x8(dst
, op
[0]);
1743 case nir_op_pack_snorm_4x8
:
1744 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1745 emit_pack_snorm_4x8(dst
, op
[0]);
1748 case nir_op_bitfield_reverse
:
1749 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1750 emit(BFREV(dst
, op
[0]));
1753 case nir_op_bit_count
:
1754 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1755 emit(CBIT(dst
, op
[0]));
1758 case nir_op_ufind_msb
:
1759 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1760 emit_find_msb_using_lzd(vec4_builder(this).at_end(), dst
, op
[0], false);
1763 case nir_op_ifind_msb
: {
1764 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1765 vec4_builder bld
= vec4_builder(this).at_end();
1768 if (devinfo
->gen
< 7) {
1769 emit_find_msb_using_lzd(bld
, dst
, op
[0], true);
1771 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1773 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1774 * count from the LSB side. If FBH didn't return an error
1775 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1776 * count into an LSB count.
1778 bld
.CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1780 inst
= bld
.ADD(dst
, src
, brw_imm_d(31));
1781 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1782 inst
->src
[0].negate
= true;
1787 case nir_op_find_lsb
: {
1788 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1789 vec4_builder bld
= vec4_builder(this).at_end();
1791 if (devinfo
->gen
< 7) {
1792 dst_reg temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1794 /* (x & -x) generates a value that consists of only the LSB of x.
1795 * For all powers of 2, findMSB(y) == findLSB(y).
1797 src_reg src
= src_reg(retype(op
[0], BRW_REGISTER_TYPE_D
));
1798 src_reg negated_src
= src
;
1800 /* One must be negated, and the other must be non-negated. It
1801 * doesn't matter which is which.
1803 negated_src
.negate
= true;
1806 bld
.AND(temp
, src
, negated_src
);
1807 emit_find_msb_using_lzd(bld
, dst
, src_reg(temp
), false);
1809 bld
.FBL(dst
, op
[0]);
1814 case nir_op_ubitfield_extract
:
1815 case nir_op_ibitfield_extract
:
1816 unreachable("should have been lowered");
1819 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1820 op
[0] = fix_3src_operand(op
[0]);
1821 op
[1] = fix_3src_operand(op
[1]);
1822 op
[2] = fix_3src_operand(op
[2]);
1824 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1828 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1829 emit(BFI1(dst
, op
[0], op
[1]));
1833 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1834 op
[0] = fix_3src_operand(op
[0]);
1835 op
[1] = fix_3src_operand(op
[1]);
1836 op
[2] = fix_3src_operand(op
[2]);
1838 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1841 case nir_op_bitfield_insert
:
1842 unreachable("not reached: should have been lowered");
1845 if (type_sz(op
[0].type
) < 8) {
1846 /* AND(val, 0x80000000) gives the sign bit.
1848 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1851 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1853 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1854 dst
.type
= BRW_REGISTER_TYPE_UD
;
1855 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1857 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1858 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1859 dst
.type
= BRW_REGISTER_TYPE_F
;
1861 if (instr
->dest
.saturate
) {
1862 inst
= emit(MOV(dst
, src_reg(dst
)));
1863 inst
->saturate
= true;
1866 /* For doubles we do the same but we need to consider:
1868 * - We use a MOV with conditional_mod instead of a CMP so that we can
1869 * skip loading a 0.0 immediate. We use a source modifier on the
1870 * source of the MOV so that we flush denormalized values to 0.
1871 * Since we want to compare against 0, this won't alter the result.
1872 * - We need to extract the high 32-bit of each DF where the sign
1874 * - We need to produce a DF result.
1877 /* Check for zero */
1878 src_reg value
= op
[0];
1880 inst
= emit(MOV(dst_null_df(), value
));
1881 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1883 /* AND each high 32-bit channel with 0x80000000u */
1884 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1885 emit(VEC4_OPCODE_PICK_HIGH_32BIT
, tmp
, op
[0]);
1886 emit(AND(tmp
, src_reg(tmp
), brw_imm_ud(0x80000000u
)));
1888 /* Add 1.0 to each channel, predicated to skip the cases where the
1889 * channel's value was 0
1891 inst
= emit(OR(tmp
, src_reg(tmp
), brw_imm_ud(0x3f800000u
)));
1892 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1894 /* Now convert the result from float to double */
1895 emit_conversion_to_double(dst
, retype(src_reg(tmp
),
1896 BRW_REGISTER_TYPE_F
),
1897 instr
->dest
.saturate
);
1902 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1903 * -> non-negative val generates 0x00000000.
1904 * Predicated OR sets 1 if val is positive.
1906 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1907 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1908 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1909 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1910 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1914 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1915 emit(SHL(dst
, op
[0], op
[1]));
1919 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1920 emit(ASR(dst
, op
[0], op
[1]));
1924 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1925 emit(SHR(dst
, op
[0], op
[1]));
1929 if (type_sz(dst
.type
) == 8) {
1930 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
1931 emit(MUL(mul_dst
, op
[1], op
[0]));
1932 inst
= emit(ADD(dst
, src_reg(mul_dst
), op
[2]));
1933 inst
->saturate
= instr
->dest
.saturate
;
1935 op
[0] = fix_3src_operand(op
[0]);
1936 op
[1] = fix_3src_operand(op
[1]);
1937 op
[2] = fix_3src_operand(op
[2]);
1939 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1940 inst
->saturate
= instr
->dest
.saturate
;
1945 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1946 inst
->saturate
= instr
->dest
.saturate
;
1950 enum brw_predicate predicate
;
1951 if (!optimize_predicate(instr
, &predicate
)) {
1952 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1953 switch (dst
.writemask
) {
1955 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1958 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1961 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1964 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1967 predicate
= BRW_PREDICATE_NORMAL
;
1971 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1972 inst
->predicate
= predicate
;
1975 case nir_op_fdot_replicated2
:
1976 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1977 inst
->saturate
= instr
->dest
.saturate
;
1980 case nir_op_fdot_replicated3
:
1981 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1982 inst
->saturate
= instr
->dest
.saturate
;
1985 case nir_op_fdot_replicated4
:
1986 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1987 inst
->saturate
= instr
->dest
.saturate
;
1990 case nir_op_fdph_replicated
:
1991 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1992 inst
->saturate
= instr
->dest
.saturate
;
1997 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
2002 unreachable("not reached: should be lowered by lower_source mods");
2005 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
2008 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
2012 unreachable("not reached: should be handled by ir_sub_to_add_neg");
2015 unreachable("Unimplemented ALU operation");
2018 /* If we need to do a boolean resolve, replace the result with -(x & 1)
2019 * to sign extend the low bit to 0/~0
2021 if (devinfo
->gen
<= 5 &&
2022 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
2023 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
2024 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
2025 masked
.writemask
= dst
.writemask
;
2026 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
2027 src_reg masked_neg
= src_reg(masked
);
2028 masked_neg
.negate
= true;
2029 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
2034 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
2036 switch (instr
->type
) {
2037 case nir_jump_break
:
2038 emit(BRW_OPCODE_BREAK
);
2041 case nir_jump_continue
:
2042 emit(BRW_OPCODE_CONTINUE
);
2045 case nir_jump_return
:
2048 unreachable("unknown jump");
2052 enum ir_texture_opcode
2053 ir_texture_opcode_for_nir_texop(nir_texop texop
)
2055 enum ir_texture_opcode op
;
2058 case nir_texop_lod
: op
= ir_lod
; break;
2059 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2060 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
2061 case nir_texop_tex
: op
= ir_tex
; break;
2062 case nir_texop_tg4
: op
= ir_tg4
; break;
2063 case nir_texop_txb
: op
= ir_txb
; break;
2064 case nir_texop_txd
: op
= ir_txd
; break;
2065 case nir_texop_txf
: op
= ir_txf
; break;
2066 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2067 case nir_texop_txl
: op
= ir_txl
; break;
2068 case nir_texop_txs
: op
= ir_txs
; break;
2069 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2071 unreachable("unknown texture opcode");
2077 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
2078 unsigned components
)
2080 return glsl_type::get_instance(brw_glsl_base_type_for_nir_type(alu_type
),
2085 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
2087 unsigned texture
= instr
->texture_index
;
2088 unsigned sampler
= instr
->sampler_index
;
2089 src_reg texture_reg
= brw_imm_ud(texture
);
2090 src_reg sampler_reg
= brw_imm_ud(sampler
);
2092 const glsl_type
*coord_type
= NULL
;
2093 src_reg shadow_comparator
;
2094 src_reg offset_value
;
2096 src_reg sample_index
;
2099 const glsl_type
*dest_type
=
2100 glsl_type_for_nir_alu_type(instr
->dest_type
,
2101 nir_tex_instr_dest_size(instr
));
2102 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
2104 /* The hardware requires a LOD for buffer textures */
2105 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
2108 /* Load the texture operation sources */
2109 uint32_t constant_offset
= 0;
2110 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2111 switch (instr
->src
[i
].src_type
) {
2112 case nir_tex_src_comparator
:
2113 shadow_comparator
= get_nir_src(instr
->src
[i
].src
,
2114 BRW_REGISTER_TYPE_F
, 1);
2117 case nir_tex_src_coord
: {
2118 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
2120 switch (instr
->op
) {
2122 case nir_texop_txf_ms
:
2123 case nir_texop_samples_identical
:
2124 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
2126 coord_type
= glsl_type::ivec(src_size
);
2130 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2132 coord_type
= glsl_type::vec(src_size
);
2138 case nir_tex_src_ddx
:
2139 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2140 nir_tex_instr_src_size(instr
, i
));
2143 case nir_tex_src_ddy
:
2144 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2145 nir_tex_instr_src_size(instr
, i
));
2148 case nir_tex_src_lod
:
2149 switch (instr
->op
) {
2152 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2156 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
2161 case nir_tex_src_ms_index
: {
2162 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2166 case nir_tex_src_offset
: {
2167 nir_const_value
*const_offset
=
2168 nir_src_as_const_value(instr
->src
[i
].src
);
2169 if (!const_offset
||
2170 !brw_texture_offset(const_offset
->i32
,
2171 nir_tex_instr_src_size(instr
, i
),
2172 &constant_offset
)) {
2174 get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
2179 case nir_tex_src_texture_offset
: {
2180 /* The highest texture which may be used by this operation is
2181 * the last element of the array. Mark it here, because the generator
2182 * doesn't have enough information to determine the bound.
2184 uint32_t array_size
= instr
->texture_array_size
;
2185 uint32_t max_used
= texture
+ array_size
- 1;
2186 if (instr
->op
== nir_texop_tg4
) {
2187 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2189 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2192 brw_mark_surface_used(&prog_data
->base
, max_used
);
2194 /* Emit code to evaluate the actual indexing expression */
2195 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2196 src_reg
temp(this, glsl_type::uint_type
);
2197 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(texture
)));
2198 texture_reg
= emit_uniformize(temp
);
2202 case nir_tex_src_sampler_offset
: {
2203 /* Emit code to evaluate the actual indexing expression */
2204 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2205 src_reg
temp(this, glsl_type::uint_type
);
2206 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
2207 sampler_reg
= emit_uniformize(temp
);
2211 case nir_tex_src_projector
:
2212 unreachable("Should be lowered by do_lower_texture_projection");
2214 case nir_tex_src_bias
:
2215 unreachable("LOD bias is not valid for vertex shaders.\n");
2218 unreachable("unknown texture source");
2222 if (instr
->op
== nir_texop_txf_ms
||
2223 instr
->op
== nir_texop_samples_identical
) {
2224 assert(coord_type
!= NULL
);
2225 if (devinfo
->gen
>= 7 &&
2226 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
2227 mcs
= emit_mcs_fetch(coord_type
, coordinate
, texture_reg
);
2229 mcs
= brw_imm_ud(0u);
2233 /* Stuff the channel select bits in the top of the texture offset */
2234 if (instr
->op
== nir_texop_tg4
) {
2235 if (instr
->component
== 1 &&
2236 (key_tex
->gather_channel_quirk_mask
& (1 << texture
))) {
2237 /* gather4 sampler is broken for green channel on RG32F --
2238 * we must ask for blue instead.
2240 constant_offset
|= 2 << 16;
2242 constant_offset
|= instr
->component
<< 16;
2246 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
2248 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
2250 lod
, lod2
, sample_index
,
2251 constant_offset
, offset_value
, mcs
,
2252 texture
, texture_reg
, sampler_reg
);
2256 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
2258 nir_ssa_values
[instr
->def
.index
] =
2259 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(instr
->def
.bit_size
, 32)));
2262 /* SIMD4x2 64bit data is stored in register space like this:
2264 * r0.0:DF x0 y0 z0 w0
2265 * r1.0:DF x1 y1 z1 w1
2267 * When we need to write data such as this to memory using 32-bit write
2268 * messages we need to shuffle it in this fashion:
2270 * r0.0:DF x0 y0 x1 y1 (to be written at base offset)
2271 * r0.0:DF z0 w0 z1 w1 (to be written at base offset + 16)
2273 * We need to do the inverse operation when we read using 32-bit messages,
2274 * which we can do by applying the same exact shuffling on the 64-bit data
2275 * read, only that because the data for each vertex is positioned differently
2276 * we need to apply different channel enables.
2278 * This function takes 64bit data and shuffles it as explained above.
2280 * The @for_write parameter is used to specify if the shuffling is being done
2281 * for proper SIMD4x2 64-bit data that needs to be shuffled prior to a 32-bit
2282 * write message (for_write = true), or instead we are doing the inverse
2283 * operation and we have just read 64-bit data using a 32-bit messages that we
2284 * need to shuffle to create valid SIMD4x2 64-bit data (for_write = false).
2286 * If @block and @ref are non-NULL, then the shuffling is done after @ref,
2287 * otherwise the instructions are emitted normally at the end. The function
2288 * returns the last instruction inserted.
2290 * Notice that @src and @dst cannot be the same register.
2293 vec4_visitor::shuffle_64bit_data(dst_reg dst
, src_reg src
, bool for_write
,
2294 bblock_t
*block
, vec4_instruction
*ref
)
2296 assert(type_sz(src
.type
) == 8);
2297 assert(type_sz(dst
.type
) == 8);
2298 assert(!regions_overlap(dst
, 2 * REG_SIZE
, src
, 2 * REG_SIZE
));
2299 assert(!ref
== !block
);
2301 const vec4_builder bld
= !ref
? vec4_builder(this).at_end() :
2302 vec4_builder(this).at(block
, ref
->next
);
2304 /* Resolve swizzle in src */
2305 vec4_instruction
*inst
;
2306 if (src
.swizzle
!= BRW_SWIZZLE_XYZW
) {
2307 dst_reg data
= dst_reg(this, glsl_type::dvec4_type
);
2308 inst
= bld
.MOV(data
, src
);
2309 src
= src_reg(data
);
2312 /* dst+0.XY = src+0.XY */
2313 inst
= bld
.group(4, 0).MOV(writemask(dst
, WRITEMASK_XY
), src
);
2315 /* dst+0.ZW = src+1.XY */
2316 inst
= bld
.group(4, for_write
? 1 : 0)
2317 .MOV(writemask(dst
, WRITEMASK_ZW
),
2318 swizzle(byte_offset(src
, REG_SIZE
), BRW_SWIZZLE_XYXY
));
2320 /* dst+1.XY = src+0.ZW */
2321 inst
= bld
.group(4, for_write
? 0 : 1)
2322 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_XY
),
2323 swizzle(src
, BRW_SWIZZLE_ZWZW
));
2325 /* dst+1.ZW = src+1.ZW */
2326 inst
= bld
.group(4, 1)
2327 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_ZW
),
2328 byte_offset(src
, REG_SIZE
));