2 * Copyright © 2013 Intel Corporation
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6 * to deal in the Software without restriction, including without limitation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 * DEALINGS IN THE SOFTWARE.
25 * \file brw_vec4_tcs.cpp
27 * Tessellaton control shader specific code derived from the vec4_visitor class.
31 #include "brw_vec4_tcs.h"
33 #include "common/gen_debug.h"
37 vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler
*compiler
,
39 const struct brw_tcs_prog_key
*key
,
40 struct brw_tcs_prog_data
*prog_data
,
41 const nir_shader
*nir
,
43 int shader_time_index
,
44 const struct brw_vue_map
*input_vue_map
)
45 : vec4_visitor(compiler
, log_data
, &key
->tex
, &prog_data
->base
,
46 nir
, mem_ctx
, false, shader_time_index
),
47 input_vue_map(input_vue_map
), key(key
)
53 vec4_tcs_visitor::setup_payload()
57 /* The payload always contains important data in r0, which contains
58 * the URB handles that are passed on to the URB write at the end
63 /* r1.0 - r4.7 may contain the input control point URB handles,
64 * which we use to pull vertex data.
68 /* Push constants may start at r5.0 */
69 reg
= setup_uniforms(reg
);
71 this->first_non_payload_grf
= reg
;
76 vec4_tcs_visitor::emit_prolog()
78 invocation_id
= src_reg(this, glsl_type::uint_type
);
79 emit(TCS_OPCODE_GET_INSTANCE_ID
, dst_reg(invocation_id
));
81 /* HS threads are dispatched with the dispatch mask set to 0xFF.
82 * If there are an odd number of output vertices, then the final
83 * HS instance dispatched will only have its bottom half doing real
84 * work, and so we need to disable the upper half:
86 if (nir
->info
.tess
.tcs_vertices_out
% 2) {
87 emit(CMP(dst_null_d(), invocation_id
,
88 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
),
91 /* Matching ENDIF is in emit_thread_end() */
92 emit(IF(BRW_PREDICATE_NORMAL
));
98 vec4_tcs_visitor::emit_thread_end()
100 vec4_instruction
*inst
;
101 current_annotation
= "thread end";
103 if (nir
->info
.tess
.tcs_vertices_out
% 2) {
104 emit(BRW_OPCODE_ENDIF
);
107 if (devinfo
->gen
== 7) {
108 struct brw_tcs_prog_data
*tcs_prog_data
=
109 (struct brw_tcs_prog_data
*) prog_data
;
111 current_annotation
= "release input vertices";
113 /* Synchronize all threads, so we know that no one is still
114 * using the input URB handles.
116 if (tcs_prog_data
->instances
> 1) {
117 dst_reg header
= dst_reg(this, glsl_type::uvec4_type
);
118 emit(TCS_OPCODE_CREATE_BARRIER_HEADER
, header
);
119 emit(SHADER_OPCODE_BARRIER
, dst_null_ud(), src_reg(header
));
122 /* Make thread 0 (invocations <1, 0>) release pairs of ICP handles.
123 * We want to compare the bottom half of invocation_id with 0, but
124 * use that truth value for the top half as well. Unfortunately,
125 * we don't have stride in the vec4 world, nor UV immediates in
126 * align16, so we need an opcode to get invocation_id<0,4,0>.
128 set_condmod(BRW_CONDITIONAL_Z
,
129 emit(TCS_OPCODE_SRC0_010_IS_ZERO
, dst_null_d(),
131 emit(IF(BRW_PREDICATE_NORMAL
));
132 for (unsigned i
= 0; i
< key
->input_vertices
; i
+= 2) {
133 /* If we have an odd number of input vertices, the last will be
134 * unpaired. We don't want to use an interleaved URB write in
137 const bool is_unpaired
= i
== key
->input_vertices
- 1;
139 dst_reg
header(this, glsl_type::uvec4_type
);
140 emit(TCS_OPCODE_RELEASE_INPUT
, header
, brw_imm_ud(i
),
141 brw_imm_ud(is_unpaired
));
143 emit(BRW_OPCODE_ENDIF
);
146 if (unlikely(INTEL_DEBUG
& DEBUG_SHADER_TIME
))
147 emit_shader_time_end();
149 inst
= emit(TCS_OPCODE_THREAD_END
);
156 vec4_tcs_visitor::emit_input_urb_read(const dst_reg
&dst
,
157 const src_reg
&vertex_index
,
158 unsigned base_offset
,
159 unsigned first_component
,
160 const src_reg
&indirect_offset
)
162 vec4_instruction
*inst
;
163 dst_reg
temp(this, glsl_type::ivec4_type
);
164 temp
.type
= dst
.type
;
166 /* Set up the message header to reference the proper parts of the URB */
167 dst_reg header
= dst_reg(this, glsl_type::uvec4_type
);
168 inst
= emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS
, header
, vertex_index
,
170 inst
->force_writemask_all
= true;
172 /* Read into a temporary, ignoring writemasking. */
173 inst
= emit(VEC4_OPCODE_URB_READ
, temp
, src_reg(header
));
174 inst
->offset
= base_offset
;
178 /* Copy the temporary to the destination to deal with writemasking.
180 * Also attempt to deal with gl_PointSize being in the .w component.
182 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
183 emit(MOV(dst
, swizzle(src_reg(temp
), BRW_SWIZZLE_WWWW
)));
185 src_reg src
= src_reg(temp
);
186 src
.swizzle
= BRW_SWZ_COMP_INPUT(first_component
);
192 vec4_tcs_visitor::emit_output_urb_read(const dst_reg
&dst
,
193 unsigned base_offset
,
194 unsigned first_component
,
195 const src_reg
&indirect_offset
)
197 vec4_instruction
*inst
;
199 /* Set up the message header to reference the proper parts of the URB */
200 dst_reg header
= dst_reg(this, glsl_type::uvec4_type
);
201 inst
= emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
, header
,
202 brw_imm_ud(dst
.writemask
<< first_component
), indirect_offset
);
203 inst
->force_writemask_all
= true;
205 vec4_instruction
*read
= emit(VEC4_OPCODE_URB_READ
, dst
, src_reg(header
));
206 read
->offset
= base_offset
;
210 if (first_component
) {
211 /* Read into a temporary and copy with a swizzle and writemask. */
212 read
->dst
= retype(dst_reg(this, glsl_type::ivec4_type
), dst
.type
);
213 emit(MOV(dst
, swizzle(src_reg(read
->dst
),
214 BRW_SWZ_COMP_INPUT(first_component
))));
219 vec4_tcs_visitor::emit_urb_write(const src_reg
&value
,
221 unsigned base_offset
,
222 const src_reg
&indirect_offset
)
227 src_reg
message(this, glsl_type::uvec4_type
, 2);
228 vec4_instruction
*inst
;
230 inst
= emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
, dst_reg(message
),
231 brw_imm_ud(writemask
), indirect_offset
);
232 inst
->force_writemask_all
= true;
233 inst
= emit(MOV(byte_offset(dst_reg(retype(message
, value
.type
)), REG_SIZE
),
235 inst
->force_writemask_all
= true;
237 inst
= emit(TCS_OPCODE_URB_WRITE
, dst_null_f(), message
);
238 inst
->offset
= base_offset
;
244 vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
246 switch (instr
->intrinsic
) {
247 case nir_intrinsic_load_invocation_id
:
248 emit(MOV(get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_UD
),
251 case nir_intrinsic_load_primitive_id
:
252 emit(TCS_OPCODE_GET_PRIMITIVE_ID
,
253 get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_UD
));
255 case nir_intrinsic_load_patch_vertices_in
:
256 emit(MOV(get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_D
),
257 brw_imm_d(key
->input_vertices
)));
259 case nir_intrinsic_load_per_vertex_input
: {
260 src_reg indirect_offset
= get_indirect_offset(instr
);
261 unsigned imm_offset
= instr
->const_index
[0];
263 nir_const_value
*vertex_const
= nir_src_as_const_value(instr
->src
[0]);
264 src_reg vertex_index
=
265 vertex_const
? src_reg(brw_imm_ud(vertex_const
->u32
[0]))
266 : get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
268 unsigned first_component
= nir_intrinsic_component(instr
);
269 if (nir_dest_bit_size(instr
->dest
) == 64) {
270 /* We need to emit up to two 32-bit URB reads, then shuffle
271 * the result into a temporary, then move to the destination
272 * honoring the writemask
274 * We don't need to divide first_component by 2 because
275 * emit_input_urb_read takes a 32-bit type.
277 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
278 dst_reg tmp_d
= retype(tmp
, BRW_REGISTER_TYPE_D
);
279 emit_input_urb_read(tmp_d
, vertex_index
, imm_offset
,
280 first_component
, indirect_offset
);
281 if (instr
->num_components
> 2) {
282 emit_input_urb_read(byte_offset(tmp_d
, REG_SIZE
), vertex_index
,
283 imm_offset
+ 1, 0, indirect_offset
);
286 src_reg tmp_src
= retype(src_reg(tmp_d
), BRW_REGISTER_TYPE_DF
);
287 dst_reg shuffled
= dst_reg(this, glsl_type::dvec4_type
);
288 shuffle_64bit_data(shuffled
, tmp_src
, false);
290 dst_reg dst
= get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_DF
);
291 dst
.writemask
= brw_writemask_for_size(instr
->num_components
);
292 emit(MOV(dst
, src_reg(shuffled
)));
294 dst_reg dst
= get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_D
);
295 dst
.writemask
= brw_writemask_for_size(instr
->num_components
);
296 emit_input_urb_read(dst
, vertex_index
, imm_offset
,
297 first_component
, indirect_offset
);
301 case nir_intrinsic_load_input
:
302 unreachable("nir_lower_io should use load_per_vertex_input intrinsics");
304 case nir_intrinsic_load_output
:
305 case nir_intrinsic_load_per_vertex_output
: {
306 src_reg indirect_offset
= get_indirect_offset(instr
);
307 unsigned imm_offset
= instr
->const_index
[0];
309 dst_reg dst
= get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_D
);
310 dst
.writemask
= brw_writemask_for_size(instr
->num_components
);
312 emit_output_urb_read(dst
, imm_offset
, nir_intrinsic_component(instr
),
316 case nir_intrinsic_store_output
:
317 case nir_intrinsic_store_per_vertex_output
: {
318 src_reg value
= get_nir_src(instr
->src
[0]);
319 unsigned mask
= instr
->const_index
[1];
320 unsigned swiz
= BRW_SWIZZLE_XYZW
;
322 src_reg indirect_offset
= get_indirect_offset(instr
);
323 unsigned imm_offset
= instr
->const_index
[0];
325 unsigned first_component
= nir_intrinsic_component(instr
);
326 if (first_component
) {
327 if (nir_src_bit_size(instr
->src
[0]) == 64)
328 first_component
/= 2;
329 assert(swiz
== BRW_SWIZZLE_XYZW
);
330 swiz
= BRW_SWZ_COMP_OUTPUT(first_component
);
331 mask
= mask
<< first_component
;
334 if (nir_src_bit_size(instr
->src
[0]) == 64) {
335 /* For 64-bit data we need to shuffle the data before we write and
336 * emit two messages. Also, since each channel is twice as large we
337 * need to fix the writemask in each 32-bit message to account for it.
339 value
= swizzle(retype(value
, BRW_REGISTER_TYPE_DF
), swiz
);
340 dst_reg shuffled
= dst_reg(this, glsl_type::dvec4_type
);
341 shuffle_64bit_data(shuffled
, value
, true);
342 src_reg shuffled_float
= src_reg(retype(shuffled
, BRW_REGISTER_TYPE_F
));
344 for (int n
= 0; n
< 2; n
++) {
345 unsigned fixed_mask
= 0;
346 if (mask
& WRITEMASK_X
)
347 fixed_mask
|= WRITEMASK_XY
;
348 if (mask
& WRITEMASK_Y
)
349 fixed_mask
|= WRITEMASK_ZW
;
350 emit_urb_write(shuffled_float
, fixed_mask
,
351 imm_offset
, indirect_offset
);
353 shuffled_float
= byte_offset(shuffled_float
, REG_SIZE
);
358 emit_urb_write(swizzle(value
, swiz
), mask
,
359 imm_offset
, indirect_offset
);
364 case nir_intrinsic_barrier
: {
365 dst_reg header
= dst_reg(this, glsl_type::uvec4_type
);
366 emit(TCS_OPCODE_CREATE_BARRIER_HEADER
, header
);
367 emit(SHADER_OPCODE_BARRIER
, dst_null_ud(), src_reg(header
));
372 vec4_visitor::nir_emit_intrinsic(instr
);
377 extern "C" const unsigned *
378 brw_compile_tcs(const struct brw_compiler
*compiler
,
381 const struct brw_tcs_prog_key
*key
,
382 struct brw_tcs_prog_data
*prog_data
,
383 const nir_shader
*src_shader
,
384 int shader_time_index
,
385 unsigned *final_assembly_size
,
388 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
389 struct brw_vue_prog_data
*vue_prog_data
= &prog_data
->base
;
390 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_CTRL
];
392 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
393 nir
->info
.outputs_written
= key
->outputs_written
;
394 nir
->info
.patch_outputs_written
= key
->patch_outputs_written
;
396 struct brw_vue_map input_vue_map
;
397 brw_compute_vue_map(devinfo
, &input_vue_map
, nir
->info
.inputs_read
,
398 nir
->info
.separate_shader
);
399 brw_compute_tess_vue_map(&vue_prog_data
->vue_map
,
400 nir
->info
.outputs_written
,
401 nir
->info
.patch_outputs_written
);
403 nir
= brw_nir_apply_sampler_key(nir
, compiler
, &key
->tex
, is_scalar
);
404 brw_nir_lower_vue_inputs(nir
, &input_vue_map
);
405 brw_nir_lower_tcs_outputs(nir
, &vue_prog_data
->vue_map
,
406 key
->tes_primitive_mode
);
407 if (key
->quads_workaround
)
408 brw_nir_apply_tcs_quads_workaround(nir
);
410 nir
= brw_postprocess_nir(nir
, compiler
, is_scalar
);
413 prog_data
->instances
= DIV_ROUND_UP(nir
->info
.tess
.tcs_vertices_out
, 8);
415 prog_data
->instances
= DIV_ROUND_UP(nir
->info
.tess
.tcs_vertices_out
, 2);
417 /* Compute URB entry size. The maximum allowed URB entry size is 32k.
418 * That divides up as follows:
420 * 32 bytes for the patch header (tessellation factors)
421 * 480 bytes for per-patch varyings (a varying component is 4 bytes and
422 * gl_MaxTessPatchComponents = 120)
423 * 16384 bytes for per-vertex varyings (a varying component is 4 bytes,
424 * gl_MaxPatchVertices = 32 and
425 * gl_MaxTessControlOutputComponents = 128)
427 * 15808 bytes left for varying packing overhead
429 const int num_per_patch_slots
= vue_prog_data
->vue_map
.num_per_patch_slots
;
430 const int num_per_vertex_slots
= vue_prog_data
->vue_map
.num_per_vertex_slots
;
431 unsigned output_size_bytes
= 0;
432 /* Note that the patch header is counted in num_per_patch_slots. */
433 output_size_bytes
+= num_per_patch_slots
* 16;
434 output_size_bytes
+= nir
->info
.tess
.tcs_vertices_out
*
435 num_per_vertex_slots
* 16;
437 assert(output_size_bytes
>= 1);
438 if (output_size_bytes
> GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES
)
441 /* URB entry sizes are stored as a multiple of 64 bytes. */
442 vue_prog_data
->urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
444 /* HS does not use the usual payload pushing from URB to GRFs,
445 * because we don't have enough registers for a full-size payload, and
446 * the hardware is broken on Haswell anyway.
448 vue_prog_data
->urb_read_length
= 0;
450 if (unlikely(INTEL_DEBUG
& DEBUG_TCS
)) {
451 fprintf(stderr
, "TCS Input ");
452 brw_print_vue_map(stderr
, &input_vue_map
);
453 fprintf(stderr
, "TCS Output ");
454 brw_print_vue_map(stderr
, &vue_prog_data
->vue_map
);
458 fs_visitor
v(compiler
, log_data
, mem_ctx
, (void *) key
,
459 &prog_data
->base
.base
, NULL
, nir
, 8,
460 shader_time_index
, &input_vue_map
);
461 if (!v
.run_tcs_single_patch()) {
463 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
467 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
468 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
470 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
471 &prog_data
->base
.base
, v
.promoted_constants
, false,
472 MESA_SHADER_TESS_CTRL
);
473 if (unlikely(INTEL_DEBUG
& DEBUG_TCS
)) {
474 g
.enable_debug(ralloc_asprintf(mem_ctx
,
475 "%s tessellation control shader %s",
476 nir
->info
.label
? nir
->info
.label
481 g
.generate_code(v
.cfg
, 8);
483 return g
.get_assembly(final_assembly_size
);
485 vec4_tcs_visitor
v(compiler
, log_data
, key
, prog_data
,
486 nir
, mem_ctx
, shader_time_index
, &input_vue_map
);
489 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
493 if (unlikely(INTEL_DEBUG
& DEBUG_TCS
))
494 v
.dump_instructions();
497 return brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
498 &prog_data
->base
, v
.cfg
,
499 final_assembly_size
);
504 } /* namespace brw */