2 * Copyright © 2012 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "util/ralloc.h"
31 test_compact_instruction(struct brw_codegen
*p
, brw_inst src
)
34 memset(&dst
, 0xd0, sizeof(dst
));
36 if (brw_try_compact_instruction(p
->devinfo
, &dst
, &src
)) {
39 brw_uncompact_instruction(p
->devinfo
, &uncompacted
, &dst
);
40 if (memcmp(&uncompacted
, &src
, sizeof(src
))) {
41 brw_debug_compact_uncompact(p
->devinfo
, &src
, &uncompacted
);
45 brw_compact_inst unchanged
;
46 memset(&unchanged
, 0xd0, sizeof(unchanged
));
47 /* It's not supposed to change dst unless it compacted. */
48 if (memcmp(&unchanged
, &dst
, sizeof(dst
))) {
49 fprintf(stderr
, "Failed to compact, but dst changed\n");
50 fprintf(stderr
, " Instruction: ");
51 brw_disassemble_inst(stderr
, p
->devinfo
, &src
, false);
60 * When doing fuzz testing, pad bits won't round-trip.
62 * This sort of a superset of skip_bit, which is testing for changing bits that
63 * aren't worth testing for fuzzing. We also just want to clear bits that
64 * become meaningless once fuzzing twiddles a related bit.
67 clear_pad_bits(const struct gen_device_info
*devinfo
, brw_inst
*inst
)
69 if (brw_inst_opcode(devinfo
, inst
) != BRW_OPCODE_SEND
&&
70 brw_inst_opcode(devinfo
, inst
) != BRW_OPCODE_SENDC
&&
71 brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
72 brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
) {
73 brw_inst_set_bits(inst
, 127, 111, 0);
76 if (devinfo
->gen
== 8 && !devinfo
->is_cherryview
&&
77 is_3src(devinfo
, (opcode
)brw_inst_opcode(devinfo
, inst
))) {
78 brw_inst_set_bits(inst
, 105, 105, 0);
79 brw_inst_set_bits(inst
, 84, 84, 0);
80 brw_inst_set_bits(inst
, 36, 35, 0);
85 skip_bit(const struct gen_device_info
*devinfo
, brw_inst
*src
, int bit
)
91 /* The compact bit -- uncompacted can't have it set. */
95 if (is_3src(devinfo
, (opcode
)brw_inst_opcode(devinfo
, src
))) {
96 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
100 if (bit
>= 126 && bit
<= 127)
109 if (bit
>= 35 && bit
<= 36)
116 if (devinfo
->gen
>= 8) {
123 if (devinfo
->gen
< 7 && bit
== 90)
126 if (bit
>= 91 && bit
<= 95)
131 /* sometimes these are pad bits. */
132 if (brw_inst_opcode(devinfo
, src
) != BRW_OPCODE_SEND
&&
133 brw_inst_opcode(devinfo
, src
) != BRW_OPCODE_SENDC
&&
134 brw_inst_src0_reg_file(devinfo
, src
) != BRW_IMMEDIATE_VALUE
&&
135 brw_inst_src1_reg_file(devinfo
, src
) != BRW_IMMEDIATE_VALUE
&&
144 test_fuzz_compact_instruction(struct brw_codegen
*p
, brw_inst src
)
146 for (int bit0
= 0; bit0
< 128; bit0
++) {
147 if (skip_bit(p
->devinfo
, &src
, bit0
))
150 for (int bit1
= 0; bit1
< 128; bit1
++) {
151 brw_inst instr
= src
;
152 uint64_t *bits
= instr
.data
;
154 if (skip_bit(p
->devinfo
, &src
, bit1
))
157 bits
[bit0
/ 64] ^= (1ull << (bit0
& 63));
158 bits
[bit1
/ 64] ^= (1ull << (bit1
& 63));
160 clear_pad_bits(p
->devinfo
, &instr
);
162 if (!test_compact_instruction(p
, instr
)) {
163 printf(" twiddled bits for fuzzing %d, %d\n", bit0
, bit1
);
173 gen_ADD_GRF_GRF_GRF(struct brw_codegen
*p
)
175 struct brw_reg g0
= brw_vec8_grf(0, 0);
176 struct brw_reg g2
= brw_vec8_grf(2, 0);
177 struct brw_reg g4
= brw_vec8_grf(4, 0);
179 brw_ADD(p
, g0
, g2
, g4
);
183 gen_ADD_GRF_GRF_IMM(struct brw_codegen
*p
)
185 struct brw_reg g0
= brw_vec8_grf(0, 0);
186 struct brw_reg g2
= brw_vec8_grf(2, 0);
188 brw_ADD(p
, g0
, g2
, brw_imm_f(1.0));
192 gen_ADD_GRF_GRF_IMM_d(struct brw_codegen
*p
)
194 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D
);
195 struct brw_reg g2
= retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_D
);
197 brw_ADD(p
, g0
, g2
, brw_imm_d(1));
201 gen_MOV_GRF_GRF(struct brw_codegen
*p
)
203 struct brw_reg g0
= brw_vec8_grf(0, 0);
204 struct brw_reg g2
= brw_vec8_grf(2, 0);
210 gen_ADD_MRF_GRF_GRF(struct brw_codegen
*p
)
212 struct brw_reg m6
= brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
, 6, 0);
213 struct brw_reg g2
= brw_vec8_grf(2, 0);
214 struct brw_reg g4
= brw_vec8_grf(4, 0);
216 brw_ADD(p
, m6
, g2
, g4
);
220 gen_ADD_vec1_GRF_GRF_GRF(struct brw_codegen
*p
)
222 struct brw_reg g0
= brw_vec1_grf(0, 0);
223 struct brw_reg g2
= brw_vec1_grf(2, 0);
224 struct brw_reg g4
= brw_vec1_grf(4, 0);
226 brw_ADD(p
, g0
, g2
, g4
);
230 gen_PLN_MRF_GRF_GRF(struct brw_codegen
*p
)
232 struct brw_reg m6
= brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
, 6, 0);
233 struct brw_reg interp
= brw_vec1_grf(2, 0);
234 struct brw_reg g4
= brw_vec8_grf(4, 0);
236 brw_PLN(p
, m6
, interp
, g4
);
240 gen_f0_0_MOV_GRF_GRF(struct brw_codegen
*p
)
242 struct brw_reg g0
= brw_vec8_grf(0, 0);
243 struct brw_reg g2
= brw_vec8_grf(2, 0);
245 brw_push_insn_state(p
);
246 brw_set_default_predicate_control(p
, true);
248 brw_pop_insn_state(p
);
251 /* The handling of f0.1 vs f0.0 changes between gen6 and gen7. Explicitly test
252 * it, so that we run the fuzzing can run over all the other bits that might
256 gen_f0_1_MOV_GRF_GRF(struct brw_codegen
*p
)
258 struct brw_reg g0
= brw_vec8_grf(0, 0);
259 struct brw_reg g2
= brw_vec8_grf(2, 0);
261 brw_push_insn_state(p
);
262 brw_set_default_predicate_control(p
, true);
263 brw_inst
*mov
= brw_MOV(p
, g0
, g2
);
264 brw_inst_set_flag_subreg_nr(p
->devinfo
, mov
, 1);
265 brw_pop_insn_state(p
);
269 void (*func
)(struct brw_codegen
*p
);
272 { gen_ADD_GRF_GRF_GRF
},
273 { gen_ADD_GRF_GRF_IMM
},
274 { gen_ADD_GRF_GRF_IMM_d
},
275 { gen_ADD_MRF_GRF_GRF
},
276 { gen_ADD_vec1_GRF_GRF_GRF
},
277 { gen_PLN_MRF_GRF_GRF
},
278 { gen_f0_0_MOV_GRF_GRF
},
279 { gen_f0_1_MOV_GRF_GRF
},
283 run_tests(const struct gen_device_info
*devinfo
)
285 brw_init_compaction_tables(devinfo
);
288 for (unsigned i
= 0; i
< ARRAY_SIZE(tests
); i
++) {
289 for (int align_16
= 0; align_16
<= 1; align_16
++) {
290 struct brw_codegen
*p
= rzalloc(NULL
, struct brw_codegen
);
291 brw_init_codegen(devinfo
, p
, p
);
293 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
295 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
297 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
300 assert(p
->nr_insn
== 1);
302 if (!test_compact_instruction(p
, p
->store
[0])) {
307 if (!test_fuzz_compact_instruction(p
, p
->store
[0])) {
320 main(int argc
, char **argv
)
322 struct gen_device_info
*devinfo
= (struct gen_device_info
*)calloc(1, sizeof(*devinfo
));
325 for (devinfo
->gen
= 5; devinfo
->gen
<= 9; devinfo
->gen
++) {
326 fail
|= run_tests(devinfo
);