2 * Copyright © 2012 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "util/ralloc.h"
31 test_compact_instruction(struct brw_codegen
*p
, brw_inst src
)
34 memset(&dst
, 0xd0, sizeof(dst
));
36 if (brw_try_compact_instruction(p
->devinfo
, &dst
, &src
)) {
39 brw_uncompact_instruction(p
->devinfo
, &uncompacted
, &dst
);
40 if (memcmp(&uncompacted
, &src
, sizeof(src
))) {
41 brw_debug_compact_uncompact(p
->devinfo
, &src
, &uncompacted
);
45 brw_compact_inst unchanged
;
46 memset(&unchanged
, 0xd0, sizeof(unchanged
));
47 /* It's not supposed to change dst unless it compacted. */
48 if (memcmp(&unchanged
, &dst
, sizeof(dst
))) {
49 fprintf(stderr
, "Failed to compact, but dst changed\n");
50 fprintf(stderr
, " Instruction: ");
51 brw_disassemble_inst(stderr
, p
->devinfo
, &src
, false);
60 * When doing fuzz testing, pad bits won't round-trip.
62 * This sort of a superset of skip_bit, which is testing for changing bits that
63 * aren't worth testing for fuzzing. We also just want to clear bits that
64 * become meaningless once fuzzing twiddles a related bit.
67 clear_pad_bits(const struct gen_device_info
*devinfo
, brw_inst
*inst
)
69 if (brw_inst_opcode(devinfo
, inst
) != BRW_OPCODE_SEND
&&
70 brw_inst_opcode(devinfo
, inst
) != BRW_OPCODE_SENDC
&&
71 brw_inst_opcode(devinfo
, inst
) != BRW_OPCODE_BREAK
&&
72 brw_inst_opcode(devinfo
, inst
) != BRW_OPCODE_CONTINUE
&&
73 brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
74 brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
) {
75 brw_inst_set_bits(inst
, 127, 111, 0);
80 skip_bit(const struct gen_device_info
*devinfo
, brw_inst
*src
, int bit
)
86 /* The compact bit -- uncompacted can't have it set. */
95 if (bit
>= 90 && bit
<= 95)
98 /* sometimes these are pad bits. */
99 if (brw_inst_opcode(devinfo
, src
) != BRW_OPCODE_SEND
&&
100 brw_inst_opcode(devinfo
, src
) != BRW_OPCODE_SENDC
&&
101 brw_inst_opcode(devinfo
, src
) != BRW_OPCODE_BREAK
&&
102 brw_inst_opcode(devinfo
, src
) != BRW_OPCODE_CONTINUE
&&
103 brw_inst_src0_reg_file(devinfo
, src
) != BRW_IMMEDIATE_VALUE
&&
104 brw_inst_src1_reg_file(devinfo
, src
) != BRW_IMMEDIATE_VALUE
&&
113 test_fuzz_compact_instruction(struct brw_codegen
*p
, brw_inst src
)
115 for (int bit0
= 0; bit0
< 128; bit0
++) {
116 if (skip_bit(p
->devinfo
, &src
, bit0
))
119 for (int bit1
= 0; bit1
< 128; bit1
++) {
120 brw_inst instr
= src
;
121 uint32_t *bits
= (uint32_t *)&instr
;
123 if (skip_bit(p
->devinfo
, &src
, bit1
))
126 bits
[bit0
/ 32] ^= (1 << (bit0
& 31));
127 bits
[bit1
/ 32] ^= (1 << (bit1
& 31));
129 clear_pad_bits(p
->devinfo
, &instr
);
131 if (!test_compact_instruction(p
, instr
)) {
132 printf(" twiddled bits for fuzzing %d, %d\n", bit0
, bit1
);
142 gen_ADD_GRF_GRF_GRF(struct brw_codegen
*p
)
144 struct brw_reg g0
= brw_vec8_grf(0, 0);
145 struct brw_reg g2
= brw_vec8_grf(2, 0);
146 struct brw_reg g4
= brw_vec8_grf(4, 0);
148 brw_ADD(p
, g0
, g2
, g4
);
152 gen_ADD_GRF_GRF_IMM(struct brw_codegen
*p
)
154 struct brw_reg g0
= brw_vec8_grf(0, 0);
155 struct brw_reg g2
= brw_vec8_grf(2, 0);
157 brw_ADD(p
, g0
, g2
, brw_imm_f(1.0));
161 gen_ADD_GRF_GRF_IMM_d(struct brw_codegen
*p
)
163 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D
);
164 struct brw_reg g2
= retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_D
);
166 brw_ADD(p
, g0
, g2
, brw_imm_d(1));
170 gen_MOV_GRF_GRF(struct brw_codegen
*p
)
172 struct brw_reg g0
= brw_vec8_grf(0, 0);
173 struct brw_reg g2
= brw_vec8_grf(2, 0);
179 gen_ADD_MRF_GRF_GRF(struct brw_codegen
*p
)
181 struct brw_reg m6
= brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
, 6, 0);
182 struct brw_reg g2
= brw_vec8_grf(2, 0);
183 struct brw_reg g4
= brw_vec8_grf(4, 0);
185 brw_ADD(p
, m6
, g2
, g4
);
189 gen_ADD_vec1_GRF_GRF_GRF(struct brw_codegen
*p
)
191 struct brw_reg g0
= brw_vec1_grf(0, 0);
192 struct brw_reg g2
= brw_vec1_grf(2, 0);
193 struct brw_reg g4
= brw_vec1_grf(4, 0);
195 brw_ADD(p
, g0
, g2
, g4
);
199 gen_PLN_MRF_GRF_GRF(struct brw_codegen
*p
)
201 struct brw_reg m6
= brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
, 6, 0);
202 struct brw_reg interp
= brw_vec1_grf(2, 0);
203 struct brw_reg g4
= brw_vec8_grf(4, 0);
205 brw_PLN(p
, m6
, interp
, g4
);
209 gen_f0_0_MOV_GRF_GRF(struct brw_codegen
*p
)
211 struct brw_reg g0
= brw_vec8_grf(0, 0);
212 struct brw_reg g2
= brw_vec8_grf(2, 0);
214 brw_push_insn_state(p
);
215 brw_set_default_predicate_control(p
, true);
217 brw_pop_insn_state(p
);
220 /* The handling of f0.1 vs f0.0 changes between gen6 and gen7. Explicitly test
221 * it, so that we run the fuzzing can run over all the other bits that might
225 gen_f0_1_MOV_GRF_GRF(struct brw_codegen
*p
)
227 struct brw_reg g0
= brw_vec8_grf(0, 0);
228 struct brw_reg g2
= brw_vec8_grf(2, 0);
230 brw_push_insn_state(p
);
231 brw_set_default_predicate_control(p
, true);
232 brw_inst
*mov
= brw_MOV(p
, g0
, g2
);
233 brw_inst_set_flag_subreg_nr(p
->devinfo
, mov
, 1);
234 brw_pop_insn_state(p
);
238 void (*func
)(struct brw_codegen
*p
);
241 { gen_ADD_GRF_GRF_GRF
},
242 { gen_ADD_GRF_GRF_IMM
},
243 { gen_ADD_GRF_GRF_IMM_d
},
244 { gen_ADD_MRF_GRF_GRF
},
245 { gen_ADD_vec1_GRF_GRF_GRF
},
246 { gen_PLN_MRF_GRF_GRF
},
247 { gen_f0_0_MOV_GRF_GRF
},
248 { gen_f0_1_MOV_GRF_GRF
},
252 run_tests(const struct gen_device_info
*devinfo
)
254 brw_init_compaction_tables(devinfo
);
257 for (int i
= 0; i
< ARRAY_SIZE(tests
); i
++) {
258 for (int align_16
= 0; align_16
<= 1; align_16
++) {
259 struct brw_codegen
*p
= rzalloc(NULL
, struct brw_codegen
);
260 brw_init_codegen(devinfo
, p
, p
);
262 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
264 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
266 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
269 assert(p
->nr_insn
== 1);
271 if (!test_compact_instruction(p
, p
->store
[0])) {
276 if (!test_fuzz_compact_instruction(p
, p
->store
[0])) {
289 main(int argc
, char **argv
)
291 struct gen_device_info
*devinfo
= (struct gen_device_info
*)calloc(1, sizeof(*devinfo
));
295 for (devinfo
->gen
= 6; devinfo
->gen
<= 7; devinfo
->gen
++) {
296 fail
|= run_tests(devinfo
);