src/intel/compiler/test_eu_validate.cpp

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <gtest/gtest.h>
  25 #include "brw_eu.h"
  26 #include "util/ralloc.h"
  27
  28 enum subgen {
  29    IS_G45 = 1,
  30    IS_BYT,
  31    IS_HSW,
  32    IS_CHV,
  33    IS_BXT,
  34    IS_KBL,
  35 };
  36
  37 static const struct gen_info {
  38    const char *name;
  39    int gen;
  40    enum subgen subgen;
  41 } gens[] = {
  42    { "brw", 4 },
  43    { "g45", 4, IS_G45 },
  44    { "ilk", 5 },
  45    { "snb", 6 },
  46    { "ivb", 7 },
  47    { "byt", 7, IS_BYT },
  48    { "hsw", 7, IS_HSW },
  49    { "bdw", 8 },
  50    { "chv", 8, IS_CHV },
  51    { "skl", 9 },
  52    { "bxt", 9, IS_BXT },
  53    { "kbl", 9, IS_KBL },
  54 };
  55
  56 class validation_test: public ::testing::TestWithParam<struct gen_info> {
  57    virtual void SetUp();
  58
  59 public:
  60    validation_test();
  61    virtual ~validation_test();
  62
  63    struct brw_codegen *p;
  64    struct gen_device_info devinfo;
  65 };
  66
  67 validation_test::validation_test()
  68 {
  69    p = rzalloc(NULL, struct brw_codegen);
  70    memset(&devinfo, 0, sizeof(devinfo));
  71 }
  72
  73 validation_test::~validation_test()
  74 {
  75    ralloc_free(p);
  76 }
  77
  78 void validation_test::SetUp()
  79 {
  80    struct gen_info info = GetParam();
  81
  82    devinfo.gen           = info.gen;
  83    devinfo.is_g4x        = info.subgen == IS_G45;
  84    devinfo.is_baytrail   = info.subgen == IS_BYT;
  85    devinfo.is_haswell    = info.subgen == IS_HSW;
  86    devinfo.is_cherryview = info.subgen == IS_CHV;
  87    devinfo.is_broxton    = info.subgen == IS_BXT;
  88    devinfo.is_kabylake   = info.subgen == IS_KBL;
  89
  90    brw_init_codegen(&devinfo, p, p);
  91 }
  92
  93 struct gen_name {
  94    template <class ParamType>
  95    std::string
  96    operator()(const ::testing::TestParamInfo<ParamType>& info) const {
  97       return info.param.name;
  98    }
  99 };
 100
 101 INSTANTIATE_TEST_CASE_P(eu_assembly, validation_test,
 102                         ::testing::ValuesIn(gens),
 103                         gen_name());
 104
 105 static bool
 106 validate(struct brw_codegen *p)
 107 {
 108    const bool print = getenv("TEST_DEBUG");
 109    struct annotation_info annotation;
 110    memset(&annotation, 0, sizeof(annotation));
 111
 112    if (print) {
 113       annotation.mem_ctx = ralloc_context(NULL);
 114       annotation.ann_count = 1;
 115       annotation.ann_size = 2;
 116       annotation.ann = rzalloc_array(annotation.mem_ctx, struct annotation,
 117                                      annotation.ann_size);
 118       annotation.ann[annotation.ann_count].offset = p->next_insn_offset;
 119    }
 120
 121    bool ret = brw_validate_instructions(p->devinfo, p->store, 0,
 122                                         p->next_insn_offset, &annotation);
 123
 124    if (print) {
 125       dump_assembly(p->store, annotation.ann_count, annotation.ann, p->devinfo);
 126       ralloc_free(annotation.mem_ctx);
 127    }
 128
 129    return ret;
 130 }
 131
 132 #define last_inst    (&p->store[p->nr_insn - 1])
 133 #define g0           brw_vec8_grf(0, 0)
 134 #define null         brw_null_reg()
 135 #define zero         brw_imm_f(0.0f)
 136
 137 static void
 138 clear_instructions(struct brw_codegen *p)
 139 {
 140    p->next_insn_offset = 0;
 141    p->nr_insn = 0;
 142 }
 143
 144 TEST_P(validation_test, sanity)
 145 {
 146    brw_ADD(p, g0, g0, g0);
 147
 148    EXPECT_TRUE(validate(p));
 149 }
 150
 151 TEST_P(validation_test, src0_null_reg)
 152 {
 153    brw_MOV(p, g0, null);
 154
 155    EXPECT_FALSE(validate(p));
 156 }
 157
 158 TEST_P(validation_test, src1_null_reg)
 159 {
 160    brw_ADD(p, g0, g0, null);
 161
 162    EXPECT_FALSE(validate(p));
 163 }
 164
 165 TEST_P(validation_test, math_src0_null_reg)
 166 {
 167    if (devinfo.gen >= 6) {
 168       gen6_math(p, g0, BRW_MATH_FUNCTION_SIN, null, null);
 169    } else {
 170       gen4_math(p, g0, BRW_MATH_FUNCTION_SIN, 0, null, BRW_MATH_PRECISION_FULL);
 171    }
 172
 173    EXPECT_FALSE(validate(p));
 174 }
 175
 176 TEST_P(validation_test, math_src1_null_reg)
 177 {
 178    if (devinfo.gen >= 6) {
 179       gen6_math(p, g0, BRW_MATH_FUNCTION_POW, g0, null);
 180       EXPECT_FALSE(validate(p));
 181    } else {
 182       /* Math instructions on Gen4/5 are actually SEND messages with payloads.
 183        * src1 is an immediate message descriptor set by gen4_math.
 184        */
 185    }
 186 }
 187
 188 TEST_P(validation_test, opcode46)
 189 {
 190    /* opcode 46 is "push" on Gen 4 and 5
 191     *              "fork" on Gen 6
 192     *              reserved on Gen 7
 193     *              "goto" on Gen8+
 194     */
 195    brw_next_insn(p, 46);
 196
 197    if (devinfo.gen == 7) {
 198       EXPECT_FALSE(validate(p));
 199    } else {
 200       EXPECT_TRUE(validate(p));
 201    }
 202 }
 203
 204 /* When the Execution Data Type is wider than the destination data type, the
 205  * destination must [...] specify a HorzStride equal to the ratio in sizes of
 206  * the two data types.
 207  */
 208 TEST_P(validation_test, dest_stride_must_be_equal_to_the_ratio_of_exec_size_to_dest_size)
 209 {
 210    brw_ADD(p, g0, g0, g0);
 211    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 212    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
 213    brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
 214
 215    EXPECT_FALSE(validate(p));
 216
 217    clear_instructions(p);
 218
 219    brw_ADD(p, g0, g0, g0);
 220    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 221    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 222    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
 223    brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
 224
 225    EXPECT_TRUE(validate(p));
 226 }
 227
 228 /* When the Execution Data Type is wider than the destination data type, the
 229  * destination must be aligned as required by the wider execution data type
 230  * [...]
 231  */
 232 TEST_P(validation_test, dst_subreg_must_be_aligned_to_exec_type_size)
 233 {
 234    brw_ADD(p, g0, g0, g0);
 235    brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 2);
 236    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 237    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 238    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
 239    brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
 240
 241    EXPECT_FALSE(validate(p));
 242
 243    clear_instructions(p);
 244
 245    brw_ADD(p, g0, g0, g0);
 246    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4);
 247    brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 8);
 248    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 249    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 250    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
 251    brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
 252    brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
 253    brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
 254    brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
 255    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
 256    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
 257    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
 258
 259    EXPECT_TRUE(validate(p));
 260 }
 261
 262 /* ExecSize must be greater than or equal to Width. */
 263 TEST_P(validation_test, exec_size_less_than_width)
 264 {
 265    brw_ADD(p, g0, g0, g0);
 266    brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_16);
 267
 268    EXPECT_FALSE(validate(p));
 269
 270    clear_instructions(p);
 271
 272    brw_ADD(p, g0, g0, g0);
 273    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_16);
 274
 275    EXPECT_FALSE(validate(p));
 276 }
 277
 278 /* If ExecSize = Width and HorzStride ≠ 0,
 279  * VertStride must be set to Width * HorzStride.
 280  */
 281 TEST_P(validation_test, vertical_stride_is_width_by_horizontal_stride)
 282 {
 283    brw_ADD(p, g0, g0, g0);
 284    brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
 285
 286    EXPECT_FALSE(validate(p));
 287
 288    clear_instructions(p);
 289
 290    brw_ADD(p, g0, g0, g0);
 291    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
 292
 293    EXPECT_FALSE(validate(p));
 294 }
 295
 296 /* If Width = 1, HorzStride must be 0 regardless of the values
 297  * of ExecSize and VertStride.
 298  */
 299 TEST_P(validation_test, horizontal_stride_must_be_0_if_width_is_1)
 300 {
 301    brw_ADD(p, g0, g0, g0);
 302    brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
 303    brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1);
 304    brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
 305
 306    EXPECT_FALSE(validate(p));
 307
 308    clear_instructions(p);
 309
 310    brw_ADD(p, g0, g0, g0);
 311    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
 312    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_1);
 313    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
 314
 315    EXPECT_FALSE(validate(p));
 316 }
 317
 318 /* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
 319 TEST_P(validation_test, scalar_region_must_be_0_1_0)
 320 {
 321    struct brw_reg g0_0 = brw_vec1_grf(0, 0);
 322
 323    brw_ADD(p, g0, g0, g0_0);
 324    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_1);
 325    brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_1);
 326    brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1);
 327    brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
 328
 329    EXPECT_FALSE(validate(p));
 330
 331    clear_instructions(p);
 332
 333    brw_ADD(p, g0, g0_0, g0);
 334    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_1);
 335    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_1);
 336    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_1);
 337    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
 338
 339    EXPECT_FALSE(validate(p));
 340 }
 341
 342 /* If VertStride = HorzStride = 0, Width must be 1 regardless of the value
 343  * of ExecSize.
 344  */
 345 TEST_P(validation_test, zero_stride_implies_0_1_0)
 346 {
 347    brw_ADD(p, g0, g0, g0);
 348    brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
 349    brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_2);
 350    brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
 351
 352    EXPECT_FALSE(validate(p));
 353
 354    clear_instructions(p);
 355
 356    brw_ADD(p, g0, g0, g0);
 357    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
 358    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_2);
 359    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
 360
 361    EXPECT_FALSE(validate(p));
 362 }
 363
 364 /* Dst.HorzStride must not be 0. */
 365 TEST_P(validation_test, dst_horizontal_stride_0)
 366 {
 367    brw_ADD(p, g0, g0, g0);
 368    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
 369
 370    EXPECT_FALSE(validate(p));
 371
 372    clear_instructions(p);
 373
 374    brw_set_default_access_mode(p, BRW_ALIGN_16);
 375
 376    brw_ADD(p, g0, g0, g0);
 377    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
 378
 379    EXPECT_FALSE(validate(p));
 380 }
 381
 382 /* VertStride must be used to cross GRF register boundaries. This rule implies
 383  * that elements within a 'Width' cannot cross GRF boundaries.
 384  */
 385 TEST_P(validation_test, must_not_cross_grf_boundary_in_a_width)
 386 {
 387    brw_ADD(p, g0, g0, g0);
 388    brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 4);
 389
 390    EXPECT_FALSE(validate(p));
 391
 392    clear_instructions(p);
 393
 394    brw_ADD(p, g0, g0, g0);
 395    brw_inst_set_src1_da1_subreg_nr(&devinfo, last_inst, 4);
 396
 397    EXPECT_FALSE(validate(p));
 398
 399    clear_instructions(p);
 400
 401    brw_ADD(p, g0, g0, g0);
 402    brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
 403    brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
 404    brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 405
 406    EXPECT_FALSE(validate(p));
 407
 408    clear_instructions(p);
 409
 410    brw_ADD(p, g0, g0, g0);
 411    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
 412    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
 413    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 414
 415    EXPECT_FALSE(validate(p));
 416 }
 417
 418 /* Destination Horizontal must be 1 in Align16 */
 419 TEST_P(validation_test, dst_hstride_on_align16_must_be_1)
 420 {
 421    brw_set_default_access_mode(p, BRW_ALIGN_16);
 422
 423    brw_ADD(p, g0, g0, g0);
 424    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 425
 426    EXPECT_FALSE(validate(p));
 427
 428    clear_instructions(p);
 429
 430    brw_ADD(p, g0, g0, g0);
 431    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
 432
 433    EXPECT_TRUE(validate(p));
 434 }
 435
 436 /* VertStride must be 0 or 4 in Align16 */
 437 TEST_P(validation_test, vstride_on_align16_must_be_0_or_4)
 438 {
 439    const struct {
 440       enum brw_vertical_stride vstride;
 441       bool expected_result;
 442    } vstride[] = {
 443       { BRW_VERTICAL_STRIDE_0, true },
 444       { BRW_VERTICAL_STRIDE_1, false },
 445       { BRW_VERTICAL_STRIDE_2, devinfo.is_haswell || devinfo.gen >= 8 },
 446       { BRW_VERTICAL_STRIDE_4, true },
 447       { BRW_VERTICAL_STRIDE_8, false },
 448       { BRW_VERTICAL_STRIDE_16, false },
 449       { BRW_VERTICAL_STRIDE_32, false },
 450       { BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, false },
 451    };
 452
 453    brw_set_default_access_mode(p, BRW_ALIGN_16);
 454
 455    for (unsigned i = 0; i < sizeof(vstride) / sizeof(vstride[0]); i++) {
 456       brw_ADD(p, g0, g0, g0);
 457       brw_inst_set_src0_vstride(&devinfo, last_inst, vstride[i].vstride);
 458
 459       EXPECT_EQ(vstride[i].expected_result, validate(p));
 460
 461       clear_instructions(p);
 462    }
 463
 464    for (unsigned i = 0; i < sizeof(vstride) / sizeof(vstride[0]); i++) {
 465       brw_ADD(p, g0, g0, g0);
 466       brw_inst_set_src1_vstride(&devinfo, last_inst, vstride[i].vstride);
 467
 468       EXPECT_EQ(vstride[i].expected_result, validate(p));
 469
 470       clear_instructions(p);
 471    }
 472 }
 473
 474 /* In Direct Addressing mode, a source cannot span more than 2 adjacent GRF
 475  * registers.
 476  */
 477 TEST_P(validation_test, source_cannot_span_more_than_2_registers)
 478 {
 479    brw_ADD(p, g0, g0, g0);
 480    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_32);
 481    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 482    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 483    brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 484    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
 485    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8);
 486    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 487
 488    EXPECT_FALSE(validate(p));
 489
 490    clear_instructions(p);
 491
 492    brw_ADD(p, g0, g0, g0);
 493    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
 494    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 495    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 496    brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 497    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
 498    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8);
 499    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 500    brw_inst_set_src1_da1_subreg_nr(&devinfo, last_inst, 2);
 501
 502    EXPECT_TRUE(validate(p));
 503
 504    clear_instructions(p);
 505
 506    brw_ADD(p, g0, g0, g0);
 507    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
 508
 509    EXPECT_TRUE(validate(p));
 510 }
 511
 512 /* A destination cannot span more than 2 adjacent GRF registers. */
 513 TEST_P(validation_test, destination_cannot_span_more_than_2_registers)
 514 {
 515    brw_ADD(p, g0, g0, g0);
 516    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_32);
 517    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 518    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 519    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 520    brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 521
 522    EXPECT_FALSE(validate(p));
 523
 524    clear_instructions(p);
 525
 526    brw_ADD(p, g0, g0, g0);
 527    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_8);
 528    brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 6);
 529    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_4);
 530    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 531    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 532    brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
 533    brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
 534    brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
 535    brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 536    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
 537    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
 538    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
 539
 540    EXPECT_TRUE(validate(p));
 541 }
 542
 543 TEST_P(validation_test, src_region_spans_two_regs_dst_region_spans_one)
 544 {
 545    /* Writes to dest are to the lower OWord */
 546    brw_ADD(p, g0, g0, g0);
 547    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 548    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 549    brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 550    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
 551    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
 552    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 553
 554    EXPECT_TRUE(validate(p));
 555
 556    clear_instructions(p);
 557
 558    /* Writes to dest are to the upper OWord */
 559    brw_ADD(p, g0, g0, g0);
 560    brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 16);
 561    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 562    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 563    brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 564    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
 565    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
 566    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 567
 568    EXPECT_TRUE(validate(p));
 569
 570    clear_instructions(p);
 571
 572    /* Writes to dest are evenly split between OWords */
 573    brw_ADD(p, g0, g0, g0);
 574    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
 575    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 576    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 577    brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 578    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
 579    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8);
 580    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 581
 582    EXPECT_TRUE(validate(p));
 583
 584    clear_instructions(p);
 585
 586    /* Writes to dest are uneven between OWords */
 587    brw_ADD(p, g0, g0, g0);
 588    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4);
 589    brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 10);
 590    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 591    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 592    brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
 593    brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
 594    brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
 595    brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 596    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
 597    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_2);
 598    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
 599
 600    if (devinfo.gen >= 9) {
 601       EXPECT_TRUE(validate(p));
 602    } else {
 603       EXPECT_FALSE(validate(p));
 604    }
 605 }
 606
 607 TEST_P(validation_test, dst_elements_must_be_evenly_split_between_registers)
 608 {
 609    brw_ADD(p, g0, g0, g0);
 610    brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 4);
 611
 612    if (devinfo.gen >= 9) {
 613       EXPECT_TRUE(validate(p));
 614    } else {
 615       EXPECT_FALSE(validate(p));
 616    }
 617
 618    clear_instructions(p);
 619
 620    brw_ADD(p, g0, g0, g0);
 621    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
 622
 623    EXPECT_TRUE(validate(p));
 624
 625    clear_instructions(p);
 626
 627    if (devinfo.gen >= 6) {
 628       gen6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null);
 629
 630       EXPECT_TRUE(validate(p));
 631
 632       clear_instructions(p);
 633
 634       gen6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null);
 635       brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 4);
 636
 637       EXPECT_FALSE(validate(p));
 638    }
 639 }
 640
 641 TEST_P(validation_test, two_src_two_dst_source_offsets_must_be_same)
 642 {
 643    brw_ADD(p, g0, g0, g0);
 644    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4);
 645    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_4);
 646    brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 16);
 647    brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_2);
 648    brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1);
 649    brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
 650    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
 651    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
 652    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
 653
 654    if (devinfo.gen <= 7) {
 655       EXPECT_FALSE(validate(p));
 656    } else {
 657       EXPECT_TRUE(validate(p));
 658    }
 659
 660    clear_instructions(p);
 661
 662    brw_ADD(p, g0, g0, g0);
 663    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4);
 664    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_4);
 665    brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
 666    brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1);
 667    brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
 668    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_8);
 669    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_2);
 670    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
 671
 672    EXPECT_TRUE(validate(p));
 673 }
 674
 675 #if 0
 676 TEST_P(validation_test, two_src_two_dst_each_dst_must_be_derived_from_one_src)
 677 {
 678    // mov (16) r10.0<2>:w r12.4<4;4,1>:w
 679
 680    brw_MOV(p, g0, g0);
 681    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
 682    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 683    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 684    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 685    brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 8);
 686    brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
 687    brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
 688    brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_4);
 689
 690    EXPECT_FALSE(validate(p));
 691
 692    clear_instructions(p);
 693
 694 #if 0
 695    brw_ADD(p, g0, g0, g0);
 696    brw_inst_set_src1_da1_subreg_nr(&devinfo, last_inst, 16);
 697    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
 698    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
 699    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
 700
 701    EXPECT_FALSE(validate(p));
 702    #endif
 703 }
 704 #endif
 705
 706 TEST_P(validation_test, one_src_two_dst)
 707 {
 708    struct brw_reg g0_0 = brw_vec1_grf(0, 0);
 709
 710    brw_ADD(p, g0, g0_0, g0_0);
 711    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
 712
 713    EXPECT_TRUE(validate(p));
 714
 715    clear_instructions(p);
 716
 717    brw_ADD(p, g0, g0, g0);
 718    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
 719    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
 720    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 721    brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 722
 723    EXPECT_TRUE(validate(p));
 724
 725    clear_instructions(p);
 726
 727    brw_ADD(p, g0, g0, g0);
 728    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
 729    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 730    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 731    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 732    brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 733    brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
 734    brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_1);
 735    brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
 736
 737    if (devinfo.gen >= 8) {
 738       EXPECT_TRUE(validate(p));
 739    } else {
 740       EXPECT_FALSE(validate(p));
 741    }
 742
 743    clear_instructions(p);
 744
 745    brw_ADD(p, g0, g0, g0);
 746    brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
 747    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 748    brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 749    brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 750    brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
 751    brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1);
 752    brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
 753    brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
 754
 755    if (devinfo.gen >= 8) {
 756       EXPECT_TRUE(validate(p));
 757    } else {
 758       EXPECT_FALSE(validate(p));
 759    }
 760 }
 761
 762 TEST_P(validation_test, packed_byte_destination)
 763 {
 764    static const struct {
 765       enum brw_reg_type dst_type;
 766       enum brw_reg_type src_type;
 767       bool neg, abs, sat;
 768       bool expected_result;
 769    } move[] = {
 770       { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_UB, 0, 0, 0, true },
 771       { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_B , 0, 0, 0, true },
 772       { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_B , 0, 0, 0, true },
 773       { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_UB, 0, 0, 0, true },
 774
 775       { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_UB, 1, 0, 0, false },
 776       { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_B , 1, 0, 0, false },
 777       { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_B , 1, 0, 0, false },
 778       { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_UB, 1, 0, 0, false },
 779
 780       { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_UB, 0, 1, 0, false },
 781       { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_B , 0, 1, 0, false },
 782       { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_B , 0, 1, 0, false },
 783       { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_UB, 0, 1, 0, false },
 784
 785       { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_UB, 0, 0, 1, false },
 786       { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_B , 0, 0, 1, false },
 787       { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_B , 0, 0, 1, false },
 788       { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_UB, 0, 0, 1, false },
 789
 790       { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_UW, 0, 0, 0, false },
 791       { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_W , 0, 0, 0, false },
 792       { BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_UD, 0, 0, 0, false },
 793       { BRW_REGISTER_TYPE_B , BRW_REGISTER_TYPE_D , 0, 0, 0, false },
 794    };
 795
 796    for (unsigned i = 0; i < sizeof(move) / sizeof(move[0]); i++) {
 797       brw_MOV(p, retype(g0, move[i].dst_type), retype(g0, move[i].src_type));
 798       brw_inst_set_src0_negate(&devinfo, last_inst, move[i].neg);
 799       brw_inst_set_src0_abs(&devinfo, last_inst, move[i].abs);
 800       brw_inst_set_saturate(&devinfo, last_inst, move[i].sat);
 801
 802       EXPECT_EQ(move[i].expected_result, validate(p));
 803
 804       clear_instructions(p);
 805    }
 806
 807    brw_SEL(p, retype(g0, BRW_REGISTER_TYPE_UB),
 808               retype(g0, BRW_REGISTER_TYPE_UB),
 809               retype(g0, BRW_REGISTER_TYPE_UB));
 810    brw_inst_set_pred_control(&devinfo, last_inst, BRW_PREDICATE_NORMAL);
 811
 812    EXPECT_FALSE(validate(p));
 813
 814    clear_instructions(p);
 815
 816    brw_SEL(p, retype(g0, BRW_REGISTER_TYPE_B),
 817               retype(g0, BRW_REGISTER_TYPE_B),
 818               retype(g0, BRW_REGISTER_TYPE_B));
 819    brw_inst_set_pred_control(&devinfo, last_inst, BRW_PREDICATE_NORMAL);
 820
 821    EXPECT_FALSE(validate(p));
 822 }
 823
 824 TEST_P(validation_test, byte_destination_relaxed_alignment)
 825 {
 826    brw_SEL(p, retype(g0, BRW_REGISTER_TYPE_B),
 827               retype(g0, BRW_REGISTER_TYPE_W),
 828               retype(g0, BRW_REGISTER_TYPE_W));
 829    brw_inst_set_pred_control(&devinfo, last_inst, BRW_PREDICATE_NORMAL);
 830    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 831
 832    EXPECT_TRUE(validate(p));
 833
 834    clear_instructions(p);
 835
 836    brw_SEL(p, retype(g0, BRW_REGISTER_TYPE_B),
 837               retype(g0, BRW_REGISTER_TYPE_W),
 838               retype(g0, BRW_REGISTER_TYPE_W));
 839    brw_inst_set_pred_control(&devinfo, last_inst, BRW_PREDICATE_NORMAL);
 840    brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
 841    brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 1);
 842
 843    if (devinfo.gen > 4 || devinfo.is_g4x) {
 844       EXPECT_TRUE(validate(p));
 845    } else {
 846       EXPECT_FALSE(validate(p));
 847    }
 848 }
 849
 850 TEST_P(validation_test, vector_immediate_destination_alignment)
 851 {
 852    static const struct {
 853       enum brw_reg_type dst_type;
 854       enum brw_reg_type src_type;
 855       unsigned subnr;
 856       unsigned exec_size;
 857       bool expected_result;
 858    } move[] = {
 859       { BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_VF,  0, BRW_EXECUTE_4, true  },
 860       { BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_VF, 16, BRW_EXECUTE_4, true  },
 861       { BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_VF,  1, BRW_EXECUTE_4, false },
 862
 863       { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_V,   0, BRW_EXECUTE_8, true  },
 864       { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_V,  16, BRW_EXECUTE_8, true  },
 865       { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_V,   1, BRW_EXECUTE_8, false },
 866
 867       { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_UV,  0, BRW_EXECUTE_8, true  },
 868       { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_UV, 16, BRW_EXECUTE_8, true  },
 869       { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_UV,  1, BRW_EXECUTE_8, false },
 870    };
 871
 872    for (unsigned i = 0; i < sizeof(move) / sizeof(move[0]); i++) {
 873       /* UV type is Gen6+ */
 874       if (devinfo.gen < 6 &&
 875           move[i].src_type == BRW_REGISTER_TYPE_UV)
 876          continue;
 877
 878       brw_MOV(p, retype(g0, move[i].dst_type), retype(zero, move[i].src_type));
 879       brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, move[i].subnr);
 880       brw_inst_set_exec_size(&devinfo, last_inst, move[i].exec_size);
 881
 882       EXPECT_EQ(move[i].expected_result, validate(p));
 883
 884       clear_instructions(p);
 885    }
 886 }
 887
 888 TEST_P(validation_test, vector_immediate_destination_stride)
 889 {
 890    static const struct {
 891       enum brw_reg_type dst_type;
 892       enum brw_reg_type src_type;
 893       unsigned stride;
 894       bool expected_result;
 895    } move[] = {
 896       { BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_VF, BRW_HORIZONTAL_STRIDE_1, true  },
 897       { BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_VF, BRW_HORIZONTAL_STRIDE_2, false },
 898       { BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_VF, BRW_HORIZONTAL_STRIDE_1, true  },
 899       { BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_VF, BRW_HORIZONTAL_STRIDE_2, false },
 900       { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_VF, BRW_HORIZONTAL_STRIDE_2, true  },
 901       { BRW_REGISTER_TYPE_B, BRW_REGISTER_TYPE_VF, BRW_HORIZONTAL_STRIDE_4, true  },
 902
 903       { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_V,  BRW_HORIZONTAL_STRIDE_1, true  },
 904       { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_V,  BRW_HORIZONTAL_STRIDE_2, false },
 905       { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_V,  BRW_HORIZONTAL_STRIDE_4, false },
 906       { BRW_REGISTER_TYPE_B, BRW_REGISTER_TYPE_V,  BRW_HORIZONTAL_STRIDE_2, true  },
 907
 908       { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_UV, BRW_HORIZONTAL_STRIDE_1, true  },
 909       { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_UV, BRW_HORIZONTAL_STRIDE_2, false },
 910       { BRW_REGISTER_TYPE_W, BRW_REGISTER_TYPE_UV, BRW_HORIZONTAL_STRIDE_4, false },
 911       { BRW_REGISTER_TYPE_B, BRW_REGISTER_TYPE_UV, BRW_HORIZONTAL_STRIDE_2, true  },
 912    };
 913
 914    for (unsigned i = 0; i < sizeof(move) / sizeof(move[0]); i++) {
 915       /* UV type is Gen6+ */
 916       if (devinfo.gen < 6 &&
 917           move[i].src_type == BRW_REGISTER_TYPE_UV)
 918          continue;
 919
 920       brw_MOV(p, retype(g0, move[i].dst_type), retype(zero, move[i].src_type));
 921       brw_inst_set_dst_hstride(&devinfo, last_inst, move[i].stride);
 922
 923       EXPECT_EQ(move[i].expected_result, validate(p));
 924
 925       clear_instructions(p);
 926    }
 927 }