2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "gen_device_info.h"
31 #include "compiler/shader_enums.h"
32 #include "intel/common/gen_gem.h"
33 #include "util/bitscan.h"
34 #include "util/macros.h"
36 #include "drm-uapi/i915_drm.h"
39 * Get the PCI ID for the device name.
41 * Returns -1 if the device is not known.
44 gen_device_name_to_pci_device_id(const char *name
)
71 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
72 if (!strcmp(name_map
[i
].name
, name
))
73 return name_map
[i
].pci_id
;
80 * Get the overridden PCI ID for the device. This is set with the
81 * INTEL_DEVID_OVERRIDE environment variable.
83 * Returns -1 if the override is not set.
86 get_pci_device_id_override(void)
88 if (geteuid() == getuid()) {
89 const char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
91 const int id
= gen_device_name_to_pci_device_id(devid_override
);
92 return id
>= 0 ? id
: strtol(devid_override
, NULL
, 0);
99 static const struct gen_device_info gen_device_info_i965
= {
101 .has_negative_rhw_bug
= true,
103 .num_subslices
= { 1, },
104 .num_eu_per_subslice
= 8,
105 .num_thread_per_eu
= 4,
106 .max_vs_threads
= 16,
108 .max_wm_threads
= 8 * 4,
112 .timestamp_frequency
= 12500000,
116 static const struct gen_device_info gen_device_info_g4x
= {
120 .has_surface_tile_offset
= true,
123 .num_subslices
= { 1, },
124 .num_eu_per_subslice
= 10,
125 .num_thread_per_eu
= 5,
126 .max_vs_threads
= 32,
128 .max_wm_threads
= 10 * 5,
132 .timestamp_frequency
= 12500000,
136 static const struct gen_device_info gen_device_info_ilk
= {
140 .has_surface_tile_offset
= true,
142 .num_subslices
= { 1, },
143 .num_eu_per_subslice
= 12,
144 .num_thread_per_eu
= 6,
145 .max_vs_threads
= 72,
146 .max_gs_threads
= 32,
147 .max_wm_threads
= 12 * 6,
151 .timestamp_frequency
= 12500000,
155 static const struct gen_device_info gen_device_info_snb_gt1
= {
158 .has_hiz_and_separate_stencil
= true,
161 .has_surface_tile_offset
= true,
162 .needs_unlit_centroid_workaround
= true,
164 .num_subslices
= { 1, },
165 .num_eu_per_subslice
= 6,
166 .num_thread_per_eu
= 6, /* Not confirmed */
167 .max_vs_threads
= 24,
168 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
169 .max_wm_threads
= 40,
173 [MESA_SHADER_VERTEX
] = 24,
176 [MESA_SHADER_VERTEX
] = 256,
177 [MESA_SHADER_GEOMETRY
] = 256,
180 .timestamp_frequency
= 12500000,
184 static const struct gen_device_info gen_device_info_snb_gt2
= {
187 .has_hiz_and_separate_stencil
= true,
190 .has_surface_tile_offset
= true,
191 .needs_unlit_centroid_workaround
= true,
193 .num_subslices
= { 1, },
194 .num_eu_per_subslice
= 12,
195 .num_thread_per_eu
= 6, /* Not confirmed */
196 .max_vs_threads
= 60,
197 .max_gs_threads
= 60,
198 .max_wm_threads
= 80,
202 [MESA_SHADER_VERTEX
] = 24,
205 [MESA_SHADER_VERTEX
] = 256,
206 [MESA_SHADER_GEOMETRY
] = 256,
209 .timestamp_frequency
= 12500000,
213 #define GEN7_FEATURES \
215 .has_hiz_and_separate_stencil = true, \
216 .must_use_separate_stencil = true, \
219 .has_64bit_types = true, \
220 .has_surface_tile_offset = true, \
221 .timestamp_frequency = 12500000
223 static const struct gen_device_info gen_device_info_ivb_gt1
= {
224 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
226 .num_subslices
= { 1, },
227 .num_eu_per_subslice
= 6,
228 .num_thread_per_eu
= 6,
230 .max_vs_threads
= 36,
231 .max_tcs_threads
= 36,
232 .max_tes_threads
= 36,
233 .max_gs_threads
= 36,
234 .max_wm_threads
= 48,
235 .max_cs_threads
= 36,
239 [MESA_SHADER_VERTEX
] = 32,
240 [MESA_SHADER_TESS_EVAL
] = 10,
243 [MESA_SHADER_VERTEX
] = 512,
244 [MESA_SHADER_TESS_CTRL
] = 32,
245 [MESA_SHADER_TESS_EVAL
] = 288,
246 [MESA_SHADER_GEOMETRY
] = 192,
252 static const struct gen_device_info gen_device_info_ivb_gt2
= {
253 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
255 .num_subslices
= { 1, },
256 .num_eu_per_subslice
= 12,
257 .num_thread_per_eu
= 8, /* Not sure why this isn't a multiple of
258 * @max_wm_threads ... */
260 .max_vs_threads
= 128,
261 .max_tcs_threads
= 128,
262 .max_tes_threads
= 128,
263 .max_gs_threads
= 128,
264 .max_wm_threads
= 172,
265 .max_cs_threads
= 64,
269 [MESA_SHADER_VERTEX
] = 32,
270 [MESA_SHADER_TESS_EVAL
] = 10,
273 [MESA_SHADER_VERTEX
] = 704,
274 [MESA_SHADER_TESS_CTRL
] = 64,
275 [MESA_SHADER_TESS_EVAL
] = 448,
276 [MESA_SHADER_GEOMETRY
] = 320,
282 static const struct gen_device_info gen_device_info_byt
= {
283 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
285 .num_subslices
= { 1, },
286 .num_eu_per_subslice
= 4,
287 .num_thread_per_eu
= 8,
290 .max_vs_threads
= 36,
291 .max_tcs_threads
= 36,
292 .max_tes_threads
= 36,
293 .max_gs_threads
= 36,
294 .max_wm_threads
= 48,
295 .max_cs_threads
= 32,
299 [MESA_SHADER_VERTEX
] = 32,
300 [MESA_SHADER_TESS_EVAL
] = 10,
303 [MESA_SHADER_VERTEX
] = 512,
304 [MESA_SHADER_TESS_CTRL
] = 32,
305 [MESA_SHADER_TESS_EVAL
] = 288,
306 [MESA_SHADER_GEOMETRY
] = 192,
312 #define HSW_FEATURES \
314 .is_haswell = true, \
315 .supports_simd16_3src = true, \
316 .has_resource_streamer = true
318 static const struct gen_device_info gen_device_info_hsw_gt1
= {
319 HSW_FEATURES
, .gt
= 1,
321 .num_subslices
= { 1, },
322 .num_eu_per_subslice
= 10,
323 .num_thread_per_eu
= 7,
325 .max_vs_threads
= 70,
326 .max_tcs_threads
= 70,
327 .max_tes_threads
= 70,
328 .max_gs_threads
= 70,
329 .max_wm_threads
= 102,
330 .max_cs_threads
= 70,
334 [MESA_SHADER_VERTEX
] = 32,
335 [MESA_SHADER_TESS_EVAL
] = 10,
338 [MESA_SHADER_VERTEX
] = 640,
339 [MESA_SHADER_TESS_CTRL
] = 64,
340 [MESA_SHADER_TESS_EVAL
] = 384,
341 [MESA_SHADER_GEOMETRY
] = 256,
347 static const struct gen_device_info gen_device_info_hsw_gt2
= {
348 HSW_FEATURES
, .gt
= 2,
350 .num_subslices
= { 2, },
351 .num_eu_per_subslice
= 10,
352 .num_thread_per_eu
= 7,
354 .max_vs_threads
= 280,
355 .max_tcs_threads
= 256,
356 .max_tes_threads
= 280,
357 .max_gs_threads
= 256,
358 .max_wm_threads
= 204,
359 .max_cs_threads
= 70,
363 [MESA_SHADER_VERTEX
] = 64,
364 [MESA_SHADER_TESS_EVAL
] = 10,
367 [MESA_SHADER_VERTEX
] = 1664,
368 [MESA_SHADER_TESS_CTRL
] = 128,
369 [MESA_SHADER_TESS_EVAL
] = 960,
370 [MESA_SHADER_GEOMETRY
] = 640,
376 static const struct gen_device_info gen_device_info_hsw_gt3
= {
377 HSW_FEATURES
, .gt
= 3,
379 .num_subslices
= { 2, },
380 .num_eu_per_subslice
= 10,
381 .num_thread_per_eu
= 7,
383 .max_vs_threads
= 280,
384 .max_tcs_threads
= 256,
385 .max_tes_threads
= 280,
386 .max_gs_threads
= 256,
387 .max_wm_threads
= 408,
388 .max_cs_threads
= 70,
392 [MESA_SHADER_VERTEX
] = 64,
393 [MESA_SHADER_TESS_EVAL
] = 10,
396 [MESA_SHADER_VERTEX
] = 1664,
397 [MESA_SHADER_TESS_CTRL
] = 128,
398 [MESA_SHADER_TESS_EVAL
] = 960,
399 [MESA_SHADER_GEOMETRY
] = 640,
405 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
406 * so keep things conservative for now and set has_sample_with_hiz = false.
408 #define GEN8_FEATURES \
410 .has_hiz_and_separate_stencil = true, \
411 .has_resource_streamer = true, \
412 .must_use_separate_stencil = true, \
414 .has_sample_with_hiz = false, \
416 .has_integer_dword_mul = true, \
417 .has_64bit_types = true, \
418 .supports_simd16_3src = true, \
419 .has_surface_tile_offset = true, \
420 .num_thread_per_eu = 7, \
421 .max_vs_threads = 504, \
422 .max_tcs_threads = 504, \
423 .max_tes_threads = 504, \
424 .max_gs_threads = 504, \
425 .max_wm_threads = 384, \
426 .timestamp_frequency = 12500000
428 static const struct gen_device_info gen_device_info_bdw_gt1
= {
429 GEN8_FEATURES
, .gt
= 1,
430 .is_broadwell
= true,
432 .num_subslices
= { 2, },
433 .num_eu_per_subslice
= 8,
435 .max_cs_threads
= 42,
439 [MESA_SHADER_VERTEX
] = 64,
440 [MESA_SHADER_TESS_EVAL
] = 34,
443 [MESA_SHADER_VERTEX
] = 2560,
444 [MESA_SHADER_TESS_CTRL
] = 504,
445 [MESA_SHADER_TESS_EVAL
] = 1536,
446 [MESA_SHADER_GEOMETRY
] = 960,
452 static const struct gen_device_info gen_device_info_bdw_gt2
= {
453 GEN8_FEATURES
, .gt
= 2,
454 .is_broadwell
= true,
456 .num_subslices
= { 3, },
457 .num_eu_per_subslice
= 8,
459 .max_cs_threads
= 56,
463 [MESA_SHADER_VERTEX
] = 64,
464 [MESA_SHADER_TESS_EVAL
] = 34,
467 [MESA_SHADER_VERTEX
] = 2560,
468 [MESA_SHADER_TESS_CTRL
] = 504,
469 [MESA_SHADER_TESS_EVAL
] = 1536,
470 [MESA_SHADER_GEOMETRY
] = 960,
476 static const struct gen_device_info gen_device_info_bdw_gt3
= {
477 GEN8_FEATURES
, .gt
= 3,
478 .is_broadwell
= true,
480 .num_subslices
= { 3, 3, },
481 .num_eu_per_subslice
= 8,
483 .max_cs_threads
= 56,
487 [MESA_SHADER_VERTEX
] = 64,
488 [MESA_SHADER_TESS_EVAL
] = 34,
491 [MESA_SHADER_VERTEX
] = 2560,
492 [MESA_SHADER_TESS_CTRL
] = 504,
493 [MESA_SHADER_TESS_EVAL
] = 1536,
494 [MESA_SHADER_GEOMETRY
] = 960,
500 static const struct gen_device_info gen_device_info_chv
= {
501 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
503 .has_integer_dword_mul
= false,
505 .num_subslices
= { 2, },
506 .num_eu_per_subslice
= 8,
508 .max_vs_threads
= 80,
509 .max_tcs_threads
= 80,
510 .max_tes_threads
= 80,
511 .max_gs_threads
= 80,
512 .max_wm_threads
= 128,
513 .max_cs_threads
= 6 * 7,
517 [MESA_SHADER_VERTEX
] = 34,
518 [MESA_SHADER_TESS_EVAL
] = 34,
521 [MESA_SHADER_VERTEX
] = 640,
522 [MESA_SHADER_TESS_CTRL
] = 80,
523 [MESA_SHADER_TESS_EVAL
] = 384,
524 [MESA_SHADER_GEOMETRY
] = 256,
530 #define GEN9_HW_INFO \
532 .max_vs_threads = 336, \
533 .max_gs_threads = 336, \
534 .max_tcs_threads = 336, \
535 .max_tes_threads = 336, \
536 .max_cs_threads = 56, \
537 .timestamp_frequency = 12000000, \
541 [MESA_SHADER_VERTEX] = 64, \
542 [MESA_SHADER_TESS_EVAL] = 34, \
545 [MESA_SHADER_VERTEX] = 1856, \
546 [MESA_SHADER_TESS_CTRL] = 672, \
547 [MESA_SHADER_TESS_EVAL] = 1120, \
548 [MESA_SHADER_GEOMETRY] = 640, \
552 #define GEN9_LP_FEATURES \
555 .has_integer_dword_mul = false, \
558 .has_sample_with_hiz = true, \
560 .num_thread_per_eu = 6, \
561 .max_vs_threads = 112, \
562 .max_tcs_threads = 112, \
563 .max_tes_threads = 112, \
564 .max_gs_threads = 112, \
565 .max_cs_threads = 6 * 6, \
566 .timestamp_frequency = 19200000, \
570 [MESA_SHADER_VERTEX] = 34, \
571 [MESA_SHADER_TESS_EVAL] = 34, \
574 [MESA_SHADER_VERTEX] = 704, \
575 [MESA_SHADER_TESS_CTRL] = 256, \
576 [MESA_SHADER_TESS_EVAL] = 416, \
577 [MESA_SHADER_GEOMETRY] = 256, \
581 #define GEN9_LP_FEATURES_3X6 \
583 .num_subslices = { 3, }, \
584 .num_eu_per_subslice = 6
586 #define GEN9_LP_FEATURES_2X6 \
588 .num_subslices = { 2, }, \
589 .num_eu_per_subslice = 6, \
590 .max_vs_threads = 56, \
591 .max_tcs_threads = 56, \
592 .max_tes_threads = 56, \
593 .max_gs_threads = 56, \
594 .max_cs_threads = 6 * 6, \
598 [MESA_SHADER_VERTEX] = 34, \
599 [MESA_SHADER_TESS_EVAL] = 34, \
602 [MESA_SHADER_VERTEX] = 352, \
603 [MESA_SHADER_TESS_CTRL] = 128, \
604 [MESA_SHADER_TESS_EVAL] = 208, \
605 [MESA_SHADER_GEOMETRY] = 128, \
609 #define GEN9_FEATURES \
612 .has_sample_with_hiz = true
614 static const struct gen_device_info gen_device_info_skl_gt1
= {
615 GEN9_FEATURES
, .gt
= 1,
618 .num_subslices
= { 2, },
619 .num_eu_per_subslice
= 6,
622 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
623 * leading to some vertices to go missing if we use too much URB.
625 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
629 static const struct gen_device_info gen_device_info_skl_gt2
= {
630 GEN9_FEATURES
, .gt
= 2,
633 .num_subslices
= { 3, },
634 .num_eu_per_subslice
= 8,
639 static const struct gen_device_info gen_device_info_skl_gt3
= {
640 GEN9_FEATURES
, .gt
= 3,
643 .num_subslices
= { 3, 3, },
644 .num_eu_per_subslice
= 8,
649 static const struct gen_device_info gen_device_info_skl_gt4
= {
650 GEN9_FEATURES
, .gt
= 4,
653 .num_subslices
= { 3, 3, 3, },
654 .num_eu_per_subslice
= 8,
656 /* From the "L3 Allocation and Programming" documentation:
658 * "URB is limited to 1008KB due to programming restrictions. This is not a
659 * restriction of the L3 implementation, but of the FF and other clients.
660 * Therefore, in a GT4 implementation it is possible for the programmed
661 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
662 * only 1008KB of this will be used."
664 .urb
.size
= 1008 / 3,
668 static const struct gen_device_info gen_device_info_bxt
= {
669 GEN9_LP_FEATURES_3X6
,
675 static const struct gen_device_info gen_device_info_bxt_2x6
= {
676 GEN9_LP_FEATURES_2X6
,
682 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
683 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
686 static const struct gen_device_info gen_device_info_kbl_gt1
= {
691 .max_cs_threads
= 7 * 6,
694 .num_subslices
= { 2, },
695 .num_eu_per_subslice
= 6,
697 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
698 * leading to some vertices to go missing if we use too much URB.
700 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
704 static const struct gen_device_info gen_device_info_kbl_gt1_5
= {
709 .max_cs_threads
= 7 * 6,
711 .num_subslices
= { 3, },
712 .num_eu_per_subslice
= 6,
717 static const struct gen_device_info gen_device_info_kbl_gt2
= {
723 .num_subslices
= { 3, },
724 .num_eu_per_subslice
= 8,
729 static const struct gen_device_info gen_device_info_kbl_gt3
= {
735 .num_subslices
= { 3, 3, },
736 .num_eu_per_subslice
= 8,
741 static const struct gen_device_info gen_device_info_kbl_gt4
= {
747 * From the "L3 Allocation and Programming" documentation:
749 * "URB is limited to 1008KB due to programming restrictions. This
750 * is not a restriction of the L3 implementation, but of the FF and
751 * other clients. Therefore, in a GT4 implementation it is
752 * possible for the programmed allocation of the L3 data array to
753 * provide 3*384KB=1152KB for URB, but only 1008KB of this
756 .urb
.size
= 1008 / 3,
758 .num_subslices
= { 3, 3, 3, },
759 .num_eu_per_subslice
= 8,
764 static const struct gen_device_info gen_device_info_glk
= {
765 GEN9_LP_FEATURES_3X6
,
766 .is_geminilake
= true,
771 static const struct gen_device_info gen_device_info_glk_2x6
= {
772 GEN9_LP_FEATURES_2X6
,
773 .is_geminilake
= true,
778 static const struct gen_device_info gen_device_info_cfl_gt1
= {
780 .is_coffeelake
= true,
784 .num_subslices
= { 2, },
785 .num_eu_per_subslice
= 6,
788 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
789 * leading to some vertices to go missing if we use too much URB.
791 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
794 static const struct gen_device_info gen_device_info_cfl_gt2
= {
796 .is_coffeelake
= true,
800 .num_subslices
= { 3, },
801 .num_eu_per_subslice
= 8,
806 static const struct gen_device_info gen_device_info_cfl_gt3
= {
808 .is_coffeelake
= true,
812 .num_subslices
= { 3, 3, },
813 .num_eu_per_subslice
= 8,
818 #define GEN10_HW_INFO \
820 .num_thread_per_eu = 7, \
821 .max_vs_threads = 728, \
822 .max_gs_threads = 432, \
823 .max_tcs_threads = 432, \
824 .max_tes_threads = 624, \
825 .max_cs_threads = 56, \
826 .timestamp_frequency = 19200000, \
830 [MESA_SHADER_VERTEX] = 64, \
831 [MESA_SHADER_TESS_EVAL] = 34, \
834 [MESA_SHADER_VERTEX] = 3936, \
835 [MESA_SHADER_TESS_CTRL] = 896, \
836 [MESA_SHADER_TESS_EVAL] = 2064, \
837 [MESA_SHADER_GEOMETRY] = 832, \
841 #define subslices(args...) { args, }
843 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
846 .has_sample_with_hiz = true, \
848 .num_slices = _slices, \
849 .num_subslices = _subslices, \
850 .num_eu_per_subslice = 8, \
853 static const struct gen_device_info gen_device_info_cnl_2x8
= {
855 GEN10_FEATURES(1, 1, subslices(2), 2),
856 .is_cannonlake
= true,
860 static const struct gen_device_info gen_device_info_cnl_3x8
= {
862 GEN10_FEATURES(1, 1, subslices(3), 3),
863 .is_cannonlake
= true,
867 static const struct gen_device_info gen_device_info_cnl_4x8
= {
869 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
870 .is_cannonlake
= true,
874 static const struct gen_device_info gen_device_info_cnl_5x8
= {
876 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
877 .is_cannonlake
= true,
881 #define GEN11_HW_INFO \
884 .max_vs_threads = 364, \
885 .max_gs_threads = 224, \
886 .max_tcs_threads = 224, \
887 .max_tes_threads = 364, \
890 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
893 .has_64bit_types = false, \
894 .has_integer_dword_mul = false, \
895 .has_sample_with_hiz = false, \
896 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
897 .num_subslices = _subslices, \
898 .num_eu_per_subslice = 8
900 #define GEN11_URB_MIN_MAX_ENTRIES \
902 [MESA_SHADER_VERTEX] = 64, \
903 [MESA_SHADER_TESS_EVAL] = 34, \
906 [MESA_SHADER_VERTEX] = 2384, \
907 [MESA_SHADER_TESS_CTRL] = 1032, \
908 [MESA_SHADER_TESS_EVAL] = 2384, \
909 [MESA_SHADER_GEOMETRY] = 1032, \
912 static const struct gen_device_info gen_device_info_icl_8x8
= {
913 GEN11_FEATURES(2, 1, subslices(8), 8),
916 GEN11_URB_MIN_MAX_ENTRIES
,
921 static const struct gen_device_info gen_device_info_icl_6x8
= {
922 GEN11_FEATURES(1, 1, subslices(6), 6),
925 GEN11_URB_MIN_MAX_ENTRIES
,
930 static const struct gen_device_info gen_device_info_icl_4x8
= {
931 GEN11_FEATURES(1, 1, subslices(4), 6),
934 GEN11_URB_MIN_MAX_ENTRIES
,
939 static const struct gen_device_info gen_device_info_icl_1x8
= {
940 GEN11_FEATURES(1, 1, subslices(1), 6),
943 GEN11_URB_MIN_MAX_ENTRIES
,
948 static const struct gen_device_info gen_device_info_ehl_4x8
= {
949 GEN11_FEATURES(1, 1, subslices(4), 4),
953 [MESA_SHADER_VERTEX
] = 64,
954 [MESA_SHADER_TESS_EVAL
] = 34,
957 [MESA_SHADER_VERTEX
] = 2384,
958 [MESA_SHADER_TESS_CTRL
] = 1032,
959 [MESA_SHADER_TESS_EVAL
] = 2384,
960 [MESA_SHADER_GEOMETRY
] = 1032,
963 .disable_ccs_repack
= true,
967 /* FIXME: Verfiy below entries when more information is available for this SKU.
969 static const struct gen_device_info gen_device_info_ehl_4x4
= {
970 GEN11_FEATURES(1, 1, subslices(4), 4),
974 [MESA_SHADER_VERTEX
] = 64,
975 [MESA_SHADER_TESS_EVAL
] = 34,
978 [MESA_SHADER_VERTEX
] = 2384,
979 [MESA_SHADER_TESS_CTRL
] = 1032,
980 [MESA_SHADER_TESS_EVAL
] = 2384,
981 [MESA_SHADER_GEOMETRY
] = 1032,
984 .disable_ccs_repack
= true,
985 .num_eu_per_subslice
= 4,
989 /* FIXME: Verfiy below entries when more information is available for this SKU.
991 static const struct gen_device_info gen_device_info_ehl_2x4
= {
992 GEN11_FEATURES(1, 1, subslices(2), 4),
996 [MESA_SHADER_VERTEX
] = 64,
997 [MESA_SHADER_TESS_EVAL
] = 34,
1000 [MESA_SHADER_VERTEX
] = 2384,
1001 [MESA_SHADER_TESS_CTRL
] = 1032,
1002 [MESA_SHADER_TESS_EVAL
] = 2384,
1003 [MESA_SHADER_GEOMETRY
] = 1032,
1006 .disable_ccs_repack
= true,
1007 .num_eu_per_subslice
=4,
1012 gen_device_info_set_eu_mask(struct gen_device_info
*devinfo
,
1017 unsigned subslice_offset
= slice
* devinfo
->eu_slice_stride
+
1018 subslice
* devinfo
->eu_subslice_stride
;
1020 for (unsigned b_eu
= 0; b_eu
< devinfo
->eu_subslice_stride
; b_eu
++) {
1021 devinfo
->eu_masks
[subslice_offset
+ b_eu
] =
1022 (((1U << devinfo
->num_eu_per_subslice
) - 1) >> (b_eu
* 8)) & 0xff;
1026 /* Generate slice/subslice/eu masks from number of
1027 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1030 * These can be overridden with values reported by the kernel either from
1031 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1032 * through the i915 query uapi.
1035 fill_masks(struct gen_device_info
*devinfo
)
1037 devinfo
->slice_masks
= (1U << devinfo
->num_slices
) - 1;
1039 /* Subslice masks */
1040 unsigned max_subslices
= 0;
1041 for (int s
= 0; s
< devinfo
->num_slices
; s
++)
1042 max_subslices
= MAX2(devinfo
->num_subslices
[s
], max_subslices
);
1043 devinfo
->subslice_slice_stride
= DIV_ROUND_UP(max_subslices
, 8);
1045 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1046 devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
] =
1047 (1U << devinfo
->num_subslices
[s
]) - 1;
1051 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(devinfo
->num_eu_per_subslice
, 8);
1052 devinfo
->eu_slice_stride
= max_subslices
* devinfo
->eu_subslice_stride
;
1054 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1055 for (int ss
= 0; ss
< devinfo
->num_subslices
[s
]; ss
++) {
1056 gen_device_info_set_eu_mask(devinfo
, s
, ss
,
1057 (1U << devinfo
->num_eu_per_subslice
) - 1);
1063 reset_masks(struct gen_device_info
*devinfo
)
1065 devinfo
->subslice_slice_stride
= 0;
1066 devinfo
->eu_subslice_stride
= 0;
1067 devinfo
->eu_slice_stride
= 0;
1069 devinfo
->num_slices
= 0;
1070 devinfo
->num_eu_per_subslice
= 0;
1071 memset(devinfo
->num_subslices
, 0, sizeof(devinfo
->num_subslices
));
1073 memset(&devinfo
->slice_masks
, 0, sizeof(devinfo
->slice_masks
));
1074 memset(devinfo
->subslice_masks
, 0, sizeof(devinfo
->subslice_masks
));
1075 memset(devinfo
->eu_masks
, 0, sizeof(devinfo
->eu_masks
));
1076 memset(devinfo
->ppipe_subslices
, 0, sizeof(devinfo
->ppipe_subslices
));
1080 update_from_topology(struct gen_device_info
*devinfo
,
1081 const struct drm_i915_query_topology_info
*topology
)
1083 reset_masks(devinfo
);
1085 devinfo
->subslice_slice_stride
= topology
->subslice_stride
;
1087 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(topology
->max_eus_per_subslice
, 8);
1088 devinfo
->eu_slice_stride
= topology
->max_subslices
* devinfo
->eu_subslice_stride
;
1090 assert(sizeof(devinfo
->slice_masks
) >= DIV_ROUND_UP(topology
->max_slices
, 8));
1091 memcpy(&devinfo
->slice_masks
, topology
->data
, DIV_ROUND_UP(topology
->max_slices
, 8));
1092 devinfo
->num_slices
= __builtin_popcount(devinfo
->slice_masks
);
1094 uint32_t subslice_mask_len
=
1095 topology
->max_slices
* topology
->subslice_stride
;
1096 assert(sizeof(devinfo
->subslice_masks
) >= subslice_mask_len
);
1097 memcpy(devinfo
->subslice_masks
, &topology
->data
[topology
->subslice_offset
],
1100 uint32_t n_subslices
= 0;
1101 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1102 if ((devinfo
->slice_masks
& (1 << s
)) == 0)
1105 for (int b
= 0; b
< devinfo
->subslice_slice_stride
; b
++) {
1106 devinfo
->num_subslices
[s
] +=
1107 __builtin_popcount(devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
+ b
]);
1109 n_subslices
+= devinfo
->num_subslices
[s
];
1111 assert(n_subslices
> 0);
1113 if (devinfo
->gen
== 11) {
1114 /* On ICL we only have one slice */
1115 assert(devinfo
->slice_masks
== 1);
1117 /* Count the number of subslices on each pixel pipe. Assume that
1118 * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
1120 unsigned subslices
= devinfo
->subslice_masks
[0];
1122 while (subslices
> 0) {
1124 devinfo
->ppipe_subslices
[ss
>= 4 ? 1 : 0] += 1;
1130 uint32_t eu_mask_len
=
1131 topology
->eu_stride
* topology
->max_subslices
* topology
->max_slices
;
1132 assert(sizeof(devinfo
->eu_masks
) >= eu_mask_len
);
1133 memcpy(devinfo
->eu_masks
, &topology
->data
[topology
->eu_offset
], eu_mask_len
);
1136 for (int b
= 0; b
< eu_mask_len
; b
++)
1137 n_eus
+= __builtin_popcount(devinfo
->eu_masks
[b
]);
1139 devinfo
->num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1143 update_from_masks(struct gen_device_info
*devinfo
, uint32_t slice_mask
,
1144 uint32_t subslice_mask
, uint32_t n_eus
)
1146 struct drm_i915_query_topology_info
*topology
;
1148 assert((slice_mask
& 0xff) == slice_mask
);
1150 size_t data_length
= 100;
1152 topology
= calloc(1, sizeof(*topology
) + data_length
);
1156 topology
->max_slices
= util_last_bit(slice_mask
);
1157 topology
->max_subslices
= util_last_bit(subslice_mask
);
1159 topology
->subslice_offset
= DIV_ROUND_UP(topology
->max_slices
, 8);
1160 topology
->subslice_stride
= DIV_ROUND_UP(topology
->max_subslices
, 8);
1162 uint32_t n_subslices
= __builtin_popcount(slice_mask
) *
1163 __builtin_popcount(subslice_mask
);
1164 uint32_t num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1165 uint32_t eu_mask
= (1U << num_eu_per_subslice
) - 1;
1167 topology
->eu_offset
= topology
->subslice_offset
+
1168 DIV_ROUND_UP(topology
->max_subslices
, 8);
1169 topology
->eu_stride
= DIV_ROUND_UP(num_eu_per_subslice
, 8);
1171 /* Set slice mask in topology */
1172 for (int b
= 0; b
< topology
->subslice_offset
; b
++)
1173 topology
->data
[b
] = (slice_mask
>> (b
* 8)) & 0xff;
1175 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1177 /* Set subslice mask in topology */
1178 for (int b
= 0; b
< topology
->subslice_stride
; b
++) {
1179 int subslice_offset
= topology
->subslice_offset
+
1180 s
* topology
->subslice_stride
+ b
;
1182 topology
->data
[subslice_offset
] = (subslice_mask
>> (b
* 8)) & 0xff;
1185 /* Set eu mask in topology */
1186 for (int ss
= 0; ss
< topology
->max_subslices
; ss
++) {
1187 for (int b
= 0; b
< topology
->eu_stride
; b
++) {
1188 int eu_offset
= topology
->eu_offset
+
1189 (s
* topology
->max_subslices
+ ss
) * topology
->eu_stride
+ b
;
1191 topology
->data
[eu_offset
] = (eu_mask
>> (b
* 8)) & 0xff;
1196 update_from_topology(devinfo
, topology
);
1203 getparam(int fd
, uint32_t param
, int *value
)
1207 struct drm_i915_getparam gp
= {
1212 int ret
= gen_ioctl(fd
, DRM_IOCTL_I915_GETPARAM
, &gp
);
1221 gen_get_device_info_from_pci_id(int pci_id
,
1222 struct gen_device_info
*devinfo
)
1226 #define CHIPSET(id, family, name) \
1227 case id: *devinfo = gen_device_info_##family; break;
1228 #include "pci_ids/i965_pci_ids.h"
1230 fprintf(stderr
, "Driver does not support the 0x%x PCI ID.\n", pci_id
);
1234 fill_masks(devinfo
);
1236 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1238 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1239 * allocate scratch space enough so that each slice has 4 slices allowed."
1241 * The equivalent internal documentation says that this programming note
1242 * applies to all Gen9+ platforms.
1244 * The hardware typically calculates the scratch space pointer by taking
1245 * the base address, and adding per-thread-scratch-space * thread ID.
1246 * Extra padding can be necessary depending how the thread IDs are
1247 * calculated for a particular shader stage.
1250 switch(devinfo
->gen
) {
1253 devinfo
->max_wm_threads
= 64 /* threads-per-PSD */
1254 * devinfo
->num_slices
1255 * 4; /* effective subslices per slice */
1258 devinfo
->max_wm_threads
= 128 /* threads-per-PSD */
1259 * devinfo
->num_slices
1260 * 8; /* subslices per slice */
1266 assert(devinfo
->num_slices
<= ARRAY_SIZE(devinfo
->num_subslices
));
1268 devinfo
->chipset_id
= pci_id
;
1273 gen_get_device_name(int devid
)
1277 #define CHIPSET(id, family, name) case id: return name;
1278 #include "pci_ids/i965_pci_ids.h"
1285 * for gen8/gen9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology
1289 getparam_topology(struct gen_device_info
*devinfo
, int fd
)
1292 if (!getparam(fd
, I915_PARAM_SLICE_MASK
, &slice_mask
))
1296 if (!getparam(fd
, I915_PARAM_EU_TOTAL
, &n_eus
))
1299 int subslice_mask
= 0;
1300 if (!getparam(fd
, I915_PARAM_SUBSLICE_MASK
, &subslice_mask
))
1303 return update_from_masks(devinfo
, slice_mask
, subslice_mask
, n_eus
);
1307 * preferred API for updating the topology in devinfo (kernel 4.17+)
1310 query_topology(struct gen_device_info
*devinfo
, int fd
)
1312 struct drm_i915_query_item item
= {
1313 .query_id
= DRM_I915_QUERY_TOPOLOGY_INFO
,
1315 struct drm_i915_query query
= {
1317 .items_ptr
= (uintptr_t) &item
,
1320 if (gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &query
))
1323 if (item
.length
< 0)
1326 struct drm_i915_query_topology_info
*topo_info
=
1327 (struct drm_i915_query_topology_info
*) calloc(1, item
.length
);
1328 item
.data_ptr
= (uintptr_t) topo_info
;
1330 if (gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &query
) ||
1334 update_from_topology(devinfo
, topo_info
);
1343 gen_get_device_info_from_fd(int fd
, struct gen_device_info
*devinfo
)
1345 int devid
= get_pci_device_id_override();
1347 if (!gen_get_device_info_from_pci_id(devid
, devinfo
))
1349 devinfo
->no_hw
= true;
1351 /* query the device id */
1352 if (!getparam(fd
, I915_PARAM_CHIPSET_ID
, &devid
))
1354 if (!gen_get_device_info_from_pci_id(devid
, devinfo
))
1356 devinfo
->no_hw
= false;
1359 /* remaining initializion queries the kernel for device info */
1363 int timestamp_frequency
;
1364 if (getparam(fd
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1365 ×tamp_frequency
))
1366 devinfo
->timestamp_frequency
= timestamp_frequency
;
1367 else if (devinfo
->gen
>= 10)
1368 /* gen10 and later requires the timestamp_frequency to be updated */
1371 if (!getparam(fd
, I915_PARAM_REVISION
, &devinfo
->revision
))
1374 if (!query_topology(devinfo
, fd
)) {
1375 if (devinfo
->gen
>= 10) {
1376 /* topology uAPI required for CNL+ (kernel 4.17+) */
1380 /* else use the kernel 4.13+ api for gen8+. For older kernels, topology
1381 * will be wrong, affecting GPU metrics. In this case, fail silently.
1383 getparam_topology(devinfo
, fd
);