2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "gen_device_info.h"
31 #include "compiler/shader_enums.h"
32 #include "intel/common/gen_gem.h"
33 #include "util/bitscan.h"
34 #include "util/macros.h"
36 #include "drm-uapi/i915_drm.h"
39 * Get the PCI ID for the device name.
41 * Returns -1 if the device is not known.
44 gen_device_name_to_pci_device_id(const char *name
)
74 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
75 if (!strcmp(name_map
[i
].name
, name
))
76 return name_map
[i
].pci_id
;
83 * Get the overridden PCI ID for the device. This is set with the
84 * INTEL_DEVID_OVERRIDE environment variable.
86 * Returns -1 if the override is not set.
89 get_pci_device_id_override(void)
91 if (geteuid() == getuid()) {
92 const char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
94 const int id
= gen_device_name_to_pci_device_id(devid_override
);
95 return id
>= 0 ? id
: strtol(devid_override
, NULL
, 0);
102 static const struct gen_device_info gen_device_info_i965
= {
104 .has_negative_rhw_bug
= true,
106 .num_subslices
= { 1, },
107 .num_eu_per_subslice
= 8,
108 .num_thread_per_eu
= 4,
109 .max_vs_threads
= 16,
111 .max_wm_threads
= 8 * 4,
115 .timestamp_frequency
= 12500000,
119 static const struct gen_device_info gen_device_info_g4x
= {
123 .has_surface_tile_offset
= true,
126 .num_subslices
= { 1, },
127 .num_eu_per_subslice
= 10,
128 .num_thread_per_eu
= 5,
129 .max_vs_threads
= 32,
131 .max_wm_threads
= 10 * 5,
135 .timestamp_frequency
= 12500000,
139 static const struct gen_device_info gen_device_info_ilk
= {
143 .has_surface_tile_offset
= true,
145 .num_subslices
= { 1, },
146 .num_eu_per_subslice
= 12,
147 .num_thread_per_eu
= 6,
148 .max_vs_threads
= 72,
149 .max_gs_threads
= 32,
150 .max_wm_threads
= 12 * 6,
154 .timestamp_frequency
= 12500000,
158 static const struct gen_device_info gen_device_info_snb_gt1
= {
161 .has_hiz_and_separate_stencil
= true,
164 .has_surface_tile_offset
= true,
165 .needs_unlit_centroid_workaround
= true,
167 .num_subslices
= { 1, },
168 .num_eu_per_subslice
= 6,
169 .num_thread_per_eu
= 6, /* Not confirmed */
170 .max_vs_threads
= 24,
171 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
172 .max_wm_threads
= 40,
176 [MESA_SHADER_VERTEX
] = 24,
179 [MESA_SHADER_VERTEX
] = 256,
180 [MESA_SHADER_GEOMETRY
] = 256,
183 .timestamp_frequency
= 12500000,
187 static const struct gen_device_info gen_device_info_snb_gt2
= {
190 .has_hiz_and_separate_stencil
= true,
193 .has_surface_tile_offset
= true,
194 .needs_unlit_centroid_workaround
= true,
196 .num_subslices
= { 1, },
197 .num_eu_per_subslice
= 12,
198 .num_thread_per_eu
= 6, /* Not confirmed */
199 .max_vs_threads
= 60,
200 .max_gs_threads
= 60,
201 .max_wm_threads
= 80,
205 [MESA_SHADER_VERTEX
] = 24,
208 [MESA_SHADER_VERTEX
] = 256,
209 [MESA_SHADER_GEOMETRY
] = 256,
212 .timestamp_frequency
= 12500000,
216 #define GEN7_FEATURES \
218 .has_hiz_and_separate_stencil = true, \
219 .must_use_separate_stencil = true, \
222 .has_64bit_types = true, \
223 .has_surface_tile_offset = true, \
224 .timestamp_frequency = 12500000
226 static const struct gen_device_info gen_device_info_ivb_gt1
= {
227 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
229 .num_subslices
= { 1, },
230 .num_eu_per_subslice
= 6,
231 .num_thread_per_eu
= 6,
233 .max_vs_threads
= 36,
234 .max_tcs_threads
= 36,
235 .max_tes_threads
= 36,
236 .max_gs_threads
= 36,
237 .max_wm_threads
= 48,
238 .max_cs_threads
= 36,
242 [MESA_SHADER_VERTEX
] = 32,
243 [MESA_SHADER_TESS_EVAL
] = 10,
246 [MESA_SHADER_VERTEX
] = 512,
247 [MESA_SHADER_TESS_CTRL
] = 32,
248 [MESA_SHADER_TESS_EVAL
] = 288,
249 [MESA_SHADER_GEOMETRY
] = 192,
255 static const struct gen_device_info gen_device_info_ivb_gt2
= {
256 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
258 .num_subslices
= { 1, },
259 .num_eu_per_subslice
= 12,
260 .num_thread_per_eu
= 8, /* Not sure why this isn't a multiple of
261 * @max_wm_threads ... */
263 .max_vs_threads
= 128,
264 .max_tcs_threads
= 128,
265 .max_tes_threads
= 128,
266 .max_gs_threads
= 128,
267 .max_wm_threads
= 172,
268 .max_cs_threads
= 64,
272 [MESA_SHADER_VERTEX
] = 32,
273 [MESA_SHADER_TESS_EVAL
] = 10,
276 [MESA_SHADER_VERTEX
] = 704,
277 [MESA_SHADER_TESS_CTRL
] = 64,
278 [MESA_SHADER_TESS_EVAL
] = 448,
279 [MESA_SHADER_GEOMETRY
] = 320,
285 static const struct gen_device_info gen_device_info_byt
= {
286 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
288 .num_subslices
= { 1, },
289 .num_eu_per_subslice
= 4,
290 .num_thread_per_eu
= 8,
293 .max_vs_threads
= 36,
294 .max_tcs_threads
= 36,
295 .max_tes_threads
= 36,
296 .max_gs_threads
= 36,
297 .max_wm_threads
= 48,
298 .max_cs_threads
= 32,
302 [MESA_SHADER_VERTEX
] = 32,
303 [MESA_SHADER_TESS_EVAL
] = 10,
306 [MESA_SHADER_VERTEX
] = 512,
307 [MESA_SHADER_TESS_CTRL
] = 32,
308 [MESA_SHADER_TESS_EVAL
] = 288,
309 [MESA_SHADER_GEOMETRY
] = 192,
315 #define HSW_FEATURES \
317 .is_haswell = true, \
318 .supports_simd16_3src = true, \
319 .has_resource_streamer = true
321 static const struct gen_device_info gen_device_info_hsw_gt1
= {
322 HSW_FEATURES
, .gt
= 1,
324 .num_subslices
= { 1, },
325 .num_eu_per_subslice
= 10,
326 .num_thread_per_eu
= 7,
328 .max_vs_threads
= 70,
329 .max_tcs_threads
= 70,
330 .max_tes_threads
= 70,
331 .max_gs_threads
= 70,
332 .max_wm_threads
= 102,
333 .max_cs_threads
= 70,
337 [MESA_SHADER_VERTEX
] = 32,
338 [MESA_SHADER_TESS_EVAL
] = 10,
341 [MESA_SHADER_VERTEX
] = 640,
342 [MESA_SHADER_TESS_CTRL
] = 64,
343 [MESA_SHADER_TESS_EVAL
] = 384,
344 [MESA_SHADER_GEOMETRY
] = 256,
350 static const struct gen_device_info gen_device_info_hsw_gt2
= {
351 HSW_FEATURES
, .gt
= 2,
353 .num_subslices
= { 2, },
354 .num_eu_per_subslice
= 10,
355 .num_thread_per_eu
= 7,
357 .max_vs_threads
= 280,
358 .max_tcs_threads
= 256,
359 .max_tes_threads
= 280,
360 .max_gs_threads
= 256,
361 .max_wm_threads
= 204,
362 .max_cs_threads
= 70,
366 [MESA_SHADER_VERTEX
] = 64,
367 [MESA_SHADER_TESS_EVAL
] = 10,
370 [MESA_SHADER_VERTEX
] = 1664,
371 [MESA_SHADER_TESS_CTRL
] = 128,
372 [MESA_SHADER_TESS_EVAL
] = 960,
373 [MESA_SHADER_GEOMETRY
] = 640,
379 static const struct gen_device_info gen_device_info_hsw_gt3
= {
380 HSW_FEATURES
, .gt
= 3,
382 .num_subslices
= { 2, },
383 .num_eu_per_subslice
= 10,
384 .num_thread_per_eu
= 7,
386 .max_vs_threads
= 280,
387 .max_tcs_threads
= 256,
388 .max_tes_threads
= 280,
389 .max_gs_threads
= 256,
390 .max_wm_threads
= 408,
391 .max_cs_threads
= 70,
395 [MESA_SHADER_VERTEX
] = 64,
396 [MESA_SHADER_TESS_EVAL
] = 10,
399 [MESA_SHADER_VERTEX
] = 1664,
400 [MESA_SHADER_TESS_CTRL
] = 128,
401 [MESA_SHADER_TESS_EVAL
] = 960,
402 [MESA_SHADER_GEOMETRY
] = 640,
408 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
409 * so keep things conservative for now and set has_sample_with_hiz = false.
411 #define GEN8_FEATURES \
413 .has_hiz_and_separate_stencil = true, \
414 .has_resource_streamer = true, \
415 .must_use_separate_stencil = true, \
417 .has_sample_with_hiz = false, \
419 .has_integer_dword_mul = true, \
420 .has_64bit_types = true, \
421 .supports_simd16_3src = true, \
422 .has_surface_tile_offset = true, \
423 .num_thread_per_eu = 7, \
424 .max_vs_threads = 504, \
425 .max_tcs_threads = 504, \
426 .max_tes_threads = 504, \
427 .max_gs_threads = 504, \
428 .max_wm_threads = 384, \
429 .timestamp_frequency = 12500000
431 static const struct gen_device_info gen_device_info_bdw_gt1
= {
432 GEN8_FEATURES
, .gt
= 1,
433 .is_broadwell
= true,
435 .num_subslices
= { 2, },
436 .num_eu_per_subslice
= 8,
438 .max_cs_threads
= 42,
442 [MESA_SHADER_VERTEX
] = 64,
443 [MESA_SHADER_TESS_EVAL
] = 34,
446 [MESA_SHADER_VERTEX
] = 2560,
447 [MESA_SHADER_TESS_CTRL
] = 504,
448 [MESA_SHADER_TESS_EVAL
] = 1536,
449 [MESA_SHADER_GEOMETRY
] = 960,
455 static const struct gen_device_info gen_device_info_bdw_gt2
= {
456 GEN8_FEATURES
, .gt
= 2,
457 .is_broadwell
= true,
459 .num_subslices
= { 3, },
460 .num_eu_per_subslice
= 8,
462 .max_cs_threads
= 56,
466 [MESA_SHADER_VERTEX
] = 64,
467 [MESA_SHADER_TESS_EVAL
] = 34,
470 [MESA_SHADER_VERTEX
] = 2560,
471 [MESA_SHADER_TESS_CTRL
] = 504,
472 [MESA_SHADER_TESS_EVAL
] = 1536,
473 [MESA_SHADER_GEOMETRY
] = 960,
479 static const struct gen_device_info gen_device_info_bdw_gt3
= {
480 GEN8_FEATURES
, .gt
= 3,
481 .is_broadwell
= true,
483 .num_subslices
= { 3, 3, },
484 .num_eu_per_subslice
= 8,
486 .max_cs_threads
= 56,
490 [MESA_SHADER_VERTEX
] = 64,
491 [MESA_SHADER_TESS_EVAL
] = 34,
494 [MESA_SHADER_VERTEX
] = 2560,
495 [MESA_SHADER_TESS_CTRL
] = 504,
496 [MESA_SHADER_TESS_EVAL
] = 1536,
497 [MESA_SHADER_GEOMETRY
] = 960,
503 static const struct gen_device_info gen_device_info_chv
= {
504 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
506 .has_integer_dword_mul
= false,
508 .num_subslices
= { 2, },
509 .num_eu_per_subslice
= 8,
511 .max_vs_threads
= 80,
512 .max_tcs_threads
= 80,
513 .max_tes_threads
= 80,
514 .max_gs_threads
= 80,
515 .max_wm_threads
= 128,
516 .max_cs_threads
= 6 * 7,
520 [MESA_SHADER_VERTEX
] = 34,
521 [MESA_SHADER_TESS_EVAL
] = 34,
524 [MESA_SHADER_VERTEX
] = 640,
525 [MESA_SHADER_TESS_CTRL
] = 80,
526 [MESA_SHADER_TESS_EVAL
] = 384,
527 [MESA_SHADER_GEOMETRY
] = 256,
533 #define GEN9_HW_INFO \
535 .max_vs_threads = 336, \
536 .max_gs_threads = 336, \
537 .max_tcs_threads = 336, \
538 .max_tes_threads = 336, \
539 .max_cs_threads = 56, \
540 .timestamp_frequency = 12000000, \
544 [MESA_SHADER_VERTEX] = 64, \
545 [MESA_SHADER_TESS_EVAL] = 34, \
548 [MESA_SHADER_VERTEX] = 1856, \
549 [MESA_SHADER_TESS_CTRL] = 672, \
550 [MESA_SHADER_TESS_EVAL] = 1120, \
551 [MESA_SHADER_GEOMETRY] = 640, \
555 #define GEN9_LP_FEATURES \
558 .has_integer_dword_mul = false, \
561 .has_sample_with_hiz = true, \
563 .num_thread_per_eu = 6, \
564 .max_vs_threads = 112, \
565 .max_tcs_threads = 112, \
566 .max_tes_threads = 112, \
567 .max_gs_threads = 112, \
568 .max_cs_threads = 6 * 6, \
569 .timestamp_frequency = 19200000, \
573 [MESA_SHADER_VERTEX] = 34, \
574 [MESA_SHADER_TESS_EVAL] = 34, \
577 [MESA_SHADER_VERTEX] = 704, \
578 [MESA_SHADER_TESS_CTRL] = 256, \
579 [MESA_SHADER_TESS_EVAL] = 416, \
580 [MESA_SHADER_GEOMETRY] = 256, \
584 #define GEN9_LP_FEATURES_3X6 \
586 .num_subslices = { 3, }, \
587 .num_eu_per_subslice = 6
589 #define GEN9_LP_FEATURES_2X6 \
591 .num_subslices = { 2, }, \
592 .num_eu_per_subslice = 6, \
593 .max_vs_threads = 56, \
594 .max_tcs_threads = 56, \
595 .max_tes_threads = 56, \
596 .max_gs_threads = 56, \
597 .max_cs_threads = 6 * 6, \
601 [MESA_SHADER_VERTEX] = 34, \
602 [MESA_SHADER_TESS_EVAL] = 34, \
605 [MESA_SHADER_VERTEX] = 352, \
606 [MESA_SHADER_TESS_CTRL] = 128, \
607 [MESA_SHADER_TESS_EVAL] = 208, \
608 [MESA_SHADER_GEOMETRY] = 128, \
612 #define GEN9_FEATURES \
615 .has_sample_with_hiz = true
617 static const struct gen_device_info gen_device_info_skl_gt1
= {
618 GEN9_FEATURES
, .gt
= 1,
621 .num_subslices
= { 2, },
622 .num_eu_per_subslice
= 6,
625 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
626 * leading to some vertices to go missing if we use too much URB.
628 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
632 static const struct gen_device_info gen_device_info_skl_gt2
= {
633 GEN9_FEATURES
, .gt
= 2,
636 .num_subslices
= { 3, },
637 .num_eu_per_subslice
= 8,
642 static const struct gen_device_info gen_device_info_skl_gt3
= {
643 GEN9_FEATURES
, .gt
= 3,
646 .num_subslices
= { 3, 3, },
647 .num_eu_per_subslice
= 8,
652 static const struct gen_device_info gen_device_info_skl_gt4
= {
653 GEN9_FEATURES
, .gt
= 4,
656 .num_subslices
= { 3, 3, 3, },
657 .num_eu_per_subslice
= 8,
659 /* From the "L3 Allocation and Programming" documentation:
661 * "URB is limited to 1008KB due to programming restrictions. This is not a
662 * restriction of the L3 implementation, but of the FF and other clients.
663 * Therefore, in a GT4 implementation it is possible for the programmed
664 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
665 * only 1008KB of this will be used."
667 .urb
.size
= 1008 / 3,
671 static const struct gen_device_info gen_device_info_bxt
= {
672 GEN9_LP_FEATURES_3X6
,
678 static const struct gen_device_info gen_device_info_bxt_2x6
= {
679 GEN9_LP_FEATURES_2X6
,
685 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
686 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
689 static const struct gen_device_info gen_device_info_kbl_gt1
= {
694 .max_cs_threads
= 7 * 6,
697 .num_subslices
= { 2, },
698 .num_eu_per_subslice
= 6,
700 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
701 * leading to some vertices to go missing if we use too much URB.
703 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
707 static const struct gen_device_info gen_device_info_kbl_gt1_5
= {
712 .max_cs_threads
= 7 * 6,
714 .num_subslices
= { 3, },
715 .num_eu_per_subslice
= 6,
720 static const struct gen_device_info gen_device_info_kbl_gt2
= {
726 .num_subslices
= { 3, },
727 .num_eu_per_subslice
= 8,
732 static const struct gen_device_info gen_device_info_kbl_gt3
= {
738 .num_subslices
= { 3, 3, },
739 .num_eu_per_subslice
= 8,
744 static const struct gen_device_info gen_device_info_kbl_gt4
= {
750 * From the "L3 Allocation and Programming" documentation:
752 * "URB is limited to 1008KB due to programming restrictions. This
753 * is not a restriction of the L3 implementation, but of the FF and
754 * other clients. Therefore, in a GT4 implementation it is
755 * possible for the programmed allocation of the L3 data array to
756 * provide 3*384KB=1152KB for URB, but only 1008KB of this
759 .urb
.size
= 1008 / 3,
761 .num_subslices
= { 3, 3, 3, },
762 .num_eu_per_subslice
= 8,
767 static const struct gen_device_info gen_device_info_glk
= {
768 GEN9_LP_FEATURES_3X6
,
769 .is_geminilake
= true,
774 static const struct gen_device_info gen_device_info_glk_2x6
= {
775 GEN9_LP_FEATURES_2X6
,
776 .is_geminilake
= true,
781 static const struct gen_device_info gen_device_info_cfl_gt1
= {
783 .is_coffeelake
= true,
787 .num_subslices
= { 2, },
788 .num_eu_per_subslice
= 6,
791 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
792 * leading to some vertices to go missing if we use too much URB.
794 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
797 static const struct gen_device_info gen_device_info_cfl_gt2
= {
799 .is_coffeelake
= true,
803 .num_subslices
= { 3, },
804 .num_eu_per_subslice
= 8,
809 static const struct gen_device_info gen_device_info_cfl_gt3
= {
811 .is_coffeelake
= true,
815 .num_subslices
= { 3, 3, },
816 .num_eu_per_subslice
= 8,
821 #define GEN10_HW_INFO \
823 .num_thread_per_eu = 7, \
824 .max_vs_threads = 728, \
825 .max_gs_threads = 432, \
826 .max_tcs_threads = 432, \
827 .max_tes_threads = 624, \
828 .max_cs_threads = 56, \
829 .timestamp_frequency = 19200000, \
833 [MESA_SHADER_VERTEX] = 64, \
834 [MESA_SHADER_TESS_EVAL] = 34, \
837 [MESA_SHADER_VERTEX] = 3936, \
838 [MESA_SHADER_TESS_CTRL] = 896, \
839 [MESA_SHADER_TESS_EVAL] = 2064, \
840 [MESA_SHADER_GEOMETRY] = 832, \
844 #define subslices(args...) { args, }
846 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
849 .has_sample_with_hiz = true, \
851 .num_slices = _slices, \
852 .num_subslices = _subslices, \
853 .num_eu_per_subslice = 8, \
856 static const struct gen_device_info gen_device_info_cnl_2x8
= {
858 GEN10_FEATURES(1, 1, subslices(2), 2),
859 .is_cannonlake
= true,
863 static const struct gen_device_info gen_device_info_cnl_3x8
= {
865 GEN10_FEATURES(1, 1, subslices(3), 3),
866 .is_cannonlake
= true,
870 static const struct gen_device_info gen_device_info_cnl_4x8
= {
872 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
873 .is_cannonlake
= true,
877 static const struct gen_device_info gen_device_info_cnl_5x8
= {
879 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
880 .is_cannonlake
= true,
884 #define GEN11_HW_INFO \
887 .max_vs_threads = 364, \
888 .max_gs_threads = 224, \
889 .max_tcs_threads = 224, \
890 .max_tes_threads = 364, \
893 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
896 .has_64bit_types = false, \
897 .has_integer_dword_mul = false, \
898 .has_sample_with_hiz = false, \
899 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
900 .num_subslices = _subslices, \
901 .num_eu_per_subslice = 8
903 #define GEN11_URB_MIN_MAX_ENTRIES \
905 [MESA_SHADER_VERTEX] = 64, \
906 [MESA_SHADER_TESS_EVAL] = 34, \
909 [MESA_SHADER_VERTEX] = 2384, \
910 [MESA_SHADER_TESS_CTRL] = 1032, \
911 [MESA_SHADER_TESS_EVAL] = 2384, \
912 [MESA_SHADER_GEOMETRY] = 1032, \
915 static const struct gen_device_info gen_device_info_icl_8x8
= {
916 GEN11_FEATURES(2, 1, subslices(8), 8),
919 GEN11_URB_MIN_MAX_ENTRIES
,
924 static const struct gen_device_info gen_device_info_icl_6x8
= {
925 GEN11_FEATURES(1, 1, subslices(6), 6),
928 GEN11_URB_MIN_MAX_ENTRIES
,
933 static const struct gen_device_info gen_device_info_icl_4x8
= {
934 GEN11_FEATURES(1, 1, subslices(4), 6),
937 GEN11_URB_MIN_MAX_ENTRIES
,
942 static const struct gen_device_info gen_device_info_icl_1x8
= {
943 GEN11_FEATURES(1, 1, subslices(1), 6),
946 GEN11_URB_MIN_MAX_ENTRIES
,
951 static const struct gen_device_info gen_device_info_ehl_4x8
= {
952 GEN11_FEATURES(1, 1, subslices(4), 4),
953 .is_elkhartlake
= true,
957 [MESA_SHADER_VERTEX
] = 64,
958 [MESA_SHADER_TESS_EVAL
] = 34,
961 [MESA_SHADER_VERTEX
] = 2384,
962 [MESA_SHADER_TESS_CTRL
] = 1032,
963 [MESA_SHADER_TESS_EVAL
] = 2384,
964 [MESA_SHADER_GEOMETRY
] = 1032,
967 .disable_ccs_repack
= true,
971 static const struct gen_device_info gen_device_info_ehl_4x6
= {
972 GEN11_FEATURES(1, 1, subslices(4), 4),
973 .is_elkhartlake
= true,
977 [MESA_SHADER_VERTEX
] = 64,
978 [MESA_SHADER_TESS_EVAL
] = 34,
981 [MESA_SHADER_VERTEX
] = 2384,
982 [MESA_SHADER_TESS_CTRL
] = 1032,
983 [MESA_SHADER_TESS_EVAL
] = 2384,
984 [MESA_SHADER_GEOMETRY
] = 1032,
987 .disable_ccs_repack
= true,
988 .num_eu_per_subslice
= 6,
992 static const struct gen_device_info gen_device_info_ehl_4x4
= {
993 GEN11_FEATURES(1, 1, subslices(4), 4),
994 .is_elkhartlake
= true,
998 [MESA_SHADER_VERTEX
] = 64,
999 [MESA_SHADER_TESS_EVAL
] = 34,
1002 [MESA_SHADER_VERTEX
] = 2384,
1003 [MESA_SHADER_TESS_CTRL
] = 1032,
1004 [MESA_SHADER_TESS_EVAL
] = 2384,
1005 [MESA_SHADER_GEOMETRY
] = 1032,
1008 .disable_ccs_repack
= true,
1009 .num_eu_per_subslice
= 4,
1013 static const struct gen_device_info gen_device_info_ehl_2x4
= {
1014 GEN11_FEATURES(1, 1, subslices(2), 4),
1015 .is_elkhartlake
= true,
1019 [MESA_SHADER_VERTEX
] = 64,
1020 [MESA_SHADER_TESS_EVAL
] = 34,
1023 [MESA_SHADER_VERTEX
] = 2384,
1024 [MESA_SHADER_TESS_CTRL
] = 1032,
1025 [MESA_SHADER_TESS_EVAL
] = 2384,
1026 [MESA_SHADER_GEOMETRY
] = 1032,
1029 .disable_ccs_repack
= true,
1030 .num_eu_per_subslice
=4,
1034 #define GEN12_URB_MIN_MAX_ENTRIES \
1036 [MESA_SHADER_VERTEX] = 64, \
1037 [MESA_SHADER_TESS_EVAL] = 34, \
1040 [MESA_SHADER_VERTEX] = 3576, \
1041 [MESA_SHADER_TESS_CTRL] = 1548, \
1042 [MESA_SHADER_TESS_EVAL] = 3576, \
1043 [MESA_SHADER_GEOMETRY] = 1548, \
1046 #define GEN12_HW_INFO \
1049 .has_sample_with_hiz = false, \
1050 .has_aux_map = true, \
1051 .max_vs_threads = 546, \
1052 .max_gs_threads = 336, \
1053 .max_tcs_threads = 336, \
1054 .max_tes_threads = 546, \
1055 .max_cs_threads = 112, /* threads per DSS */ \
1057 GEN12_URB_MIN_MAX_ENTRIES, \
1060 #define GEN12_FEATURES(_gt, _slices, _dual_subslices, _l3) \
1063 .has_64bit_types = false, \
1064 .has_integer_dword_mul = false, \
1065 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
1066 .simulator_id = 22, \
1067 .urb.size = (_gt) == 1 ? 512 : 1024, \
1068 .num_subslices = _dual_subslices, \
1069 .num_eu_per_subslice = 16
1071 #define dual_subslices(args...) { args, }
1073 static const struct gen_device_info gen_device_info_tgl_1x2x16
= {
1074 GEN12_FEATURES(1, 1, dual_subslices(2), 8),
1077 static const struct gen_device_info gen_device_info_tgl_1x6x16
= {
1078 GEN12_FEATURES(2, 1, dual_subslices(6), 8),
1082 gen_device_info_set_eu_mask(struct gen_device_info
*devinfo
,
1087 unsigned subslice_offset
= slice
* devinfo
->eu_slice_stride
+
1088 subslice
* devinfo
->eu_subslice_stride
;
1090 for (unsigned b_eu
= 0; b_eu
< devinfo
->eu_subslice_stride
; b_eu
++) {
1091 devinfo
->eu_masks
[subslice_offset
+ b_eu
] =
1092 (((1U << devinfo
->num_eu_per_subslice
) - 1) >> (b_eu
* 8)) & 0xff;
1096 /* Generate slice/subslice/eu masks from number of
1097 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1100 * These can be overridden with values reported by the kernel either from
1101 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1102 * through the i915 query uapi.
1105 fill_masks(struct gen_device_info
*devinfo
)
1107 devinfo
->slice_masks
= (1U << devinfo
->num_slices
) - 1;
1109 /* Subslice masks */
1110 unsigned max_subslices
= 0;
1111 for (int s
= 0; s
< devinfo
->num_slices
; s
++)
1112 max_subslices
= MAX2(devinfo
->num_subslices
[s
], max_subslices
);
1113 devinfo
->subslice_slice_stride
= DIV_ROUND_UP(max_subslices
, 8);
1115 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1116 devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
] =
1117 (1U << devinfo
->num_subslices
[s
]) - 1;
1121 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(devinfo
->num_eu_per_subslice
, 8);
1122 devinfo
->eu_slice_stride
= max_subslices
* devinfo
->eu_subslice_stride
;
1124 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1125 for (int ss
= 0; ss
< devinfo
->num_subslices
[s
]; ss
++) {
1126 gen_device_info_set_eu_mask(devinfo
, s
, ss
,
1127 (1U << devinfo
->num_eu_per_subslice
) - 1);
1133 reset_masks(struct gen_device_info
*devinfo
)
1135 devinfo
->subslice_slice_stride
= 0;
1136 devinfo
->eu_subslice_stride
= 0;
1137 devinfo
->eu_slice_stride
= 0;
1139 devinfo
->num_slices
= 0;
1140 devinfo
->num_eu_per_subslice
= 0;
1141 memset(devinfo
->num_subslices
, 0, sizeof(devinfo
->num_subslices
));
1143 memset(&devinfo
->slice_masks
, 0, sizeof(devinfo
->slice_masks
));
1144 memset(devinfo
->subslice_masks
, 0, sizeof(devinfo
->subslice_masks
));
1145 memset(devinfo
->eu_masks
, 0, sizeof(devinfo
->eu_masks
));
1146 memset(devinfo
->ppipe_subslices
, 0, sizeof(devinfo
->ppipe_subslices
));
1150 update_from_topology(struct gen_device_info
*devinfo
,
1151 const struct drm_i915_query_topology_info
*topology
)
1153 reset_masks(devinfo
);
1155 devinfo
->subslice_slice_stride
= topology
->subslice_stride
;
1157 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(topology
->max_eus_per_subslice
, 8);
1158 devinfo
->eu_slice_stride
= topology
->max_subslices
* devinfo
->eu_subslice_stride
;
1160 assert(sizeof(devinfo
->slice_masks
) >= DIV_ROUND_UP(topology
->max_slices
, 8));
1161 memcpy(&devinfo
->slice_masks
, topology
->data
, DIV_ROUND_UP(topology
->max_slices
, 8));
1162 devinfo
->num_slices
= __builtin_popcount(devinfo
->slice_masks
);
1164 uint32_t subslice_mask_len
=
1165 topology
->max_slices
* topology
->subslice_stride
;
1166 assert(sizeof(devinfo
->subslice_masks
) >= subslice_mask_len
);
1167 memcpy(devinfo
->subslice_masks
, &topology
->data
[topology
->subslice_offset
],
1170 uint32_t n_subslices
= 0;
1171 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1172 if ((devinfo
->slice_masks
& (1 << s
)) == 0)
1175 for (int b
= 0; b
< devinfo
->subslice_slice_stride
; b
++) {
1176 devinfo
->num_subslices
[s
] +=
1177 __builtin_popcount(devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
+ b
]);
1179 n_subslices
+= devinfo
->num_subslices
[s
];
1181 assert(n_subslices
> 0);
1183 if (devinfo
->gen
== 11) {
1184 /* On ICL we only have one slice */
1185 assert(devinfo
->slice_masks
== 1);
1187 /* Count the number of subslices on each pixel pipe. Assume that
1188 * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
1190 unsigned subslices
= devinfo
->subslice_masks
[0];
1192 while (subslices
> 0) {
1194 devinfo
->ppipe_subslices
[ss
>= 4 ? 1 : 0] += 1;
1200 uint32_t eu_mask_len
=
1201 topology
->eu_stride
* topology
->max_subslices
* topology
->max_slices
;
1202 assert(sizeof(devinfo
->eu_masks
) >= eu_mask_len
);
1203 memcpy(devinfo
->eu_masks
, &topology
->data
[topology
->eu_offset
], eu_mask_len
);
1206 for (int b
= 0; b
< eu_mask_len
; b
++)
1207 n_eus
+= __builtin_popcount(devinfo
->eu_masks
[b
]);
1209 devinfo
->num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1213 update_from_masks(struct gen_device_info
*devinfo
, uint32_t slice_mask
,
1214 uint32_t subslice_mask
, uint32_t n_eus
)
1216 struct drm_i915_query_topology_info
*topology
;
1218 assert((slice_mask
& 0xff) == slice_mask
);
1220 size_t data_length
= 100;
1222 topology
= calloc(1, sizeof(*topology
) + data_length
);
1226 topology
->max_slices
= util_last_bit(slice_mask
);
1227 topology
->max_subslices
= util_last_bit(subslice_mask
);
1229 topology
->subslice_offset
= DIV_ROUND_UP(topology
->max_slices
, 8);
1230 topology
->subslice_stride
= DIV_ROUND_UP(topology
->max_subslices
, 8);
1232 uint32_t n_subslices
= __builtin_popcount(slice_mask
) *
1233 __builtin_popcount(subslice_mask
);
1234 uint32_t num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1235 uint32_t eu_mask
= (1U << num_eu_per_subslice
) - 1;
1237 topology
->eu_offset
= topology
->subslice_offset
+
1238 DIV_ROUND_UP(topology
->max_subslices
, 8);
1239 topology
->eu_stride
= DIV_ROUND_UP(num_eu_per_subslice
, 8);
1241 /* Set slice mask in topology */
1242 for (int b
= 0; b
< topology
->subslice_offset
; b
++)
1243 topology
->data
[b
] = (slice_mask
>> (b
* 8)) & 0xff;
1245 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1247 /* Set subslice mask in topology */
1248 for (int b
= 0; b
< topology
->subslice_stride
; b
++) {
1249 int subslice_offset
= topology
->subslice_offset
+
1250 s
* topology
->subslice_stride
+ b
;
1252 topology
->data
[subslice_offset
] = (subslice_mask
>> (b
* 8)) & 0xff;
1255 /* Set eu mask in topology */
1256 for (int ss
= 0; ss
< topology
->max_subslices
; ss
++) {
1257 for (int b
= 0; b
< topology
->eu_stride
; b
++) {
1258 int eu_offset
= topology
->eu_offset
+
1259 (s
* topology
->max_subslices
+ ss
) * topology
->eu_stride
+ b
;
1261 topology
->data
[eu_offset
] = (eu_mask
>> (b
* 8)) & 0xff;
1266 update_from_topology(devinfo
, topology
);
1273 getparam(int fd
, uint32_t param
, int *value
)
1277 struct drm_i915_getparam gp
= {
1282 int ret
= gen_ioctl(fd
, DRM_IOCTL_I915_GETPARAM
, &gp
);
1291 gen_get_device_info_from_pci_id(int pci_id
,
1292 struct gen_device_info
*devinfo
)
1296 #define CHIPSET(id, family, name) \
1297 case id: *devinfo = gen_device_info_##family; break;
1298 #include "pci_ids/i965_pci_ids.h"
1299 #include "pci_ids/iris_pci_ids.h"
1301 fprintf(stderr
, "Driver does not support the 0x%x PCI ID.\n", pci_id
);
1305 fill_masks(devinfo
);
1307 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1309 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1310 * allocate scratch space enough so that each slice has 4 slices allowed."
1312 * The equivalent internal documentation says that this programming note
1313 * applies to all Gen9+ platforms.
1315 * The hardware typically calculates the scratch space pointer by taking
1316 * the base address, and adding per-thread-scratch-space * thread ID.
1317 * Extra padding can be necessary depending how the thread IDs are
1318 * calculated for a particular shader stage.
1321 switch(devinfo
->gen
) {
1324 devinfo
->max_wm_threads
= 64 /* threads-per-PSD */
1325 * devinfo
->num_slices
1326 * 4; /* effective subslices per slice */
1330 devinfo
->max_wm_threads
= 128 /* threads-per-PSD */
1331 * devinfo
->num_slices
1332 * 8; /* subslices per slice */
1335 assert(devinfo
->gen
< 9);
1339 assert(devinfo
->num_slices
<= ARRAY_SIZE(devinfo
->num_subslices
));
1341 devinfo
->chipset_id
= pci_id
;
1346 gen_get_device_name(int devid
)
1350 #define CHIPSET(id, family, name) case id: return name;
1351 #include "pci_ids/i965_pci_ids.h"
1352 #include "pci_ids/iris_pci_ids.h"
1359 * for gen8/gen9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology
1363 getparam_topology(struct gen_device_info
*devinfo
, int fd
)
1366 if (!getparam(fd
, I915_PARAM_SLICE_MASK
, &slice_mask
))
1370 if (!getparam(fd
, I915_PARAM_EU_TOTAL
, &n_eus
))
1373 int subslice_mask
= 0;
1374 if (!getparam(fd
, I915_PARAM_SUBSLICE_MASK
, &subslice_mask
))
1377 return update_from_masks(devinfo
, slice_mask
, subslice_mask
, n_eus
);
1381 * preferred API for updating the topology in devinfo (kernel 4.17+)
1384 query_topology(struct gen_device_info
*devinfo
, int fd
)
1386 struct drm_i915_query_item item
= {
1387 .query_id
= DRM_I915_QUERY_TOPOLOGY_INFO
,
1389 struct drm_i915_query query
= {
1391 .items_ptr
= (uintptr_t) &item
,
1394 if (gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &query
))
1397 if (item
.length
< 0)
1400 struct drm_i915_query_topology_info
*topo_info
=
1401 (struct drm_i915_query_topology_info
*) calloc(1, item
.length
);
1402 item
.data_ptr
= (uintptr_t) topo_info
;
1404 if (gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &query
) ||
1408 update_from_topology(devinfo
, topo_info
);
1417 gen_get_device_info_from_fd(int fd
, struct gen_device_info
*devinfo
)
1419 int devid
= get_pci_device_id_override();
1421 if (!gen_get_device_info_from_pci_id(devid
, devinfo
))
1423 devinfo
->no_hw
= true;
1425 /* query the device id */
1426 if (!getparam(fd
, I915_PARAM_CHIPSET_ID
, &devid
))
1428 if (!gen_get_device_info_from_pci_id(devid
, devinfo
))
1430 devinfo
->no_hw
= false;
1433 /* remaining initializion queries the kernel for device info */
1437 int timestamp_frequency
;
1438 if (getparam(fd
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1439 ×tamp_frequency
))
1440 devinfo
->timestamp_frequency
= timestamp_frequency
;
1441 else if (devinfo
->gen
>= 10)
1442 /* gen10 and later requires the timestamp_frequency to be updated */
1445 if (!getparam(fd
, I915_PARAM_REVISION
, &devinfo
->revision
))
1448 if (!query_topology(devinfo
, fd
)) {
1449 if (devinfo
->gen
>= 10) {
1450 /* topology uAPI required for CNL+ (kernel 4.17+) */
1454 /* else use the kernel 4.13+ api for gen8+. For older kernels, topology
1455 * will be wrong, affecting GPU metrics. In this case, fail silently.
1457 getparam_topology(devinfo
, fd
);