projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
intel: devinfo: add simulator id
[mesa.git] / src / intel / dev / gen_device_info.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdio.h>
26 #include <stdlib.h>
27 #include <string.h>
28 #include <unistd.h>
29 #include "gen_device_info.h"
30 #include "compiler/shader_enums.h"
31 #include "util/bitscan.h"
32 #include "util/macros.h"
33
34 #include <i915_drm.h>
35
36 /**
37 * Get the PCI ID for the device name.
38 *
39 * Returns -1 if the device is not known.
40 */
41 int
42 gen_device_name_to_pci_device_id(const char *name)
43 {
44 static const struct {
45 const char *name;
46 int pci_id;
47 } name_map[] = {
48 { "brw", 0x2a02 },
49 { "g4x", 0x2a42 },
50 { "ilk", 0x0042 },
51 { "snb", 0x0126 },
52 { "ivb", 0x016a },
53 { "hsw", 0x0d2e },
54 { "byt", 0x0f33 },
55 { "bdw", 0x162e },
56 { "chv", 0x22B3 },
57 { "skl", 0x1912 },
58 { "bxt", 0x5A85 },
59 { "kbl", 0x5912 },
60 { "glk", 0x3185 },
61 { "cfl", 0x3E9B },
62 { "cnl", 0x5a52 },
63 { "icl", 0x8a52 },
64 };
65
66 for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
67 if (!strcmp(name_map[i].name, name))
68 return name_map[i].pci_id;
69 }
70
71 return -1;
72 }
73
74 /**
75 * Get the overridden PCI ID for the device. This is set with the
76 * INTEL_DEVID_OVERRIDE environment variable.
77 *
78 * Returns -1 if the override is not set.
79 */
80 int
81 gen_get_pci_device_id_override(void)
82 {
83 if (geteuid() == getuid()) {
84 const char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
85 if (devid_override) {
86 const int id = gen_device_name_to_pci_device_id(devid_override);
87 return id >= 0 ? id : strtol(devid_override, NULL, 0);
88 }
89 }
90
91 return -1;
92 }
93
94 static const struct gen_device_info gen_device_info_i965 = {
95 .gen = 4,
96 .has_negative_rhw_bug = true,
97 .num_slices = 1,
98 .num_subslices = { 1, },
99 .num_eu_per_subslice = 8,
100 .num_thread_per_eu = 4,
101 .max_vs_threads = 16,
102 .max_gs_threads = 2,
103 .max_wm_threads = 8 * 4,
104 .urb = {
105 .size = 256,
106 },
107 .timestamp_frequency = 12500000,
108 .simulator_id = -1,
109 };
110
111 static const struct gen_device_info gen_device_info_g4x = {
112 .gen = 4,
113 .has_pln = true,
114 .has_compr4 = true,
115 .has_surface_tile_offset = true,
116 .is_g4x = true,
117 .num_slices = 1,
118 .num_subslices = { 1, },
119 .num_eu_per_subslice = 10,
120 .num_thread_per_eu = 5,
121 .max_vs_threads = 32,
122 .max_gs_threads = 2,
123 .max_wm_threads = 10 * 5,
124 .urb = {
125 .size = 384,
126 },
127 .timestamp_frequency = 12500000,
128 .simulator_id = -1,
129 };
130
131 static const struct gen_device_info gen_device_info_ilk = {
132 .gen = 5,
133 .has_pln = true,
134 .has_compr4 = true,
135 .has_surface_tile_offset = true,
136 .num_slices = 1,
137 .num_subslices = { 1, },
138 .num_eu_per_subslice = 12,
139 .num_thread_per_eu = 6,
140 .max_vs_threads = 72,
141 .max_gs_threads = 32,
142 .max_wm_threads = 12 * 6,
143 .urb = {
144 .size = 1024,
145 },
146 .timestamp_frequency = 12500000,
147 .simulator_id = -1,
148 };
149
150 static const struct gen_device_info gen_device_info_snb_gt1 = {
151 .gen = 6,
152 .gt = 1,
153 .has_hiz_and_separate_stencil = true,
154 .has_llc = true,
155 .has_pln = true,
156 .has_surface_tile_offset = true,
157 .needs_unlit_centroid_workaround = true,
158 .num_slices = 1,
159 .num_subslices = { 1, },
160 .num_eu_per_subslice = 6,
161 .num_thread_per_eu = 6, /* Not confirmed */
162 .max_vs_threads = 24,
163 .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
164 .max_wm_threads = 40,
165 .urb = {
166 .size = 32,
167 .min_entries = {
168 [MESA_SHADER_VERTEX] = 24,
169 },
170 .max_entries = {
171 [MESA_SHADER_VERTEX] = 256,
172 [MESA_SHADER_GEOMETRY] = 256,
173 },
174 },
175 .timestamp_frequency = 12500000,
176 .simulator_id = -1,
177 };
178
179 static const struct gen_device_info gen_device_info_snb_gt2 = {
180 .gen = 6,
181 .gt = 2,
182 .has_hiz_and_separate_stencil = true,
183 .has_llc = true,
184 .has_pln = true,
185 .has_surface_tile_offset = true,
186 .needs_unlit_centroid_workaround = true,
187 .num_slices = 1,
188 .num_subslices = { 1, },
189 .num_eu_per_subslice = 12,
190 .num_thread_per_eu = 6, /* Not confirmed */
191 .max_vs_threads = 60,
192 .max_gs_threads = 60,
193 .max_wm_threads = 80,
194 .urb = {
195 .size = 64,
196 .min_entries = {
197 [MESA_SHADER_VERTEX] = 24,
198 },
199 .max_entries = {
200 [MESA_SHADER_VERTEX] = 256,
201 [MESA_SHADER_GEOMETRY] = 256,
202 },
203 },
204 .timestamp_frequency = 12500000,
205 .simulator_id = -1,
206 };
207
208 #define GEN7_FEATURES \
209 .gen = 7, \
210 .has_hiz_and_separate_stencil = true, \
211 .must_use_separate_stencil = true, \
212 .has_llc = true, \
213 .has_pln = true, \
214 .has_64bit_types = true, \
215 .has_surface_tile_offset = true, \
216 .timestamp_frequency = 12500000
217
218 static const struct gen_device_info gen_device_info_ivb_gt1 = {
219 GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
220 .num_slices = 1,
221 .num_subslices = { 1, },
222 .num_eu_per_subslice = 6,
223 .num_thread_per_eu = 6,
224 .l3_banks = 2,
225 .max_vs_threads = 36,
226 .max_tcs_threads = 36,
227 .max_tes_threads = 36,
228 .max_gs_threads = 36,
229 .max_wm_threads = 48,
230 .max_cs_threads = 36,
231 .urb = {
232 .size = 128,
233 .min_entries = {
234 [MESA_SHADER_VERTEX] = 32,
235 [MESA_SHADER_TESS_EVAL] = 10,
236 },
237 .max_entries = {
238 [MESA_SHADER_VERTEX] = 512,
239 [MESA_SHADER_TESS_CTRL] = 32,
240 [MESA_SHADER_TESS_EVAL] = 288,
241 [MESA_SHADER_GEOMETRY] = 192,
242 },
243 },
244 .simulator_id = 7,
245 };
246
247 static const struct gen_device_info gen_device_info_ivb_gt2 = {
248 GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
249 .num_slices = 1,
250 .num_subslices = { 1, },
251 .num_eu_per_subslice = 12,
252 .num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
253 * @max_wm_threads ... */
254 .l3_banks = 4,
255 .max_vs_threads = 128,
256 .max_tcs_threads = 128,
257 .max_tes_threads = 128,
258 .max_gs_threads = 128,
259 .max_wm_threads = 172,
260 .max_cs_threads = 64,
261 .urb = {
262 .size = 256,
263 .min_entries = {
264 [MESA_SHADER_VERTEX] = 32,
265 [MESA_SHADER_TESS_EVAL] = 10,
266 },
267 .max_entries = {
268 [MESA_SHADER_VERTEX] = 704,
269 [MESA_SHADER_TESS_CTRL] = 64,
270 [MESA_SHADER_TESS_EVAL] = 448,
271 [MESA_SHADER_GEOMETRY] = 320,
272 },
273 },
274 .simulator_id = 7,
275 };
276
277 static const struct gen_device_info gen_device_info_byt = {
278 GEN7_FEATURES, .is_baytrail = true, .gt = 1,
279 .num_slices = 1,
280 .num_subslices = { 1, },
281 .num_eu_per_subslice = 4,
282 .num_thread_per_eu = 8,
283 .l3_banks = 1,
284 .has_llc = false,
285 .max_vs_threads = 36,
286 .max_tcs_threads = 36,
287 .max_tes_threads = 36,
288 .max_gs_threads = 36,
289 .max_wm_threads = 48,
290 .max_cs_threads = 32,
291 .urb = {
292 .size = 128,
293 .min_entries = {
294 [MESA_SHADER_VERTEX] = 32,
295 [MESA_SHADER_TESS_EVAL] = 10,
296 },
297 .max_entries = {
298 [MESA_SHADER_VERTEX] = 512,
299 [MESA_SHADER_TESS_CTRL] = 32,
300 [MESA_SHADER_TESS_EVAL] = 288,
301 [MESA_SHADER_GEOMETRY] = 192,
302 },
303 },
304 .simulator_id = 10,
305 };
306
307 #define HSW_FEATURES \
308 GEN7_FEATURES, \
309 .is_haswell = true, \
310 .supports_simd16_3src = true, \
311 .has_resource_streamer = true
312
313 static const struct gen_device_info gen_device_info_hsw_gt1 = {
314 HSW_FEATURES, .gt = 1,
315 .num_slices = 1,
316 .num_subslices = { 1, },
317 .num_eu_per_subslice = 10,
318 .num_thread_per_eu = 7,
319 .l3_banks = 2,
320 .max_vs_threads = 70,
321 .max_tcs_threads = 70,
322 .max_tes_threads = 70,
323 .max_gs_threads = 70,
324 .max_wm_threads = 102,
325 .max_cs_threads = 70,
326 .urb = {
327 .size = 128,
328 .min_entries = {
329 [MESA_SHADER_VERTEX] = 32,
330 [MESA_SHADER_TESS_EVAL] = 10,
331 },
332 .max_entries = {
333 [MESA_SHADER_VERTEX] = 640,
334 [MESA_SHADER_TESS_CTRL] = 64,
335 [MESA_SHADER_TESS_EVAL] = 384,
336 [MESA_SHADER_GEOMETRY] = 256,
337 },
338 },
339 .simulator_id = 9,
340 };
341
342 static const struct gen_device_info gen_device_info_hsw_gt2 = {
343 HSW_FEATURES, .gt = 2,
344 .num_slices = 1,
345 .num_subslices = { 2, },
346 .num_eu_per_subslice = 10,
347 .num_thread_per_eu = 7,
348 .l3_banks = 4,
349 .max_vs_threads = 280,
350 .max_tcs_threads = 256,
351 .max_tes_threads = 280,
352 .max_gs_threads = 256,
353 .max_wm_threads = 204,
354 .max_cs_threads = 70,
355 .urb = {
356 .size = 256,
357 .min_entries = {
358 [MESA_SHADER_VERTEX] = 64,
359 [MESA_SHADER_TESS_EVAL] = 10,
360 },
361 .max_entries = {
362 [MESA_SHADER_VERTEX] = 1664,
363 [MESA_SHADER_TESS_CTRL] = 128,
364 [MESA_SHADER_TESS_EVAL] = 960,
365 [MESA_SHADER_GEOMETRY] = 640,
366 },
367 },
368 .simulator_id = 9,
369 };
370
371 static const struct gen_device_info gen_device_info_hsw_gt3 = {
372 HSW_FEATURES, .gt = 3,
373 .num_slices = 2,
374 .num_subslices = { 2, },
375 .num_eu_per_subslice = 10,
376 .num_thread_per_eu = 7,
377 .l3_banks = 8,
378 .max_vs_threads = 280,
379 .max_tcs_threads = 256,
380 .max_tes_threads = 280,
381 .max_gs_threads = 256,
382 .max_wm_threads = 408,
383 .max_cs_threads = 70,
384 .urb = {
385 .size = 512,
386 .min_entries = {
387 [MESA_SHADER_VERTEX] = 64,
388 [MESA_SHADER_TESS_EVAL] = 10,
389 },
390 .max_entries = {
391 [MESA_SHADER_VERTEX] = 1664,
392 [MESA_SHADER_TESS_CTRL] = 128,
393 [MESA_SHADER_TESS_EVAL] = 960,
394 [MESA_SHADER_GEOMETRY] = 640,
395 },
396 },
397 .simulator_id = 9,
398 };
399
400 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
401 * so keep things conservative for now and set has_sample_with_hiz = false.
402 */
403 #define GEN8_FEATURES \
404 .gen = 8, \
405 .has_hiz_and_separate_stencil = true, \
406 .has_resource_streamer = true, \
407 .must_use_separate_stencil = true, \
408 .has_llc = true, \
409 .has_sample_with_hiz = false, \
410 .has_pln = true, \
411 .has_integer_dword_mul = true, \
412 .has_64bit_types = true, \
413 .supports_simd16_3src = true, \
414 .has_surface_tile_offset = true, \
415 .max_vs_threads = 504, \
416 .max_tcs_threads = 504, \
417 .max_tes_threads = 504, \
418 .max_gs_threads = 504, \
419 .max_wm_threads = 384, \
420 .timestamp_frequency = 12500000
421
422 static const struct gen_device_info gen_device_info_bdw_gt1 = {
423 GEN8_FEATURES, .gt = 1,
424 .is_broadwell = true,
425 .num_slices = 1,
426 .num_subslices = { 2, },
427 .num_eu_per_subslice = 8,
428 .num_thread_per_eu = 7,
429 .l3_banks = 2,
430 .max_cs_threads = 42,
431 .urb = {
432 .size = 192,
433 .min_entries = {
434 [MESA_SHADER_VERTEX] = 64,
435 [MESA_SHADER_TESS_EVAL] = 34,
436 },
437 .max_entries = {
438 [MESA_SHADER_VERTEX] = 2560,
439 [MESA_SHADER_TESS_CTRL] = 504,
440 [MESA_SHADER_TESS_EVAL] = 1536,
441 [MESA_SHADER_GEOMETRY] = 960,
442 },
443 },
444 .simulator_id = 11,
445 };
446
447 static const struct gen_device_info gen_device_info_bdw_gt2 = {
448 GEN8_FEATURES, .gt = 2,
449 .is_broadwell = true,
450 .num_slices = 1,
451 .num_subslices = { 3, },
452 .num_eu_per_subslice = 8,
453 .num_thread_per_eu = 7,
454 .l3_banks = 4,
455 .max_cs_threads = 56,
456 .urb = {
457 .size = 384,
458 .min_entries = {
459 [MESA_SHADER_VERTEX] = 64,
460 [MESA_SHADER_TESS_EVAL] = 34,
461 },
462 .max_entries = {
463 [MESA_SHADER_VERTEX] = 2560,
464 [MESA_SHADER_TESS_CTRL] = 504,
465 [MESA_SHADER_TESS_EVAL] = 1536,
466 [MESA_SHADER_GEOMETRY] = 960,
467 },
468 },
469 .simulator_id = 11,
470 };
471
472 static const struct gen_device_info gen_device_info_bdw_gt3 = {
473 GEN8_FEATURES, .gt = 3,
474 .is_broadwell = true,
475 .num_slices = 2,
476 .num_subslices = { 3, 3, },
477 .num_eu_per_subslice = 8,
478 .num_thread_per_eu = 7,
479 .l3_banks = 8,
480 .max_cs_threads = 56,
481 .urb = {
482 .size = 384,
483 .min_entries = {
484 [MESA_SHADER_VERTEX] = 64,
485 [MESA_SHADER_TESS_EVAL] = 34,
486 },
487 .max_entries = {
488 [MESA_SHADER_VERTEX] = 2560,
489 [MESA_SHADER_TESS_CTRL] = 504,
490 [MESA_SHADER_TESS_EVAL] = 1536,
491 [MESA_SHADER_GEOMETRY] = 960,
492 },
493 },
494 .simulator_id = 11,
495 };
496
497 static const struct gen_device_info gen_device_info_chv = {
498 GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
499 .has_llc = false,
500 .has_integer_dword_mul = false,
501 .num_slices = 1,
502 .num_subslices = { 2, },
503 .num_eu_per_subslice = 8,
504 .num_thread_per_eu = 7,
505 .l3_banks = 2,
506 .max_vs_threads = 80,
507 .max_tcs_threads = 80,
508 .max_tes_threads = 80,
509 .max_gs_threads = 80,
510 .max_wm_threads = 128,
511 .max_cs_threads = 6 * 7,
512 .urb = {
513 .size = 192,
514 .min_entries = {
515 [MESA_SHADER_VERTEX] = 34,
516 [MESA_SHADER_TESS_EVAL] = 34,
517 },
518 .max_entries = {
519 [MESA_SHADER_VERTEX] = 640,
520 [MESA_SHADER_TESS_CTRL] = 80,
521 [MESA_SHADER_TESS_EVAL] = 384,
522 [MESA_SHADER_GEOMETRY] = 256,
523 },
524 },
525 .simulator_id = 13,
526 };
527
528 #define GEN9_HW_INFO \
529 .gen = 9, \
530 .max_vs_threads = 336, \
531 .max_gs_threads = 336, \
532 .max_tcs_threads = 336, \
533 .max_tes_threads = 336, \
534 .max_cs_threads = 56, \
535 .timestamp_frequency = 12000000, \
536 .urb = { \
537 .size = 384, \
538 .min_entries = { \
539 [MESA_SHADER_VERTEX] = 64, \
540 [MESA_SHADER_TESS_EVAL] = 34, \
541 }, \
542 .max_entries = { \
543 [MESA_SHADER_VERTEX] = 1856, \
544 [MESA_SHADER_TESS_CTRL] = 672, \
545 [MESA_SHADER_TESS_EVAL] = 1120, \
546 [MESA_SHADER_GEOMETRY] = 640, \
547 }, \
548 }
549
550 #define GEN9_LP_FEATURES \
551 GEN8_FEATURES, \
552 GEN9_HW_INFO, \
553 .has_integer_dword_mul = false, \
554 .gt = 1, \
555 .has_llc = false, \
556 .has_sample_with_hiz = true, \
557 .num_slices = 1, \
558 .num_thread_per_eu = 6, \
559 .max_vs_threads = 112, \
560 .max_tcs_threads = 112, \
561 .max_tes_threads = 112, \
562 .max_gs_threads = 112, \
563 .max_cs_threads = 6 * 6, \
564 .timestamp_frequency = 19200000, \
565 .urb = { \
566 .size = 192, \
567 .min_entries = { \
568 [MESA_SHADER_VERTEX] = 34, \
569 [MESA_SHADER_TESS_EVAL] = 34, \
570 }, \
571 .max_entries = { \
572 [MESA_SHADER_VERTEX] = 704, \
573 [MESA_SHADER_TESS_CTRL] = 256, \
574 [MESA_SHADER_TESS_EVAL] = 416, \
575 [MESA_SHADER_GEOMETRY] = 256, \
576 }, \
577 }
578
579 #define GEN9_LP_FEATURES_3X6 \
580 GEN9_LP_FEATURES, \
581 .num_subslices = { 3, }, \
582 .num_eu_per_subslice = 6
583
584 #define GEN9_LP_FEATURES_2X6 \
585 GEN9_LP_FEATURES, \
586 .num_subslices = { 2, }, \
587 .num_eu_per_subslice = 6, \
588 .max_vs_threads = 56, \
589 .max_tcs_threads = 56, \
590 .max_tes_threads = 56, \
591 .max_gs_threads = 56, \
592 .max_cs_threads = 6 * 6, \
593 .urb = { \
594 .size = 128, \
595 .min_entries = { \
596 [MESA_SHADER_VERTEX] = 34, \
597 [MESA_SHADER_TESS_EVAL] = 34, \
598 }, \
599 .max_entries = { \
600 [MESA_SHADER_VERTEX] = 352, \
601 [MESA_SHADER_TESS_CTRL] = 128, \
602 [MESA_SHADER_TESS_EVAL] = 208, \
603 [MESA_SHADER_GEOMETRY] = 128, \
604 }, \
605 }
606
607 #define GEN9_FEATURES \
608 GEN8_FEATURES, \
609 GEN9_HW_INFO, \
610 .has_sample_with_hiz = true, \
611 .num_thread_per_eu = 7
612
613 static const struct gen_device_info gen_device_info_skl_gt1 = {
614 GEN9_FEATURES, .gt = 1,
615 .is_skylake = true,
616 .num_slices = 1,
617 .num_subslices = { 2, },
618 .num_eu_per_subslice = 6,
619 .l3_banks = 2,
620 .urb.size = 192,
621 .simulator_id = 12,
622 };
623
624 static const struct gen_device_info gen_device_info_skl_gt2 = {
625 GEN9_FEATURES, .gt = 2,
626 .is_skylake = true,
627 .num_slices = 1,
628 .num_subslices = { 3, },
629 .num_eu_per_subslice = 8,
630 .l3_banks = 4,
631 .simulator_id = 12,
632 };
633
634 static const struct gen_device_info gen_device_info_skl_gt3 = {
635 GEN9_FEATURES, .gt = 3,
636 .is_skylake = true,
637 .num_slices = 2,
638 .num_subslices = { 3, 3, },
639 .num_eu_per_subslice = 8,
640 .l3_banks = 8,
641 .simulator_id = 12,
642 };
643
644 static const struct gen_device_info gen_device_info_skl_gt4 = {
645 GEN9_FEATURES, .gt = 4,
646 .is_skylake = true,
647 .num_slices = 3,
648 .num_subslices = { 3, 3, 3, },
649 .num_eu_per_subslice = 8,
650 .l3_banks = 12,
651 /* From the "L3 Allocation and Programming" documentation:
652 *
653 * "URB is limited to 1008KB due to programming restrictions. This is not a
654 * restriction of the L3 implementation, but of the FF and other clients.
655 * Therefore, in a GT4 implementation it is possible for the programmed
656 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
657 * only 1008KB of this will be used."
658 */
659 .urb.size = 1008 / 3,
660 .simulator_id = 12,
661 };
662
663 static const struct gen_device_info gen_device_info_bxt = {
664 GEN9_LP_FEATURES_3X6,
665 .is_broxton = true,
666 .l3_banks = 2,
667 .simulator_id = 14,
668 };
669
670 static const struct gen_device_info gen_device_info_bxt_2x6 = {
671 GEN9_LP_FEATURES_2X6,
672 .is_broxton = true,
673 .l3_banks = 1,
674 .simulator_id = 14,
675 };
676 /*
677 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
678 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
679 */
680
681 static const struct gen_device_info gen_device_info_kbl_gt1 = {
682 GEN9_FEATURES,
683 .is_kabylake = true,
684 .gt = 1,
685
686 .max_cs_threads = 7 * 6,
687 .urb.size = 192,
688 .num_slices = 1,
689 .num_subslices = { 2, },
690 .num_eu_per_subslice = 6,
691 .l3_banks = 2,
692 .simulator_id = 16,
693 };
694
695 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
696 GEN9_FEATURES,
697 .is_kabylake = true,
698 .gt = 1,
699
700 .max_cs_threads = 7 * 6,
701 .num_slices = 1,
702 .num_subslices = { 3, },
703 .num_eu_per_subslice = 6,
704 .l3_banks = 4,
705 .simulator_id = 16,
706 };
707
708 static const struct gen_device_info gen_device_info_kbl_gt2 = {
709 GEN9_FEATURES,
710 .is_kabylake = true,
711 .gt = 2,
712
713 .num_slices = 1,
714 .num_subslices = { 3, },
715 .num_eu_per_subslice = 8,
716 .l3_banks = 4,
717 .simulator_id = 16,
718 };
719
720 static const struct gen_device_info gen_device_info_kbl_gt3 = {
721 GEN9_FEATURES,
722 .is_kabylake = true,
723 .gt = 3,
724
725 .num_slices = 2,
726 .num_subslices = { 3, 3, },
727 .num_eu_per_subslice = 8,
728 .l3_banks = 8,
729 .simulator_id = 16,
730 };
731
732 static const struct gen_device_info gen_device_info_kbl_gt4 = {
733 GEN9_FEATURES,
734 .is_kabylake = true,
735 .gt = 4,
736
737 /*
738 * From the "L3 Allocation and Programming" documentation:
739 *
740 * "URB is limited to 1008KB due to programming restrictions. This
741 * is not a restriction of the L3 implementation, but of the FF and
742 * other clients. Therefore, in a GT4 implementation it is
743 * possible for the programmed allocation of the L3 data array to
744 * provide 3*384KB=1152KB for URB, but only 1008KB of this
745 * will be used."
746 */
747 .urb.size = 1008 / 3,
748 .num_slices = 3,
749 .num_subslices = { 3, 3, 3, },
750 .num_eu_per_subslice = 8,
751 .l3_banks = 12,
752 .simulator_id = 16,
753 };
754
755 static const struct gen_device_info gen_device_info_glk = {
756 GEN9_LP_FEATURES_3X6,
757 .is_geminilake = true,
758 .l3_banks = 2,
759 .simulator_id = 17,
760 };
761
762 static const struct gen_device_info gen_device_info_glk_2x6 = {
763 GEN9_LP_FEATURES_2X6,
764 .is_geminilake = true,
765 .l3_banks = 2,
766 .simulator_id = 17,
767 };
768
769 static const struct gen_device_info gen_device_info_cfl_gt1 = {
770 GEN9_FEATURES,
771 .is_coffeelake = true,
772 .gt = 1,
773
774 .num_slices = 1,
775 .num_subslices = { 2, },
776 .num_eu_per_subslice = 6,
777 .l3_banks = 2,
778 .simulator_id = 24,
779 };
780 static const struct gen_device_info gen_device_info_cfl_gt2 = {
781 GEN9_FEATURES,
782 .is_coffeelake = true,
783 .gt = 2,
784
785 .num_slices = 1,
786 .num_subslices = { 3, },
787 .num_eu_per_subslice = 8,
788 .l3_banks = 4,
789 .simulator_id = 24,
790 };
791
792 static const struct gen_device_info gen_device_info_cfl_gt3 = {
793 GEN9_FEATURES,
794 .is_coffeelake = true,
795 .gt = 3,
796
797 .num_slices = 2,
798 .num_subslices = { 3, 3, },
799 .num_eu_per_subslice = 8,
800 .l3_banks = 8,
801 .simulator_id = 24,
802 };
803
804 #define GEN10_HW_INFO \
805 .gen = 10, \
806 .num_thread_per_eu = 7, \
807 .max_vs_threads = 728, \
808 .max_gs_threads = 432, \
809 .max_tcs_threads = 432, \
810 .max_tes_threads = 624, \
811 .max_cs_threads = 56, \
812 .timestamp_frequency = 19200000, \
813 .urb = { \
814 .size = 256, \
815 .min_entries = { \
816 [MESA_SHADER_VERTEX] = 64, \
817 [MESA_SHADER_TESS_EVAL] = 34, \
818 }, \
819 .max_entries = { \
820 [MESA_SHADER_VERTEX] = 3936, \
821 [MESA_SHADER_TESS_CTRL] = 896, \
822 [MESA_SHADER_TESS_EVAL] = 2064, \
823 [MESA_SHADER_GEOMETRY] = 832, \
824 }, \
825 }
826
827 #define subslices(args...) { args, }
828
829 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
830 GEN8_FEATURES, \
831 GEN10_HW_INFO, \
832 .has_sample_with_hiz = true, \
833 .gt = _gt, \
834 .num_slices = _slices, \
835 .num_subslices = _subslices, \
836 .num_eu_per_subslice = 8, \
837 .l3_banks = _l3
838
839 static const struct gen_device_info gen_device_info_cnl_2x8 = {
840 /* GT0.5 */
841 GEN10_FEATURES(1, 1, subslices(2), 2),
842 .is_cannonlake = true,
843 .simulator_id = 15,
844 };
845
846 static const struct gen_device_info gen_device_info_cnl_3x8 = {
847 /* GT1 */
848 GEN10_FEATURES(1, 1, subslices(3), 3),
849 .is_cannonlake = true,
850 .simulator_id = 15,
851 };
852
853 static const struct gen_device_info gen_device_info_cnl_4x8 = {
854 /* GT 1.5 */
855 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
856 .is_cannonlake = true,
857 .simulator_id = 15,
858 };
859
860 static const struct gen_device_info gen_device_info_cnl_5x8 = {
861 /* GT2 */
862 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
863 .is_cannonlake = true,
864 .simulator_id = 15,
865 };
866
867 #define GEN11_HW_INFO \
868 .gen = 11, \
869 .has_pln = false, \
870 .max_vs_threads = 364, \
871 .max_gs_threads = 224, \
872 .max_tcs_threads = 224, \
873 .max_tes_threads = 364, \
874 .max_cs_threads = 56, \
875 .urb = { \
876 .size = 1024, \
877 .min_entries = { \
878 [MESA_SHADER_VERTEX] = 64, \
879 [MESA_SHADER_TESS_EVAL] = 34, \
880 }, \
881 .max_entries = { \
882 [MESA_SHADER_VERTEX] = 2384, \
883 [MESA_SHADER_TESS_CTRL] = 1032, \
884 [MESA_SHADER_TESS_EVAL] = 2384, \
885 [MESA_SHADER_GEOMETRY] = 1032, \
886 }, \
887 }
888
889 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
890 GEN8_FEATURES, \
891 GEN11_HW_INFO, \
892 .has_64bit_types = false, \
893 .has_integer_dword_mul = false, \
894 .has_sample_with_hiz = false, \
895 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
896 .num_subslices = _subslices, \
897 .num_eu_per_subslice = 8
898
899 static const struct gen_device_info gen_device_info_icl_8x8 = {
900 GEN11_FEATURES(2, 1, subslices(8), 8),
901 .simulator_id = 19,
902 };
903
904 static const struct gen_device_info gen_device_info_icl_6x8 = {
905 GEN11_FEATURES(1, 1, subslices(6), 6),
906 .simulator_id = 19,
907 };
908
909 static const struct gen_device_info gen_device_info_icl_4x8 = {
910 GEN11_FEATURES(1, 1, subslices(4), 6),
911 .simulator_id = 19,
912 };
913
914 static const struct gen_device_info gen_device_info_icl_1x8 = {
915 GEN11_FEATURES(1, 1, subslices(1), 6),
916 .simulator_id = 19,
917 };
918
919 static void
920 gen_device_info_set_eu_mask(struct gen_device_info *devinfo,
921 unsigned slice,
922 unsigned subslice,
923 unsigned eu_mask)
924 {
925 unsigned subslice_offset = slice * devinfo->eu_slice_stride +
926 subslice * devinfo->eu_subslice_stride;
927
928 for (unsigned b_eu = 0; b_eu < devinfo->eu_subslice_stride; b_eu++) {
929 devinfo->eu_masks[subslice_offset + b_eu] =
930 (((1U << devinfo->num_eu_per_subslice) - 1) >> (b_eu * 8)) & 0xff;
931 }
932 }
933
934 /* Generate slice/subslice/eu masks from number of
935 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
936 * structure.
937 *
938 * These can be overridden with values reported by the kernel either from
939 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
940 * through the i915 query uapi.
941 */
942 static void
943 fill_masks(struct gen_device_info *devinfo)
944 {
945 devinfo->slice_masks = (1U << devinfo->num_slices) - 1;
946
947 /* Subslice masks */
948 unsigned max_subslices = 0;
949 for (int s = 0; s < devinfo->num_slices; s++)
950 max_subslices = MAX2(devinfo->num_subslices[s], max_subslices);
951 devinfo->subslice_slice_stride = DIV_ROUND_UP(max_subslices, 8);
952
953 for (int s = 0; s < devinfo->num_slices; s++) {
954 devinfo->subslice_masks[s * devinfo->subslice_slice_stride] =
955 (1U << devinfo->num_subslices[s]) - 1;
956 }
957
958 /* EU masks */
959 devinfo->eu_subslice_stride = DIV_ROUND_UP(devinfo->num_eu_per_subslice, 8);
960 devinfo->eu_slice_stride = max_subslices * devinfo->eu_subslice_stride;
961
962 for (int s = 0; s < devinfo->num_slices; s++) {
963 for (int ss = 0; ss < devinfo->num_subslices[s]; ss++) {
964 gen_device_info_set_eu_mask(devinfo, s, ss,
965 (1U << devinfo->num_eu_per_subslice) - 1);
966 }
967 }
968 }
969
970 void
971 gen_device_info_update_from_masks(struct gen_device_info *devinfo,
972 uint32_t slice_mask,
973 uint32_t subslice_mask,
974 uint32_t n_eus)
975 {
976 struct {
977 struct drm_i915_query_topology_info base;
978 uint8_t data[100];
979 } topology;
980
981 assert((slice_mask & 0xff) == slice_mask);
982
983 memset(&topology, 0, sizeof(topology));
984
985 topology.base.max_slices = util_last_bit(slice_mask);
986 topology.base.max_subslices = util_last_bit(subslice_mask);
987
988 topology.base.subslice_offset = DIV_ROUND_UP(topology.base.max_slices, 8);
989 topology.base.subslice_stride = DIV_ROUND_UP(topology.base.max_subslices, 8);
990
991 uint32_t n_subslices = __builtin_popcount(slice_mask) *
992 __builtin_popcount(subslice_mask);
993 uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
994 uint32_t eu_mask = (1U << num_eu_per_subslice) - 1;
995
996 topology.base.eu_offset = topology.base.subslice_offset +
997 DIV_ROUND_UP(topology.base.max_subslices, 8);
998 topology.base.eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8);
999
1000 /* Set slice mask in topology */
1001 for (int b = 0; b < topology.base.subslice_offset; b++)
1002 topology.base.data[b] = (slice_mask >> (b * 8)) & 0xff;
1003
1004 for (int s = 0; s < topology.base.max_slices; s++) {
1005
1006 /* Set subslice mask in topology */
1007 for (int b = 0; b < topology.base.subslice_stride; b++) {
1008 int subslice_offset = topology.base.subslice_offset +
1009 s * topology.base.subslice_stride + b;
1010
1011 topology.base.data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff;
1012 }
1013
1014 /* Set eu mask in topology */
1015 for (int ss = 0; ss < topology.base.max_subslices; ss++) {
1016 for (int b = 0; b < topology.base.eu_stride; b++) {
1017 int eu_offset = topology.base.eu_offset +
1018 (s * topology.base.max_subslices + ss) * topology.base.eu_stride + b;
1019
1020 topology.base.data[eu_offset] = (eu_mask >> (b * 8)) & 0xff;
1021 }
1022 }
1023 }
1024
1025 gen_device_info_update_from_topology(devinfo, &topology.base);
1026 }
1027
1028 static void
1029 reset_masks(struct gen_device_info *devinfo)
1030 {
1031 devinfo->subslice_slice_stride = 0;
1032 devinfo->eu_subslice_stride = 0;
1033 devinfo->eu_slice_stride = 0;
1034
1035 devinfo->num_slices = 0;
1036 devinfo->num_eu_per_subslice = 0;
1037 memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices));
1038
1039 memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
1040 memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
1041 memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
1042 }
1043
1044 void
1045 gen_device_info_update_from_topology(struct gen_device_info *devinfo,
1046 const struct drm_i915_query_topology_info *topology)
1047 {
1048 reset_masks(devinfo);
1049
1050 devinfo->subslice_slice_stride = topology->subslice_stride;
1051
1052 devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8);
1053 devinfo->eu_slice_stride = topology->max_subslices * devinfo->eu_subslice_stride;
1054
1055 assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8));
1056 memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8));
1057 devinfo->num_slices = __builtin_popcount(devinfo->slice_masks);
1058
1059 uint32_t subslice_mask_len =
1060 topology->max_slices * topology->subslice_stride;
1061 assert(sizeof(devinfo->subslice_masks) >= subslice_mask_len);
1062 memcpy(devinfo->subslice_masks, &topology->data[topology->subslice_offset],
1063 subslice_mask_len);
1064
1065 uint32_t n_subslices = 0;
1066 for (int s = 0; s < topology->max_slices; s++) {
1067 if ((devinfo->slice_masks & (1UL << s)) == 0)
1068 continue;
1069
1070 for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
1071 devinfo->num_subslices[s] +=
1072 __builtin_popcount(devinfo->subslice_masks[b]);
1073 }
1074 n_subslices += devinfo->num_subslices[s];
1075 }
1076 assert(n_subslices > 0);
1077
1078 uint32_t eu_mask_len =
1079 topology->eu_stride * topology->max_subslices * topology->max_slices;
1080 assert(sizeof(devinfo->eu_masks) >= eu_mask_len);
1081 memcpy(devinfo->eu_masks, &topology->data[topology->eu_offset], eu_mask_len);
1082
1083 uint32_t n_eus = 0;
1084 for (int b = 0; b < eu_mask_len; b++)
1085 n_eus += __builtin_popcount(devinfo->eu_masks[b]);
1086
1087 devinfo->num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1088 }
1089
1090 bool
1091 gen_get_device_info(int devid, struct gen_device_info *devinfo)
1092 {
1093 switch (devid) {
1094 #undef CHIPSET
1095 #define CHIPSET(id, family, name) \
1096 case id: *devinfo = gen_device_info_##family; break;
1097 #include "pci_ids/i965_pci_ids.h"
1098 default:
1099 fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
1100 return false;
1101 }
1102
1103 fill_masks(devinfo);
1104
1105 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1106 *
1107 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1108 * allocate scratch space enough so that each slice has 4 slices allowed."
1109 *
1110 * The equivalent internal documentation says that this programming note
1111 * applies to all Gen9+ platforms.
1112 *
1113 * The hardware typically calculates the scratch space pointer by taking
1114 * the base address, and adding per-thread-scratch-space * thread ID.
1115 * Extra padding can be necessary depending how the thread IDs are
1116 * calculated for a particular shader stage.
1117 */
1118
1119 switch(devinfo->gen) {
1120 case 9:
1121 case 10:
1122 devinfo->max_wm_threads = 64 /* threads-per-PSD */
1123 * devinfo->num_slices
1124 * 4; /* effective subslices per slice */
1125 break;
1126 case 11:
1127 devinfo->max_wm_threads = 128 /* threads-per-PSD */
1128 * devinfo->num_slices
1129 * 8; /* subslices per slice */
1130 break;
1131 default:
1132 break;
1133 }
1134
1135 assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
1136
1137 return true;
1138 }
1139
1140 const char *
1141 gen_get_device_name(int devid)
1142 {
1143 switch (devid) {
1144 #undef CHIPSET
1145 #define CHIPSET(id, family, name) case id: return name;
1146 #include "pci_ids/i965_pci_ids.h"
1147 default:
1148 return NULL;
1149 }
1150 }