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intel: Disable loading drivers on DG1 devices for now
[mesa.git] / src / intel / dev / gen_device_info.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <stdio.h>
27 #include <stdlib.h>
28 #include <string.h>
29 #include <unistd.h>
30 #include "gen_device_info.h"
31 #include "compiler/shader_enums.h"
32 #include "intel/common/gen_gem.h"
33 #include "util/bitscan.h"
34 #include "util/macros.h"
35
36 #include "drm-uapi/i915_drm.h"
37
38 static const struct {
39 const char *name;
40 int pci_id;
41 } name_map[] = {
42 { "brw", 0x2a02 },
43 { "g4x", 0x2a42 },
44 { "ilk", 0x0042 },
45 { "snb", 0x0126 },
46 { "ivb", 0x016a },
47 { "hsw", 0x0d2e },
48 { "byt", 0x0f33 },
49 { "bdw", 0x162e },
50 { "chv", 0x22B3 },
51 { "skl", 0x1912 },
52 { "bxt", 0x5A85 },
53 { "kbl", 0x5912 },
54 { "aml", 0x591C },
55 { "glk", 0x3185 },
56 { "cfl", 0x3E9B },
57 { "whl", 0x3EA1 },
58 { "cml", 0x9b41 },
59 { "cnl", 0x5a52 },
60 { "icl", 0x8a52 },
61 { "ehl", 0x4500 },
62 { "jsl", 0x4E71 },
63 { "tgl", 0x9a49 },
64 { "rkl", 0x4c8a },
65 { "dg1", 0x4905 },
66 };
67
68 /**
69 * Get the PCI ID for the device name.
70 *
71 * Returns -1 if the device is not known.
72 */
73 int
74 gen_device_name_to_pci_device_id(const char *name)
75 {
76 for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
77 if (!strcmp(name_map[i].name, name))
78 return name_map[i].pci_id;
79 }
80
81 return -1;
82 }
83
84 static const struct gen_device_info gen_device_info_i965 = {
85 .gen = 4,
86 .has_negative_rhw_bug = true,
87 .num_slices = 1,
88 .num_subslices = { 1, },
89 .num_eu_per_subslice = 8,
90 .num_thread_per_eu = 4,
91 .max_vs_threads = 16,
92 .max_gs_threads = 2,
93 .max_wm_threads = 8 * 4,
94 .urb = {
95 .size = 256,
96 },
97 .timestamp_frequency = 12500000,
98 .simulator_id = -1,
99 };
100
101 static const struct gen_device_info gen_device_info_g4x = {
102 .gen = 4,
103 .has_pln = true,
104 .has_compr4 = true,
105 .has_surface_tile_offset = true,
106 .is_g4x = true,
107 .num_slices = 1,
108 .num_subslices = { 1, },
109 .num_eu_per_subslice = 10,
110 .num_thread_per_eu = 5,
111 .max_vs_threads = 32,
112 .max_gs_threads = 2,
113 .max_wm_threads = 10 * 5,
114 .urb = {
115 .size = 384,
116 },
117 .timestamp_frequency = 12500000,
118 .simulator_id = -1,
119 };
120
121 static const struct gen_device_info gen_device_info_ilk = {
122 .gen = 5,
123 .has_pln = true,
124 .has_compr4 = true,
125 .has_surface_tile_offset = true,
126 .num_slices = 1,
127 .num_subslices = { 1, },
128 .num_eu_per_subslice = 12,
129 .num_thread_per_eu = 6,
130 .max_vs_threads = 72,
131 .max_gs_threads = 32,
132 .max_wm_threads = 12 * 6,
133 .urb = {
134 .size = 1024,
135 },
136 .timestamp_frequency = 12500000,
137 .simulator_id = -1,
138 };
139
140 static const struct gen_device_info gen_device_info_snb_gt1 = {
141 .gen = 6,
142 .gt = 1,
143 .has_hiz_and_separate_stencil = true,
144 .has_llc = true,
145 .has_pln = true,
146 .has_surface_tile_offset = true,
147 .needs_unlit_centroid_workaround = true,
148 .num_slices = 1,
149 .num_subslices = { 1, },
150 .num_eu_per_subslice = 6,
151 .num_thread_per_eu = 6, /* Not confirmed */
152 .max_vs_threads = 24,
153 .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
154 .max_wm_threads = 40,
155 .urb = {
156 .size = 32,
157 .min_entries = {
158 [MESA_SHADER_VERTEX] = 24,
159 },
160 .max_entries = {
161 [MESA_SHADER_VERTEX] = 256,
162 [MESA_SHADER_GEOMETRY] = 256,
163 },
164 },
165 .timestamp_frequency = 12500000,
166 .simulator_id = -1,
167 };
168
169 static const struct gen_device_info gen_device_info_snb_gt2 = {
170 .gen = 6,
171 .gt = 2,
172 .has_hiz_and_separate_stencil = true,
173 .has_llc = true,
174 .has_pln = true,
175 .has_surface_tile_offset = true,
176 .needs_unlit_centroid_workaround = true,
177 .num_slices = 1,
178 .num_subslices = { 1, },
179 .num_eu_per_subslice = 12,
180 .num_thread_per_eu = 6, /* Not confirmed */
181 .max_vs_threads = 60,
182 .max_gs_threads = 60,
183 .max_wm_threads = 80,
184 .urb = {
185 .size = 64,
186 .min_entries = {
187 [MESA_SHADER_VERTEX] = 24,
188 },
189 .max_entries = {
190 [MESA_SHADER_VERTEX] = 256,
191 [MESA_SHADER_GEOMETRY] = 256,
192 },
193 },
194 .timestamp_frequency = 12500000,
195 .simulator_id = -1,
196 };
197
198 #define GEN7_FEATURES \
199 .gen = 7, \
200 .has_hiz_and_separate_stencil = true, \
201 .must_use_separate_stencil = true, \
202 .has_llc = true, \
203 .has_pln = true, \
204 .has_64bit_float = true, \
205 .has_surface_tile_offset = true, \
206 .timestamp_frequency = 12500000
207
208 static const struct gen_device_info gen_device_info_ivb_gt1 = {
209 GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
210 .num_slices = 1,
211 .num_subslices = { 1, },
212 .num_eu_per_subslice = 6,
213 .num_thread_per_eu = 6,
214 .l3_banks = 2,
215 .max_vs_threads = 36,
216 .max_tcs_threads = 36,
217 .max_tes_threads = 36,
218 .max_gs_threads = 36,
219 .max_wm_threads = 48,
220 .max_cs_threads = 36,
221 .urb = {
222 .min_entries = {
223 [MESA_SHADER_VERTEX] = 32,
224 [MESA_SHADER_TESS_EVAL] = 10,
225 },
226 .max_entries = {
227 [MESA_SHADER_VERTEX] = 512,
228 [MESA_SHADER_TESS_CTRL] = 32,
229 [MESA_SHADER_TESS_EVAL] = 288,
230 [MESA_SHADER_GEOMETRY] = 192,
231 },
232 },
233 .simulator_id = 7,
234 };
235
236 static const struct gen_device_info gen_device_info_ivb_gt2 = {
237 GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
238 .num_slices = 1,
239 .num_subslices = { 1, },
240 .num_eu_per_subslice = 12,
241 .num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
242 * @max_wm_threads ... */
243 .l3_banks = 4,
244 .max_vs_threads = 128,
245 .max_tcs_threads = 128,
246 .max_tes_threads = 128,
247 .max_gs_threads = 128,
248 .max_wm_threads = 172,
249 .max_cs_threads = 64,
250 .urb = {
251 .min_entries = {
252 [MESA_SHADER_VERTEX] = 32,
253 [MESA_SHADER_TESS_EVAL] = 10,
254 },
255 .max_entries = {
256 [MESA_SHADER_VERTEX] = 704,
257 [MESA_SHADER_TESS_CTRL] = 64,
258 [MESA_SHADER_TESS_EVAL] = 448,
259 [MESA_SHADER_GEOMETRY] = 320,
260 },
261 },
262 .simulator_id = 7,
263 };
264
265 static const struct gen_device_info gen_device_info_byt = {
266 GEN7_FEATURES, .is_baytrail = true, .gt = 1,
267 .num_slices = 1,
268 .num_subslices = { 1, },
269 .num_eu_per_subslice = 4,
270 .num_thread_per_eu = 8,
271 .l3_banks = 1,
272 .has_llc = false,
273 .max_vs_threads = 36,
274 .max_tcs_threads = 36,
275 .max_tes_threads = 36,
276 .max_gs_threads = 36,
277 .max_wm_threads = 48,
278 .max_cs_threads = 32,
279 .urb = {
280 .min_entries = {
281 [MESA_SHADER_VERTEX] = 32,
282 [MESA_SHADER_TESS_EVAL] = 10,
283 },
284 .max_entries = {
285 [MESA_SHADER_VERTEX] = 512,
286 [MESA_SHADER_TESS_CTRL] = 32,
287 [MESA_SHADER_TESS_EVAL] = 288,
288 [MESA_SHADER_GEOMETRY] = 192,
289 },
290 },
291 .simulator_id = 10,
292 };
293
294 #define HSW_FEATURES \
295 GEN7_FEATURES, \
296 .is_haswell = true, \
297 .supports_simd16_3src = true, \
298 .has_resource_streamer = true
299
300 static const struct gen_device_info gen_device_info_hsw_gt1 = {
301 HSW_FEATURES, .gt = 1,
302 .num_slices = 1,
303 .num_subslices = { 1, },
304 .num_eu_per_subslice = 10,
305 .num_thread_per_eu = 7,
306 .l3_banks = 2,
307 .max_vs_threads = 70,
308 .max_tcs_threads = 70,
309 .max_tes_threads = 70,
310 .max_gs_threads = 70,
311 .max_wm_threads = 102,
312 .max_cs_threads = 70,
313 .urb = {
314 .min_entries = {
315 [MESA_SHADER_VERTEX] = 32,
316 [MESA_SHADER_TESS_EVAL] = 10,
317 },
318 .max_entries = {
319 [MESA_SHADER_VERTEX] = 640,
320 [MESA_SHADER_TESS_CTRL] = 64,
321 [MESA_SHADER_TESS_EVAL] = 384,
322 [MESA_SHADER_GEOMETRY] = 256,
323 },
324 },
325 .simulator_id = 9,
326 };
327
328 static const struct gen_device_info gen_device_info_hsw_gt2 = {
329 HSW_FEATURES, .gt = 2,
330 .num_slices = 1,
331 .num_subslices = { 2, },
332 .num_eu_per_subslice = 10,
333 .num_thread_per_eu = 7,
334 .l3_banks = 4,
335 .max_vs_threads = 280,
336 .max_tcs_threads = 256,
337 .max_tes_threads = 280,
338 .max_gs_threads = 256,
339 .max_wm_threads = 204,
340 .max_cs_threads = 70,
341 .urb = {
342 .min_entries = {
343 [MESA_SHADER_VERTEX] = 64,
344 [MESA_SHADER_TESS_EVAL] = 10,
345 },
346 .max_entries = {
347 [MESA_SHADER_VERTEX] = 1664,
348 [MESA_SHADER_TESS_CTRL] = 128,
349 [MESA_SHADER_TESS_EVAL] = 960,
350 [MESA_SHADER_GEOMETRY] = 640,
351 },
352 },
353 .simulator_id = 9,
354 };
355
356 static const struct gen_device_info gen_device_info_hsw_gt3 = {
357 HSW_FEATURES, .gt = 3,
358 .num_slices = 2,
359 .num_subslices = { 2, },
360 .num_eu_per_subslice = 10,
361 .num_thread_per_eu = 7,
362 .l3_banks = 8,
363 .max_vs_threads = 280,
364 .max_tcs_threads = 256,
365 .max_tes_threads = 280,
366 .max_gs_threads = 256,
367 .max_wm_threads = 408,
368 .max_cs_threads = 70,
369 .urb = {
370 .min_entries = {
371 [MESA_SHADER_VERTEX] = 64,
372 [MESA_SHADER_TESS_EVAL] = 10,
373 },
374 .max_entries = {
375 [MESA_SHADER_VERTEX] = 1664,
376 [MESA_SHADER_TESS_CTRL] = 128,
377 [MESA_SHADER_TESS_EVAL] = 960,
378 [MESA_SHADER_GEOMETRY] = 640,
379 },
380 },
381 .simulator_id = 9,
382 };
383
384 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
385 * so keep things conservative for now and set has_sample_with_hiz = false.
386 */
387 #define GEN8_FEATURES \
388 .gen = 8, \
389 .has_hiz_and_separate_stencil = true, \
390 .has_resource_streamer = true, \
391 .must_use_separate_stencil = true, \
392 .has_llc = true, \
393 .has_sample_with_hiz = false, \
394 .has_pln = true, \
395 .has_integer_dword_mul = true, \
396 .has_64bit_float = true, \
397 .has_64bit_int = true, \
398 .supports_simd16_3src = true, \
399 .has_surface_tile_offset = true, \
400 .num_thread_per_eu = 7, \
401 .max_vs_threads = 504, \
402 .max_tcs_threads = 504, \
403 .max_tes_threads = 504, \
404 .max_gs_threads = 504, \
405 .max_wm_threads = 384, \
406 .timestamp_frequency = 12500000
407
408 static const struct gen_device_info gen_device_info_bdw_gt1 = {
409 GEN8_FEATURES, .gt = 1,
410 .is_broadwell = true,
411 .num_slices = 1,
412 .num_subslices = { 2, },
413 .num_eu_per_subslice = 6,
414 .l3_banks = 2,
415 .max_cs_threads = 42,
416 .urb = {
417 .min_entries = {
418 [MESA_SHADER_VERTEX] = 64,
419 [MESA_SHADER_TESS_EVAL] = 34,
420 },
421 .max_entries = {
422 [MESA_SHADER_VERTEX] = 2560,
423 [MESA_SHADER_TESS_CTRL] = 504,
424 [MESA_SHADER_TESS_EVAL] = 1536,
425 /* Reduced from 960, seems to be similar to the bug on Gen9 GT1. */
426 [MESA_SHADER_GEOMETRY] = 690,
427 },
428 },
429 .simulator_id = 11,
430 };
431
432 static const struct gen_device_info gen_device_info_bdw_gt2 = {
433 GEN8_FEATURES, .gt = 2,
434 .is_broadwell = true,
435 .num_slices = 1,
436 .num_subslices = { 3, },
437 .num_eu_per_subslice = 8,
438 .l3_banks = 4,
439 .max_cs_threads = 56,
440 .urb = {
441 .min_entries = {
442 [MESA_SHADER_VERTEX] = 64,
443 [MESA_SHADER_TESS_EVAL] = 34,
444 },
445 .max_entries = {
446 [MESA_SHADER_VERTEX] = 2560,
447 [MESA_SHADER_TESS_CTRL] = 504,
448 [MESA_SHADER_TESS_EVAL] = 1536,
449 [MESA_SHADER_GEOMETRY] = 960,
450 },
451 },
452 .simulator_id = 11,
453 };
454
455 static const struct gen_device_info gen_device_info_bdw_gt3 = {
456 GEN8_FEATURES, .gt = 3,
457 .is_broadwell = true,
458 .num_slices = 2,
459 .num_subslices = { 3, 3, },
460 .num_eu_per_subslice = 8,
461 .l3_banks = 8,
462 .max_cs_threads = 56,
463 .urb = {
464 .min_entries = {
465 [MESA_SHADER_VERTEX] = 64,
466 [MESA_SHADER_TESS_EVAL] = 34,
467 },
468 .max_entries = {
469 [MESA_SHADER_VERTEX] = 2560,
470 [MESA_SHADER_TESS_CTRL] = 504,
471 [MESA_SHADER_TESS_EVAL] = 1536,
472 [MESA_SHADER_GEOMETRY] = 960,
473 },
474 },
475 .simulator_id = 11,
476 };
477
478 static const struct gen_device_info gen_device_info_chv = {
479 GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
480 .has_llc = false,
481 .has_integer_dword_mul = false,
482 .num_slices = 1,
483 .num_subslices = { 2, },
484 .num_eu_per_subslice = 8,
485 .l3_banks = 2,
486 .max_vs_threads = 80,
487 .max_tcs_threads = 80,
488 .max_tes_threads = 80,
489 .max_gs_threads = 80,
490 .max_wm_threads = 128,
491 .max_cs_threads = 6 * 7,
492 .urb = {
493 .min_entries = {
494 [MESA_SHADER_VERTEX] = 34,
495 [MESA_SHADER_TESS_EVAL] = 34,
496 },
497 .max_entries = {
498 [MESA_SHADER_VERTEX] = 640,
499 [MESA_SHADER_TESS_CTRL] = 80,
500 [MESA_SHADER_TESS_EVAL] = 384,
501 [MESA_SHADER_GEOMETRY] = 256,
502 },
503 },
504 .simulator_id = 13,
505 };
506
507 #define GEN9_HW_INFO \
508 .gen = 9, \
509 .max_vs_threads = 336, \
510 .max_gs_threads = 336, \
511 .max_tcs_threads = 336, \
512 .max_tes_threads = 336, \
513 .max_cs_threads = 56, \
514 .timestamp_frequency = 12000000, \
515 .urb = { \
516 .min_entries = { \
517 [MESA_SHADER_VERTEX] = 64, \
518 [MESA_SHADER_TESS_EVAL] = 34, \
519 }, \
520 .max_entries = { \
521 [MESA_SHADER_VERTEX] = 1856, \
522 [MESA_SHADER_TESS_CTRL] = 672, \
523 [MESA_SHADER_TESS_EVAL] = 1120, \
524 [MESA_SHADER_GEOMETRY] = 640, \
525 }, \
526 }
527
528 #define GEN9_LP_FEATURES \
529 GEN8_FEATURES, \
530 GEN9_HW_INFO, \
531 .has_integer_dword_mul = false, \
532 .gt = 1, \
533 .has_llc = false, \
534 .has_sample_with_hiz = true, \
535 .num_slices = 1, \
536 .num_thread_per_eu = 6, \
537 .max_vs_threads = 112, \
538 .max_tcs_threads = 112, \
539 .max_tes_threads = 112, \
540 .max_gs_threads = 112, \
541 .max_cs_threads = 6 * 6, \
542 .timestamp_frequency = 19200000, \
543 .urb = { \
544 .min_entries = { \
545 [MESA_SHADER_VERTEX] = 34, \
546 [MESA_SHADER_TESS_EVAL] = 34, \
547 }, \
548 .max_entries = { \
549 [MESA_SHADER_VERTEX] = 704, \
550 [MESA_SHADER_TESS_CTRL] = 256, \
551 [MESA_SHADER_TESS_EVAL] = 416, \
552 [MESA_SHADER_GEOMETRY] = 256, \
553 }, \
554 }
555
556 #define GEN9_LP_FEATURES_3X6 \
557 GEN9_LP_FEATURES, \
558 .num_subslices = { 3, }, \
559 .num_eu_per_subslice = 6
560
561 #define GEN9_LP_FEATURES_2X6 \
562 GEN9_LP_FEATURES, \
563 .num_subslices = { 2, }, \
564 .num_eu_per_subslice = 6, \
565 .max_vs_threads = 56, \
566 .max_tcs_threads = 56, \
567 .max_tes_threads = 56, \
568 .max_gs_threads = 56, \
569 .max_cs_threads = 6 * 6, \
570 .urb = { \
571 .min_entries = { \
572 [MESA_SHADER_VERTEX] = 34, \
573 [MESA_SHADER_TESS_EVAL] = 34, \
574 }, \
575 .max_entries = { \
576 [MESA_SHADER_VERTEX] = 352, \
577 [MESA_SHADER_TESS_CTRL] = 128, \
578 [MESA_SHADER_TESS_EVAL] = 208, \
579 [MESA_SHADER_GEOMETRY] = 128, \
580 }, \
581 }
582
583 #define GEN9_FEATURES \
584 GEN8_FEATURES, \
585 GEN9_HW_INFO, \
586 .has_sample_with_hiz = true
587
588 static const struct gen_device_info gen_device_info_skl_gt1 = {
589 GEN9_FEATURES, .gt = 1,
590 .is_skylake = true,
591 .num_slices = 1,
592 .num_subslices = { 2, },
593 .num_eu_per_subslice = 6,
594 .l3_banks = 2,
595 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
596 * leading to some vertices to go missing if we use too much URB.
597 */
598 .urb.max_entries[MESA_SHADER_VERTEX] = 928,
599 .simulator_id = 12,
600 };
601
602 static const struct gen_device_info gen_device_info_skl_gt2 = {
603 GEN9_FEATURES, .gt = 2,
604 .is_skylake = true,
605 .num_slices = 1,
606 .num_subslices = { 3, },
607 .num_eu_per_subslice = 8,
608 .l3_banks = 4,
609 .simulator_id = 12,
610 };
611
612 static const struct gen_device_info gen_device_info_skl_gt3 = {
613 GEN9_FEATURES, .gt = 3,
614 .is_skylake = true,
615 .num_slices = 2,
616 .num_subslices = { 3, 3, },
617 .num_eu_per_subslice = 8,
618 .l3_banks = 8,
619 .simulator_id = 12,
620 };
621
622 static const struct gen_device_info gen_device_info_skl_gt4 = {
623 GEN9_FEATURES, .gt = 4,
624 .is_skylake = true,
625 .num_slices = 3,
626 .num_subslices = { 3, 3, 3, },
627 .num_eu_per_subslice = 8,
628 .l3_banks = 12,
629 /* From the "L3 Allocation and Programming" documentation:
630 *
631 * "URB is limited to 1008KB due to programming restrictions. This is not a
632 * restriction of the L3 implementation, but of the FF and other clients.
633 * Therefore, in a GT4 implementation it is possible for the programmed
634 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
635 * only 1008KB of this will be used."
636 */
637 .simulator_id = 12,
638 };
639
640 static const struct gen_device_info gen_device_info_bxt = {
641 GEN9_LP_FEATURES_3X6,
642 .is_broxton = true,
643 .l3_banks = 2,
644 .simulator_id = 14,
645 };
646
647 static const struct gen_device_info gen_device_info_bxt_2x6 = {
648 GEN9_LP_FEATURES_2X6,
649 .is_broxton = true,
650 .l3_banks = 1,
651 .simulator_id = 14,
652 };
653 /*
654 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
655 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
656 */
657
658 static const struct gen_device_info gen_device_info_kbl_gt1 = {
659 GEN9_FEATURES,
660 .is_kabylake = true,
661 .gt = 1,
662
663 .max_cs_threads = 7 * 6,
664 .num_slices = 1,
665 .num_subslices = { 2, },
666 .num_eu_per_subslice = 6,
667 .l3_banks = 2,
668 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
669 * leading to some vertices to go missing if we use too much URB.
670 */
671 .urb.max_entries[MESA_SHADER_VERTEX] = 928,
672 .simulator_id = 16,
673 };
674
675 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
676 GEN9_FEATURES,
677 .is_kabylake = true,
678 .gt = 1,
679
680 .max_cs_threads = 7 * 6,
681 .num_slices = 1,
682 .num_subslices = { 3, },
683 .num_eu_per_subslice = 6,
684 .l3_banks = 4,
685 .simulator_id = 16,
686 };
687
688 static const struct gen_device_info gen_device_info_kbl_gt2 = {
689 GEN9_FEATURES,
690 .is_kabylake = true,
691 .gt = 2,
692
693 .num_slices = 1,
694 .num_subslices = { 3, },
695 .num_eu_per_subslice = 8,
696 .l3_banks = 4,
697 .simulator_id = 16,
698 };
699
700 static const struct gen_device_info gen_device_info_kbl_gt3 = {
701 GEN9_FEATURES,
702 .is_kabylake = true,
703 .gt = 3,
704
705 .num_slices = 2,
706 .num_subslices = { 3, 3, },
707 .num_eu_per_subslice = 8,
708 .l3_banks = 8,
709 .simulator_id = 16,
710 };
711
712 static const struct gen_device_info gen_device_info_kbl_gt4 = {
713 GEN9_FEATURES,
714 .is_kabylake = true,
715 .gt = 4,
716
717 /*
718 * From the "L3 Allocation and Programming" documentation:
719 *
720 * "URB is limited to 1008KB due to programming restrictions. This
721 * is not a restriction of the L3 implementation, but of the FF and
722 * other clients. Therefore, in a GT4 implementation it is
723 * possible for the programmed allocation of the L3 data array to
724 * provide 3*384KB=1152KB for URB, but only 1008KB of this
725 * will be used."
726 */
727 .num_slices = 3,
728 .num_subslices = { 3, 3, 3, },
729 .num_eu_per_subslice = 8,
730 .l3_banks = 12,
731 .simulator_id = 16,
732 };
733
734 static const struct gen_device_info gen_device_info_glk = {
735 GEN9_LP_FEATURES_3X6,
736 .is_geminilake = true,
737 .l3_banks = 2,
738 .simulator_id = 17,
739 };
740
741 static const struct gen_device_info gen_device_info_glk_2x6 = {
742 GEN9_LP_FEATURES_2X6,
743 .is_geminilake = true,
744 .l3_banks = 2,
745 .simulator_id = 17,
746 };
747
748 static const struct gen_device_info gen_device_info_cfl_gt1 = {
749 GEN9_FEATURES,
750 .is_coffeelake = true,
751 .gt = 1,
752
753 .num_slices = 1,
754 .num_subslices = { 2, },
755 .num_eu_per_subslice = 6,
756 .l3_banks = 2,
757 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
758 * leading to some vertices to go missing if we use too much URB.
759 */
760 .urb.max_entries[MESA_SHADER_VERTEX] = 928,
761 .simulator_id = 24,
762 };
763 static const struct gen_device_info gen_device_info_cfl_gt2 = {
764 GEN9_FEATURES,
765 .is_coffeelake = true,
766 .gt = 2,
767
768 .num_slices = 1,
769 .num_subslices = { 3, },
770 .num_eu_per_subslice = 8,
771 .l3_banks = 4,
772 .simulator_id = 24,
773 };
774
775 static const struct gen_device_info gen_device_info_cfl_gt3 = {
776 GEN9_FEATURES,
777 .is_coffeelake = true,
778 .gt = 3,
779
780 .num_slices = 2,
781 .num_subslices = { 3, 3, },
782 .num_eu_per_subslice = 8,
783 .l3_banks = 8,
784 .simulator_id = 24,
785 };
786
787 #define GEN10_HW_INFO \
788 .gen = 10, \
789 .num_thread_per_eu = 7, \
790 .max_vs_threads = 728, \
791 .max_gs_threads = 432, \
792 .max_tcs_threads = 432, \
793 .max_tes_threads = 624, \
794 .max_cs_threads = 56, \
795 .timestamp_frequency = 19200000, \
796 .urb = { \
797 .min_entries = { \
798 [MESA_SHADER_VERTEX] = 64, \
799 [MESA_SHADER_TESS_EVAL] = 34, \
800 }, \
801 .max_entries = { \
802 [MESA_SHADER_VERTEX] = 3936, \
803 [MESA_SHADER_TESS_CTRL] = 896, \
804 [MESA_SHADER_TESS_EVAL] = 2064, \
805 [MESA_SHADER_GEOMETRY] = 832, \
806 }, \
807 }
808
809 #define subslices(args...) { args, }
810
811 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
812 GEN8_FEATURES, \
813 GEN10_HW_INFO, \
814 .has_sample_with_hiz = true, \
815 .gt = _gt, \
816 .num_slices = _slices, \
817 .num_subslices = _subslices, \
818 .num_eu_per_subslice = 8, \
819 .l3_banks = _l3
820
821 static const struct gen_device_info gen_device_info_cnl_gt0_5 = {
822 /* GT0.5 */
823 GEN10_FEATURES(1, 1, subslices(2), 2),
824 .is_cannonlake = true,
825 .simulator_id = 15,
826 };
827
828 static const struct gen_device_info gen_device_info_cnl_gt1 = {
829 /* GT1 */
830 GEN10_FEATURES(1, 1, subslices(3), 3),
831 .is_cannonlake = true,
832 .simulator_id = 15,
833 };
834
835 static const struct gen_device_info gen_device_info_cnl_gt1_5 = {
836 /* GT 1.5 */
837 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
838 .is_cannonlake = true,
839 .simulator_id = 15,
840 };
841
842 static const struct gen_device_info gen_device_info_cnl_gt2 = {
843 /* GT2 */
844 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
845 .is_cannonlake = true,
846 .simulator_id = 15,
847 };
848
849 #define GEN11_HW_INFO \
850 .gen = 11, \
851 .has_pln = false, \
852 .max_vs_threads = 364, \
853 .max_gs_threads = 224, \
854 .max_tcs_threads = 224, \
855 .max_tes_threads = 364, \
856 .max_cs_threads = 56
857
858 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
859 GEN8_FEATURES, \
860 GEN11_HW_INFO, \
861 .has_64bit_float = false, \
862 .has_64bit_int = false, \
863 .has_integer_dword_mul = false, \
864 .has_sample_with_hiz = false, \
865 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
866 .num_subslices = _subslices, \
867 .num_eu_per_subslice = 8
868
869 #define GEN11_URB_MIN_MAX_ENTRIES \
870 .min_entries = { \
871 [MESA_SHADER_VERTEX] = 64, \
872 [MESA_SHADER_TESS_EVAL] = 34, \
873 }, \
874 .max_entries = { \
875 [MESA_SHADER_VERTEX] = 2384, \
876 [MESA_SHADER_TESS_CTRL] = 1032, \
877 [MESA_SHADER_TESS_EVAL] = 2384, \
878 [MESA_SHADER_GEOMETRY] = 1032, \
879 }
880
881 static const struct gen_device_info gen_device_info_icl_gt2 = {
882 GEN11_FEATURES(2, 1, subslices(8), 8),
883 .urb = {
884 GEN11_URB_MIN_MAX_ENTRIES,
885 },
886 .simulator_id = 19,
887 };
888
889 static const struct gen_device_info gen_device_info_icl_gt1_5 = {
890 GEN11_FEATURES(1, 1, subslices(6), 6),
891 .urb = {
892 GEN11_URB_MIN_MAX_ENTRIES,
893 },
894 .simulator_id = 19,
895 };
896
897 static const struct gen_device_info gen_device_info_icl_gt1 = {
898 GEN11_FEATURES(1, 1, subslices(4), 6),
899 .urb = {
900 GEN11_URB_MIN_MAX_ENTRIES,
901 },
902 .simulator_id = 19,
903 };
904
905 static const struct gen_device_info gen_device_info_icl_gt0_5 = {
906 GEN11_FEATURES(1, 1, subslices(1), 6),
907 .urb = {
908 GEN11_URB_MIN_MAX_ENTRIES,
909 },
910 .simulator_id = 19,
911 };
912
913 static const struct gen_device_info gen_device_info_ehl_7 = {
914 GEN11_FEATURES(1, 1, subslices(4), 4),
915 .is_elkhartlake = true,
916 .urb = {
917 .min_entries = {
918 [MESA_SHADER_VERTEX] = 64,
919 [MESA_SHADER_TESS_EVAL] = 34,
920 },
921 .max_entries = {
922 [MESA_SHADER_VERTEX] = 2384,
923 [MESA_SHADER_TESS_CTRL] = 1032,
924 [MESA_SHADER_TESS_EVAL] = 2384,
925 [MESA_SHADER_GEOMETRY] = 1032,
926 },
927 },
928 .disable_ccs_repack = true,
929 .simulator_id = 28,
930 };
931
932 static const struct gen_device_info gen_device_info_ehl_6 = {
933 GEN11_FEATURES(1, 1, subslices(4), 4),
934 .is_elkhartlake = true,
935 .urb = {
936 .min_entries = {
937 [MESA_SHADER_VERTEX] = 64,
938 [MESA_SHADER_TESS_EVAL] = 34,
939 },
940 .max_entries = {
941 [MESA_SHADER_VERTEX] = 2384,
942 [MESA_SHADER_TESS_CTRL] = 1032,
943 [MESA_SHADER_TESS_EVAL] = 2384,
944 [MESA_SHADER_GEOMETRY] = 1032,
945 },
946 },
947 .disable_ccs_repack = true,
948 .num_eu_per_subslice = 6,
949 .simulator_id = 28,
950 };
951
952 static const struct gen_device_info gen_device_info_ehl_5 = {
953 GEN11_FEATURES(1, 1, subslices(4), 4),
954 .is_elkhartlake = true,
955 .urb = {
956 .min_entries = {
957 [MESA_SHADER_VERTEX] = 64,
958 [MESA_SHADER_TESS_EVAL] = 34,
959 },
960 .max_entries = {
961 [MESA_SHADER_VERTEX] = 2384,
962 [MESA_SHADER_TESS_CTRL] = 1032,
963 [MESA_SHADER_TESS_EVAL] = 2384,
964 [MESA_SHADER_GEOMETRY] = 1032,
965 },
966 },
967 .disable_ccs_repack = true,
968 .num_eu_per_subslice = 4,
969 .simulator_id = 28,
970 };
971
972 static const struct gen_device_info gen_device_info_ehl_4 = {
973 GEN11_FEATURES(1, 1, subslices(2), 4),
974 .is_elkhartlake = true,
975 .urb = {
976 .min_entries = {
977 [MESA_SHADER_VERTEX] = 64,
978 [MESA_SHADER_TESS_EVAL] = 34,
979 },
980 .max_entries = {
981 [MESA_SHADER_VERTEX] = 2384,
982 [MESA_SHADER_TESS_CTRL] = 1032,
983 [MESA_SHADER_TESS_EVAL] = 2384,
984 [MESA_SHADER_GEOMETRY] = 1032,
985 },
986 },
987 .disable_ccs_repack = true,
988 .num_eu_per_subslice =4,
989 .simulator_id = 28,
990 };
991
992 #define GEN12_URB_MIN_MAX_ENTRIES \
993 .min_entries = { \
994 [MESA_SHADER_VERTEX] = 64, \
995 [MESA_SHADER_TESS_EVAL] = 34, \
996 }, \
997 .max_entries = { \
998 [MESA_SHADER_VERTEX] = 3576, \
999 [MESA_SHADER_TESS_CTRL] = 1548, \
1000 [MESA_SHADER_TESS_EVAL] = 3576, \
1001 [MESA_SHADER_GEOMETRY] = 1548, \
1002 }
1003
1004 #define GEN12_HW_INFO \
1005 .gen = 12, \
1006 .has_pln = false, \
1007 .has_sample_with_hiz = false, \
1008 .has_aux_map = true, \
1009 .max_vs_threads = 546, \
1010 .max_gs_threads = 336, \
1011 .max_tcs_threads = 336, \
1012 .max_tes_threads = 546, \
1013 .max_cs_threads = 112, /* threads per DSS */ \
1014 .urb = { \
1015 GEN12_URB_MIN_MAX_ENTRIES, \
1016 }
1017
1018 #define GEN12_FEATURES(_gt, _slices, _l3) \
1019 GEN8_FEATURES, \
1020 GEN12_HW_INFO, \
1021 .has_64bit_float = false, \
1022 .has_64bit_int = false, \
1023 .has_integer_dword_mul = false, \
1024 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
1025 .simulator_id = 22, \
1026 .num_eu_per_subslice = 16
1027
1028 #define dual_subslices(args...) { args, }
1029
1030 #define GEN12_GT05_FEATURES \
1031 GEN12_FEATURES(1, 1, 4), \
1032 .num_subslices = dual_subslices(1)
1033
1034 #define GEN12_GT_FEATURES(_gt) \
1035 GEN12_FEATURES(_gt, 1, _gt == 1 ? 4 : 8), \
1036 .num_subslices = dual_subslices(_gt == 1 ? 2 : 6)
1037
1038 static const struct gen_device_info gen_device_info_tgl_gt1 = {
1039 GEN12_GT_FEATURES(1),
1040 };
1041
1042 static const struct gen_device_info gen_device_info_tgl_gt2 = {
1043 GEN12_GT_FEATURES(2),
1044 };
1045
1046 static const struct gen_device_info gen_device_info_rkl_gt05 = {
1047 GEN12_GT05_FEATURES,
1048 };
1049
1050 static const struct gen_device_info gen_device_info_rkl_gt1 = {
1051 GEN12_GT_FEATURES(1),
1052 };
1053
1054 #define GEN12_DG1_FEATURES \
1055 GEN12_GT_FEATURES(2), \
1056 .is_dg1 = true, \
1057 .has_llc = false, \
1058 .urb.size = 768, \
1059 .simulator_id = 30
1060
1061 UNUSED static const struct gen_device_info gen_device_info_dg1 = {
1062 GEN12_DG1_FEATURES,
1063 };
1064
1065 static void
1066 gen_device_info_set_eu_mask(struct gen_device_info *devinfo,
1067 unsigned slice,
1068 unsigned subslice,
1069 unsigned eu_mask)
1070 {
1071 unsigned subslice_offset = slice * devinfo->eu_slice_stride +
1072 subslice * devinfo->eu_subslice_stride;
1073
1074 for (unsigned b_eu = 0; b_eu < devinfo->eu_subslice_stride; b_eu++) {
1075 devinfo->eu_masks[subslice_offset + b_eu] =
1076 (((1U << devinfo->num_eu_per_subslice) - 1) >> (b_eu * 8)) & 0xff;
1077 }
1078 }
1079
1080 /* Generate slice/subslice/eu masks from number of
1081 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1082 * structure.
1083 *
1084 * These can be overridden with values reported by the kernel either from
1085 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1086 * through the i915 query uapi.
1087 */
1088 static void
1089 fill_masks(struct gen_device_info *devinfo)
1090 {
1091 devinfo->slice_masks = (1U << devinfo->num_slices) - 1;
1092
1093 /* Subslice masks */
1094 unsigned max_subslices = 0;
1095 for (int s = 0; s < devinfo->num_slices; s++)
1096 max_subslices = MAX2(devinfo->num_subslices[s], max_subslices);
1097 devinfo->subslice_slice_stride = DIV_ROUND_UP(max_subslices, 8);
1098
1099 for (int s = 0; s < devinfo->num_slices; s++) {
1100 devinfo->subslice_masks[s * devinfo->subslice_slice_stride] =
1101 (1U << devinfo->num_subslices[s]) - 1;
1102 }
1103
1104 /* EU masks */
1105 devinfo->eu_subslice_stride = DIV_ROUND_UP(devinfo->num_eu_per_subslice, 8);
1106 devinfo->eu_slice_stride = max_subslices * devinfo->eu_subslice_stride;
1107
1108 for (int s = 0; s < devinfo->num_slices; s++) {
1109 for (int ss = 0; ss < devinfo->num_subslices[s]; ss++) {
1110 gen_device_info_set_eu_mask(devinfo, s, ss,
1111 (1U << devinfo->num_eu_per_subslice) - 1);
1112 }
1113 }
1114 }
1115
1116 static void
1117 reset_masks(struct gen_device_info *devinfo)
1118 {
1119 devinfo->subslice_slice_stride = 0;
1120 devinfo->eu_subslice_stride = 0;
1121 devinfo->eu_slice_stride = 0;
1122
1123 devinfo->num_slices = 0;
1124 devinfo->num_eu_per_subslice = 0;
1125 memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices));
1126
1127 memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
1128 memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
1129 memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
1130 memset(devinfo->ppipe_subslices, 0, sizeof(devinfo->ppipe_subslices));
1131 }
1132
1133 static void
1134 update_from_topology(struct gen_device_info *devinfo,
1135 const struct drm_i915_query_topology_info *topology)
1136 {
1137 reset_masks(devinfo);
1138
1139 devinfo->subslice_slice_stride = topology->subslice_stride;
1140
1141 devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8);
1142 devinfo->eu_slice_stride = topology->max_subslices * devinfo->eu_subslice_stride;
1143
1144 assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8));
1145 memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8));
1146 devinfo->num_slices = __builtin_popcount(devinfo->slice_masks);
1147
1148 uint32_t subslice_mask_len =
1149 topology->max_slices * topology->subslice_stride;
1150 assert(sizeof(devinfo->subslice_masks) >= subslice_mask_len);
1151 memcpy(devinfo->subslice_masks, &topology->data[topology->subslice_offset],
1152 subslice_mask_len);
1153
1154 uint32_t n_subslices = 0;
1155 for (int s = 0; s < topology->max_slices; s++) {
1156 if ((devinfo->slice_masks & (1 << s)) == 0)
1157 continue;
1158
1159 for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
1160 devinfo->num_subslices[s] +=
1161 __builtin_popcount(devinfo->subslice_masks[s * devinfo->subslice_slice_stride + b]);
1162 }
1163 n_subslices += devinfo->num_subslices[s];
1164 }
1165 assert(n_subslices > 0);
1166
1167 if (devinfo->gen == 11) {
1168 /* On ICL we only have one slice */
1169 assert(devinfo->slice_masks == 1);
1170
1171 /* Count the number of subslices on each pixel pipe. Assume that
1172 * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
1173 */
1174 unsigned subslices = devinfo->subslice_masks[0];
1175 unsigned ss = 0;
1176 while (subslices > 0) {
1177 if (subslices & 1)
1178 devinfo->ppipe_subslices[ss >= 4 ? 1 : 0] += 1;
1179 subslices >>= 1;
1180 ss++;
1181 }
1182 }
1183
1184 if (devinfo->gen == 12 && devinfo->num_slices == 1) {
1185 if (n_subslices >= 6) {
1186 assert(n_subslices == 6);
1187 devinfo->l3_banks = 8;
1188 } else if (n_subslices > 2) {
1189 devinfo->l3_banks = 6;
1190 } else {
1191 devinfo->l3_banks = 4;
1192 }
1193 }
1194
1195 uint32_t eu_mask_len =
1196 topology->eu_stride * topology->max_subslices * topology->max_slices;
1197 assert(sizeof(devinfo->eu_masks) >= eu_mask_len);
1198 memcpy(devinfo->eu_masks, &topology->data[topology->eu_offset], eu_mask_len);
1199
1200 uint32_t n_eus = 0;
1201 for (int b = 0; b < eu_mask_len; b++)
1202 n_eus += __builtin_popcount(devinfo->eu_masks[b]);
1203
1204 devinfo->num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1205 }
1206
1207 static bool
1208 update_from_masks(struct gen_device_info *devinfo, uint32_t slice_mask,
1209 uint32_t subslice_mask, uint32_t n_eus)
1210 {
1211 struct drm_i915_query_topology_info *topology;
1212
1213 assert((slice_mask & 0xff) == slice_mask);
1214
1215 size_t data_length = 100;
1216
1217 topology = calloc(1, sizeof(*topology) + data_length);
1218 if (!topology)
1219 return false;
1220
1221 topology->max_slices = util_last_bit(slice_mask);
1222 topology->max_subslices = util_last_bit(subslice_mask);
1223
1224 topology->subslice_offset = DIV_ROUND_UP(topology->max_slices, 8);
1225 topology->subslice_stride = DIV_ROUND_UP(topology->max_subslices, 8);
1226
1227 uint32_t n_subslices = __builtin_popcount(slice_mask) *
1228 __builtin_popcount(subslice_mask);
1229 uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1230 uint32_t eu_mask = (1U << num_eu_per_subslice) - 1;
1231
1232 topology->eu_offset = topology->subslice_offset +
1233 DIV_ROUND_UP(topology->max_subslices, 8);
1234 topology->eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8);
1235
1236 /* Set slice mask in topology */
1237 for (int b = 0; b < topology->subslice_offset; b++)
1238 topology->data[b] = (slice_mask >> (b * 8)) & 0xff;
1239
1240 for (int s = 0; s < topology->max_slices; s++) {
1241
1242 /* Set subslice mask in topology */
1243 for (int b = 0; b < topology->subslice_stride; b++) {
1244 int subslice_offset = topology->subslice_offset +
1245 s * topology->subslice_stride + b;
1246
1247 topology->data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff;
1248 }
1249
1250 /* Set eu mask in topology */
1251 for (int ss = 0; ss < topology->max_subslices; ss++) {
1252 for (int b = 0; b < topology->eu_stride; b++) {
1253 int eu_offset = topology->eu_offset +
1254 (s * topology->max_subslices + ss) * topology->eu_stride + b;
1255
1256 topology->data[eu_offset] = (eu_mask >> (b * 8)) & 0xff;
1257 }
1258 }
1259 }
1260
1261 update_from_topology(devinfo, topology);
1262 free(topology);
1263
1264 return true;
1265 }
1266
1267 static bool
1268 getparam(int fd, uint32_t param, int *value)
1269 {
1270 int tmp;
1271
1272 struct drm_i915_getparam gp = {
1273 .param = param,
1274 .value = &tmp,
1275 };
1276
1277 int ret = gen_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
1278 if (ret != 0)
1279 return false;
1280
1281 *value = tmp;
1282 return true;
1283 }
1284
1285 bool
1286 gen_get_device_info_from_pci_id(int pci_id,
1287 struct gen_device_info *devinfo)
1288 {
1289 switch (pci_id) {
1290 #undef CHIPSET
1291 #define CHIPSET(id, family, fam_str, name) \
1292 case id: *devinfo = gen_device_info_##family; break;
1293 #include "pci_ids/i965_pci_ids.h"
1294 #include "pci_ids/iris_pci_ids.h"
1295 default:
1296 fprintf(stderr, "Driver does not support the 0x%x PCI ID.\n", pci_id);
1297 return false;
1298 }
1299
1300 fill_masks(devinfo);
1301
1302 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1303 *
1304 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1305 * allocate scratch space enough so that each slice has 4 slices allowed."
1306 *
1307 * The equivalent internal documentation says that this programming note
1308 * applies to all Gen9+ platforms.
1309 *
1310 * The hardware typically calculates the scratch space pointer by taking
1311 * the base address, and adding per-thread-scratch-space * thread ID.
1312 * Extra padding can be necessary depending how the thread IDs are
1313 * calculated for a particular shader stage.
1314 */
1315
1316 switch(devinfo->gen) {
1317 case 9:
1318 case 10:
1319 devinfo->max_wm_threads = 64 /* threads-per-PSD */
1320 * devinfo->num_slices
1321 * 4; /* effective subslices per slice */
1322 break;
1323 case 11:
1324 case 12:
1325 devinfo->max_wm_threads = 128 /* threads-per-PSD */
1326 * devinfo->num_slices
1327 * 8; /* subslices per slice */
1328 break;
1329 default:
1330 assert(devinfo->gen < 9);
1331 break;
1332 }
1333
1334 assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
1335
1336 devinfo->chipset_id = pci_id;
1337 return true;
1338 }
1339
1340 const char *
1341 gen_get_device_name(int devid)
1342 {
1343 switch (devid) {
1344 #undef CHIPSET
1345 #define CHIPSET(id, family, fam_str, name) case id: return name " (" fam_str ")"; break;
1346 #include "pci_ids/i965_pci_ids.h"
1347 #include "pci_ids/iris_pci_ids.h"
1348 default:
1349 return NULL;
1350 }
1351 }
1352
1353 /**
1354 * for gen8/gen9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology
1355 * (kernel 4.13+)
1356 */
1357 static bool
1358 getparam_topology(struct gen_device_info *devinfo, int fd)
1359 {
1360 int slice_mask = 0;
1361 if (!getparam(fd, I915_PARAM_SLICE_MASK, &slice_mask))
1362 return false;
1363
1364 int n_eus;
1365 if (!getparam(fd, I915_PARAM_EU_TOTAL, &n_eus))
1366 return false;
1367
1368 int subslice_mask = 0;
1369 if (!getparam(fd, I915_PARAM_SUBSLICE_MASK, &subslice_mask))
1370 return false;
1371
1372 return update_from_masks(devinfo, slice_mask, subslice_mask, n_eus);
1373 }
1374
1375 /**
1376 * preferred API for updating the topology in devinfo (kernel 4.17+)
1377 */
1378 static bool
1379 query_topology(struct gen_device_info *devinfo, int fd)
1380 {
1381 struct drm_i915_query_item item = {
1382 .query_id = DRM_I915_QUERY_TOPOLOGY_INFO,
1383 };
1384 struct drm_i915_query query = {
1385 .num_items = 1,
1386 .items_ptr = (uintptr_t) &item,
1387 };
1388
1389 if (gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &query))
1390 return false;
1391
1392 if (item.length < 0)
1393 return false;
1394
1395 struct drm_i915_query_topology_info *topo_info =
1396 (struct drm_i915_query_topology_info *) calloc(1, item.length);
1397 item.data_ptr = (uintptr_t) topo_info;
1398
1399 if (gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &query) ||
1400 item.length <= 0)
1401 return false;
1402
1403 update_from_topology(devinfo, topo_info);
1404
1405 free(topo_info);
1406
1407 return true;
1408
1409 }
1410
1411 int
1412 gen_get_aperture_size(int fd, uint64_t *size)
1413 {
1414 struct drm_i915_gem_get_aperture aperture = { 0 };
1415
1416 int ret = gen_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
1417 if (ret == 0 && size)
1418 *size = aperture.aper_size;
1419
1420 return ret;
1421 }
1422
1423 static bool
1424 gen_has_get_tiling(int fd)
1425 {
1426 int ret;
1427
1428 struct drm_i915_gem_create gem_create = {
1429 .size = 4096,
1430 };
1431
1432 if (gen_ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create)) {
1433 unreachable("Failed to create GEM BO");
1434 return false;
1435 }
1436
1437 struct drm_i915_gem_get_tiling get_tiling = {
1438 .handle = gem_create.handle,
1439 };
1440 ret = gen_ioctl(fd, DRM_IOCTL_I915_GEM_SET_TILING, &get_tiling);
1441
1442 struct drm_gem_close close = {
1443 .handle = gem_create.handle,
1444 };
1445 gen_ioctl(fd, DRM_IOCTL_GEM_CLOSE, &close);
1446
1447 return ret == 0;
1448 }
1449
1450 bool
1451 gen_get_device_info_from_fd(int fd, struct gen_device_info *devinfo)
1452 {
1453 int devid = 0;
1454
1455 const char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
1456 if (devid_override && strlen(devid_override) > 0) {
1457 if (geteuid() == getuid()) {
1458 devid = gen_device_name_to_pci_device_id(devid_override);
1459 /* Fallback to PCI ID. */
1460 if (devid <= 0)
1461 devid = strtol(devid_override, NULL, 0);
1462 if (devid <= 0) {
1463 fprintf(stderr, "Invalid INTEL_DEVID_OVERRIDE=\"%s\". "
1464 "Use a valid numeric PCI ID or one of the supported "
1465 "platform names: %s", devid_override, name_map[0].name);
1466 for (unsigned i = 1; i < ARRAY_SIZE(name_map); i++)
1467 fprintf(stderr, ", %s", name_map[i].name);
1468 fprintf(stderr, "\n");
1469 return false;
1470 }
1471 } else {
1472 fprintf(stderr, "Ignoring INTEL_DEVID_OVERRIDE=\"%s\" because "
1473 "real and effective user ID don't match.\n", devid_override);
1474 }
1475 }
1476
1477 if (devid > 0) {
1478 if (!gen_get_device_info_from_pci_id(devid, devinfo))
1479 return false;
1480 devinfo->no_hw = true;
1481 } else {
1482 /* query the device id */
1483 if (!getparam(fd, I915_PARAM_CHIPSET_ID, &devid))
1484 return false;
1485 if (!gen_get_device_info_from_pci_id(devid, devinfo))
1486 return false;
1487 devinfo->no_hw = false;
1488 }
1489
1490 /* remaining initializion queries the kernel for device info */
1491 if (devinfo->no_hw)
1492 return true;
1493
1494 int timestamp_frequency;
1495 if (getparam(fd, I915_PARAM_CS_TIMESTAMP_FREQUENCY,
1496 &timestamp_frequency))
1497 devinfo->timestamp_frequency = timestamp_frequency;
1498 else if (devinfo->gen >= 10)
1499 /* gen10 and later requires the timestamp_frequency to be updated */
1500 return false;
1501
1502 if (!getparam(fd, I915_PARAM_REVISION, &devinfo->revision))
1503 devinfo->revision = 0;
1504
1505 if (!query_topology(devinfo, fd)) {
1506 if (devinfo->gen >= 10) {
1507 /* topology uAPI required for CNL+ (kernel 4.17+) */
1508 return false;
1509 }
1510
1511 /* else use the kernel 4.13+ api for gen8+. For older kernels, topology
1512 * will be wrong, affecting GPU metrics. In this case, fail silently.
1513 */
1514 getparam_topology(devinfo, fd);
1515 }
1516
1517 gen_get_aperture_size(fd, &devinfo->aperture_bytes);
1518 devinfo->has_tiling_uapi = gen_has_get_tiling(fd);
1519
1520 return true;
1521 }