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intel: fix urb size for CFL GT1
[mesa.git] / src / intel / dev / gen_device_info.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdio.h>
26 #include <stdlib.h>
27 #include <string.h>
28 #include <unistd.h>
29 #include "gen_device_info.h"
30 #include "compiler/shader_enums.h"
31 #include "util/bitscan.h"
32 #include "util/macros.h"
33
34 #include "drm-uapi/i915_drm.h"
35
36 /**
37 * Get the PCI ID for the device name.
38 *
39 * Returns -1 if the device is not known.
40 */
41 int
42 gen_device_name_to_pci_device_id(const char *name)
43 {
44 static const struct {
45 const char *name;
46 int pci_id;
47 } name_map[] = {
48 { "brw", 0x2a02 },
49 { "g4x", 0x2a42 },
50 { "ilk", 0x0042 },
51 { "snb", 0x0126 },
52 { "ivb", 0x016a },
53 { "hsw", 0x0d2e },
54 { "byt", 0x0f33 },
55 { "bdw", 0x162e },
56 { "chv", 0x22B3 },
57 { "skl", 0x1912 },
58 { "bxt", 0x5A85 },
59 { "kbl", 0x5912 },
60 { "aml", 0x591C },
61 { "glk", 0x3185 },
62 { "cfl", 0x3E9B },
63 { "whl", 0x3EA1 },
64 { "cnl", 0x5a52 },
65 { "icl", 0x8a52 },
66 };
67
68 for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
69 if (!strcmp(name_map[i].name, name))
70 return name_map[i].pci_id;
71 }
72
73 return -1;
74 }
75
76 /**
77 * Get the overridden PCI ID for the device. This is set with the
78 * INTEL_DEVID_OVERRIDE environment variable.
79 *
80 * Returns -1 if the override is not set.
81 */
82 int
83 gen_get_pci_device_id_override(void)
84 {
85 if (geteuid() == getuid()) {
86 const char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
87 if (devid_override) {
88 const int id = gen_device_name_to_pci_device_id(devid_override);
89 return id >= 0 ? id : strtol(devid_override, NULL, 0);
90 }
91 }
92
93 return -1;
94 }
95
96 static const struct gen_device_info gen_device_info_i965 = {
97 .gen = 4,
98 .has_negative_rhw_bug = true,
99 .num_slices = 1,
100 .num_subslices = { 1, },
101 .num_eu_per_subslice = 8,
102 .num_thread_per_eu = 4,
103 .max_vs_threads = 16,
104 .max_gs_threads = 2,
105 .max_wm_threads = 8 * 4,
106 .urb = {
107 .size = 256,
108 },
109 .timestamp_frequency = 12500000,
110 .simulator_id = -1,
111 };
112
113 static const struct gen_device_info gen_device_info_g4x = {
114 .gen = 4,
115 .has_pln = true,
116 .has_compr4 = true,
117 .has_surface_tile_offset = true,
118 .is_g4x = true,
119 .num_slices = 1,
120 .num_subslices = { 1, },
121 .num_eu_per_subslice = 10,
122 .num_thread_per_eu = 5,
123 .max_vs_threads = 32,
124 .max_gs_threads = 2,
125 .max_wm_threads = 10 * 5,
126 .urb = {
127 .size = 384,
128 },
129 .timestamp_frequency = 12500000,
130 .simulator_id = -1,
131 };
132
133 static const struct gen_device_info gen_device_info_ilk = {
134 .gen = 5,
135 .has_pln = true,
136 .has_compr4 = true,
137 .has_surface_tile_offset = true,
138 .num_slices = 1,
139 .num_subslices = { 1, },
140 .num_eu_per_subslice = 12,
141 .num_thread_per_eu = 6,
142 .max_vs_threads = 72,
143 .max_gs_threads = 32,
144 .max_wm_threads = 12 * 6,
145 .urb = {
146 .size = 1024,
147 },
148 .timestamp_frequency = 12500000,
149 .simulator_id = -1,
150 };
151
152 static const struct gen_device_info gen_device_info_snb_gt1 = {
153 .gen = 6,
154 .gt = 1,
155 .has_hiz_and_separate_stencil = true,
156 .has_llc = true,
157 .has_pln = true,
158 .has_surface_tile_offset = true,
159 .needs_unlit_centroid_workaround = true,
160 .num_slices = 1,
161 .num_subslices = { 1, },
162 .num_eu_per_subslice = 6,
163 .num_thread_per_eu = 6, /* Not confirmed */
164 .max_vs_threads = 24,
165 .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
166 .max_wm_threads = 40,
167 .urb = {
168 .size = 32,
169 .min_entries = {
170 [MESA_SHADER_VERTEX] = 24,
171 },
172 .max_entries = {
173 [MESA_SHADER_VERTEX] = 256,
174 [MESA_SHADER_GEOMETRY] = 256,
175 },
176 },
177 .timestamp_frequency = 12500000,
178 .simulator_id = -1,
179 };
180
181 static const struct gen_device_info gen_device_info_snb_gt2 = {
182 .gen = 6,
183 .gt = 2,
184 .has_hiz_and_separate_stencil = true,
185 .has_llc = true,
186 .has_pln = true,
187 .has_surface_tile_offset = true,
188 .needs_unlit_centroid_workaround = true,
189 .num_slices = 1,
190 .num_subslices = { 1, },
191 .num_eu_per_subslice = 12,
192 .num_thread_per_eu = 6, /* Not confirmed */
193 .max_vs_threads = 60,
194 .max_gs_threads = 60,
195 .max_wm_threads = 80,
196 .urb = {
197 .size = 64,
198 .min_entries = {
199 [MESA_SHADER_VERTEX] = 24,
200 },
201 .max_entries = {
202 [MESA_SHADER_VERTEX] = 256,
203 [MESA_SHADER_GEOMETRY] = 256,
204 },
205 },
206 .timestamp_frequency = 12500000,
207 .simulator_id = -1,
208 };
209
210 #define GEN7_FEATURES \
211 .gen = 7, \
212 .has_hiz_and_separate_stencil = true, \
213 .must_use_separate_stencil = true, \
214 .has_llc = true, \
215 .has_pln = true, \
216 .has_64bit_types = true, \
217 .has_surface_tile_offset = true, \
218 .timestamp_frequency = 12500000
219
220 static const struct gen_device_info gen_device_info_ivb_gt1 = {
221 GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
222 .num_slices = 1,
223 .num_subslices = { 1, },
224 .num_eu_per_subslice = 6,
225 .num_thread_per_eu = 6,
226 .l3_banks = 2,
227 .max_vs_threads = 36,
228 .max_tcs_threads = 36,
229 .max_tes_threads = 36,
230 .max_gs_threads = 36,
231 .max_wm_threads = 48,
232 .max_cs_threads = 36,
233 .urb = {
234 .size = 128,
235 .min_entries = {
236 [MESA_SHADER_VERTEX] = 32,
237 [MESA_SHADER_TESS_EVAL] = 10,
238 },
239 .max_entries = {
240 [MESA_SHADER_VERTEX] = 512,
241 [MESA_SHADER_TESS_CTRL] = 32,
242 [MESA_SHADER_TESS_EVAL] = 288,
243 [MESA_SHADER_GEOMETRY] = 192,
244 },
245 },
246 .simulator_id = 7,
247 };
248
249 static const struct gen_device_info gen_device_info_ivb_gt2 = {
250 GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
251 .num_slices = 1,
252 .num_subslices = { 1, },
253 .num_eu_per_subslice = 12,
254 .num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
255 * @max_wm_threads ... */
256 .l3_banks = 4,
257 .max_vs_threads = 128,
258 .max_tcs_threads = 128,
259 .max_tes_threads = 128,
260 .max_gs_threads = 128,
261 .max_wm_threads = 172,
262 .max_cs_threads = 64,
263 .urb = {
264 .size = 256,
265 .min_entries = {
266 [MESA_SHADER_VERTEX] = 32,
267 [MESA_SHADER_TESS_EVAL] = 10,
268 },
269 .max_entries = {
270 [MESA_SHADER_VERTEX] = 704,
271 [MESA_SHADER_TESS_CTRL] = 64,
272 [MESA_SHADER_TESS_EVAL] = 448,
273 [MESA_SHADER_GEOMETRY] = 320,
274 },
275 },
276 .simulator_id = 7,
277 };
278
279 static const struct gen_device_info gen_device_info_byt = {
280 GEN7_FEATURES, .is_baytrail = true, .gt = 1,
281 .num_slices = 1,
282 .num_subslices = { 1, },
283 .num_eu_per_subslice = 4,
284 .num_thread_per_eu = 8,
285 .l3_banks = 1,
286 .has_llc = false,
287 .max_vs_threads = 36,
288 .max_tcs_threads = 36,
289 .max_tes_threads = 36,
290 .max_gs_threads = 36,
291 .max_wm_threads = 48,
292 .max_cs_threads = 32,
293 .urb = {
294 .size = 128,
295 .min_entries = {
296 [MESA_SHADER_VERTEX] = 32,
297 [MESA_SHADER_TESS_EVAL] = 10,
298 },
299 .max_entries = {
300 [MESA_SHADER_VERTEX] = 512,
301 [MESA_SHADER_TESS_CTRL] = 32,
302 [MESA_SHADER_TESS_EVAL] = 288,
303 [MESA_SHADER_GEOMETRY] = 192,
304 },
305 },
306 .simulator_id = 10,
307 };
308
309 #define HSW_FEATURES \
310 GEN7_FEATURES, \
311 .is_haswell = true, \
312 .supports_simd16_3src = true, \
313 .has_resource_streamer = true
314
315 static const struct gen_device_info gen_device_info_hsw_gt1 = {
316 HSW_FEATURES, .gt = 1,
317 .num_slices = 1,
318 .num_subslices = { 1, },
319 .num_eu_per_subslice = 10,
320 .num_thread_per_eu = 7,
321 .l3_banks = 2,
322 .max_vs_threads = 70,
323 .max_tcs_threads = 70,
324 .max_tes_threads = 70,
325 .max_gs_threads = 70,
326 .max_wm_threads = 102,
327 .max_cs_threads = 70,
328 .urb = {
329 .size = 128,
330 .min_entries = {
331 [MESA_SHADER_VERTEX] = 32,
332 [MESA_SHADER_TESS_EVAL] = 10,
333 },
334 .max_entries = {
335 [MESA_SHADER_VERTEX] = 640,
336 [MESA_SHADER_TESS_CTRL] = 64,
337 [MESA_SHADER_TESS_EVAL] = 384,
338 [MESA_SHADER_GEOMETRY] = 256,
339 },
340 },
341 .simulator_id = 9,
342 };
343
344 static const struct gen_device_info gen_device_info_hsw_gt2 = {
345 HSW_FEATURES, .gt = 2,
346 .num_slices = 1,
347 .num_subslices = { 2, },
348 .num_eu_per_subslice = 10,
349 .num_thread_per_eu = 7,
350 .l3_banks = 4,
351 .max_vs_threads = 280,
352 .max_tcs_threads = 256,
353 .max_tes_threads = 280,
354 .max_gs_threads = 256,
355 .max_wm_threads = 204,
356 .max_cs_threads = 70,
357 .urb = {
358 .size = 256,
359 .min_entries = {
360 [MESA_SHADER_VERTEX] = 64,
361 [MESA_SHADER_TESS_EVAL] = 10,
362 },
363 .max_entries = {
364 [MESA_SHADER_VERTEX] = 1664,
365 [MESA_SHADER_TESS_CTRL] = 128,
366 [MESA_SHADER_TESS_EVAL] = 960,
367 [MESA_SHADER_GEOMETRY] = 640,
368 },
369 },
370 .simulator_id = 9,
371 };
372
373 static const struct gen_device_info gen_device_info_hsw_gt3 = {
374 HSW_FEATURES, .gt = 3,
375 .num_slices = 2,
376 .num_subslices = { 2, },
377 .num_eu_per_subslice = 10,
378 .num_thread_per_eu = 7,
379 .l3_banks = 8,
380 .max_vs_threads = 280,
381 .max_tcs_threads = 256,
382 .max_tes_threads = 280,
383 .max_gs_threads = 256,
384 .max_wm_threads = 408,
385 .max_cs_threads = 70,
386 .urb = {
387 .size = 512,
388 .min_entries = {
389 [MESA_SHADER_VERTEX] = 64,
390 [MESA_SHADER_TESS_EVAL] = 10,
391 },
392 .max_entries = {
393 [MESA_SHADER_VERTEX] = 1664,
394 [MESA_SHADER_TESS_CTRL] = 128,
395 [MESA_SHADER_TESS_EVAL] = 960,
396 [MESA_SHADER_GEOMETRY] = 640,
397 },
398 },
399 .simulator_id = 9,
400 };
401
402 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
403 * so keep things conservative for now and set has_sample_with_hiz = false.
404 */
405 #define GEN8_FEATURES \
406 .gen = 8, \
407 .has_hiz_and_separate_stencil = true, \
408 .has_resource_streamer = true, \
409 .must_use_separate_stencil = true, \
410 .has_llc = true, \
411 .has_sample_with_hiz = false, \
412 .has_pln = true, \
413 .has_integer_dword_mul = true, \
414 .has_64bit_types = true, \
415 .supports_simd16_3src = true, \
416 .has_surface_tile_offset = true, \
417 .max_vs_threads = 504, \
418 .max_tcs_threads = 504, \
419 .max_tes_threads = 504, \
420 .max_gs_threads = 504, \
421 .max_wm_threads = 384, \
422 .timestamp_frequency = 12500000
423
424 static const struct gen_device_info gen_device_info_bdw_gt1 = {
425 GEN8_FEATURES, .gt = 1,
426 .is_broadwell = true,
427 .num_slices = 1,
428 .num_subslices = { 2, },
429 .num_eu_per_subslice = 8,
430 .num_thread_per_eu = 7,
431 .l3_banks = 2,
432 .max_cs_threads = 42,
433 .urb = {
434 .size = 192,
435 .min_entries = {
436 [MESA_SHADER_VERTEX] = 64,
437 [MESA_SHADER_TESS_EVAL] = 34,
438 },
439 .max_entries = {
440 [MESA_SHADER_VERTEX] = 2560,
441 [MESA_SHADER_TESS_CTRL] = 504,
442 [MESA_SHADER_TESS_EVAL] = 1536,
443 [MESA_SHADER_GEOMETRY] = 960,
444 },
445 },
446 .simulator_id = 11,
447 };
448
449 static const struct gen_device_info gen_device_info_bdw_gt2 = {
450 GEN8_FEATURES, .gt = 2,
451 .is_broadwell = true,
452 .num_slices = 1,
453 .num_subslices = { 3, },
454 .num_eu_per_subslice = 8,
455 .num_thread_per_eu = 7,
456 .l3_banks = 4,
457 .max_cs_threads = 56,
458 .urb = {
459 .size = 384,
460 .min_entries = {
461 [MESA_SHADER_VERTEX] = 64,
462 [MESA_SHADER_TESS_EVAL] = 34,
463 },
464 .max_entries = {
465 [MESA_SHADER_VERTEX] = 2560,
466 [MESA_SHADER_TESS_CTRL] = 504,
467 [MESA_SHADER_TESS_EVAL] = 1536,
468 [MESA_SHADER_GEOMETRY] = 960,
469 },
470 },
471 .simulator_id = 11,
472 };
473
474 static const struct gen_device_info gen_device_info_bdw_gt3 = {
475 GEN8_FEATURES, .gt = 3,
476 .is_broadwell = true,
477 .num_slices = 2,
478 .num_subslices = { 3, 3, },
479 .num_eu_per_subslice = 8,
480 .num_thread_per_eu = 7,
481 .l3_banks = 8,
482 .max_cs_threads = 56,
483 .urb = {
484 .size = 384,
485 .min_entries = {
486 [MESA_SHADER_VERTEX] = 64,
487 [MESA_SHADER_TESS_EVAL] = 34,
488 },
489 .max_entries = {
490 [MESA_SHADER_VERTEX] = 2560,
491 [MESA_SHADER_TESS_CTRL] = 504,
492 [MESA_SHADER_TESS_EVAL] = 1536,
493 [MESA_SHADER_GEOMETRY] = 960,
494 },
495 },
496 .simulator_id = 11,
497 };
498
499 static const struct gen_device_info gen_device_info_chv = {
500 GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
501 .has_llc = false,
502 .has_integer_dword_mul = false,
503 .num_slices = 1,
504 .num_subslices = { 2, },
505 .num_eu_per_subslice = 8,
506 .num_thread_per_eu = 7,
507 .l3_banks = 2,
508 .max_vs_threads = 80,
509 .max_tcs_threads = 80,
510 .max_tes_threads = 80,
511 .max_gs_threads = 80,
512 .max_wm_threads = 128,
513 .max_cs_threads = 6 * 7,
514 .urb = {
515 .size = 192,
516 .min_entries = {
517 [MESA_SHADER_VERTEX] = 34,
518 [MESA_SHADER_TESS_EVAL] = 34,
519 },
520 .max_entries = {
521 [MESA_SHADER_VERTEX] = 640,
522 [MESA_SHADER_TESS_CTRL] = 80,
523 [MESA_SHADER_TESS_EVAL] = 384,
524 [MESA_SHADER_GEOMETRY] = 256,
525 },
526 },
527 .simulator_id = 13,
528 };
529
530 #define GEN9_HW_INFO \
531 .gen = 9, \
532 .max_vs_threads = 336, \
533 .max_gs_threads = 336, \
534 .max_tcs_threads = 336, \
535 .max_tes_threads = 336, \
536 .max_cs_threads = 56, \
537 .timestamp_frequency = 12000000, \
538 .urb = { \
539 .size = 384, \
540 .min_entries = { \
541 [MESA_SHADER_VERTEX] = 64, \
542 [MESA_SHADER_TESS_EVAL] = 34, \
543 }, \
544 .max_entries = { \
545 [MESA_SHADER_VERTEX] = 1856, \
546 [MESA_SHADER_TESS_CTRL] = 672, \
547 [MESA_SHADER_TESS_EVAL] = 1120, \
548 [MESA_SHADER_GEOMETRY] = 640, \
549 }, \
550 }
551
552 #define GEN9_LP_FEATURES \
553 GEN8_FEATURES, \
554 GEN9_HW_INFO, \
555 .has_integer_dword_mul = false, \
556 .gt = 1, \
557 .has_llc = false, \
558 .has_sample_with_hiz = true, \
559 .num_slices = 1, \
560 .num_thread_per_eu = 6, \
561 .max_vs_threads = 112, \
562 .max_tcs_threads = 112, \
563 .max_tes_threads = 112, \
564 .max_gs_threads = 112, \
565 .max_cs_threads = 6 * 6, \
566 .timestamp_frequency = 19200000, \
567 .urb = { \
568 .size = 192, \
569 .min_entries = { \
570 [MESA_SHADER_VERTEX] = 34, \
571 [MESA_SHADER_TESS_EVAL] = 34, \
572 }, \
573 .max_entries = { \
574 [MESA_SHADER_VERTEX] = 704, \
575 [MESA_SHADER_TESS_CTRL] = 256, \
576 [MESA_SHADER_TESS_EVAL] = 416, \
577 [MESA_SHADER_GEOMETRY] = 256, \
578 }, \
579 }
580
581 #define GEN9_LP_FEATURES_3X6 \
582 GEN9_LP_FEATURES, \
583 .num_subslices = { 3, }, \
584 .num_eu_per_subslice = 6
585
586 #define GEN9_LP_FEATURES_2X6 \
587 GEN9_LP_FEATURES, \
588 .num_subslices = { 2, }, \
589 .num_eu_per_subslice = 6, \
590 .max_vs_threads = 56, \
591 .max_tcs_threads = 56, \
592 .max_tes_threads = 56, \
593 .max_gs_threads = 56, \
594 .max_cs_threads = 6 * 6, \
595 .urb = { \
596 .size = 128, \
597 .min_entries = { \
598 [MESA_SHADER_VERTEX] = 34, \
599 [MESA_SHADER_TESS_EVAL] = 34, \
600 }, \
601 .max_entries = { \
602 [MESA_SHADER_VERTEX] = 352, \
603 [MESA_SHADER_TESS_CTRL] = 128, \
604 [MESA_SHADER_TESS_EVAL] = 208, \
605 [MESA_SHADER_GEOMETRY] = 128, \
606 }, \
607 }
608
609 #define GEN9_FEATURES \
610 GEN8_FEATURES, \
611 GEN9_HW_INFO, \
612 .has_sample_with_hiz = true, \
613 .num_thread_per_eu = 7
614
615 static const struct gen_device_info gen_device_info_skl_gt1 = {
616 GEN9_FEATURES, .gt = 1,
617 .is_skylake = true,
618 .num_slices = 1,
619 .num_subslices = { 2, },
620 .num_eu_per_subslice = 6,
621 .l3_banks = 2,
622 .urb.size = 192,
623 .simulator_id = 12,
624 };
625
626 static const struct gen_device_info gen_device_info_skl_gt2 = {
627 GEN9_FEATURES, .gt = 2,
628 .is_skylake = true,
629 .num_slices = 1,
630 .num_subslices = { 3, },
631 .num_eu_per_subslice = 8,
632 .l3_banks = 4,
633 .simulator_id = 12,
634 };
635
636 static const struct gen_device_info gen_device_info_skl_gt3 = {
637 GEN9_FEATURES, .gt = 3,
638 .is_skylake = true,
639 .num_slices = 2,
640 .num_subslices = { 3, 3, },
641 .num_eu_per_subslice = 8,
642 .l3_banks = 8,
643 .simulator_id = 12,
644 };
645
646 static const struct gen_device_info gen_device_info_skl_gt4 = {
647 GEN9_FEATURES, .gt = 4,
648 .is_skylake = true,
649 .num_slices = 3,
650 .num_subslices = { 3, 3, 3, },
651 .num_eu_per_subslice = 8,
652 .l3_banks = 12,
653 /* From the "L3 Allocation and Programming" documentation:
654 *
655 * "URB is limited to 1008KB due to programming restrictions. This is not a
656 * restriction of the L3 implementation, but of the FF and other clients.
657 * Therefore, in a GT4 implementation it is possible for the programmed
658 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
659 * only 1008KB of this will be used."
660 */
661 .urb.size = 1008 / 3,
662 .simulator_id = 12,
663 };
664
665 static const struct gen_device_info gen_device_info_bxt = {
666 GEN9_LP_FEATURES_3X6,
667 .is_broxton = true,
668 .l3_banks = 2,
669 .simulator_id = 14,
670 };
671
672 static const struct gen_device_info gen_device_info_bxt_2x6 = {
673 GEN9_LP_FEATURES_2X6,
674 .is_broxton = true,
675 .l3_banks = 1,
676 .simulator_id = 14,
677 };
678 /*
679 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
680 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
681 */
682
683 static const struct gen_device_info gen_device_info_kbl_gt1 = {
684 GEN9_FEATURES,
685 .is_kabylake = true,
686 .gt = 1,
687
688 .max_cs_threads = 7 * 6,
689 .urb.size = 192,
690 .num_slices = 1,
691 .num_subslices = { 2, },
692 .num_eu_per_subslice = 6,
693 .l3_banks = 2,
694 .simulator_id = 16,
695 };
696
697 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
698 GEN9_FEATURES,
699 .is_kabylake = true,
700 .gt = 1,
701
702 .max_cs_threads = 7 * 6,
703 .num_slices = 1,
704 .num_subslices = { 3, },
705 .num_eu_per_subslice = 6,
706 .l3_banks = 4,
707 .simulator_id = 16,
708 };
709
710 static const struct gen_device_info gen_device_info_kbl_gt2 = {
711 GEN9_FEATURES,
712 .is_kabylake = true,
713 .gt = 2,
714
715 .num_slices = 1,
716 .num_subslices = { 3, },
717 .num_eu_per_subslice = 8,
718 .l3_banks = 4,
719 .simulator_id = 16,
720 };
721
722 static const struct gen_device_info gen_device_info_kbl_gt3 = {
723 GEN9_FEATURES,
724 .is_kabylake = true,
725 .gt = 3,
726
727 .num_slices = 2,
728 .num_subslices = { 3, 3, },
729 .num_eu_per_subslice = 8,
730 .l3_banks = 8,
731 .simulator_id = 16,
732 };
733
734 static const struct gen_device_info gen_device_info_kbl_gt4 = {
735 GEN9_FEATURES,
736 .is_kabylake = true,
737 .gt = 4,
738
739 /*
740 * From the "L3 Allocation and Programming" documentation:
741 *
742 * "URB is limited to 1008KB due to programming restrictions. This
743 * is not a restriction of the L3 implementation, but of the FF and
744 * other clients. Therefore, in a GT4 implementation it is
745 * possible for the programmed allocation of the L3 data array to
746 * provide 3*384KB=1152KB for URB, but only 1008KB of this
747 * will be used."
748 */
749 .urb.size = 1008 / 3,
750 .num_slices = 3,
751 .num_subslices = { 3, 3, 3, },
752 .num_eu_per_subslice = 8,
753 .l3_banks = 12,
754 .simulator_id = 16,
755 };
756
757 static const struct gen_device_info gen_device_info_glk = {
758 GEN9_LP_FEATURES_3X6,
759 .is_geminilake = true,
760 .l3_banks = 2,
761 .simulator_id = 17,
762 };
763
764 static const struct gen_device_info gen_device_info_glk_2x6 = {
765 GEN9_LP_FEATURES_2X6,
766 .is_geminilake = true,
767 .l3_banks = 2,
768 .simulator_id = 17,
769 };
770
771 static const struct gen_device_info gen_device_info_cfl_gt1 = {
772 GEN9_FEATURES,
773 .is_coffeelake = true,
774 .gt = 1,
775
776 .num_slices = 1,
777 .num_subslices = { 2, },
778 .num_eu_per_subslice = 6,
779 .l3_banks = 2,
780 .urb.size = 192,
781 .simulator_id = 24,
782 };
783 static const struct gen_device_info gen_device_info_cfl_gt2 = {
784 GEN9_FEATURES,
785 .is_coffeelake = true,
786 .gt = 2,
787
788 .num_slices = 1,
789 .num_subslices = { 3, },
790 .num_eu_per_subslice = 8,
791 .l3_banks = 4,
792 .simulator_id = 24,
793 };
794
795 static const struct gen_device_info gen_device_info_cfl_gt3 = {
796 GEN9_FEATURES,
797 .is_coffeelake = true,
798 .gt = 3,
799
800 .num_slices = 2,
801 .num_subslices = { 3, 3, },
802 .num_eu_per_subslice = 8,
803 .l3_banks = 8,
804 .simulator_id = 24,
805 };
806
807 #define GEN10_HW_INFO \
808 .gen = 10, \
809 .num_thread_per_eu = 7, \
810 .max_vs_threads = 728, \
811 .max_gs_threads = 432, \
812 .max_tcs_threads = 432, \
813 .max_tes_threads = 624, \
814 .max_cs_threads = 56, \
815 .timestamp_frequency = 19200000, \
816 .urb = { \
817 .size = 256, \
818 .min_entries = { \
819 [MESA_SHADER_VERTEX] = 64, \
820 [MESA_SHADER_TESS_EVAL] = 34, \
821 }, \
822 .max_entries = { \
823 [MESA_SHADER_VERTEX] = 3936, \
824 [MESA_SHADER_TESS_CTRL] = 896, \
825 [MESA_SHADER_TESS_EVAL] = 2064, \
826 [MESA_SHADER_GEOMETRY] = 832, \
827 }, \
828 }
829
830 #define subslices(args...) { args, }
831
832 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
833 GEN8_FEATURES, \
834 GEN10_HW_INFO, \
835 .has_sample_with_hiz = true, \
836 .gt = _gt, \
837 .num_slices = _slices, \
838 .num_subslices = _subslices, \
839 .num_eu_per_subslice = 8, \
840 .l3_banks = _l3
841
842 static const struct gen_device_info gen_device_info_cnl_2x8 = {
843 /* GT0.5 */
844 GEN10_FEATURES(1, 1, subslices(2), 2),
845 .is_cannonlake = true,
846 .simulator_id = 15,
847 };
848
849 static const struct gen_device_info gen_device_info_cnl_3x8 = {
850 /* GT1 */
851 GEN10_FEATURES(1, 1, subslices(3), 3),
852 .is_cannonlake = true,
853 .simulator_id = 15,
854 };
855
856 static const struct gen_device_info gen_device_info_cnl_4x8 = {
857 /* GT 1.5 */
858 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
859 .is_cannonlake = true,
860 .simulator_id = 15,
861 };
862
863 static const struct gen_device_info gen_device_info_cnl_5x8 = {
864 /* GT2 */
865 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
866 .is_cannonlake = true,
867 .simulator_id = 15,
868 };
869
870 #define GEN11_HW_INFO \
871 .gen = 11, \
872 .has_pln = false, \
873 .max_vs_threads = 364, \
874 .max_gs_threads = 224, \
875 .max_tcs_threads = 224, \
876 .max_tes_threads = 364, \
877 .max_cs_threads = 56
878
879 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
880 GEN8_FEATURES, \
881 GEN11_HW_INFO, \
882 .has_64bit_types = false, \
883 .has_integer_dword_mul = false, \
884 .has_sample_with_hiz = false, \
885 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
886 .num_subslices = _subslices, \
887 .num_eu_per_subslice = 8
888
889 #define GEN11_URB_MIN_MAX_ENTRIES \
890 .min_entries = { \
891 [MESA_SHADER_VERTEX] = 64, \
892 [MESA_SHADER_TESS_EVAL] = 34, \
893 }, \
894 .max_entries = { \
895 [MESA_SHADER_VERTEX] = 2384, \
896 [MESA_SHADER_TESS_CTRL] = 1032, \
897 [MESA_SHADER_TESS_EVAL] = 2384, \
898 [MESA_SHADER_GEOMETRY] = 1032, \
899 }
900
901 static const struct gen_device_info gen_device_info_icl_8x8 = {
902 GEN11_FEATURES(2, 1, subslices(8), 8),
903 .urb = {
904 .size = 1024,
905 GEN11_URB_MIN_MAX_ENTRIES,
906 },
907 .simulator_id = 19,
908 };
909
910 static const struct gen_device_info gen_device_info_icl_6x8 = {
911 GEN11_FEATURES(1, 1, subslices(6), 6),
912 .urb = {
913 .size = 768,
914 GEN11_URB_MIN_MAX_ENTRIES,
915 },
916 .simulator_id = 19,
917 };
918
919 static const struct gen_device_info gen_device_info_icl_4x8 = {
920 GEN11_FEATURES(1, 1, subslices(4), 6),
921 .urb = {
922 .size = 768,
923 GEN11_URB_MIN_MAX_ENTRIES,
924 },
925 .simulator_id = 19,
926 };
927
928 static const struct gen_device_info gen_device_info_icl_1x8 = {
929 GEN11_FEATURES(1, 1, subslices(1), 6),
930 .urb = {
931 .size = 768,
932 GEN11_URB_MIN_MAX_ENTRIES,
933 },
934 .simulator_id = 19,
935 };
936
937 static void
938 gen_device_info_set_eu_mask(struct gen_device_info *devinfo,
939 unsigned slice,
940 unsigned subslice,
941 unsigned eu_mask)
942 {
943 unsigned subslice_offset = slice * devinfo->eu_slice_stride +
944 subslice * devinfo->eu_subslice_stride;
945
946 for (unsigned b_eu = 0; b_eu < devinfo->eu_subslice_stride; b_eu++) {
947 devinfo->eu_masks[subslice_offset + b_eu] =
948 (((1U << devinfo->num_eu_per_subslice) - 1) >> (b_eu * 8)) & 0xff;
949 }
950 }
951
952 /* Generate slice/subslice/eu masks from number of
953 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
954 * structure.
955 *
956 * These can be overridden with values reported by the kernel either from
957 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
958 * through the i915 query uapi.
959 */
960 static void
961 fill_masks(struct gen_device_info *devinfo)
962 {
963 devinfo->slice_masks = (1U << devinfo->num_slices) - 1;
964
965 /* Subslice masks */
966 unsigned max_subslices = 0;
967 for (int s = 0; s < devinfo->num_slices; s++)
968 max_subslices = MAX2(devinfo->num_subslices[s], max_subslices);
969 devinfo->subslice_slice_stride = DIV_ROUND_UP(max_subslices, 8);
970
971 for (int s = 0; s < devinfo->num_slices; s++) {
972 devinfo->subslice_masks[s * devinfo->subslice_slice_stride] =
973 (1U << devinfo->num_subslices[s]) - 1;
974 }
975
976 /* EU masks */
977 devinfo->eu_subslice_stride = DIV_ROUND_UP(devinfo->num_eu_per_subslice, 8);
978 devinfo->eu_slice_stride = max_subslices * devinfo->eu_subslice_stride;
979
980 for (int s = 0; s < devinfo->num_slices; s++) {
981 for (int ss = 0; ss < devinfo->num_subslices[s]; ss++) {
982 gen_device_info_set_eu_mask(devinfo, s, ss,
983 (1U << devinfo->num_eu_per_subslice) - 1);
984 }
985 }
986 }
987
988 void
989 gen_device_info_update_from_masks(struct gen_device_info *devinfo,
990 uint32_t slice_mask,
991 uint32_t subslice_mask,
992 uint32_t n_eus)
993 {
994 struct {
995 struct drm_i915_query_topology_info base;
996 uint8_t data[100];
997 } topology;
998
999 assert((slice_mask & 0xff) == slice_mask);
1000
1001 memset(&topology, 0, sizeof(topology));
1002
1003 topology.base.max_slices = util_last_bit(slice_mask);
1004 topology.base.max_subslices = util_last_bit(subslice_mask);
1005
1006 topology.base.subslice_offset = DIV_ROUND_UP(topology.base.max_slices, 8);
1007 topology.base.subslice_stride = DIV_ROUND_UP(topology.base.max_subslices, 8);
1008
1009 uint32_t n_subslices = __builtin_popcount(slice_mask) *
1010 __builtin_popcount(subslice_mask);
1011 uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1012 uint32_t eu_mask = (1U << num_eu_per_subslice) - 1;
1013
1014 topology.base.eu_offset = topology.base.subslice_offset +
1015 DIV_ROUND_UP(topology.base.max_subslices, 8);
1016 topology.base.eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8);
1017
1018 /* Set slice mask in topology */
1019 for (int b = 0; b < topology.base.subslice_offset; b++)
1020 topology.base.data[b] = (slice_mask >> (b * 8)) & 0xff;
1021
1022 for (int s = 0; s < topology.base.max_slices; s++) {
1023
1024 /* Set subslice mask in topology */
1025 for (int b = 0; b < topology.base.subslice_stride; b++) {
1026 int subslice_offset = topology.base.subslice_offset +
1027 s * topology.base.subslice_stride + b;
1028
1029 topology.base.data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff;
1030 }
1031
1032 /* Set eu mask in topology */
1033 for (int ss = 0; ss < topology.base.max_subslices; ss++) {
1034 for (int b = 0; b < topology.base.eu_stride; b++) {
1035 int eu_offset = topology.base.eu_offset +
1036 (s * topology.base.max_subslices + ss) * topology.base.eu_stride + b;
1037
1038 topology.base.data[eu_offset] = (eu_mask >> (b * 8)) & 0xff;
1039 }
1040 }
1041 }
1042
1043 gen_device_info_update_from_topology(devinfo, &topology.base);
1044 }
1045
1046 static void
1047 reset_masks(struct gen_device_info *devinfo)
1048 {
1049 devinfo->subslice_slice_stride = 0;
1050 devinfo->eu_subslice_stride = 0;
1051 devinfo->eu_slice_stride = 0;
1052
1053 devinfo->num_slices = 0;
1054 devinfo->num_eu_per_subslice = 0;
1055 memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices));
1056
1057 memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
1058 memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
1059 memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
1060 }
1061
1062 void
1063 gen_device_info_update_from_topology(struct gen_device_info *devinfo,
1064 const struct drm_i915_query_topology_info *topology)
1065 {
1066 reset_masks(devinfo);
1067
1068 devinfo->subslice_slice_stride = topology->subslice_stride;
1069
1070 devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8);
1071 devinfo->eu_slice_stride = topology->max_subslices * devinfo->eu_subslice_stride;
1072
1073 assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8));
1074 memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8));
1075 devinfo->num_slices = __builtin_popcount(devinfo->slice_masks);
1076
1077 uint32_t subslice_mask_len =
1078 topology->max_slices * topology->subslice_stride;
1079 assert(sizeof(devinfo->subslice_masks) >= subslice_mask_len);
1080 memcpy(devinfo->subslice_masks, &topology->data[topology->subslice_offset],
1081 subslice_mask_len);
1082
1083 uint32_t n_subslices = 0;
1084 for (int s = 0; s < topology->max_slices; s++) {
1085 if ((devinfo->slice_masks & (1UL << s)) == 0)
1086 continue;
1087
1088 for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
1089 devinfo->num_subslices[s] +=
1090 __builtin_popcount(devinfo->subslice_masks[b]);
1091 }
1092 n_subslices += devinfo->num_subslices[s];
1093 }
1094 assert(n_subslices > 0);
1095
1096 uint32_t eu_mask_len =
1097 topology->eu_stride * topology->max_subslices * topology->max_slices;
1098 assert(sizeof(devinfo->eu_masks) >= eu_mask_len);
1099 memcpy(devinfo->eu_masks, &topology->data[topology->eu_offset], eu_mask_len);
1100
1101 uint32_t n_eus = 0;
1102 for (int b = 0; b < eu_mask_len; b++)
1103 n_eus += __builtin_popcount(devinfo->eu_masks[b]);
1104
1105 devinfo->num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1106 }
1107
1108 bool
1109 gen_get_device_info(int devid, struct gen_device_info *devinfo)
1110 {
1111 switch (devid) {
1112 #undef CHIPSET
1113 #define CHIPSET(id, family, name) \
1114 case id: *devinfo = gen_device_info_##family; break;
1115 #include "pci_ids/i965_pci_ids.h"
1116 default:
1117 fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
1118 return false;
1119 }
1120
1121 fill_masks(devinfo);
1122
1123 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1124 *
1125 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1126 * allocate scratch space enough so that each slice has 4 slices allowed."
1127 *
1128 * The equivalent internal documentation says that this programming note
1129 * applies to all Gen9+ platforms.
1130 *
1131 * The hardware typically calculates the scratch space pointer by taking
1132 * the base address, and adding per-thread-scratch-space * thread ID.
1133 * Extra padding can be necessary depending how the thread IDs are
1134 * calculated for a particular shader stage.
1135 */
1136
1137 switch(devinfo->gen) {
1138 case 9:
1139 case 10:
1140 devinfo->max_wm_threads = 64 /* threads-per-PSD */
1141 * devinfo->num_slices
1142 * 4; /* effective subslices per slice */
1143 break;
1144 case 11:
1145 devinfo->max_wm_threads = 128 /* threads-per-PSD */
1146 * devinfo->num_slices
1147 * 8; /* subslices per slice */
1148 break;
1149 default:
1150 break;
1151 }
1152
1153 assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
1154
1155 return true;
1156 }
1157
1158 const char *
1159 gen_get_device_name(int devid)
1160 {
1161 switch (devid) {
1162 #undef CHIPSET
1163 #define CHIPSET(id, family, name) case id: return name;
1164 #include "pci_ids/i965_pci_ids.h"
1165 default:
1166 return NULL;
1167 }
1168 }