2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "gen_device_info.h"
31 #include "compiler/shader_enums.h"
32 #include "intel/common/gen_gem.h"
33 #include "util/bitscan.h"
34 #include "util/macros.h"
36 #include "drm-uapi/i915_drm.h"
39 * Get the PCI ID for the device name.
41 * Returns -1 if the device is not known.
44 gen_device_name_to_pci_device_id(const char *name
)
73 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
74 if (!strcmp(name_map
[i
].name
, name
))
75 return name_map
[i
].pci_id
;
82 * Get the overridden PCI ID for the device. This is set with the
83 * INTEL_DEVID_OVERRIDE environment variable.
85 * Returns -1 if the override is not set.
88 get_pci_device_id_override(void)
90 if (geteuid() == getuid()) {
91 const char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
93 const int id
= gen_device_name_to_pci_device_id(devid_override
);
94 return id
>= 0 ? id
: strtol(devid_override
, NULL
, 0);
101 static const struct gen_device_info gen_device_info_i965
= {
103 .has_negative_rhw_bug
= true,
105 .num_subslices
= { 1, },
106 .num_eu_per_subslice
= 8,
107 .num_thread_per_eu
= 4,
108 .max_vs_threads
= 16,
110 .max_wm_threads
= 8 * 4,
114 .timestamp_frequency
= 12500000,
118 static const struct gen_device_info gen_device_info_g4x
= {
122 .has_surface_tile_offset
= true,
125 .num_subslices
= { 1, },
126 .num_eu_per_subslice
= 10,
127 .num_thread_per_eu
= 5,
128 .max_vs_threads
= 32,
130 .max_wm_threads
= 10 * 5,
134 .timestamp_frequency
= 12500000,
138 static const struct gen_device_info gen_device_info_ilk
= {
142 .has_surface_tile_offset
= true,
144 .num_subslices
= { 1, },
145 .num_eu_per_subslice
= 12,
146 .num_thread_per_eu
= 6,
147 .max_vs_threads
= 72,
148 .max_gs_threads
= 32,
149 .max_wm_threads
= 12 * 6,
153 .timestamp_frequency
= 12500000,
157 static const struct gen_device_info gen_device_info_snb_gt1
= {
160 .has_hiz_and_separate_stencil
= true,
163 .has_surface_tile_offset
= true,
164 .needs_unlit_centroid_workaround
= true,
166 .num_subslices
= { 1, },
167 .num_eu_per_subslice
= 6,
168 .num_thread_per_eu
= 6, /* Not confirmed */
169 .max_vs_threads
= 24,
170 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
171 .max_wm_threads
= 40,
175 [MESA_SHADER_VERTEX
] = 24,
178 [MESA_SHADER_VERTEX
] = 256,
179 [MESA_SHADER_GEOMETRY
] = 256,
182 .timestamp_frequency
= 12500000,
186 static const struct gen_device_info gen_device_info_snb_gt2
= {
189 .has_hiz_and_separate_stencil
= true,
192 .has_surface_tile_offset
= true,
193 .needs_unlit_centroid_workaround
= true,
195 .num_subslices
= { 1, },
196 .num_eu_per_subslice
= 12,
197 .num_thread_per_eu
= 6, /* Not confirmed */
198 .max_vs_threads
= 60,
199 .max_gs_threads
= 60,
200 .max_wm_threads
= 80,
204 [MESA_SHADER_VERTEX
] = 24,
207 [MESA_SHADER_VERTEX
] = 256,
208 [MESA_SHADER_GEOMETRY
] = 256,
211 .timestamp_frequency
= 12500000,
215 #define GEN7_FEATURES \
217 .has_hiz_and_separate_stencil = true, \
218 .must_use_separate_stencil = true, \
221 .has_64bit_types = true, \
222 .has_surface_tile_offset = true, \
223 .timestamp_frequency = 12500000
225 static const struct gen_device_info gen_device_info_ivb_gt1
= {
226 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
228 .num_subslices
= { 1, },
229 .num_eu_per_subslice
= 6,
230 .num_thread_per_eu
= 6,
232 .max_vs_threads
= 36,
233 .max_tcs_threads
= 36,
234 .max_tes_threads
= 36,
235 .max_gs_threads
= 36,
236 .max_wm_threads
= 48,
237 .max_cs_threads
= 36,
241 [MESA_SHADER_VERTEX
] = 32,
242 [MESA_SHADER_TESS_EVAL
] = 10,
245 [MESA_SHADER_VERTEX
] = 512,
246 [MESA_SHADER_TESS_CTRL
] = 32,
247 [MESA_SHADER_TESS_EVAL
] = 288,
248 [MESA_SHADER_GEOMETRY
] = 192,
254 static const struct gen_device_info gen_device_info_ivb_gt2
= {
255 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
257 .num_subslices
= { 1, },
258 .num_eu_per_subslice
= 12,
259 .num_thread_per_eu
= 8, /* Not sure why this isn't a multiple of
260 * @max_wm_threads ... */
262 .max_vs_threads
= 128,
263 .max_tcs_threads
= 128,
264 .max_tes_threads
= 128,
265 .max_gs_threads
= 128,
266 .max_wm_threads
= 172,
267 .max_cs_threads
= 64,
271 [MESA_SHADER_VERTEX
] = 32,
272 [MESA_SHADER_TESS_EVAL
] = 10,
275 [MESA_SHADER_VERTEX
] = 704,
276 [MESA_SHADER_TESS_CTRL
] = 64,
277 [MESA_SHADER_TESS_EVAL
] = 448,
278 [MESA_SHADER_GEOMETRY
] = 320,
284 static const struct gen_device_info gen_device_info_byt
= {
285 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
287 .num_subslices
= { 1, },
288 .num_eu_per_subslice
= 4,
289 .num_thread_per_eu
= 8,
292 .max_vs_threads
= 36,
293 .max_tcs_threads
= 36,
294 .max_tes_threads
= 36,
295 .max_gs_threads
= 36,
296 .max_wm_threads
= 48,
297 .max_cs_threads
= 32,
301 [MESA_SHADER_VERTEX
] = 32,
302 [MESA_SHADER_TESS_EVAL
] = 10,
305 [MESA_SHADER_VERTEX
] = 512,
306 [MESA_SHADER_TESS_CTRL
] = 32,
307 [MESA_SHADER_TESS_EVAL
] = 288,
308 [MESA_SHADER_GEOMETRY
] = 192,
314 #define HSW_FEATURES \
316 .is_haswell = true, \
317 .supports_simd16_3src = true, \
318 .has_resource_streamer = true
320 static const struct gen_device_info gen_device_info_hsw_gt1
= {
321 HSW_FEATURES
, .gt
= 1,
323 .num_subslices
= { 1, },
324 .num_eu_per_subslice
= 10,
325 .num_thread_per_eu
= 7,
327 .max_vs_threads
= 70,
328 .max_tcs_threads
= 70,
329 .max_tes_threads
= 70,
330 .max_gs_threads
= 70,
331 .max_wm_threads
= 102,
332 .max_cs_threads
= 70,
336 [MESA_SHADER_VERTEX
] = 32,
337 [MESA_SHADER_TESS_EVAL
] = 10,
340 [MESA_SHADER_VERTEX
] = 640,
341 [MESA_SHADER_TESS_CTRL
] = 64,
342 [MESA_SHADER_TESS_EVAL
] = 384,
343 [MESA_SHADER_GEOMETRY
] = 256,
349 static const struct gen_device_info gen_device_info_hsw_gt2
= {
350 HSW_FEATURES
, .gt
= 2,
352 .num_subslices
= { 2, },
353 .num_eu_per_subslice
= 10,
354 .num_thread_per_eu
= 7,
356 .max_vs_threads
= 280,
357 .max_tcs_threads
= 256,
358 .max_tes_threads
= 280,
359 .max_gs_threads
= 256,
360 .max_wm_threads
= 204,
361 .max_cs_threads
= 70,
365 [MESA_SHADER_VERTEX
] = 64,
366 [MESA_SHADER_TESS_EVAL
] = 10,
369 [MESA_SHADER_VERTEX
] = 1664,
370 [MESA_SHADER_TESS_CTRL
] = 128,
371 [MESA_SHADER_TESS_EVAL
] = 960,
372 [MESA_SHADER_GEOMETRY
] = 640,
378 static const struct gen_device_info gen_device_info_hsw_gt3
= {
379 HSW_FEATURES
, .gt
= 3,
381 .num_subslices
= { 2, },
382 .num_eu_per_subslice
= 10,
383 .num_thread_per_eu
= 7,
385 .max_vs_threads
= 280,
386 .max_tcs_threads
= 256,
387 .max_tes_threads
= 280,
388 .max_gs_threads
= 256,
389 .max_wm_threads
= 408,
390 .max_cs_threads
= 70,
394 [MESA_SHADER_VERTEX
] = 64,
395 [MESA_SHADER_TESS_EVAL
] = 10,
398 [MESA_SHADER_VERTEX
] = 1664,
399 [MESA_SHADER_TESS_CTRL
] = 128,
400 [MESA_SHADER_TESS_EVAL
] = 960,
401 [MESA_SHADER_GEOMETRY
] = 640,
407 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
408 * so keep things conservative for now and set has_sample_with_hiz = false.
410 #define GEN8_FEATURES \
412 .has_hiz_and_separate_stencil = true, \
413 .has_resource_streamer = true, \
414 .must_use_separate_stencil = true, \
416 .has_sample_with_hiz = false, \
418 .has_integer_dword_mul = true, \
419 .has_64bit_types = true, \
420 .supports_simd16_3src = true, \
421 .has_surface_tile_offset = true, \
422 .num_thread_per_eu = 7, \
423 .max_vs_threads = 504, \
424 .max_tcs_threads = 504, \
425 .max_tes_threads = 504, \
426 .max_gs_threads = 504, \
427 .max_wm_threads = 384, \
428 .timestamp_frequency = 12500000
430 static const struct gen_device_info gen_device_info_bdw_gt1
= {
431 GEN8_FEATURES
, .gt
= 1,
432 .is_broadwell
= true,
434 .num_subslices
= { 2, },
435 .num_eu_per_subslice
= 8,
437 .max_cs_threads
= 42,
441 [MESA_SHADER_VERTEX
] = 64,
442 [MESA_SHADER_TESS_EVAL
] = 34,
445 [MESA_SHADER_VERTEX
] = 2560,
446 [MESA_SHADER_TESS_CTRL
] = 504,
447 [MESA_SHADER_TESS_EVAL
] = 1536,
448 [MESA_SHADER_GEOMETRY
] = 960,
454 static const struct gen_device_info gen_device_info_bdw_gt2
= {
455 GEN8_FEATURES
, .gt
= 2,
456 .is_broadwell
= true,
458 .num_subslices
= { 3, },
459 .num_eu_per_subslice
= 8,
461 .max_cs_threads
= 56,
465 [MESA_SHADER_VERTEX
] = 64,
466 [MESA_SHADER_TESS_EVAL
] = 34,
469 [MESA_SHADER_VERTEX
] = 2560,
470 [MESA_SHADER_TESS_CTRL
] = 504,
471 [MESA_SHADER_TESS_EVAL
] = 1536,
472 [MESA_SHADER_GEOMETRY
] = 960,
478 static const struct gen_device_info gen_device_info_bdw_gt3
= {
479 GEN8_FEATURES
, .gt
= 3,
480 .is_broadwell
= true,
482 .num_subslices
= { 3, 3, },
483 .num_eu_per_subslice
= 8,
485 .max_cs_threads
= 56,
489 [MESA_SHADER_VERTEX
] = 64,
490 [MESA_SHADER_TESS_EVAL
] = 34,
493 [MESA_SHADER_VERTEX
] = 2560,
494 [MESA_SHADER_TESS_CTRL
] = 504,
495 [MESA_SHADER_TESS_EVAL
] = 1536,
496 [MESA_SHADER_GEOMETRY
] = 960,
502 static const struct gen_device_info gen_device_info_chv
= {
503 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
505 .has_integer_dword_mul
= false,
507 .num_subslices
= { 2, },
508 .num_eu_per_subslice
= 8,
510 .max_vs_threads
= 80,
511 .max_tcs_threads
= 80,
512 .max_tes_threads
= 80,
513 .max_gs_threads
= 80,
514 .max_wm_threads
= 128,
515 .max_cs_threads
= 6 * 7,
519 [MESA_SHADER_VERTEX
] = 34,
520 [MESA_SHADER_TESS_EVAL
] = 34,
523 [MESA_SHADER_VERTEX
] = 640,
524 [MESA_SHADER_TESS_CTRL
] = 80,
525 [MESA_SHADER_TESS_EVAL
] = 384,
526 [MESA_SHADER_GEOMETRY
] = 256,
532 #define GEN9_HW_INFO \
534 .max_vs_threads = 336, \
535 .max_gs_threads = 336, \
536 .max_tcs_threads = 336, \
537 .max_tes_threads = 336, \
538 .max_cs_threads = 56, \
539 .timestamp_frequency = 12000000, \
543 [MESA_SHADER_VERTEX] = 64, \
544 [MESA_SHADER_TESS_EVAL] = 34, \
547 [MESA_SHADER_VERTEX] = 1856, \
548 [MESA_SHADER_TESS_CTRL] = 672, \
549 [MESA_SHADER_TESS_EVAL] = 1120, \
550 [MESA_SHADER_GEOMETRY] = 640, \
554 #define GEN9_LP_FEATURES \
557 .has_integer_dword_mul = false, \
560 .has_sample_with_hiz = true, \
562 .num_thread_per_eu = 6, \
563 .max_vs_threads = 112, \
564 .max_tcs_threads = 112, \
565 .max_tes_threads = 112, \
566 .max_gs_threads = 112, \
567 .max_cs_threads = 6 * 6, \
568 .timestamp_frequency = 19200000, \
572 [MESA_SHADER_VERTEX] = 34, \
573 [MESA_SHADER_TESS_EVAL] = 34, \
576 [MESA_SHADER_VERTEX] = 704, \
577 [MESA_SHADER_TESS_CTRL] = 256, \
578 [MESA_SHADER_TESS_EVAL] = 416, \
579 [MESA_SHADER_GEOMETRY] = 256, \
583 #define GEN9_LP_FEATURES_3X6 \
585 .num_subslices = { 3, }, \
586 .num_eu_per_subslice = 6
588 #define GEN9_LP_FEATURES_2X6 \
590 .num_subslices = { 2, }, \
591 .num_eu_per_subslice = 6, \
592 .max_vs_threads = 56, \
593 .max_tcs_threads = 56, \
594 .max_tes_threads = 56, \
595 .max_gs_threads = 56, \
596 .max_cs_threads = 6 * 6, \
600 [MESA_SHADER_VERTEX] = 34, \
601 [MESA_SHADER_TESS_EVAL] = 34, \
604 [MESA_SHADER_VERTEX] = 352, \
605 [MESA_SHADER_TESS_CTRL] = 128, \
606 [MESA_SHADER_TESS_EVAL] = 208, \
607 [MESA_SHADER_GEOMETRY] = 128, \
611 #define GEN9_FEATURES \
614 .has_sample_with_hiz = true
616 static const struct gen_device_info gen_device_info_skl_gt1
= {
617 GEN9_FEATURES
, .gt
= 1,
620 .num_subslices
= { 2, },
621 .num_eu_per_subslice
= 6,
624 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
625 * leading to some vertices to go missing if we use too much URB.
627 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
631 static const struct gen_device_info gen_device_info_skl_gt2
= {
632 GEN9_FEATURES
, .gt
= 2,
635 .num_subslices
= { 3, },
636 .num_eu_per_subslice
= 8,
641 static const struct gen_device_info gen_device_info_skl_gt3
= {
642 GEN9_FEATURES
, .gt
= 3,
645 .num_subslices
= { 3, 3, },
646 .num_eu_per_subslice
= 8,
651 static const struct gen_device_info gen_device_info_skl_gt4
= {
652 GEN9_FEATURES
, .gt
= 4,
655 .num_subslices
= { 3, 3, 3, },
656 .num_eu_per_subslice
= 8,
658 /* From the "L3 Allocation and Programming" documentation:
660 * "URB is limited to 1008KB due to programming restrictions. This is not a
661 * restriction of the L3 implementation, but of the FF and other clients.
662 * Therefore, in a GT4 implementation it is possible for the programmed
663 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
664 * only 1008KB of this will be used."
666 .urb
.size
= 1008 / 3,
670 static const struct gen_device_info gen_device_info_bxt
= {
671 GEN9_LP_FEATURES_3X6
,
677 static const struct gen_device_info gen_device_info_bxt_2x6
= {
678 GEN9_LP_FEATURES_2X6
,
684 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
685 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
688 static const struct gen_device_info gen_device_info_kbl_gt1
= {
693 .max_cs_threads
= 7 * 6,
696 .num_subslices
= { 2, },
697 .num_eu_per_subslice
= 6,
699 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
700 * leading to some vertices to go missing if we use too much URB.
702 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
706 static const struct gen_device_info gen_device_info_kbl_gt1_5
= {
711 .max_cs_threads
= 7 * 6,
713 .num_subslices
= { 3, },
714 .num_eu_per_subslice
= 6,
719 static const struct gen_device_info gen_device_info_kbl_gt2
= {
725 .num_subslices
= { 3, },
726 .num_eu_per_subslice
= 8,
731 static const struct gen_device_info gen_device_info_kbl_gt3
= {
737 .num_subslices
= { 3, 3, },
738 .num_eu_per_subslice
= 8,
743 static const struct gen_device_info gen_device_info_kbl_gt4
= {
749 * From the "L3 Allocation and Programming" documentation:
751 * "URB is limited to 1008KB due to programming restrictions. This
752 * is not a restriction of the L3 implementation, but of the FF and
753 * other clients. Therefore, in a GT4 implementation it is
754 * possible for the programmed allocation of the L3 data array to
755 * provide 3*384KB=1152KB for URB, but only 1008KB of this
758 .urb
.size
= 1008 / 3,
760 .num_subslices
= { 3, 3, 3, },
761 .num_eu_per_subslice
= 8,
766 static const struct gen_device_info gen_device_info_glk
= {
767 GEN9_LP_FEATURES_3X6
,
768 .is_geminilake
= true,
773 static const struct gen_device_info gen_device_info_glk_2x6
= {
774 GEN9_LP_FEATURES_2X6
,
775 .is_geminilake
= true,
780 static const struct gen_device_info gen_device_info_cfl_gt1
= {
782 .is_coffeelake
= true,
786 .num_subslices
= { 2, },
787 .num_eu_per_subslice
= 6,
790 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
791 * leading to some vertices to go missing if we use too much URB.
793 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
796 static const struct gen_device_info gen_device_info_cfl_gt2
= {
798 .is_coffeelake
= true,
802 .num_subslices
= { 3, },
803 .num_eu_per_subslice
= 8,
808 static const struct gen_device_info gen_device_info_cfl_gt3
= {
810 .is_coffeelake
= true,
814 .num_subslices
= { 3, 3, },
815 .num_eu_per_subslice
= 8,
820 #define GEN10_HW_INFO \
822 .num_thread_per_eu = 7, \
823 .max_vs_threads = 728, \
824 .max_gs_threads = 432, \
825 .max_tcs_threads = 432, \
826 .max_tes_threads = 624, \
827 .max_cs_threads = 56, \
828 .timestamp_frequency = 19200000, \
832 [MESA_SHADER_VERTEX] = 64, \
833 [MESA_SHADER_TESS_EVAL] = 34, \
836 [MESA_SHADER_VERTEX] = 3936, \
837 [MESA_SHADER_TESS_CTRL] = 896, \
838 [MESA_SHADER_TESS_EVAL] = 2064, \
839 [MESA_SHADER_GEOMETRY] = 832, \
843 #define subslices(args...) { args, }
845 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
848 .has_sample_with_hiz = true, \
850 .num_slices = _slices, \
851 .num_subslices = _subslices, \
852 .num_eu_per_subslice = 8, \
855 static const struct gen_device_info gen_device_info_cnl_2x8
= {
857 GEN10_FEATURES(1, 1, subslices(2), 2),
858 .is_cannonlake
= true,
862 static const struct gen_device_info gen_device_info_cnl_3x8
= {
864 GEN10_FEATURES(1, 1, subslices(3), 3),
865 .is_cannonlake
= true,
869 static const struct gen_device_info gen_device_info_cnl_4x8
= {
871 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
872 .is_cannonlake
= true,
876 static const struct gen_device_info gen_device_info_cnl_5x8
= {
878 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
879 .is_cannonlake
= true,
883 #define GEN11_HW_INFO \
886 .max_vs_threads = 364, \
887 .max_gs_threads = 224, \
888 .max_tcs_threads = 224, \
889 .max_tes_threads = 364, \
892 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
895 .has_64bit_types = false, \
896 .has_integer_dword_mul = false, \
897 .has_sample_with_hiz = false, \
898 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
899 .num_subslices = _subslices, \
900 .num_eu_per_subslice = 8
902 #define GEN11_URB_MIN_MAX_ENTRIES \
904 [MESA_SHADER_VERTEX] = 64, \
905 [MESA_SHADER_TESS_EVAL] = 34, \
908 [MESA_SHADER_VERTEX] = 2384, \
909 [MESA_SHADER_TESS_CTRL] = 1032, \
910 [MESA_SHADER_TESS_EVAL] = 2384, \
911 [MESA_SHADER_GEOMETRY] = 1032, \
914 static const struct gen_device_info gen_device_info_icl_8x8
= {
915 GEN11_FEATURES(2, 1, subslices(8), 8),
918 GEN11_URB_MIN_MAX_ENTRIES
,
923 static const struct gen_device_info gen_device_info_icl_6x8
= {
924 GEN11_FEATURES(1, 1, subslices(6), 6),
927 GEN11_URB_MIN_MAX_ENTRIES
,
932 static const struct gen_device_info gen_device_info_icl_4x8
= {
933 GEN11_FEATURES(1, 1, subslices(4), 6),
936 GEN11_URB_MIN_MAX_ENTRIES
,
941 static const struct gen_device_info gen_device_info_icl_1x8
= {
942 GEN11_FEATURES(1, 1, subslices(1), 6),
945 GEN11_URB_MIN_MAX_ENTRIES
,
950 static const struct gen_device_info gen_device_info_ehl_4x8
= {
951 GEN11_FEATURES(1, 1, subslices(4), 4),
952 .is_elkhartlake
= true,
956 [MESA_SHADER_VERTEX
] = 64,
957 [MESA_SHADER_TESS_EVAL
] = 34,
960 [MESA_SHADER_VERTEX
] = 2384,
961 [MESA_SHADER_TESS_CTRL
] = 1032,
962 [MESA_SHADER_TESS_EVAL
] = 2384,
963 [MESA_SHADER_GEOMETRY
] = 1032,
966 .disable_ccs_repack
= true,
970 /* FIXME: Verfiy below entries when more information is available for this SKU.
972 static const struct gen_device_info gen_device_info_ehl_4x4
= {
973 GEN11_FEATURES(1, 1, subslices(4), 4),
974 .is_elkhartlake
= true,
978 [MESA_SHADER_VERTEX
] = 64,
979 [MESA_SHADER_TESS_EVAL
] = 34,
982 [MESA_SHADER_VERTEX
] = 2384,
983 [MESA_SHADER_TESS_CTRL
] = 1032,
984 [MESA_SHADER_TESS_EVAL
] = 2384,
985 [MESA_SHADER_GEOMETRY
] = 1032,
988 .disable_ccs_repack
= true,
989 .num_eu_per_subslice
= 4,
993 /* FIXME: Verfiy below entries when more information is available for this SKU.
995 static const struct gen_device_info gen_device_info_ehl_2x4
= {
996 GEN11_FEATURES(1, 1, subslices(2), 4),
997 .is_elkhartlake
= true,
1001 [MESA_SHADER_VERTEX
] = 64,
1002 [MESA_SHADER_TESS_EVAL
] = 34,
1005 [MESA_SHADER_VERTEX
] = 2384,
1006 [MESA_SHADER_TESS_CTRL
] = 1032,
1007 [MESA_SHADER_TESS_EVAL
] = 2384,
1008 [MESA_SHADER_GEOMETRY
] = 1032,
1011 .disable_ccs_repack
= true,
1012 .num_eu_per_subslice
=4,
1016 #define GEN12_URB_MIN_MAX_ENTRIES \
1018 [MESA_SHADER_VERTEX] = 64, \
1019 [MESA_SHADER_TESS_EVAL] = 34, \
1022 [MESA_SHADER_VERTEX] = 3576, \
1023 [MESA_SHADER_TESS_CTRL] = 1548, \
1024 [MESA_SHADER_TESS_EVAL] = 3576, \
1025 [MESA_SHADER_GEOMETRY] = 1548, \
1028 #define GEN12_HW_INFO \
1031 .has_sample_with_hiz = false, \
1032 .has_aux_map = true, \
1033 .max_vs_threads = 546, \
1034 .max_gs_threads = 336, \
1035 .max_tcs_threads = 336, \
1036 .max_tes_threads = 546, \
1037 .max_cs_threads = 112, /* threads per DSS */ \
1039 GEN12_URB_MIN_MAX_ENTRIES, \
1042 #define GEN12_FEATURES(_gt, _slices, _dual_subslices, _l3) \
1045 .has_64bit_types = false, \
1046 .has_integer_dword_mul = false, \
1047 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
1048 .simulator_id = 22, \
1049 .urb.size = (_gt) == 1 ? 512 : 1024, \
1050 .num_subslices = _dual_subslices, \
1051 .num_eu_per_subslice = 16
1053 #define dual_subslices(args...) { args, }
1055 static const struct gen_device_info gen_device_info_tgl_1x2x16
= {
1056 GEN12_FEATURES(1, 1, dual_subslices(2), 8),
1059 static const struct gen_device_info gen_device_info_tgl_1x6x16
= {
1060 GEN12_FEATURES(2, 1, dual_subslices(6), 8),
1064 gen_device_info_set_eu_mask(struct gen_device_info
*devinfo
,
1069 unsigned subslice_offset
= slice
* devinfo
->eu_slice_stride
+
1070 subslice
* devinfo
->eu_subslice_stride
;
1072 for (unsigned b_eu
= 0; b_eu
< devinfo
->eu_subslice_stride
; b_eu
++) {
1073 devinfo
->eu_masks
[subslice_offset
+ b_eu
] =
1074 (((1U << devinfo
->num_eu_per_subslice
) - 1) >> (b_eu
* 8)) & 0xff;
1078 /* Generate slice/subslice/eu masks from number of
1079 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1082 * These can be overridden with values reported by the kernel either from
1083 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1084 * through the i915 query uapi.
1087 fill_masks(struct gen_device_info
*devinfo
)
1089 devinfo
->slice_masks
= (1U << devinfo
->num_slices
) - 1;
1091 /* Subslice masks */
1092 unsigned max_subslices
= 0;
1093 for (int s
= 0; s
< devinfo
->num_slices
; s
++)
1094 max_subslices
= MAX2(devinfo
->num_subslices
[s
], max_subslices
);
1095 devinfo
->subslice_slice_stride
= DIV_ROUND_UP(max_subslices
, 8);
1097 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1098 devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
] =
1099 (1U << devinfo
->num_subslices
[s
]) - 1;
1103 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(devinfo
->num_eu_per_subslice
, 8);
1104 devinfo
->eu_slice_stride
= max_subslices
* devinfo
->eu_subslice_stride
;
1106 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1107 for (int ss
= 0; ss
< devinfo
->num_subslices
[s
]; ss
++) {
1108 gen_device_info_set_eu_mask(devinfo
, s
, ss
,
1109 (1U << devinfo
->num_eu_per_subslice
) - 1);
1115 reset_masks(struct gen_device_info
*devinfo
)
1117 devinfo
->subslice_slice_stride
= 0;
1118 devinfo
->eu_subslice_stride
= 0;
1119 devinfo
->eu_slice_stride
= 0;
1121 devinfo
->num_slices
= 0;
1122 devinfo
->num_eu_per_subslice
= 0;
1123 memset(devinfo
->num_subslices
, 0, sizeof(devinfo
->num_subslices
));
1125 memset(&devinfo
->slice_masks
, 0, sizeof(devinfo
->slice_masks
));
1126 memset(devinfo
->subslice_masks
, 0, sizeof(devinfo
->subslice_masks
));
1127 memset(devinfo
->eu_masks
, 0, sizeof(devinfo
->eu_masks
));
1128 memset(devinfo
->ppipe_subslices
, 0, sizeof(devinfo
->ppipe_subslices
));
1132 update_from_topology(struct gen_device_info
*devinfo
,
1133 const struct drm_i915_query_topology_info
*topology
)
1135 reset_masks(devinfo
);
1137 devinfo
->subslice_slice_stride
= topology
->subslice_stride
;
1139 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(topology
->max_eus_per_subslice
, 8);
1140 devinfo
->eu_slice_stride
= topology
->max_subslices
* devinfo
->eu_subslice_stride
;
1142 assert(sizeof(devinfo
->slice_masks
) >= DIV_ROUND_UP(topology
->max_slices
, 8));
1143 memcpy(&devinfo
->slice_masks
, topology
->data
, DIV_ROUND_UP(topology
->max_slices
, 8));
1144 devinfo
->num_slices
= __builtin_popcount(devinfo
->slice_masks
);
1146 uint32_t subslice_mask_len
=
1147 topology
->max_slices
* topology
->subslice_stride
;
1148 assert(sizeof(devinfo
->subslice_masks
) >= subslice_mask_len
);
1149 memcpy(devinfo
->subslice_masks
, &topology
->data
[topology
->subslice_offset
],
1152 uint32_t n_subslices
= 0;
1153 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1154 if ((devinfo
->slice_masks
& (1 << s
)) == 0)
1157 for (int b
= 0; b
< devinfo
->subslice_slice_stride
; b
++) {
1158 devinfo
->num_subslices
[s
] +=
1159 __builtin_popcount(devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
+ b
]);
1161 n_subslices
+= devinfo
->num_subslices
[s
];
1163 assert(n_subslices
> 0);
1165 if (devinfo
->gen
== 11) {
1166 /* On ICL we only have one slice */
1167 assert(devinfo
->slice_masks
== 1);
1169 /* Count the number of subslices on each pixel pipe. Assume that
1170 * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
1172 unsigned subslices
= devinfo
->subslice_masks
[0];
1174 while (subslices
> 0) {
1176 devinfo
->ppipe_subslices
[ss
>= 4 ? 1 : 0] += 1;
1182 uint32_t eu_mask_len
=
1183 topology
->eu_stride
* topology
->max_subslices
* topology
->max_slices
;
1184 assert(sizeof(devinfo
->eu_masks
) >= eu_mask_len
);
1185 memcpy(devinfo
->eu_masks
, &topology
->data
[topology
->eu_offset
], eu_mask_len
);
1188 for (int b
= 0; b
< eu_mask_len
; b
++)
1189 n_eus
+= __builtin_popcount(devinfo
->eu_masks
[b
]);
1191 devinfo
->num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1195 update_from_masks(struct gen_device_info
*devinfo
, uint32_t slice_mask
,
1196 uint32_t subslice_mask
, uint32_t n_eus
)
1198 struct drm_i915_query_topology_info
*topology
;
1200 assert((slice_mask
& 0xff) == slice_mask
);
1202 size_t data_length
= 100;
1204 topology
= calloc(1, sizeof(*topology
) + data_length
);
1208 topology
->max_slices
= util_last_bit(slice_mask
);
1209 topology
->max_subslices
= util_last_bit(subslice_mask
);
1211 topology
->subslice_offset
= DIV_ROUND_UP(topology
->max_slices
, 8);
1212 topology
->subslice_stride
= DIV_ROUND_UP(topology
->max_subslices
, 8);
1214 uint32_t n_subslices
= __builtin_popcount(slice_mask
) *
1215 __builtin_popcount(subslice_mask
);
1216 uint32_t num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1217 uint32_t eu_mask
= (1U << num_eu_per_subslice
) - 1;
1219 topology
->eu_offset
= topology
->subslice_offset
+
1220 DIV_ROUND_UP(topology
->max_subslices
, 8);
1221 topology
->eu_stride
= DIV_ROUND_UP(num_eu_per_subslice
, 8);
1223 /* Set slice mask in topology */
1224 for (int b
= 0; b
< topology
->subslice_offset
; b
++)
1225 topology
->data
[b
] = (slice_mask
>> (b
* 8)) & 0xff;
1227 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1229 /* Set subslice mask in topology */
1230 for (int b
= 0; b
< topology
->subslice_stride
; b
++) {
1231 int subslice_offset
= topology
->subslice_offset
+
1232 s
* topology
->subslice_stride
+ b
;
1234 topology
->data
[subslice_offset
] = (subslice_mask
>> (b
* 8)) & 0xff;
1237 /* Set eu mask in topology */
1238 for (int ss
= 0; ss
< topology
->max_subslices
; ss
++) {
1239 for (int b
= 0; b
< topology
->eu_stride
; b
++) {
1240 int eu_offset
= topology
->eu_offset
+
1241 (s
* topology
->max_subslices
+ ss
) * topology
->eu_stride
+ b
;
1243 topology
->data
[eu_offset
] = (eu_mask
>> (b
* 8)) & 0xff;
1248 update_from_topology(devinfo
, topology
);
1255 getparam(int fd
, uint32_t param
, int *value
)
1259 struct drm_i915_getparam gp
= {
1264 int ret
= gen_ioctl(fd
, DRM_IOCTL_I915_GETPARAM
, &gp
);
1273 gen_get_device_info_from_pci_id(int pci_id
,
1274 struct gen_device_info
*devinfo
)
1278 #define CHIPSET(id, family, name) \
1279 case id: *devinfo = gen_device_info_##family; break;
1280 #include "pci_ids/i965_pci_ids.h"
1281 #include "pci_ids/iris_pci_ids.h"
1283 fprintf(stderr
, "Driver does not support the 0x%x PCI ID.\n", pci_id
);
1287 fill_masks(devinfo
);
1289 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1291 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1292 * allocate scratch space enough so that each slice has 4 slices allowed."
1294 * The equivalent internal documentation says that this programming note
1295 * applies to all Gen9+ platforms.
1297 * The hardware typically calculates the scratch space pointer by taking
1298 * the base address, and adding per-thread-scratch-space * thread ID.
1299 * Extra padding can be necessary depending how the thread IDs are
1300 * calculated for a particular shader stage.
1303 switch(devinfo
->gen
) {
1306 devinfo
->max_wm_threads
= 64 /* threads-per-PSD */
1307 * devinfo
->num_slices
1308 * 4; /* effective subslices per slice */
1312 devinfo
->max_wm_threads
= 128 /* threads-per-PSD */
1313 * devinfo
->num_slices
1314 * 8; /* subslices per slice */
1317 assert(devinfo
->gen
< 9);
1321 assert(devinfo
->num_slices
<= ARRAY_SIZE(devinfo
->num_subslices
));
1323 devinfo
->chipset_id
= pci_id
;
1328 gen_get_device_name(int devid
)
1332 #define CHIPSET(id, family, name) case id: return name;
1333 #include "pci_ids/i965_pci_ids.h"
1334 #include "pci_ids/iris_pci_ids.h"
1341 * for gen8/gen9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology
1345 getparam_topology(struct gen_device_info
*devinfo
, int fd
)
1348 if (!getparam(fd
, I915_PARAM_SLICE_MASK
, &slice_mask
))
1352 if (!getparam(fd
, I915_PARAM_EU_TOTAL
, &n_eus
))
1355 int subslice_mask
= 0;
1356 if (!getparam(fd
, I915_PARAM_SUBSLICE_MASK
, &subslice_mask
))
1359 return update_from_masks(devinfo
, slice_mask
, subslice_mask
, n_eus
);
1363 * preferred API for updating the topology in devinfo (kernel 4.17+)
1366 query_topology(struct gen_device_info
*devinfo
, int fd
)
1368 struct drm_i915_query_item item
= {
1369 .query_id
= DRM_I915_QUERY_TOPOLOGY_INFO
,
1371 struct drm_i915_query query
= {
1373 .items_ptr
= (uintptr_t) &item
,
1376 if (gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &query
))
1379 if (item
.length
< 0)
1382 struct drm_i915_query_topology_info
*topo_info
=
1383 (struct drm_i915_query_topology_info
*) calloc(1, item
.length
);
1384 item
.data_ptr
= (uintptr_t) topo_info
;
1386 if (gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &query
) ||
1390 update_from_topology(devinfo
, topo_info
);
1399 gen_get_device_info_from_fd(int fd
, struct gen_device_info
*devinfo
)
1401 int devid
= get_pci_device_id_override();
1403 if (!gen_get_device_info_from_pci_id(devid
, devinfo
))
1405 devinfo
->no_hw
= true;
1407 /* query the device id */
1408 if (!getparam(fd
, I915_PARAM_CHIPSET_ID
, &devid
))
1410 if (!gen_get_device_info_from_pci_id(devid
, devinfo
))
1412 devinfo
->no_hw
= false;
1415 /* remaining initializion queries the kernel for device info */
1419 int timestamp_frequency
;
1420 if (getparam(fd
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1421 ×tamp_frequency
))
1422 devinfo
->timestamp_frequency
= timestamp_frequency
;
1423 else if (devinfo
->gen
>= 10)
1424 /* gen10 and later requires the timestamp_frequency to be updated */
1427 if (!getparam(fd
, I915_PARAM_REVISION
, &devinfo
->revision
))
1430 if (!query_topology(devinfo
, fd
)) {
1431 if (devinfo
->gen
>= 10) {
1432 /* topology uAPI required for CNL+ (kernel 4.17+) */
1436 /* else use the kernel 4.13+ api for gen8+. For older kernels, topology
1437 * will be wrong, affecting GPU metrics. In this case, fail silently.
1439 getparam_topology(devinfo
, fd
);