2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "gen_device_info.h"
31 #include "compiler/shader_enums.h"
32 #include "intel/common/gen_gem.h"
33 #include "util/bitscan.h"
34 #include "util/macros.h"
36 #include "drm-uapi/i915_drm.h"
68 * Get the PCI ID for the device name.
70 * Returns -1 if the device is not known.
73 gen_device_name_to_pci_device_id(const char *name
)
75 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
76 if (!strcmp(name_map
[i
].name
, name
))
77 return name_map
[i
].pci_id
;
83 static const struct gen_device_info gen_device_info_i965
= {
85 .has_negative_rhw_bug
= true,
87 .num_subslices
= { 1, },
88 .num_eu_per_subslice
= 8,
89 .num_thread_per_eu
= 4,
92 .max_wm_threads
= 8 * 4,
96 .timestamp_frequency
= 12500000,
100 static const struct gen_device_info gen_device_info_g4x
= {
104 .has_surface_tile_offset
= true,
107 .num_subslices
= { 1, },
108 .num_eu_per_subslice
= 10,
109 .num_thread_per_eu
= 5,
110 .max_vs_threads
= 32,
112 .max_wm_threads
= 10 * 5,
116 .timestamp_frequency
= 12500000,
120 static const struct gen_device_info gen_device_info_ilk
= {
124 .has_surface_tile_offset
= true,
126 .num_subslices
= { 1, },
127 .num_eu_per_subslice
= 12,
128 .num_thread_per_eu
= 6,
129 .max_vs_threads
= 72,
130 .max_gs_threads
= 32,
131 .max_wm_threads
= 12 * 6,
135 .timestamp_frequency
= 12500000,
139 static const struct gen_device_info gen_device_info_snb_gt1
= {
142 .has_hiz_and_separate_stencil
= true,
145 .has_surface_tile_offset
= true,
146 .needs_unlit_centroid_workaround
= true,
148 .num_subslices
= { 1, },
149 .num_eu_per_subslice
= 6,
150 .num_thread_per_eu
= 6, /* Not confirmed */
151 .max_vs_threads
= 24,
152 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
153 .max_wm_threads
= 40,
157 [MESA_SHADER_VERTEX
] = 24,
160 [MESA_SHADER_VERTEX
] = 256,
161 [MESA_SHADER_GEOMETRY
] = 256,
164 .timestamp_frequency
= 12500000,
168 static const struct gen_device_info gen_device_info_snb_gt2
= {
171 .has_hiz_and_separate_stencil
= true,
174 .has_surface_tile_offset
= true,
175 .needs_unlit_centroid_workaround
= true,
177 .num_subslices
= { 1, },
178 .num_eu_per_subslice
= 12,
179 .num_thread_per_eu
= 6, /* Not confirmed */
180 .max_vs_threads
= 60,
181 .max_gs_threads
= 60,
182 .max_wm_threads
= 80,
186 [MESA_SHADER_VERTEX
] = 24,
189 [MESA_SHADER_VERTEX
] = 256,
190 [MESA_SHADER_GEOMETRY
] = 256,
193 .timestamp_frequency
= 12500000,
197 #define GEN7_FEATURES \
199 .has_hiz_and_separate_stencil = true, \
200 .must_use_separate_stencil = true, \
203 .has_64bit_float = true, \
204 .has_surface_tile_offset = true, \
205 .timestamp_frequency = 12500000
207 static const struct gen_device_info gen_device_info_ivb_gt1
= {
208 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
210 .num_subslices
= { 1, },
211 .num_eu_per_subslice
= 6,
212 .num_thread_per_eu
= 6,
214 .max_vs_threads
= 36,
215 .max_tcs_threads
= 36,
216 .max_tes_threads
= 36,
217 .max_gs_threads
= 36,
218 .max_wm_threads
= 48,
219 .max_cs_threads
= 36,
223 [MESA_SHADER_VERTEX
] = 32,
224 [MESA_SHADER_TESS_EVAL
] = 10,
227 [MESA_SHADER_VERTEX
] = 512,
228 [MESA_SHADER_TESS_CTRL
] = 32,
229 [MESA_SHADER_TESS_EVAL
] = 288,
230 [MESA_SHADER_GEOMETRY
] = 192,
236 static const struct gen_device_info gen_device_info_ivb_gt2
= {
237 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
239 .num_subslices
= { 1, },
240 .num_eu_per_subslice
= 12,
241 .num_thread_per_eu
= 8, /* Not sure why this isn't a multiple of
242 * @max_wm_threads ... */
244 .max_vs_threads
= 128,
245 .max_tcs_threads
= 128,
246 .max_tes_threads
= 128,
247 .max_gs_threads
= 128,
248 .max_wm_threads
= 172,
249 .max_cs_threads
= 64,
253 [MESA_SHADER_VERTEX
] = 32,
254 [MESA_SHADER_TESS_EVAL
] = 10,
257 [MESA_SHADER_VERTEX
] = 704,
258 [MESA_SHADER_TESS_CTRL
] = 64,
259 [MESA_SHADER_TESS_EVAL
] = 448,
260 [MESA_SHADER_GEOMETRY
] = 320,
266 static const struct gen_device_info gen_device_info_byt
= {
267 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
269 .num_subslices
= { 1, },
270 .num_eu_per_subslice
= 4,
271 .num_thread_per_eu
= 8,
274 .max_vs_threads
= 36,
275 .max_tcs_threads
= 36,
276 .max_tes_threads
= 36,
277 .max_gs_threads
= 36,
278 .max_wm_threads
= 48,
279 .max_cs_threads
= 32,
283 [MESA_SHADER_VERTEX
] = 32,
284 [MESA_SHADER_TESS_EVAL
] = 10,
287 [MESA_SHADER_VERTEX
] = 512,
288 [MESA_SHADER_TESS_CTRL
] = 32,
289 [MESA_SHADER_TESS_EVAL
] = 288,
290 [MESA_SHADER_GEOMETRY
] = 192,
296 #define HSW_FEATURES \
298 .is_haswell = true, \
299 .supports_simd16_3src = true, \
300 .has_resource_streamer = true
302 static const struct gen_device_info gen_device_info_hsw_gt1
= {
303 HSW_FEATURES
, .gt
= 1,
305 .num_subslices
= { 1, },
306 .num_eu_per_subslice
= 10,
307 .num_thread_per_eu
= 7,
309 .max_vs_threads
= 70,
310 .max_tcs_threads
= 70,
311 .max_tes_threads
= 70,
312 .max_gs_threads
= 70,
313 .max_wm_threads
= 102,
314 .max_cs_threads
= 70,
318 [MESA_SHADER_VERTEX
] = 32,
319 [MESA_SHADER_TESS_EVAL
] = 10,
322 [MESA_SHADER_VERTEX
] = 640,
323 [MESA_SHADER_TESS_CTRL
] = 64,
324 [MESA_SHADER_TESS_EVAL
] = 384,
325 [MESA_SHADER_GEOMETRY
] = 256,
331 static const struct gen_device_info gen_device_info_hsw_gt2
= {
332 HSW_FEATURES
, .gt
= 2,
334 .num_subslices
= { 2, },
335 .num_eu_per_subslice
= 10,
336 .num_thread_per_eu
= 7,
338 .max_vs_threads
= 280,
339 .max_tcs_threads
= 256,
340 .max_tes_threads
= 280,
341 .max_gs_threads
= 256,
342 .max_wm_threads
= 204,
343 .max_cs_threads
= 70,
347 [MESA_SHADER_VERTEX
] = 64,
348 [MESA_SHADER_TESS_EVAL
] = 10,
351 [MESA_SHADER_VERTEX
] = 1664,
352 [MESA_SHADER_TESS_CTRL
] = 128,
353 [MESA_SHADER_TESS_EVAL
] = 960,
354 [MESA_SHADER_GEOMETRY
] = 640,
360 static const struct gen_device_info gen_device_info_hsw_gt3
= {
361 HSW_FEATURES
, .gt
= 3,
363 .num_subslices
= { 2, },
364 .num_eu_per_subslice
= 10,
365 .num_thread_per_eu
= 7,
367 .max_vs_threads
= 280,
368 .max_tcs_threads
= 256,
369 .max_tes_threads
= 280,
370 .max_gs_threads
= 256,
371 .max_wm_threads
= 408,
372 .max_cs_threads
= 70,
376 [MESA_SHADER_VERTEX
] = 64,
377 [MESA_SHADER_TESS_EVAL
] = 10,
380 [MESA_SHADER_VERTEX
] = 1664,
381 [MESA_SHADER_TESS_CTRL
] = 128,
382 [MESA_SHADER_TESS_EVAL
] = 960,
383 [MESA_SHADER_GEOMETRY
] = 640,
389 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
390 * so keep things conservative for now and set has_sample_with_hiz = false.
392 #define GEN8_FEATURES \
394 .has_hiz_and_separate_stencil = true, \
395 .has_resource_streamer = true, \
396 .must_use_separate_stencil = true, \
398 .has_sample_with_hiz = false, \
400 .has_integer_dword_mul = true, \
401 .has_64bit_float = true, \
402 .has_64bit_int = true, \
403 .supports_simd16_3src = true, \
404 .has_surface_tile_offset = true, \
405 .num_thread_per_eu = 7, \
406 .max_vs_threads = 504, \
407 .max_tcs_threads = 504, \
408 .max_tes_threads = 504, \
409 .max_gs_threads = 504, \
410 .max_wm_threads = 384, \
411 .timestamp_frequency = 12500000
413 static const struct gen_device_info gen_device_info_bdw_gt1
= {
414 GEN8_FEATURES
, .gt
= 1,
415 .is_broadwell
= true,
417 .num_subslices
= { 2, },
418 .num_eu_per_subslice
= 6,
420 .max_cs_threads
= 42,
424 [MESA_SHADER_VERTEX
] = 64,
425 [MESA_SHADER_TESS_EVAL
] = 34,
428 [MESA_SHADER_VERTEX
] = 2560,
429 [MESA_SHADER_TESS_CTRL
] = 504,
430 [MESA_SHADER_TESS_EVAL
] = 1536,
431 /* Reduced from 960, seems to be similar to the bug on Gen9 GT1. */
432 [MESA_SHADER_GEOMETRY
] = 690,
438 static const struct gen_device_info gen_device_info_bdw_gt2
= {
439 GEN8_FEATURES
, .gt
= 2,
440 .is_broadwell
= true,
442 .num_subslices
= { 3, },
443 .num_eu_per_subslice
= 8,
445 .max_cs_threads
= 56,
449 [MESA_SHADER_VERTEX
] = 64,
450 [MESA_SHADER_TESS_EVAL
] = 34,
453 [MESA_SHADER_VERTEX
] = 2560,
454 [MESA_SHADER_TESS_CTRL
] = 504,
455 [MESA_SHADER_TESS_EVAL
] = 1536,
456 [MESA_SHADER_GEOMETRY
] = 960,
462 static const struct gen_device_info gen_device_info_bdw_gt3
= {
463 GEN8_FEATURES
, .gt
= 3,
464 .is_broadwell
= true,
466 .num_subslices
= { 3, 3, },
467 .num_eu_per_subslice
= 8,
469 .max_cs_threads
= 56,
473 [MESA_SHADER_VERTEX
] = 64,
474 [MESA_SHADER_TESS_EVAL
] = 34,
477 [MESA_SHADER_VERTEX
] = 2560,
478 [MESA_SHADER_TESS_CTRL
] = 504,
479 [MESA_SHADER_TESS_EVAL
] = 1536,
480 [MESA_SHADER_GEOMETRY
] = 960,
486 static const struct gen_device_info gen_device_info_chv
= {
487 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
489 .has_integer_dword_mul
= false,
491 .num_subslices
= { 2, },
492 .num_eu_per_subslice
= 8,
494 .max_vs_threads
= 80,
495 .max_tcs_threads
= 80,
496 .max_tes_threads
= 80,
497 .max_gs_threads
= 80,
498 .max_wm_threads
= 128,
499 .max_cs_threads
= 6 * 7,
503 [MESA_SHADER_VERTEX
] = 34,
504 [MESA_SHADER_TESS_EVAL
] = 34,
507 [MESA_SHADER_VERTEX
] = 640,
508 [MESA_SHADER_TESS_CTRL
] = 80,
509 [MESA_SHADER_TESS_EVAL
] = 384,
510 [MESA_SHADER_GEOMETRY
] = 256,
516 #define GEN9_HW_INFO \
518 .max_vs_threads = 336, \
519 .max_gs_threads = 336, \
520 .max_tcs_threads = 336, \
521 .max_tes_threads = 336, \
522 .max_cs_threads = 56, \
523 .timestamp_frequency = 12000000, \
527 [MESA_SHADER_VERTEX] = 64, \
528 [MESA_SHADER_TESS_EVAL] = 34, \
531 [MESA_SHADER_VERTEX] = 1856, \
532 [MESA_SHADER_TESS_CTRL] = 672, \
533 [MESA_SHADER_TESS_EVAL] = 1120, \
534 [MESA_SHADER_GEOMETRY] = 640, \
538 #define GEN9_LP_FEATURES \
541 .has_integer_dword_mul = false, \
544 .has_sample_with_hiz = true, \
546 .num_thread_per_eu = 6, \
547 .max_vs_threads = 112, \
548 .max_tcs_threads = 112, \
549 .max_tes_threads = 112, \
550 .max_gs_threads = 112, \
551 .max_cs_threads = 6 * 6, \
552 .timestamp_frequency = 19200000, \
556 [MESA_SHADER_VERTEX] = 34, \
557 [MESA_SHADER_TESS_EVAL] = 34, \
560 [MESA_SHADER_VERTEX] = 704, \
561 [MESA_SHADER_TESS_CTRL] = 256, \
562 [MESA_SHADER_TESS_EVAL] = 416, \
563 [MESA_SHADER_GEOMETRY] = 256, \
567 #define GEN9_LP_FEATURES_3X6 \
569 .num_subslices = { 3, }, \
570 .num_eu_per_subslice = 6
572 #define GEN9_LP_FEATURES_2X6 \
574 .num_subslices = { 2, }, \
575 .num_eu_per_subslice = 6, \
576 .max_vs_threads = 56, \
577 .max_tcs_threads = 56, \
578 .max_tes_threads = 56, \
579 .max_gs_threads = 56, \
580 .max_cs_threads = 6 * 6, \
584 [MESA_SHADER_VERTEX] = 34, \
585 [MESA_SHADER_TESS_EVAL] = 34, \
588 [MESA_SHADER_VERTEX] = 352, \
589 [MESA_SHADER_TESS_CTRL] = 128, \
590 [MESA_SHADER_TESS_EVAL] = 208, \
591 [MESA_SHADER_GEOMETRY] = 128, \
595 #define GEN9_FEATURES \
598 .has_sample_with_hiz = true
600 static const struct gen_device_info gen_device_info_skl_gt1
= {
601 GEN9_FEATURES
, .gt
= 1,
604 .num_subslices
= { 2, },
605 .num_eu_per_subslice
= 6,
608 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
609 * leading to some vertices to go missing if we use too much URB.
611 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
615 static const struct gen_device_info gen_device_info_skl_gt2
= {
616 GEN9_FEATURES
, .gt
= 2,
619 .num_subslices
= { 3, },
620 .num_eu_per_subslice
= 8,
625 static const struct gen_device_info gen_device_info_skl_gt3
= {
626 GEN9_FEATURES
, .gt
= 3,
629 .num_subslices
= { 3, 3, },
630 .num_eu_per_subslice
= 8,
635 static const struct gen_device_info gen_device_info_skl_gt4
= {
636 GEN9_FEATURES
, .gt
= 4,
639 .num_subslices
= { 3, 3, 3, },
640 .num_eu_per_subslice
= 8,
642 /* From the "L3 Allocation and Programming" documentation:
644 * "URB is limited to 1008KB due to programming restrictions. This is not a
645 * restriction of the L3 implementation, but of the FF and other clients.
646 * Therefore, in a GT4 implementation it is possible for the programmed
647 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
648 * only 1008KB of this will be used."
650 .urb
.size
= 1008 / 3,
654 static const struct gen_device_info gen_device_info_bxt
= {
655 GEN9_LP_FEATURES_3X6
,
661 static const struct gen_device_info gen_device_info_bxt_2x6
= {
662 GEN9_LP_FEATURES_2X6
,
668 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
669 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
672 static const struct gen_device_info gen_device_info_kbl_gt1
= {
677 .max_cs_threads
= 7 * 6,
680 .num_subslices
= { 2, },
681 .num_eu_per_subslice
= 6,
683 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
684 * leading to some vertices to go missing if we use too much URB.
686 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
690 static const struct gen_device_info gen_device_info_kbl_gt1_5
= {
695 .max_cs_threads
= 7 * 6,
697 .num_subslices
= { 3, },
698 .num_eu_per_subslice
= 6,
703 static const struct gen_device_info gen_device_info_kbl_gt2
= {
709 .num_subslices
= { 3, },
710 .num_eu_per_subslice
= 8,
715 static const struct gen_device_info gen_device_info_kbl_gt3
= {
721 .num_subslices
= { 3, 3, },
722 .num_eu_per_subslice
= 8,
727 static const struct gen_device_info gen_device_info_kbl_gt4
= {
733 * From the "L3 Allocation and Programming" documentation:
735 * "URB is limited to 1008KB due to programming restrictions. This
736 * is not a restriction of the L3 implementation, but of the FF and
737 * other clients. Therefore, in a GT4 implementation it is
738 * possible for the programmed allocation of the L3 data array to
739 * provide 3*384KB=1152KB for URB, but only 1008KB of this
742 .urb
.size
= 1008 / 3,
744 .num_subslices
= { 3, 3, 3, },
745 .num_eu_per_subslice
= 8,
750 static const struct gen_device_info gen_device_info_glk
= {
751 GEN9_LP_FEATURES_3X6
,
752 .is_geminilake
= true,
757 static const struct gen_device_info gen_device_info_glk_2x6
= {
758 GEN9_LP_FEATURES_2X6
,
759 .is_geminilake
= true,
764 static const struct gen_device_info gen_device_info_cfl_gt1
= {
766 .is_coffeelake
= true,
770 .num_subslices
= { 2, },
771 .num_eu_per_subslice
= 6,
774 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
775 * leading to some vertices to go missing if we use too much URB.
777 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
780 static const struct gen_device_info gen_device_info_cfl_gt2
= {
782 .is_coffeelake
= true,
786 .num_subslices
= { 3, },
787 .num_eu_per_subslice
= 8,
792 static const struct gen_device_info gen_device_info_cfl_gt3
= {
794 .is_coffeelake
= true,
798 .num_subslices
= { 3, 3, },
799 .num_eu_per_subslice
= 8,
804 #define GEN10_HW_INFO \
806 .num_thread_per_eu = 7, \
807 .max_vs_threads = 728, \
808 .max_gs_threads = 432, \
809 .max_tcs_threads = 432, \
810 .max_tes_threads = 624, \
811 .max_cs_threads = 56, \
812 .timestamp_frequency = 19200000, \
816 [MESA_SHADER_VERTEX] = 64, \
817 [MESA_SHADER_TESS_EVAL] = 34, \
820 [MESA_SHADER_VERTEX] = 3936, \
821 [MESA_SHADER_TESS_CTRL] = 896, \
822 [MESA_SHADER_TESS_EVAL] = 2064, \
823 [MESA_SHADER_GEOMETRY] = 832, \
827 #define subslices(args...) { args, }
829 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
832 .has_sample_with_hiz = true, \
834 .num_slices = _slices, \
835 .num_subslices = _subslices, \
836 .num_eu_per_subslice = 8, \
839 static const struct gen_device_info gen_device_info_cnl_gt0_5
= {
841 GEN10_FEATURES(1, 1, subslices(2), 2),
842 .is_cannonlake
= true,
846 static const struct gen_device_info gen_device_info_cnl_gt1
= {
848 GEN10_FEATURES(1, 1, subslices(3), 3),
849 .is_cannonlake
= true,
853 static const struct gen_device_info gen_device_info_cnl_gt1_5
= {
855 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
856 .is_cannonlake
= true,
860 static const struct gen_device_info gen_device_info_cnl_gt2
= {
862 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
863 .is_cannonlake
= true,
867 #define GEN11_HW_INFO \
870 .max_vs_threads = 364, \
871 .max_gs_threads = 224, \
872 .max_tcs_threads = 224, \
873 .max_tes_threads = 364, \
876 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
879 .has_64bit_float = false, \
880 .has_64bit_int = false, \
881 .has_integer_dword_mul = false, \
882 .has_sample_with_hiz = false, \
883 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
884 .num_subslices = _subslices, \
885 .num_eu_per_subslice = 8
887 #define GEN11_URB_MIN_MAX_ENTRIES \
889 [MESA_SHADER_VERTEX] = 64, \
890 [MESA_SHADER_TESS_EVAL] = 34, \
893 [MESA_SHADER_VERTEX] = 2384, \
894 [MESA_SHADER_TESS_CTRL] = 1032, \
895 [MESA_SHADER_TESS_EVAL] = 2384, \
896 [MESA_SHADER_GEOMETRY] = 1032, \
899 static const struct gen_device_info gen_device_info_icl_gt2
= {
900 GEN11_FEATURES(2, 1, subslices(8), 8),
903 GEN11_URB_MIN_MAX_ENTRIES
,
908 static const struct gen_device_info gen_device_info_icl_gt1_5
= {
909 GEN11_FEATURES(1, 1, subslices(6), 6),
912 GEN11_URB_MIN_MAX_ENTRIES
,
917 static const struct gen_device_info gen_device_info_icl_gt1
= {
918 GEN11_FEATURES(1, 1, subslices(4), 6),
921 GEN11_URB_MIN_MAX_ENTRIES
,
926 static const struct gen_device_info gen_device_info_icl_gt0_5
= {
927 GEN11_FEATURES(1, 1, subslices(1), 6),
930 GEN11_URB_MIN_MAX_ENTRIES
,
935 static const struct gen_device_info gen_device_info_ehl_7
= {
936 GEN11_FEATURES(1, 1, subslices(4), 4),
937 .is_elkhartlake
= true,
941 [MESA_SHADER_VERTEX
] = 64,
942 [MESA_SHADER_TESS_EVAL
] = 34,
945 [MESA_SHADER_VERTEX
] = 2384,
946 [MESA_SHADER_TESS_CTRL
] = 1032,
947 [MESA_SHADER_TESS_EVAL
] = 2384,
948 [MESA_SHADER_GEOMETRY
] = 1032,
951 .disable_ccs_repack
= true,
955 static const struct gen_device_info gen_device_info_ehl_6
= {
956 GEN11_FEATURES(1, 1, subslices(4), 4),
957 .is_elkhartlake
= true,
961 [MESA_SHADER_VERTEX
] = 64,
962 [MESA_SHADER_TESS_EVAL
] = 34,
965 [MESA_SHADER_VERTEX
] = 2384,
966 [MESA_SHADER_TESS_CTRL
] = 1032,
967 [MESA_SHADER_TESS_EVAL
] = 2384,
968 [MESA_SHADER_GEOMETRY
] = 1032,
971 .disable_ccs_repack
= true,
972 .num_eu_per_subslice
= 6,
976 static const struct gen_device_info gen_device_info_ehl_5
= {
977 GEN11_FEATURES(1, 1, subslices(4), 4),
978 .is_elkhartlake
= true,
982 [MESA_SHADER_VERTEX
] = 64,
983 [MESA_SHADER_TESS_EVAL
] = 34,
986 [MESA_SHADER_VERTEX
] = 2384,
987 [MESA_SHADER_TESS_CTRL
] = 1032,
988 [MESA_SHADER_TESS_EVAL
] = 2384,
989 [MESA_SHADER_GEOMETRY
] = 1032,
992 .disable_ccs_repack
= true,
993 .num_eu_per_subslice
= 4,
997 static const struct gen_device_info gen_device_info_ehl_4
= {
998 GEN11_FEATURES(1, 1, subslices(2), 4),
999 .is_elkhartlake
= true,
1003 [MESA_SHADER_VERTEX
] = 64,
1004 [MESA_SHADER_TESS_EVAL
] = 34,
1007 [MESA_SHADER_VERTEX
] = 2384,
1008 [MESA_SHADER_TESS_CTRL
] = 1032,
1009 [MESA_SHADER_TESS_EVAL
] = 2384,
1010 [MESA_SHADER_GEOMETRY
] = 1032,
1013 .disable_ccs_repack
= true,
1014 .num_eu_per_subslice
=4,
1018 #define GEN12_URB_MIN_MAX_ENTRIES \
1020 [MESA_SHADER_VERTEX] = 64, \
1021 [MESA_SHADER_TESS_EVAL] = 34, \
1024 [MESA_SHADER_VERTEX] = 3576, \
1025 [MESA_SHADER_TESS_CTRL] = 1548, \
1026 [MESA_SHADER_TESS_EVAL] = 3576, \
1027 [MESA_SHADER_GEOMETRY] = 1548, \
1030 #define GEN12_HW_INFO \
1033 .has_sample_with_hiz = false, \
1034 .has_aux_map = true, \
1035 .max_vs_threads = 546, \
1036 .max_gs_threads = 336, \
1037 .max_tcs_threads = 336, \
1038 .max_tes_threads = 546, \
1039 .max_cs_threads = 112, /* threads per DSS */ \
1041 GEN12_URB_MIN_MAX_ENTRIES, \
1044 #define GEN12_FEATURES(_gt, _slices, _l3) \
1047 .has_64bit_float = false, \
1048 .has_64bit_int = false, \
1049 .has_integer_dword_mul = false, \
1050 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
1051 .simulator_id = 22, \
1052 .urb.size = (_gt) == 1 ? 512 : 1024, \
1053 .num_eu_per_subslice = 16
1055 #define dual_subslices(args...) { args, }
1057 #define GEN12_GT05_FEATURES \
1058 GEN12_FEATURES(1, 1, 4), \
1059 .num_subslices = dual_subslices(1)
1061 #define GEN12_GT_FEATURES(_gt) \
1062 GEN12_FEATURES(1, 1, _gt == 1 ? 4 : 8), \
1063 .num_subslices = dual_subslices(_gt == 1 ? 2 : 6)
1065 static const struct gen_device_info gen_device_info_tgl_gt1
= {
1066 GEN12_GT_FEATURES(1),
1069 static const struct gen_device_info gen_device_info_tgl_gt2
= {
1070 GEN12_GT_FEATURES(2),
1073 static const struct gen_device_info gen_device_info_rkl_gt05
= {
1074 GEN12_GT05_FEATURES
,
1077 static const struct gen_device_info gen_device_info_rkl_gt1
= {
1078 GEN12_GT_FEATURES(1),
1082 gen_device_info_set_eu_mask(struct gen_device_info
*devinfo
,
1087 unsigned subslice_offset
= slice
* devinfo
->eu_slice_stride
+
1088 subslice
* devinfo
->eu_subslice_stride
;
1090 for (unsigned b_eu
= 0; b_eu
< devinfo
->eu_subslice_stride
; b_eu
++) {
1091 devinfo
->eu_masks
[subslice_offset
+ b_eu
] =
1092 (((1U << devinfo
->num_eu_per_subslice
) - 1) >> (b_eu
* 8)) & 0xff;
1096 /* Generate slice/subslice/eu masks from number of
1097 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1100 * These can be overridden with values reported by the kernel either from
1101 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1102 * through the i915 query uapi.
1105 fill_masks(struct gen_device_info
*devinfo
)
1107 devinfo
->slice_masks
= (1U << devinfo
->num_slices
) - 1;
1109 /* Subslice masks */
1110 unsigned max_subslices
= 0;
1111 for (int s
= 0; s
< devinfo
->num_slices
; s
++)
1112 max_subslices
= MAX2(devinfo
->num_subslices
[s
], max_subslices
);
1113 devinfo
->subslice_slice_stride
= DIV_ROUND_UP(max_subslices
, 8);
1115 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1116 devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
] =
1117 (1U << devinfo
->num_subslices
[s
]) - 1;
1121 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(devinfo
->num_eu_per_subslice
, 8);
1122 devinfo
->eu_slice_stride
= max_subslices
* devinfo
->eu_subslice_stride
;
1124 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1125 for (int ss
= 0; ss
< devinfo
->num_subslices
[s
]; ss
++) {
1126 gen_device_info_set_eu_mask(devinfo
, s
, ss
,
1127 (1U << devinfo
->num_eu_per_subslice
) - 1);
1133 reset_masks(struct gen_device_info
*devinfo
)
1135 devinfo
->subslice_slice_stride
= 0;
1136 devinfo
->eu_subslice_stride
= 0;
1137 devinfo
->eu_slice_stride
= 0;
1139 devinfo
->num_slices
= 0;
1140 devinfo
->num_eu_per_subslice
= 0;
1141 memset(devinfo
->num_subslices
, 0, sizeof(devinfo
->num_subslices
));
1143 memset(&devinfo
->slice_masks
, 0, sizeof(devinfo
->slice_masks
));
1144 memset(devinfo
->subslice_masks
, 0, sizeof(devinfo
->subslice_masks
));
1145 memset(devinfo
->eu_masks
, 0, sizeof(devinfo
->eu_masks
));
1146 memset(devinfo
->ppipe_subslices
, 0, sizeof(devinfo
->ppipe_subslices
));
1150 update_from_topology(struct gen_device_info
*devinfo
,
1151 const struct drm_i915_query_topology_info
*topology
)
1153 reset_masks(devinfo
);
1155 devinfo
->subslice_slice_stride
= topology
->subslice_stride
;
1157 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(topology
->max_eus_per_subslice
, 8);
1158 devinfo
->eu_slice_stride
= topology
->max_subslices
* devinfo
->eu_subslice_stride
;
1160 assert(sizeof(devinfo
->slice_masks
) >= DIV_ROUND_UP(topology
->max_slices
, 8));
1161 memcpy(&devinfo
->slice_masks
, topology
->data
, DIV_ROUND_UP(topology
->max_slices
, 8));
1162 devinfo
->num_slices
= __builtin_popcount(devinfo
->slice_masks
);
1164 uint32_t subslice_mask_len
=
1165 topology
->max_slices
* topology
->subslice_stride
;
1166 assert(sizeof(devinfo
->subslice_masks
) >= subslice_mask_len
);
1167 memcpy(devinfo
->subslice_masks
, &topology
->data
[topology
->subslice_offset
],
1170 uint32_t n_subslices
= 0;
1171 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1172 if ((devinfo
->slice_masks
& (1 << s
)) == 0)
1175 for (int b
= 0; b
< devinfo
->subslice_slice_stride
; b
++) {
1176 devinfo
->num_subslices
[s
] +=
1177 __builtin_popcount(devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
+ b
]);
1179 n_subslices
+= devinfo
->num_subslices
[s
];
1181 assert(n_subslices
> 0);
1183 if (devinfo
->gen
== 11) {
1184 /* On ICL we only have one slice */
1185 assert(devinfo
->slice_masks
== 1);
1187 /* Count the number of subslices on each pixel pipe. Assume that
1188 * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
1190 unsigned subslices
= devinfo
->subslice_masks
[0];
1192 while (subslices
> 0) {
1194 devinfo
->ppipe_subslices
[ss
>= 4 ? 1 : 0] += 1;
1200 if (devinfo
->gen
== 12 && devinfo
->num_slices
== 1) {
1201 if (n_subslices
>= 6) {
1202 assert(n_subslices
== 6);
1203 devinfo
->l3_banks
= 8;
1204 } else if (n_subslices
> 2) {
1205 devinfo
->l3_banks
= 6;
1207 devinfo
->l3_banks
= 4;
1211 uint32_t eu_mask_len
=
1212 topology
->eu_stride
* topology
->max_subslices
* topology
->max_slices
;
1213 assert(sizeof(devinfo
->eu_masks
) >= eu_mask_len
);
1214 memcpy(devinfo
->eu_masks
, &topology
->data
[topology
->eu_offset
], eu_mask_len
);
1217 for (int b
= 0; b
< eu_mask_len
; b
++)
1218 n_eus
+= __builtin_popcount(devinfo
->eu_masks
[b
]);
1220 devinfo
->num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1224 update_from_masks(struct gen_device_info
*devinfo
, uint32_t slice_mask
,
1225 uint32_t subslice_mask
, uint32_t n_eus
)
1227 struct drm_i915_query_topology_info
*topology
;
1229 assert((slice_mask
& 0xff) == slice_mask
);
1231 size_t data_length
= 100;
1233 topology
= calloc(1, sizeof(*topology
) + data_length
);
1237 topology
->max_slices
= util_last_bit(slice_mask
);
1238 topology
->max_subslices
= util_last_bit(subslice_mask
);
1240 topology
->subslice_offset
= DIV_ROUND_UP(topology
->max_slices
, 8);
1241 topology
->subslice_stride
= DIV_ROUND_UP(topology
->max_subslices
, 8);
1243 uint32_t n_subslices
= __builtin_popcount(slice_mask
) *
1244 __builtin_popcount(subslice_mask
);
1245 uint32_t num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1246 uint32_t eu_mask
= (1U << num_eu_per_subslice
) - 1;
1248 topology
->eu_offset
= topology
->subslice_offset
+
1249 DIV_ROUND_UP(topology
->max_subslices
, 8);
1250 topology
->eu_stride
= DIV_ROUND_UP(num_eu_per_subslice
, 8);
1252 /* Set slice mask in topology */
1253 for (int b
= 0; b
< topology
->subslice_offset
; b
++)
1254 topology
->data
[b
] = (slice_mask
>> (b
* 8)) & 0xff;
1256 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1258 /* Set subslice mask in topology */
1259 for (int b
= 0; b
< topology
->subslice_stride
; b
++) {
1260 int subslice_offset
= topology
->subslice_offset
+
1261 s
* topology
->subslice_stride
+ b
;
1263 topology
->data
[subslice_offset
] = (subslice_mask
>> (b
* 8)) & 0xff;
1266 /* Set eu mask in topology */
1267 for (int ss
= 0; ss
< topology
->max_subslices
; ss
++) {
1268 for (int b
= 0; b
< topology
->eu_stride
; b
++) {
1269 int eu_offset
= topology
->eu_offset
+
1270 (s
* topology
->max_subslices
+ ss
) * topology
->eu_stride
+ b
;
1272 topology
->data
[eu_offset
] = (eu_mask
>> (b
* 8)) & 0xff;
1277 update_from_topology(devinfo
, topology
);
1284 getparam(int fd
, uint32_t param
, int *value
)
1288 struct drm_i915_getparam gp
= {
1293 int ret
= gen_ioctl(fd
, DRM_IOCTL_I915_GETPARAM
, &gp
);
1302 gen_get_device_info_from_pci_id(int pci_id
,
1303 struct gen_device_info
*devinfo
)
1307 #define CHIPSET(id, family, fam_str, name) \
1308 case id: *devinfo = gen_device_info_##family; break;
1309 #include "pci_ids/i965_pci_ids.h"
1310 #include "pci_ids/iris_pci_ids.h"
1312 fprintf(stderr
, "Driver does not support the 0x%x PCI ID.\n", pci_id
);
1316 fill_masks(devinfo
);
1318 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1320 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1321 * allocate scratch space enough so that each slice has 4 slices allowed."
1323 * The equivalent internal documentation says that this programming note
1324 * applies to all Gen9+ platforms.
1326 * The hardware typically calculates the scratch space pointer by taking
1327 * the base address, and adding per-thread-scratch-space * thread ID.
1328 * Extra padding can be necessary depending how the thread IDs are
1329 * calculated for a particular shader stage.
1332 switch(devinfo
->gen
) {
1335 devinfo
->max_wm_threads
= 64 /* threads-per-PSD */
1336 * devinfo
->num_slices
1337 * 4; /* effective subslices per slice */
1341 devinfo
->max_wm_threads
= 128 /* threads-per-PSD */
1342 * devinfo
->num_slices
1343 * 8; /* subslices per slice */
1346 assert(devinfo
->gen
< 9);
1350 assert(devinfo
->num_slices
<= ARRAY_SIZE(devinfo
->num_subslices
));
1352 devinfo
->chipset_id
= pci_id
;
1357 gen_get_device_name(int devid
)
1361 #define CHIPSET(id, family, fam_str, name) case id: return name " (" fam_str ")"; break;
1362 #include "pci_ids/i965_pci_ids.h"
1363 #include "pci_ids/iris_pci_ids.h"
1370 * for gen8/gen9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology
1374 getparam_topology(struct gen_device_info
*devinfo
, int fd
)
1377 if (!getparam(fd
, I915_PARAM_SLICE_MASK
, &slice_mask
))
1381 if (!getparam(fd
, I915_PARAM_EU_TOTAL
, &n_eus
))
1384 int subslice_mask
= 0;
1385 if (!getparam(fd
, I915_PARAM_SUBSLICE_MASK
, &subslice_mask
))
1388 return update_from_masks(devinfo
, slice_mask
, subslice_mask
, n_eus
);
1392 * preferred API for updating the topology in devinfo (kernel 4.17+)
1395 query_topology(struct gen_device_info
*devinfo
, int fd
)
1397 struct drm_i915_query_item item
= {
1398 .query_id
= DRM_I915_QUERY_TOPOLOGY_INFO
,
1400 struct drm_i915_query query
= {
1402 .items_ptr
= (uintptr_t) &item
,
1405 if (gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &query
))
1408 if (item
.length
< 0)
1411 struct drm_i915_query_topology_info
*topo_info
=
1412 (struct drm_i915_query_topology_info
*) calloc(1, item
.length
);
1413 item
.data_ptr
= (uintptr_t) topo_info
;
1415 if (gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &query
) ||
1419 update_from_topology(devinfo
, topo_info
);
1428 gen_get_device_info_from_fd(int fd
, struct gen_device_info
*devinfo
)
1432 const char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
1433 if (devid_override
&& strlen(devid_override
) > 0) {
1434 if (geteuid() == getuid()) {
1435 devid
= gen_device_name_to_pci_device_id(devid_override
);
1436 /* Fallback to PCI ID. */
1438 devid
= strtol(devid_override
, NULL
, 0);
1440 fprintf(stderr
, "Invalid INTEL_DEVID_OVERRIDE=\"%s\". "
1441 "Use a valid numeric PCI ID or one of the supported "
1442 "platform names: %s", devid_override
, name_map
[0].name
);
1443 for (unsigned i
= 1; i
< ARRAY_SIZE(name_map
); i
++)
1444 fprintf(stderr
, ", %s", name_map
[i
].name
);
1445 fprintf(stderr
, "\n");
1449 fprintf(stderr
, "Ignoring INTEL_DEVID_OVERRIDE=\"%s\" because "
1450 "real and effective user ID don't match.\n", devid_override
);
1455 if (!gen_get_device_info_from_pci_id(devid
, devinfo
))
1457 devinfo
->no_hw
= true;
1459 /* query the device id */
1460 if (!getparam(fd
, I915_PARAM_CHIPSET_ID
, &devid
))
1462 if (!gen_get_device_info_from_pci_id(devid
, devinfo
))
1464 devinfo
->no_hw
= false;
1467 /* remaining initializion queries the kernel for device info */
1471 int timestamp_frequency
;
1472 if (getparam(fd
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1473 ×tamp_frequency
))
1474 devinfo
->timestamp_frequency
= timestamp_frequency
;
1475 else if (devinfo
->gen
>= 10)
1476 /* gen10 and later requires the timestamp_frequency to be updated */
1479 if (!getparam(fd
, I915_PARAM_REVISION
, &devinfo
->revision
))
1480 devinfo
->revision
= 0;
1482 if (!query_topology(devinfo
, fd
)) {
1483 if (devinfo
->gen
>= 10) {
1484 /* topology uAPI required for CNL+ (kernel 4.17+) */
1488 /* else use the kernel 4.13+ api for gen8+. For older kernels, topology
1489 * will be wrong, affecting GPU metrics. In this case, fail silently.
1491 getparam_topology(devinfo
, fd
);