2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "gen_device_info.h"
30 #include "compiler/shader_enums.h"
31 #include "util/bitscan.h"
32 #include "util/macros.h"
37 * Get the PCI ID for the device name.
39 * Returns -1 if the device is not known.
42 gen_device_name_to_pci_device_id(const char *name
)
67 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
68 if (!strcmp(name_map
[i
].name
, name
))
69 return name_map
[i
].pci_id
;
76 * Get the overridden PCI ID for the device. This is set with the
77 * INTEL_DEVID_OVERRIDE environment variable.
79 * Returns -1 if the override is not set.
82 gen_get_pci_device_id_override(void)
84 if (geteuid() == getuid()) {
85 const char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
87 const int id
= gen_device_name_to_pci_device_id(devid_override
);
88 return id
>= 0 ? id
: strtol(devid_override
, NULL
, 0);
95 static const struct gen_device_info gen_device_info_i965
= {
97 .has_negative_rhw_bug
= true,
99 .num_subslices
= { 1, },
100 .num_eu_per_subslice
= 8,
101 .num_thread_per_eu
= 4,
102 .max_vs_threads
= 16,
104 .max_wm_threads
= 8 * 4,
108 .timestamp_frequency
= 12500000,
112 static const struct gen_device_info gen_device_info_g4x
= {
116 .has_surface_tile_offset
= true,
119 .num_subslices
= { 1, },
120 .num_eu_per_subslice
= 10,
121 .num_thread_per_eu
= 5,
122 .max_vs_threads
= 32,
124 .max_wm_threads
= 10 * 5,
128 .timestamp_frequency
= 12500000,
132 static const struct gen_device_info gen_device_info_ilk
= {
136 .has_surface_tile_offset
= true,
138 .num_subslices
= { 1, },
139 .num_eu_per_subslice
= 12,
140 .num_thread_per_eu
= 6,
141 .max_vs_threads
= 72,
142 .max_gs_threads
= 32,
143 .max_wm_threads
= 12 * 6,
147 .timestamp_frequency
= 12500000,
151 static const struct gen_device_info gen_device_info_snb_gt1
= {
154 .has_hiz_and_separate_stencil
= true,
157 .has_surface_tile_offset
= true,
158 .needs_unlit_centroid_workaround
= true,
160 .num_subslices
= { 1, },
161 .num_eu_per_subslice
= 6,
162 .num_thread_per_eu
= 6, /* Not confirmed */
163 .max_vs_threads
= 24,
164 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
165 .max_wm_threads
= 40,
169 [MESA_SHADER_VERTEX
] = 24,
172 [MESA_SHADER_VERTEX
] = 256,
173 [MESA_SHADER_GEOMETRY
] = 256,
176 .timestamp_frequency
= 12500000,
180 static const struct gen_device_info gen_device_info_snb_gt2
= {
183 .has_hiz_and_separate_stencil
= true,
186 .has_surface_tile_offset
= true,
187 .needs_unlit_centroid_workaround
= true,
189 .num_subslices
= { 1, },
190 .num_eu_per_subslice
= 12,
191 .num_thread_per_eu
= 6, /* Not confirmed */
192 .max_vs_threads
= 60,
193 .max_gs_threads
= 60,
194 .max_wm_threads
= 80,
198 [MESA_SHADER_VERTEX
] = 24,
201 [MESA_SHADER_VERTEX
] = 256,
202 [MESA_SHADER_GEOMETRY
] = 256,
205 .timestamp_frequency
= 12500000,
209 #define GEN7_FEATURES \
211 .has_hiz_and_separate_stencil = true, \
212 .must_use_separate_stencil = true, \
215 .has_64bit_types = true, \
216 .has_surface_tile_offset = true, \
217 .timestamp_frequency = 12500000
219 static const struct gen_device_info gen_device_info_ivb_gt1
= {
220 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
222 .num_subslices
= { 1, },
223 .num_eu_per_subslice
= 6,
224 .num_thread_per_eu
= 6,
226 .max_vs_threads
= 36,
227 .max_tcs_threads
= 36,
228 .max_tes_threads
= 36,
229 .max_gs_threads
= 36,
230 .max_wm_threads
= 48,
231 .max_cs_threads
= 36,
235 [MESA_SHADER_VERTEX
] = 32,
236 [MESA_SHADER_TESS_EVAL
] = 10,
239 [MESA_SHADER_VERTEX
] = 512,
240 [MESA_SHADER_TESS_CTRL
] = 32,
241 [MESA_SHADER_TESS_EVAL
] = 288,
242 [MESA_SHADER_GEOMETRY
] = 192,
248 static const struct gen_device_info gen_device_info_ivb_gt2
= {
249 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
251 .num_subslices
= { 1, },
252 .num_eu_per_subslice
= 12,
253 .num_thread_per_eu
= 8, /* Not sure why this isn't a multiple of
254 * @max_wm_threads ... */
256 .max_vs_threads
= 128,
257 .max_tcs_threads
= 128,
258 .max_tes_threads
= 128,
259 .max_gs_threads
= 128,
260 .max_wm_threads
= 172,
261 .max_cs_threads
= 64,
265 [MESA_SHADER_VERTEX
] = 32,
266 [MESA_SHADER_TESS_EVAL
] = 10,
269 [MESA_SHADER_VERTEX
] = 704,
270 [MESA_SHADER_TESS_CTRL
] = 64,
271 [MESA_SHADER_TESS_EVAL
] = 448,
272 [MESA_SHADER_GEOMETRY
] = 320,
278 static const struct gen_device_info gen_device_info_byt
= {
279 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
281 .num_subslices
= { 1, },
282 .num_eu_per_subslice
= 4,
283 .num_thread_per_eu
= 8,
286 .max_vs_threads
= 36,
287 .max_tcs_threads
= 36,
288 .max_tes_threads
= 36,
289 .max_gs_threads
= 36,
290 .max_wm_threads
= 48,
291 .max_cs_threads
= 32,
295 [MESA_SHADER_VERTEX
] = 32,
296 [MESA_SHADER_TESS_EVAL
] = 10,
299 [MESA_SHADER_VERTEX
] = 512,
300 [MESA_SHADER_TESS_CTRL
] = 32,
301 [MESA_SHADER_TESS_EVAL
] = 288,
302 [MESA_SHADER_GEOMETRY
] = 192,
308 #define HSW_FEATURES \
310 .is_haswell = true, \
311 .supports_simd16_3src = true, \
312 .has_resource_streamer = true
314 static const struct gen_device_info gen_device_info_hsw_gt1
= {
315 HSW_FEATURES
, .gt
= 1,
317 .num_subslices
= { 1, },
318 .num_eu_per_subslice
= 10,
319 .num_thread_per_eu
= 7,
321 .max_vs_threads
= 70,
322 .max_tcs_threads
= 70,
323 .max_tes_threads
= 70,
324 .max_gs_threads
= 70,
325 .max_wm_threads
= 102,
326 .max_cs_threads
= 70,
330 [MESA_SHADER_VERTEX
] = 32,
331 [MESA_SHADER_TESS_EVAL
] = 10,
334 [MESA_SHADER_VERTEX
] = 640,
335 [MESA_SHADER_TESS_CTRL
] = 64,
336 [MESA_SHADER_TESS_EVAL
] = 384,
337 [MESA_SHADER_GEOMETRY
] = 256,
343 static const struct gen_device_info gen_device_info_hsw_gt2
= {
344 HSW_FEATURES
, .gt
= 2,
346 .num_subslices
= { 2, },
347 .num_eu_per_subslice
= 10,
348 .num_thread_per_eu
= 7,
350 .max_vs_threads
= 280,
351 .max_tcs_threads
= 256,
352 .max_tes_threads
= 280,
353 .max_gs_threads
= 256,
354 .max_wm_threads
= 204,
355 .max_cs_threads
= 70,
359 [MESA_SHADER_VERTEX
] = 64,
360 [MESA_SHADER_TESS_EVAL
] = 10,
363 [MESA_SHADER_VERTEX
] = 1664,
364 [MESA_SHADER_TESS_CTRL
] = 128,
365 [MESA_SHADER_TESS_EVAL
] = 960,
366 [MESA_SHADER_GEOMETRY
] = 640,
372 static const struct gen_device_info gen_device_info_hsw_gt3
= {
373 HSW_FEATURES
, .gt
= 3,
375 .num_subslices
= { 2, },
376 .num_eu_per_subslice
= 10,
377 .num_thread_per_eu
= 7,
379 .max_vs_threads
= 280,
380 .max_tcs_threads
= 256,
381 .max_tes_threads
= 280,
382 .max_gs_threads
= 256,
383 .max_wm_threads
= 408,
384 .max_cs_threads
= 70,
388 [MESA_SHADER_VERTEX
] = 64,
389 [MESA_SHADER_TESS_EVAL
] = 10,
392 [MESA_SHADER_VERTEX
] = 1664,
393 [MESA_SHADER_TESS_CTRL
] = 128,
394 [MESA_SHADER_TESS_EVAL
] = 960,
395 [MESA_SHADER_GEOMETRY
] = 640,
401 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
402 * so keep things conservative for now and set has_sample_with_hiz = false.
404 #define GEN8_FEATURES \
406 .has_hiz_and_separate_stencil = true, \
407 .has_resource_streamer = true, \
408 .must_use_separate_stencil = true, \
410 .has_sample_with_hiz = false, \
412 .has_integer_dword_mul = true, \
413 .has_64bit_types = true, \
414 .supports_simd16_3src = true, \
415 .has_surface_tile_offset = true, \
416 .max_vs_threads = 504, \
417 .max_tcs_threads = 504, \
418 .max_tes_threads = 504, \
419 .max_gs_threads = 504, \
420 .max_wm_threads = 384, \
421 .timestamp_frequency = 12500000
423 static const struct gen_device_info gen_device_info_bdw_gt1
= {
424 GEN8_FEATURES
, .gt
= 1,
425 .is_broadwell
= true,
427 .num_subslices
= { 2, },
428 .num_eu_per_subslice
= 8,
429 .num_thread_per_eu
= 7,
431 .max_cs_threads
= 42,
435 [MESA_SHADER_VERTEX
] = 64,
436 [MESA_SHADER_TESS_EVAL
] = 34,
439 [MESA_SHADER_VERTEX
] = 2560,
440 [MESA_SHADER_TESS_CTRL
] = 504,
441 [MESA_SHADER_TESS_EVAL
] = 1536,
442 [MESA_SHADER_GEOMETRY
] = 960,
448 static const struct gen_device_info gen_device_info_bdw_gt2
= {
449 GEN8_FEATURES
, .gt
= 2,
450 .is_broadwell
= true,
452 .num_subslices
= { 3, },
453 .num_eu_per_subslice
= 8,
454 .num_thread_per_eu
= 7,
456 .max_cs_threads
= 56,
460 [MESA_SHADER_VERTEX
] = 64,
461 [MESA_SHADER_TESS_EVAL
] = 34,
464 [MESA_SHADER_VERTEX
] = 2560,
465 [MESA_SHADER_TESS_CTRL
] = 504,
466 [MESA_SHADER_TESS_EVAL
] = 1536,
467 [MESA_SHADER_GEOMETRY
] = 960,
473 static const struct gen_device_info gen_device_info_bdw_gt3
= {
474 GEN8_FEATURES
, .gt
= 3,
475 .is_broadwell
= true,
477 .num_subslices
= { 3, 3, },
478 .num_eu_per_subslice
= 8,
479 .num_thread_per_eu
= 7,
481 .max_cs_threads
= 56,
485 [MESA_SHADER_VERTEX
] = 64,
486 [MESA_SHADER_TESS_EVAL
] = 34,
489 [MESA_SHADER_VERTEX
] = 2560,
490 [MESA_SHADER_TESS_CTRL
] = 504,
491 [MESA_SHADER_TESS_EVAL
] = 1536,
492 [MESA_SHADER_GEOMETRY
] = 960,
498 static const struct gen_device_info gen_device_info_chv
= {
499 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
501 .has_integer_dword_mul
= false,
503 .num_subslices
= { 2, },
504 .num_eu_per_subslice
= 8,
505 .num_thread_per_eu
= 7,
507 .max_vs_threads
= 80,
508 .max_tcs_threads
= 80,
509 .max_tes_threads
= 80,
510 .max_gs_threads
= 80,
511 .max_wm_threads
= 128,
512 .max_cs_threads
= 6 * 7,
516 [MESA_SHADER_VERTEX
] = 34,
517 [MESA_SHADER_TESS_EVAL
] = 34,
520 [MESA_SHADER_VERTEX
] = 640,
521 [MESA_SHADER_TESS_CTRL
] = 80,
522 [MESA_SHADER_TESS_EVAL
] = 384,
523 [MESA_SHADER_GEOMETRY
] = 256,
529 #define GEN9_HW_INFO \
531 .max_vs_threads = 336, \
532 .max_gs_threads = 336, \
533 .max_tcs_threads = 336, \
534 .max_tes_threads = 336, \
535 .max_cs_threads = 56, \
536 .timestamp_frequency = 12000000, \
540 [MESA_SHADER_VERTEX] = 64, \
541 [MESA_SHADER_TESS_EVAL] = 34, \
544 [MESA_SHADER_VERTEX] = 1856, \
545 [MESA_SHADER_TESS_CTRL] = 672, \
546 [MESA_SHADER_TESS_EVAL] = 1120, \
547 [MESA_SHADER_GEOMETRY] = 640, \
551 #define GEN9_LP_FEATURES \
554 .has_integer_dword_mul = false, \
557 .has_sample_with_hiz = true, \
559 .num_thread_per_eu = 6, \
560 .max_vs_threads = 112, \
561 .max_tcs_threads = 112, \
562 .max_tes_threads = 112, \
563 .max_gs_threads = 112, \
564 .max_cs_threads = 6 * 6, \
565 .timestamp_frequency = 19200000, \
569 [MESA_SHADER_VERTEX] = 34, \
570 [MESA_SHADER_TESS_EVAL] = 34, \
573 [MESA_SHADER_VERTEX] = 704, \
574 [MESA_SHADER_TESS_CTRL] = 256, \
575 [MESA_SHADER_TESS_EVAL] = 416, \
576 [MESA_SHADER_GEOMETRY] = 256, \
580 #define GEN9_LP_FEATURES_3X6 \
582 .num_subslices = { 3, }, \
583 .num_eu_per_subslice = 6
585 #define GEN9_LP_FEATURES_2X6 \
587 .num_subslices = { 2, }, \
588 .num_eu_per_subslice = 6, \
589 .max_vs_threads = 56, \
590 .max_tcs_threads = 56, \
591 .max_tes_threads = 56, \
592 .max_gs_threads = 56, \
593 .max_cs_threads = 6 * 6, \
597 [MESA_SHADER_VERTEX] = 34, \
598 [MESA_SHADER_TESS_EVAL] = 34, \
601 [MESA_SHADER_VERTEX] = 352, \
602 [MESA_SHADER_TESS_CTRL] = 128, \
603 [MESA_SHADER_TESS_EVAL] = 208, \
604 [MESA_SHADER_GEOMETRY] = 128, \
608 #define GEN9_FEATURES \
611 .has_sample_with_hiz = true, \
612 .num_thread_per_eu = 7
614 static const struct gen_device_info gen_device_info_skl_gt1
= {
615 GEN9_FEATURES
, .gt
= 1,
618 .num_subslices
= { 2, },
619 .num_eu_per_subslice
= 6,
625 static const struct gen_device_info gen_device_info_skl_gt2
= {
626 GEN9_FEATURES
, .gt
= 2,
629 .num_subslices
= { 3, },
630 .num_eu_per_subslice
= 8,
635 static const struct gen_device_info gen_device_info_skl_gt3
= {
636 GEN9_FEATURES
, .gt
= 3,
639 .num_subslices
= { 3, 3, },
640 .num_eu_per_subslice
= 8,
645 static const struct gen_device_info gen_device_info_skl_gt4
= {
646 GEN9_FEATURES
, .gt
= 4,
649 .num_subslices
= { 3, 3, 3, },
650 .num_eu_per_subslice
= 8,
652 /* From the "L3 Allocation and Programming" documentation:
654 * "URB is limited to 1008KB due to programming restrictions. This is not a
655 * restriction of the L3 implementation, but of the FF and other clients.
656 * Therefore, in a GT4 implementation it is possible for the programmed
657 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
658 * only 1008KB of this will be used."
660 .urb
.size
= 1008 / 3,
664 static const struct gen_device_info gen_device_info_bxt
= {
665 GEN9_LP_FEATURES_3X6
,
671 static const struct gen_device_info gen_device_info_bxt_2x6
= {
672 GEN9_LP_FEATURES_2X6
,
678 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
679 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
682 static const struct gen_device_info gen_device_info_kbl_gt1
= {
687 .max_cs_threads
= 7 * 6,
690 .num_subslices
= { 2, },
691 .num_eu_per_subslice
= 6,
696 static const struct gen_device_info gen_device_info_kbl_gt1_5
= {
701 .max_cs_threads
= 7 * 6,
703 .num_subslices
= { 3, },
704 .num_eu_per_subslice
= 6,
709 static const struct gen_device_info gen_device_info_kbl_gt2
= {
715 .num_subslices
= { 3, },
716 .num_eu_per_subslice
= 8,
721 static const struct gen_device_info gen_device_info_kbl_gt3
= {
727 .num_subslices
= { 3, 3, },
728 .num_eu_per_subslice
= 8,
733 static const struct gen_device_info gen_device_info_kbl_gt4
= {
739 * From the "L3 Allocation and Programming" documentation:
741 * "URB is limited to 1008KB due to programming restrictions. This
742 * is not a restriction of the L3 implementation, but of the FF and
743 * other clients. Therefore, in a GT4 implementation it is
744 * possible for the programmed allocation of the L3 data array to
745 * provide 3*384KB=1152KB for URB, but only 1008KB of this
748 .urb
.size
= 1008 / 3,
750 .num_subslices
= { 3, 3, 3, },
751 .num_eu_per_subslice
= 8,
756 static const struct gen_device_info gen_device_info_glk
= {
757 GEN9_LP_FEATURES_3X6
,
758 .is_geminilake
= true,
763 static const struct gen_device_info gen_device_info_glk_2x6
= {
764 GEN9_LP_FEATURES_2X6
,
765 .is_geminilake
= true,
770 static const struct gen_device_info gen_device_info_cfl_gt1
= {
772 .is_coffeelake
= true,
776 .num_subslices
= { 2, },
777 .num_eu_per_subslice
= 6,
781 static const struct gen_device_info gen_device_info_cfl_gt2
= {
783 .is_coffeelake
= true,
787 .num_subslices
= { 3, },
788 .num_eu_per_subslice
= 8,
793 static const struct gen_device_info gen_device_info_cfl_gt3
= {
795 .is_coffeelake
= true,
799 .num_subslices
= { 3, 3, },
800 .num_eu_per_subslice
= 8,
805 #define GEN10_HW_INFO \
807 .num_thread_per_eu = 7, \
808 .max_vs_threads = 728, \
809 .max_gs_threads = 432, \
810 .max_tcs_threads = 432, \
811 .max_tes_threads = 624, \
812 .max_cs_threads = 56, \
813 .timestamp_frequency = 19200000, \
817 [MESA_SHADER_VERTEX] = 64, \
818 [MESA_SHADER_TESS_EVAL] = 34, \
821 [MESA_SHADER_VERTEX] = 3936, \
822 [MESA_SHADER_TESS_CTRL] = 896, \
823 [MESA_SHADER_TESS_EVAL] = 2064, \
824 [MESA_SHADER_GEOMETRY] = 832, \
828 #define subslices(args...) { args, }
830 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
833 .has_sample_with_hiz = true, \
835 .num_slices = _slices, \
836 .num_subslices = _subslices, \
837 .num_eu_per_subslice = 8, \
840 static const struct gen_device_info gen_device_info_cnl_2x8
= {
842 GEN10_FEATURES(1, 1, subslices(2), 2),
843 .is_cannonlake
= true,
847 static const struct gen_device_info gen_device_info_cnl_3x8
= {
849 GEN10_FEATURES(1, 1, subslices(3), 3),
850 .is_cannonlake
= true,
854 static const struct gen_device_info gen_device_info_cnl_4x8
= {
856 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
857 .is_cannonlake
= true,
861 static const struct gen_device_info gen_device_info_cnl_5x8
= {
863 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
864 .is_cannonlake
= true,
868 #define GEN11_HW_INFO \
871 .max_vs_threads = 364, \
872 .max_gs_threads = 224, \
873 .max_tcs_threads = 224, \
874 .max_tes_threads = 364, \
877 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
880 .has_64bit_types = false, \
881 .has_integer_dword_mul = false, \
882 .has_sample_with_hiz = false, \
883 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
884 .num_subslices = _subslices, \
885 .num_eu_per_subslice = 8
887 #define GEN11_URB_MIN_MAX_ENTRIES \
889 [MESA_SHADER_VERTEX] = 64, \
890 [MESA_SHADER_TESS_EVAL] = 34, \
893 [MESA_SHADER_VERTEX] = 2384, \
894 [MESA_SHADER_TESS_CTRL] = 1032, \
895 [MESA_SHADER_TESS_EVAL] = 2384, \
896 [MESA_SHADER_GEOMETRY] = 1032, \
899 static const struct gen_device_info gen_device_info_icl_8x8
= {
900 GEN11_FEATURES(2, 1, subslices(8), 8),
903 GEN11_URB_MIN_MAX_ENTRIES
,
908 static const struct gen_device_info gen_device_info_icl_6x8
= {
909 GEN11_FEATURES(1, 1, subslices(6), 6),
912 GEN11_URB_MIN_MAX_ENTRIES
,
917 static const struct gen_device_info gen_device_info_icl_4x8
= {
918 GEN11_FEATURES(1, 1, subslices(4), 6),
921 GEN11_URB_MIN_MAX_ENTRIES
,
926 static const struct gen_device_info gen_device_info_icl_1x8
= {
927 GEN11_FEATURES(1, 1, subslices(1), 6),
930 GEN11_URB_MIN_MAX_ENTRIES
,
936 gen_device_info_set_eu_mask(struct gen_device_info
*devinfo
,
941 unsigned subslice_offset
= slice
* devinfo
->eu_slice_stride
+
942 subslice
* devinfo
->eu_subslice_stride
;
944 for (unsigned b_eu
= 0; b_eu
< devinfo
->eu_subslice_stride
; b_eu
++) {
945 devinfo
->eu_masks
[subslice_offset
+ b_eu
] =
946 (((1U << devinfo
->num_eu_per_subslice
) - 1) >> (b_eu
* 8)) & 0xff;
950 /* Generate slice/subslice/eu masks from number of
951 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
954 * These can be overridden with values reported by the kernel either from
955 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
956 * through the i915 query uapi.
959 fill_masks(struct gen_device_info
*devinfo
)
961 devinfo
->slice_masks
= (1U << devinfo
->num_slices
) - 1;
964 unsigned max_subslices
= 0;
965 for (int s
= 0; s
< devinfo
->num_slices
; s
++)
966 max_subslices
= MAX2(devinfo
->num_subslices
[s
], max_subslices
);
967 devinfo
->subslice_slice_stride
= DIV_ROUND_UP(max_subslices
, 8);
969 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
970 devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
] =
971 (1U << devinfo
->num_subslices
[s
]) - 1;
975 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(devinfo
->num_eu_per_subslice
, 8);
976 devinfo
->eu_slice_stride
= max_subslices
* devinfo
->eu_subslice_stride
;
978 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
979 for (int ss
= 0; ss
< devinfo
->num_subslices
[s
]; ss
++) {
980 gen_device_info_set_eu_mask(devinfo
, s
, ss
,
981 (1U << devinfo
->num_eu_per_subslice
) - 1);
987 gen_device_info_update_from_masks(struct gen_device_info
*devinfo
,
989 uint32_t subslice_mask
,
993 struct drm_i915_query_topology_info base
;
997 assert((slice_mask
& 0xff) == slice_mask
);
999 memset(&topology
, 0, sizeof(topology
));
1001 topology
.base
.max_slices
= util_last_bit(slice_mask
);
1002 topology
.base
.max_subslices
= util_last_bit(subslice_mask
);
1004 topology
.base
.subslice_offset
= DIV_ROUND_UP(topology
.base
.max_slices
, 8);
1005 topology
.base
.subslice_stride
= DIV_ROUND_UP(topology
.base
.max_subslices
, 8);
1007 uint32_t n_subslices
= __builtin_popcount(slice_mask
) *
1008 __builtin_popcount(subslice_mask
);
1009 uint32_t num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1010 uint32_t eu_mask
= (1U << num_eu_per_subslice
) - 1;
1012 topology
.base
.eu_offset
= topology
.base
.subslice_offset
+
1013 DIV_ROUND_UP(topology
.base
.max_subslices
, 8);
1014 topology
.base
.eu_stride
= DIV_ROUND_UP(num_eu_per_subslice
, 8);
1016 /* Set slice mask in topology */
1017 for (int b
= 0; b
< topology
.base
.subslice_offset
; b
++)
1018 topology
.base
.data
[b
] = (slice_mask
>> (b
* 8)) & 0xff;
1020 for (int s
= 0; s
< topology
.base
.max_slices
; s
++) {
1022 /* Set subslice mask in topology */
1023 for (int b
= 0; b
< topology
.base
.subslice_stride
; b
++) {
1024 int subslice_offset
= topology
.base
.subslice_offset
+
1025 s
* topology
.base
.subslice_stride
+ b
;
1027 topology
.base
.data
[subslice_offset
] = (subslice_mask
>> (b
* 8)) & 0xff;
1030 /* Set eu mask in topology */
1031 for (int ss
= 0; ss
< topology
.base
.max_subslices
; ss
++) {
1032 for (int b
= 0; b
< topology
.base
.eu_stride
; b
++) {
1033 int eu_offset
= topology
.base
.eu_offset
+
1034 (s
* topology
.base
.max_subslices
+ ss
) * topology
.base
.eu_stride
+ b
;
1036 topology
.base
.data
[eu_offset
] = (eu_mask
>> (b
* 8)) & 0xff;
1041 gen_device_info_update_from_topology(devinfo
, &topology
.base
);
1045 reset_masks(struct gen_device_info
*devinfo
)
1047 devinfo
->subslice_slice_stride
= 0;
1048 devinfo
->eu_subslice_stride
= 0;
1049 devinfo
->eu_slice_stride
= 0;
1051 devinfo
->num_slices
= 0;
1052 devinfo
->num_eu_per_subslice
= 0;
1053 memset(devinfo
->num_subslices
, 0, sizeof(devinfo
->num_subslices
));
1055 memset(&devinfo
->slice_masks
, 0, sizeof(devinfo
->slice_masks
));
1056 memset(devinfo
->subslice_masks
, 0, sizeof(devinfo
->subslice_masks
));
1057 memset(devinfo
->eu_masks
, 0, sizeof(devinfo
->eu_masks
));
1061 gen_device_info_update_from_topology(struct gen_device_info
*devinfo
,
1062 const struct drm_i915_query_topology_info
*topology
)
1064 reset_masks(devinfo
);
1066 devinfo
->subslice_slice_stride
= topology
->subslice_stride
;
1068 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(topology
->max_eus_per_subslice
, 8);
1069 devinfo
->eu_slice_stride
= topology
->max_subslices
* devinfo
->eu_subslice_stride
;
1071 assert(sizeof(devinfo
->slice_masks
) >= DIV_ROUND_UP(topology
->max_slices
, 8));
1072 memcpy(&devinfo
->slice_masks
, topology
->data
, DIV_ROUND_UP(topology
->max_slices
, 8));
1073 devinfo
->num_slices
= __builtin_popcount(devinfo
->slice_masks
);
1075 uint32_t subslice_mask_len
=
1076 topology
->max_slices
* topology
->subslice_stride
;
1077 assert(sizeof(devinfo
->subslice_masks
) >= subslice_mask_len
);
1078 memcpy(devinfo
->subslice_masks
, &topology
->data
[topology
->subslice_offset
],
1081 uint32_t n_subslices
= 0;
1082 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1083 if ((devinfo
->slice_masks
& (1UL << s
)) == 0)
1086 for (int b
= 0; b
< devinfo
->subslice_slice_stride
; b
++) {
1087 devinfo
->num_subslices
[s
] +=
1088 __builtin_popcount(devinfo
->subslice_masks
[b
]);
1090 n_subslices
+= devinfo
->num_subslices
[s
];
1092 assert(n_subslices
> 0);
1094 uint32_t eu_mask_len
=
1095 topology
->eu_stride
* topology
->max_subslices
* topology
->max_slices
;
1096 assert(sizeof(devinfo
->eu_masks
) >= eu_mask_len
);
1097 memcpy(devinfo
->eu_masks
, &topology
->data
[topology
->eu_offset
], eu_mask_len
);
1100 for (int b
= 0; b
< eu_mask_len
; b
++)
1101 n_eus
+= __builtin_popcount(devinfo
->eu_masks
[b
]);
1103 devinfo
->num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1107 gen_get_device_info(int devid
, struct gen_device_info
*devinfo
)
1111 #define CHIPSET(id, family, name) \
1112 case id: *devinfo = gen_device_info_##family; break;
1113 #include "pci_ids/i965_pci_ids.h"
1115 fprintf(stderr
, "i965_dri.so does not support the 0x%x PCI ID.\n", devid
);
1119 fill_masks(devinfo
);
1121 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1123 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1124 * allocate scratch space enough so that each slice has 4 slices allowed."
1126 * The equivalent internal documentation says that this programming note
1127 * applies to all Gen9+ platforms.
1129 * The hardware typically calculates the scratch space pointer by taking
1130 * the base address, and adding per-thread-scratch-space * thread ID.
1131 * Extra padding can be necessary depending how the thread IDs are
1132 * calculated for a particular shader stage.
1135 switch(devinfo
->gen
) {
1138 devinfo
->max_wm_threads
= 64 /* threads-per-PSD */
1139 * devinfo
->num_slices
1140 * 4; /* effective subslices per slice */
1143 devinfo
->max_wm_threads
= 128 /* threads-per-PSD */
1144 * devinfo
->num_slices
1145 * 8; /* subslices per slice */
1151 assert(devinfo
->num_slices
<= ARRAY_SIZE(devinfo
->num_subslices
));
1157 gen_get_device_name(int devid
)
1161 #define CHIPSET(id, family, name) case id: return name;
1162 #include "pci_ids/i965_pci_ids.h"