2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "gen_device_info.h"
30 #include "compiler/shader_enums.h"
31 #include "util/bitscan.h"
32 #include "util/macros.h"
34 #include "drm-uapi/i915_drm.h"
37 * Get the PCI ID for the device name.
39 * Returns -1 if the device is not known.
42 gen_device_name_to_pci_device_id(const char *name
)
68 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
69 if (!strcmp(name_map
[i
].name
, name
))
70 return name_map
[i
].pci_id
;
77 * Get the overridden PCI ID for the device. This is set with the
78 * INTEL_DEVID_OVERRIDE environment variable.
80 * Returns -1 if the override is not set.
83 gen_get_pci_device_id_override(void)
85 if (geteuid() == getuid()) {
86 const char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
88 const int id
= gen_device_name_to_pci_device_id(devid_override
);
89 return id
>= 0 ? id
: strtol(devid_override
, NULL
, 0);
96 static const struct gen_device_info gen_device_info_i965
= {
98 .has_negative_rhw_bug
= true,
100 .num_subslices
= { 1, },
101 .num_eu_per_subslice
= 8,
102 .num_thread_per_eu
= 4,
103 .max_vs_threads
= 16,
105 .max_wm_threads
= 8 * 4,
109 .timestamp_frequency
= 12500000,
113 static const struct gen_device_info gen_device_info_g4x
= {
117 .has_surface_tile_offset
= true,
120 .num_subslices
= { 1, },
121 .num_eu_per_subslice
= 10,
122 .num_thread_per_eu
= 5,
123 .max_vs_threads
= 32,
125 .max_wm_threads
= 10 * 5,
129 .timestamp_frequency
= 12500000,
133 static const struct gen_device_info gen_device_info_ilk
= {
137 .has_surface_tile_offset
= true,
139 .num_subslices
= { 1, },
140 .num_eu_per_subslice
= 12,
141 .num_thread_per_eu
= 6,
142 .max_vs_threads
= 72,
143 .max_gs_threads
= 32,
144 .max_wm_threads
= 12 * 6,
148 .timestamp_frequency
= 12500000,
152 static const struct gen_device_info gen_device_info_snb_gt1
= {
155 .has_hiz_and_separate_stencil
= true,
158 .has_surface_tile_offset
= true,
159 .needs_unlit_centroid_workaround
= true,
161 .num_subslices
= { 1, },
162 .num_eu_per_subslice
= 6,
163 .num_thread_per_eu
= 6, /* Not confirmed */
164 .max_vs_threads
= 24,
165 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
166 .max_wm_threads
= 40,
170 [MESA_SHADER_VERTEX
] = 24,
173 [MESA_SHADER_VERTEX
] = 256,
174 [MESA_SHADER_GEOMETRY
] = 256,
177 .timestamp_frequency
= 12500000,
181 static const struct gen_device_info gen_device_info_snb_gt2
= {
184 .has_hiz_and_separate_stencil
= true,
187 .has_surface_tile_offset
= true,
188 .needs_unlit_centroid_workaround
= true,
190 .num_subslices
= { 1, },
191 .num_eu_per_subslice
= 12,
192 .num_thread_per_eu
= 6, /* Not confirmed */
193 .max_vs_threads
= 60,
194 .max_gs_threads
= 60,
195 .max_wm_threads
= 80,
199 [MESA_SHADER_VERTEX
] = 24,
202 [MESA_SHADER_VERTEX
] = 256,
203 [MESA_SHADER_GEOMETRY
] = 256,
206 .timestamp_frequency
= 12500000,
210 #define GEN7_FEATURES \
212 .has_hiz_and_separate_stencil = true, \
213 .must_use_separate_stencil = true, \
216 .has_64bit_types = true, \
217 .has_surface_tile_offset = true, \
218 .timestamp_frequency = 12500000
220 static const struct gen_device_info gen_device_info_ivb_gt1
= {
221 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
223 .num_subslices
= { 1, },
224 .num_eu_per_subslice
= 6,
225 .num_thread_per_eu
= 6,
227 .max_vs_threads
= 36,
228 .max_tcs_threads
= 36,
229 .max_tes_threads
= 36,
230 .max_gs_threads
= 36,
231 .max_wm_threads
= 48,
232 .max_cs_threads
= 36,
236 [MESA_SHADER_VERTEX
] = 32,
237 [MESA_SHADER_TESS_EVAL
] = 10,
240 [MESA_SHADER_VERTEX
] = 512,
241 [MESA_SHADER_TESS_CTRL
] = 32,
242 [MESA_SHADER_TESS_EVAL
] = 288,
243 [MESA_SHADER_GEOMETRY
] = 192,
249 static const struct gen_device_info gen_device_info_ivb_gt2
= {
250 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
252 .num_subslices
= { 1, },
253 .num_eu_per_subslice
= 12,
254 .num_thread_per_eu
= 8, /* Not sure why this isn't a multiple of
255 * @max_wm_threads ... */
257 .max_vs_threads
= 128,
258 .max_tcs_threads
= 128,
259 .max_tes_threads
= 128,
260 .max_gs_threads
= 128,
261 .max_wm_threads
= 172,
262 .max_cs_threads
= 64,
266 [MESA_SHADER_VERTEX
] = 32,
267 [MESA_SHADER_TESS_EVAL
] = 10,
270 [MESA_SHADER_VERTEX
] = 704,
271 [MESA_SHADER_TESS_CTRL
] = 64,
272 [MESA_SHADER_TESS_EVAL
] = 448,
273 [MESA_SHADER_GEOMETRY
] = 320,
279 static const struct gen_device_info gen_device_info_byt
= {
280 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
282 .num_subslices
= { 1, },
283 .num_eu_per_subslice
= 4,
284 .num_thread_per_eu
= 8,
287 .max_vs_threads
= 36,
288 .max_tcs_threads
= 36,
289 .max_tes_threads
= 36,
290 .max_gs_threads
= 36,
291 .max_wm_threads
= 48,
292 .max_cs_threads
= 32,
296 [MESA_SHADER_VERTEX
] = 32,
297 [MESA_SHADER_TESS_EVAL
] = 10,
300 [MESA_SHADER_VERTEX
] = 512,
301 [MESA_SHADER_TESS_CTRL
] = 32,
302 [MESA_SHADER_TESS_EVAL
] = 288,
303 [MESA_SHADER_GEOMETRY
] = 192,
309 #define HSW_FEATURES \
311 .is_haswell = true, \
312 .supports_simd16_3src = true, \
313 .has_resource_streamer = true
315 static const struct gen_device_info gen_device_info_hsw_gt1
= {
316 HSW_FEATURES
, .gt
= 1,
318 .num_subslices
= { 1, },
319 .num_eu_per_subslice
= 10,
320 .num_thread_per_eu
= 7,
322 .max_vs_threads
= 70,
323 .max_tcs_threads
= 70,
324 .max_tes_threads
= 70,
325 .max_gs_threads
= 70,
326 .max_wm_threads
= 102,
327 .max_cs_threads
= 70,
331 [MESA_SHADER_VERTEX
] = 32,
332 [MESA_SHADER_TESS_EVAL
] = 10,
335 [MESA_SHADER_VERTEX
] = 640,
336 [MESA_SHADER_TESS_CTRL
] = 64,
337 [MESA_SHADER_TESS_EVAL
] = 384,
338 [MESA_SHADER_GEOMETRY
] = 256,
344 static const struct gen_device_info gen_device_info_hsw_gt2
= {
345 HSW_FEATURES
, .gt
= 2,
347 .num_subslices
= { 2, },
348 .num_eu_per_subslice
= 10,
349 .num_thread_per_eu
= 7,
351 .max_vs_threads
= 280,
352 .max_tcs_threads
= 256,
353 .max_tes_threads
= 280,
354 .max_gs_threads
= 256,
355 .max_wm_threads
= 204,
356 .max_cs_threads
= 70,
360 [MESA_SHADER_VERTEX
] = 64,
361 [MESA_SHADER_TESS_EVAL
] = 10,
364 [MESA_SHADER_VERTEX
] = 1664,
365 [MESA_SHADER_TESS_CTRL
] = 128,
366 [MESA_SHADER_TESS_EVAL
] = 960,
367 [MESA_SHADER_GEOMETRY
] = 640,
373 static const struct gen_device_info gen_device_info_hsw_gt3
= {
374 HSW_FEATURES
, .gt
= 3,
376 .num_subslices
= { 2, },
377 .num_eu_per_subslice
= 10,
378 .num_thread_per_eu
= 7,
380 .max_vs_threads
= 280,
381 .max_tcs_threads
= 256,
382 .max_tes_threads
= 280,
383 .max_gs_threads
= 256,
384 .max_wm_threads
= 408,
385 .max_cs_threads
= 70,
389 [MESA_SHADER_VERTEX
] = 64,
390 [MESA_SHADER_TESS_EVAL
] = 10,
393 [MESA_SHADER_VERTEX
] = 1664,
394 [MESA_SHADER_TESS_CTRL
] = 128,
395 [MESA_SHADER_TESS_EVAL
] = 960,
396 [MESA_SHADER_GEOMETRY
] = 640,
402 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
403 * so keep things conservative for now and set has_sample_with_hiz = false.
405 #define GEN8_FEATURES \
407 .has_hiz_and_separate_stencil = true, \
408 .has_resource_streamer = true, \
409 .must_use_separate_stencil = true, \
411 .has_sample_with_hiz = false, \
413 .has_integer_dword_mul = true, \
414 .has_64bit_types = true, \
415 .supports_simd16_3src = true, \
416 .has_surface_tile_offset = true, \
417 .max_vs_threads = 504, \
418 .max_tcs_threads = 504, \
419 .max_tes_threads = 504, \
420 .max_gs_threads = 504, \
421 .max_wm_threads = 384, \
422 .timestamp_frequency = 12500000
424 static const struct gen_device_info gen_device_info_bdw_gt1
= {
425 GEN8_FEATURES
, .gt
= 1,
426 .is_broadwell
= true,
428 .num_subslices
= { 2, },
429 .num_eu_per_subslice
= 8,
430 .num_thread_per_eu
= 7,
432 .max_cs_threads
= 42,
436 [MESA_SHADER_VERTEX
] = 64,
437 [MESA_SHADER_TESS_EVAL
] = 34,
440 [MESA_SHADER_VERTEX
] = 2560,
441 [MESA_SHADER_TESS_CTRL
] = 504,
442 [MESA_SHADER_TESS_EVAL
] = 1536,
443 [MESA_SHADER_GEOMETRY
] = 960,
449 static const struct gen_device_info gen_device_info_bdw_gt2
= {
450 GEN8_FEATURES
, .gt
= 2,
451 .is_broadwell
= true,
453 .num_subslices
= { 3, },
454 .num_eu_per_subslice
= 8,
455 .num_thread_per_eu
= 7,
457 .max_cs_threads
= 56,
461 [MESA_SHADER_VERTEX
] = 64,
462 [MESA_SHADER_TESS_EVAL
] = 34,
465 [MESA_SHADER_VERTEX
] = 2560,
466 [MESA_SHADER_TESS_CTRL
] = 504,
467 [MESA_SHADER_TESS_EVAL
] = 1536,
468 [MESA_SHADER_GEOMETRY
] = 960,
474 static const struct gen_device_info gen_device_info_bdw_gt3
= {
475 GEN8_FEATURES
, .gt
= 3,
476 .is_broadwell
= true,
478 .num_subslices
= { 3, 3, },
479 .num_eu_per_subslice
= 8,
480 .num_thread_per_eu
= 7,
482 .max_cs_threads
= 56,
486 [MESA_SHADER_VERTEX
] = 64,
487 [MESA_SHADER_TESS_EVAL
] = 34,
490 [MESA_SHADER_VERTEX
] = 2560,
491 [MESA_SHADER_TESS_CTRL
] = 504,
492 [MESA_SHADER_TESS_EVAL
] = 1536,
493 [MESA_SHADER_GEOMETRY
] = 960,
499 static const struct gen_device_info gen_device_info_chv
= {
500 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
502 .has_integer_dword_mul
= false,
504 .num_subslices
= { 2, },
505 .num_eu_per_subslice
= 8,
506 .num_thread_per_eu
= 7,
508 .max_vs_threads
= 80,
509 .max_tcs_threads
= 80,
510 .max_tes_threads
= 80,
511 .max_gs_threads
= 80,
512 .max_wm_threads
= 128,
513 .max_cs_threads
= 6 * 7,
517 [MESA_SHADER_VERTEX
] = 34,
518 [MESA_SHADER_TESS_EVAL
] = 34,
521 [MESA_SHADER_VERTEX
] = 640,
522 [MESA_SHADER_TESS_CTRL
] = 80,
523 [MESA_SHADER_TESS_EVAL
] = 384,
524 [MESA_SHADER_GEOMETRY
] = 256,
530 #define GEN9_HW_INFO \
532 .max_vs_threads = 336, \
533 .max_gs_threads = 336, \
534 .max_tcs_threads = 336, \
535 .max_tes_threads = 336, \
536 .max_cs_threads = 56, \
537 .timestamp_frequency = 12000000, \
541 [MESA_SHADER_VERTEX] = 64, \
542 [MESA_SHADER_TESS_EVAL] = 34, \
545 [MESA_SHADER_VERTEX] = 1856, \
546 [MESA_SHADER_TESS_CTRL] = 672, \
547 [MESA_SHADER_TESS_EVAL] = 1120, \
548 [MESA_SHADER_GEOMETRY] = 640, \
552 #define GEN9_LP_FEATURES \
555 .has_integer_dword_mul = false, \
558 .has_sample_with_hiz = true, \
560 .num_thread_per_eu = 6, \
561 .max_vs_threads = 112, \
562 .max_tcs_threads = 112, \
563 .max_tes_threads = 112, \
564 .max_gs_threads = 112, \
565 .max_cs_threads = 6 * 6, \
566 .timestamp_frequency = 19200000, \
570 [MESA_SHADER_VERTEX] = 34, \
571 [MESA_SHADER_TESS_EVAL] = 34, \
574 [MESA_SHADER_VERTEX] = 704, \
575 [MESA_SHADER_TESS_CTRL] = 256, \
576 [MESA_SHADER_TESS_EVAL] = 416, \
577 [MESA_SHADER_GEOMETRY] = 256, \
581 #define GEN9_LP_FEATURES_3X6 \
583 .num_subslices = { 3, }, \
584 .num_eu_per_subslice = 6
586 #define GEN9_LP_FEATURES_2X6 \
588 .num_subslices = { 2, }, \
589 .num_eu_per_subslice = 6, \
590 .max_vs_threads = 56, \
591 .max_tcs_threads = 56, \
592 .max_tes_threads = 56, \
593 .max_gs_threads = 56, \
594 .max_cs_threads = 6 * 6, \
598 [MESA_SHADER_VERTEX] = 34, \
599 [MESA_SHADER_TESS_EVAL] = 34, \
602 [MESA_SHADER_VERTEX] = 352, \
603 [MESA_SHADER_TESS_CTRL] = 128, \
604 [MESA_SHADER_TESS_EVAL] = 208, \
605 [MESA_SHADER_GEOMETRY] = 128, \
609 #define GEN9_FEATURES \
612 .has_sample_with_hiz = true, \
613 .num_thread_per_eu = 7
615 static const struct gen_device_info gen_device_info_skl_gt1
= {
616 GEN9_FEATURES
, .gt
= 1,
619 .num_subslices
= { 2, },
620 .num_eu_per_subslice
= 6,
626 static const struct gen_device_info gen_device_info_skl_gt2
= {
627 GEN9_FEATURES
, .gt
= 2,
630 .num_subslices
= { 3, },
631 .num_eu_per_subslice
= 8,
636 static const struct gen_device_info gen_device_info_skl_gt3
= {
637 GEN9_FEATURES
, .gt
= 3,
640 .num_subslices
= { 3, 3, },
641 .num_eu_per_subslice
= 8,
646 static const struct gen_device_info gen_device_info_skl_gt4
= {
647 GEN9_FEATURES
, .gt
= 4,
650 .num_subslices
= { 3, 3, 3, },
651 .num_eu_per_subslice
= 8,
653 /* From the "L3 Allocation and Programming" documentation:
655 * "URB is limited to 1008KB due to programming restrictions. This is not a
656 * restriction of the L3 implementation, but of the FF and other clients.
657 * Therefore, in a GT4 implementation it is possible for the programmed
658 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
659 * only 1008KB of this will be used."
661 .urb
.size
= 1008 / 3,
665 static const struct gen_device_info gen_device_info_bxt
= {
666 GEN9_LP_FEATURES_3X6
,
672 static const struct gen_device_info gen_device_info_bxt_2x6
= {
673 GEN9_LP_FEATURES_2X6
,
679 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
680 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
683 static const struct gen_device_info gen_device_info_kbl_gt1
= {
688 .max_cs_threads
= 7 * 6,
691 .num_subslices
= { 2, },
692 .num_eu_per_subslice
= 6,
697 static const struct gen_device_info gen_device_info_kbl_gt1_5
= {
702 .max_cs_threads
= 7 * 6,
704 .num_subslices
= { 3, },
705 .num_eu_per_subslice
= 6,
710 static const struct gen_device_info gen_device_info_kbl_gt2
= {
716 .num_subslices
= { 3, },
717 .num_eu_per_subslice
= 8,
722 static const struct gen_device_info gen_device_info_kbl_gt3
= {
728 .num_subslices
= { 3, 3, },
729 .num_eu_per_subslice
= 8,
734 static const struct gen_device_info gen_device_info_kbl_gt4
= {
740 * From the "L3 Allocation and Programming" documentation:
742 * "URB is limited to 1008KB due to programming restrictions. This
743 * is not a restriction of the L3 implementation, but of the FF and
744 * other clients. Therefore, in a GT4 implementation it is
745 * possible for the programmed allocation of the L3 data array to
746 * provide 3*384KB=1152KB for URB, but only 1008KB of this
749 .urb
.size
= 1008 / 3,
751 .num_subslices
= { 3, 3, 3, },
752 .num_eu_per_subslice
= 8,
757 static const struct gen_device_info gen_device_info_glk
= {
758 GEN9_LP_FEATURES_3X6
,
759 .is_geminilake
= true,
764 static const struct gen_device_info gen_device_info_glk_2x6
= {
765 GEN9_LP_FEATURES_2X6
,
766 .is_geminilake
= true,
771 static const struct gen_device_info gen_device_info_cfl_gt1
= {
773 .is_coffeelake
= true,
777 .num_subslices
= { 2, },
778 .num_eu_per_subslice
= 6,
783 static const struct gen_device_info gen_device_info_cfl_gt2
= {
785 .is_coffeelake
= true,
789 .num_subslices
= { 3, },
790 .num_eu_per_subslice
= 8,
795 static const struct gen_device_info gen_device_info_cfl_gt3
= {
797 .is_coffeelake
= true,
801 .num_subslices
= { 3, 3, },
802 .num_eu_per_subslice
= 8,
807 #define GEN10_HW_INFO \
809 .num_thread_per_eu = 7, \
810 .max_vs_threads = 728, \
811 .max_gs_threads = 432, \
812 .max_tcs_threads = 432, \
813 .max_tes_threads = 624, \
814 .max_cs_threads = 56, \
815 .timestamp_frequency = 19200000, \
819 [MESA_SHADER_VERTEX] = 64, \
820 [MESA_SHADER_TESS_EVAL] = 34, \
823 [MESA_SHADER_VERTEX] = 3936, \
824 [MESA_SHADER_TESS_CTRL] = 896, \
825 [MESA_SHADER_TESS_EVAL] = 2064, \
826 [MESA_SHADER_GEOMETRY] = 832, \
830 #define subslices(args...) { args, }
832 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
835 .has_sample_with_hiz = true, \
837 .num_slices = _slices, \
838 .num_subslices = _subslices, \
839 .num_eu_per_subslice = 8, \
842 static const struct gen_device_info gen_device_info_cnl_2x8
= {
844 GEN10_FEATURES(1, 1, subslices(2), 2),
845 .is_cannonlake
= true,
849 static const struct gen_device_info gen_device_info_cnl_3x8
= {
851 GEN10_FEATURES(1, 1, subslices(3), 3),
852 .is_cannonlake
= true,
856 static const struct gen_device_info gen_device_info_cnl_4x8
= {
858 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
859 .is_cannonlake
= true,
863 static const struct gen_device_info gen_device_info_cnl_5x8
= {
865 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
866 .is_cannonlake
= true,
870 #define GEN11_HW_INFO \
873 .max_vs_threads = 364, \
874 .max_gs_threads = 224, \
875 .max_tcs_threads = 224, \
876 .max_tes_threads = 364, \
879 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
882 .has_64bit_types = false, \
883 .has_integer_dword_mul = false, \
884 .has_sample_with_hiz = false, \
885 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
886 .num_subslices = _subslices, \
887 .num_eu_per_subslice = 8
889 #define GEN11_URB_MIN_MAX_ENTRIES \
891 [MESA_SHADER_VERTEX] = 64, \
892 [MESA_SHADER_TESS_EVAL] = 34, \
895 [MESA_SHADER_VERTEX] = 2384, \
896 [MESA_SHADER_TESS_CTRL] = 1032, \
897 [MESA_SHADER_TESS_EVAL] = 2384, \
898 [MESA_SHADER_GEOMETRY] = 1032, \
901 static const struct gen_device_info gen_device_info_icl_8x8
= {
902 GEN11_FEATURES(2, 1, subslices(8), 8),
905 GEN11_URB_MIN_MAX_ENTRIES
,
910 static const struct gen_device_info gen_device_info_icl_6x8
= {
911 GEN11_FEATURES(1, 1, subslices(6), 6),
914 GEN11_URB_MIN_MAX_ENTRIES
,
919 static const struct gen_device_info gen_device_info_icl_4x8
= {
920 GEN11_FEATURES(1, 1, subslices(4), 6),
923 GEN11_URB_MIN_MAX_ENTRIES
,
928 static const struct gen_device_info gen_device_info_icl_1x8
= {
929 GEN11_FEATURES(1, 1, subslices(1), 6),
932 GEN11_URB_MIN_MAX_ENTRIES
,
937 static const struct gen_device_info gen_device_info_ehl_4x8
= {
938 GEN11_FEATURES(1, 1, subslices(4), 4),
942 [MESA_SHADER_VERTEX
] = 64,
943 [MESA_SHADER_TESS_EVAL
] = 34,
946 [MESA_SHADER_VERTEX
] = 2384,
947 [MESA_SHADER_TESS_CTRL
] = 1032,
948 [MESA_SHADER_TESS_EVAL
] = 2384,
949 [MESA_SHADER_GEOMETRY
] = 1032,
955 /* FIXME: Verfiy below entries when more information is available for this SKU.
957 static const struct gen_device_info gen_device_info_ehl_4x4
= {
958 GEN11_FEATURES(1, 1, subslices(4), 4),
962 [MESA_SHADER_VERTEX
] = 64,
963 [MESA_SHADER_TESS_EVAL
] = 34,
966 [MESA_SHADER_VERTEX
] = 2384,
967 [MESA_SHADER_TESS_CTRL
] = 1032,
968 [MESA_SHADER_TESS_EVAL
] = 2384,
969 [MESA_SHADER_GEOMETRY
] = 1032,
972 .num_eu_per_subslice
= 4,
976 /* FIXME: Verfiy below entries when more information is available for this SKU.
978 static const struct gen_device_info gen_device_info_ehl_2x4
= {
979 GEN11_FEATURES(1, 1, subslices(2), 4),
983 [MESA_SHADER_VERTEX
] = 64,
984 [MESA_SHADER_TESS_EVAL
] = 34,
987 [MESA_SHADER_VERTEX
] = 2384,
988 [MESA_SHADER_TESS_CTRL
] = 1032,
989 [MESA_SHADER_TESS_EVAL
] = 2384,
990 [MESA_SHADER_GEOMETRY
] = 1032,
993 .num_eu_per_subslice
=4,
998 gen_device_info_set_eu_mask(struct gen_device_info
*devinfo
,
1003 unsigned subslice_offset
= slice
* devinfo
->eu_slice_stride
+
1004 subslice
* devinfo
->eu_subslice_stride
;
1006 for (unsigned b_eu
= 0; b_eu
< devinfo
->eu_subslice_stride
; b_eu
++) {
1007 devinfo
->eu_masks
[subslice_offset
+ b_eu
] =
1008 (((1U << devinfo
->num_eu_per_subslice
) - 1) >> (b_eu
* 8)) & 0xff;
1012 /* Generate slice/subslice/eu masks from number of
1013 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1016 * These can be overridden with values reported by the kernel either from
1017 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1018 * through the i915 query uapi.
1021 fill_masks(struct gen_device_info
*devinfo
)
1023 devinfo
->slice_masks
= (1U << devinfo
->num_slices
) - 1;
1025 /* Subslice masks */
1026 unsigned max_subslices
= 0;
1027 for (int s
= 0; s
< devinfo
->num_slices
; s
++)
1028 max_subslices
= MAX2(devinfo
->num_subslices
[s
], max_subslices
);
1029 devinfo
->subslice_slice_stride
= DIV_ROUND_UP(max_subslices
, 8);
1031 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1032 devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
] =
1033 (1U << devinfo
->num_subslices
[s
]) - 1;
1037 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(devinfo
->num_eu_per_subslice
, 8);
1038 devinfo
->eu_slice_stride
= max_subslices
* devinfo
->eu_subslice_stride
;
1040 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1041 for (int ss
= 0; ss
< devinfo
->num_subslices
[s
]; ss
++) {
1042 gen_device_info_set_eu_mask(devinfo
, s
, ss
,
1043 (1U << devinfo
->num_eu_per_subslice
) - 1);
1049 gen_device_info_update_from_masks(struct gen_device_info
*devinfo
,
1050 uint32_t slice_mask
,
1051 uint32_t subslice_mask
,
1055 struct drm_i915_query_topology_info base
;
1059 assert((slice_mask
& 0xff) == slice_mask
);
1061 memset(&topology
, 0, sizeof(topology
));
1063 topology
.base
.max_slices
= util_last_bit(slice_mask
);
1064 topology
.base
.max_subslices
= util_last_bit(subslice_mask
);
1066 topology
.base
.subslice_offset
= DIV_ROUND_UP(topology
.base
.max_slices
, 8);
1067 topology
.base
.subslice_stride
= DIV_ROUND_UP(topology
.base
.max_subslices
, 8);
1069 uint32_t n_subslices
= __builtin_popcount(slice_mask
) *
1070 __builtin_popcount(subslice_mask
);
1071 uint32_t num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1072 uint32_t eu_mask
= (1U << num_eu_per_subslice
) - 1;
1074 topology
.base
.eu_offset
= topology
.base
.subslice_offset
+
1075 DIV_ROUND_UP(topology
.base
.max_subslices
, 8);
1076 topology
.base
.eu_stride
= DIV_ROUND_UP(num_eu_per_subslice
, 8);
1078 /* Set slice mask in topology */
1079 for (int b
= 0; b
< topology
.base
.subslice_offset
; b
++)
1080 topology
.base
.data
[b
] = (slice_mask
>> (b
* 8)) & 0xff;
1082 for (int s
= 0; s
< topology
.base
.max_slices
; s
++) {
1084 /* Set subslice mask in topology */
1085 for (int b
= 0; b
< topology
.base
.subslice_stride
; b
++) {
1086 int subslice_offset
= topology
.base
.subslice_offset
+
1087 s
* topology
.base
.subslice_stride
+ b
;
1089 topology
.base
.data
[subslice_offset
] = (subslice_mask
>> (b
* 8)) & 0xff;
1092 /* Set eu mask in topology */
1093 for (int ss
= 0; ss
< topology
.base
.max_subslices
; ss
++) {
1094 for (int b
= 0; b
< topology
.base
.eu_stride
; b
++) {
1095 int eu_offset
= topology
.base
.eu_offset
+
1096 (s
* topology
.base
.max_subslices
+ ss
) * topology
.base
.eu_stride
+ b
;
1098 topology
.base
.data
[eu_offset
] = (eu_mask
>> (b
* 8)) & 0xff;
1103 gen_device_info_update_from_topology(devinfo
, &topology
.base
);
1107 reset_masks(struct gen_device_info
*devinfo
)
1109 devinfo
->subslice_slice_stride
= 0;
1110 devinfo
->eu_subslice_stride
= 0;
1111 devinfo
->eu_slice_stride
= 0;
1113 devinfo
->num_slices
= 0;
1114 devinfo
->num_eu_per_subslice
= 0;
1115 memset(devinfo
->num_subslices
, 0, sizeof(devinfo
->num_subslices
));
1117 memset(&devinfo
->slice_masks
, 0, sizeof(devinfo
->slice_masks
));
1118 memset(devinfo
->subslice_masks
, 0, sizeof(devinfo
->subslice_masks
));
1119 memset(devinfo
->eu_masks
, 0, sizeof(devinfo
->eu_masks
));
1123 gen_device_info_update_from_topology(struct gen_device_info
*devinfo
,
1124 const struct drm_i915_query_topology_info
*topology
)
1126 reset_masks(devinfo
);
1128 devinfo
->subslice_slice_stride
= topology
->subslice_stride
;
1130 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(topology
->max_eus_per_subslice
, 8);
1131 devinfo
->eu_slice_stride
= topology
->max_subslices
* devinfo
->eu_subslice_stride
;
1133 assert(sizeof(devinfo
->slice_masks
) >= DIV_ROUND_UP(topology
->max_slices
, 8));
1134 memcpy(&devinfo
->slice_masks
, topology
->data
, DIV_ROUND_UP(topology
->max_slices
, 8));
1135 devinfo
->num_slices
= __builtin_popcount(devinfo
->slice_masks
);
1137 uint32_t subslice_mask_len
=
1138 topology
->max_slices
* topology
->subslice_stride
;
1139 assert(sizeof(devinfo
->subslice_masks
) >= subslice_mask_len
);
1140 memcpy(devinfo
->subslice_masks
, &topology
->data
[topology
->subslice_offset
],
1143 uint32_t n_subslices
= 0;
1144 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1145 if ((devinfo
->slice_masks
& (1UL << s
)) == 0)
1148 for (int b
= 0; b
< devinfo
->subslice_slice_stride
; b
++) {
1149 devinfo
->num_subslices
[s
] +=
1150 __builtin_popcount(devinfo
->subslice_masks
[b
]);
1152 n_subslices
+= devinfo
->num_subslices
[s
];
1154 assert(n_subslices
> 0);
1156 uint32_t eu_mask_len
=
1157 topology
->eu_stride
* topology
->max_subslices
* topology
->max_slices
;
1158 assert(sizeof(devinfo
->eu_masks
) >= eu_mask_len
);
1159 memcpy(devinfo
->eu_masks
, &topology
->data
[topology
->eu_offset
], eu_mask_len
);
1162 for (int b
= 0; b
< eu_mask_len
; b
++)
1163 n_eus
+= __builtin_popcount(devinfo
->eu_masks
[b
]);
1165 devinfo
->num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1169 gen_get_device_info(int devid
, struct gen_device_info
*devinfo
)
1173 #define CHIPSET(id, family, name) \
1174 case id: *devinfo = gen_device_info_##family; break;
1175 #include "pci_ids/i965_pci_ids.h"
1177 fprintf(stderr
, "i965_dri.so does not support the 0x%x PCI ID.\n", devid
);
1181 fill_masks(devinfo
);
1183 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1185 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1186 * allocate scratch space enough so that each slice has 4 slices allowed."
1188 * The equivalent internal documentation says that this programming note
1189 * applies to all Gen9+ platforms.
1191 * The hardware typically calculates the scratch space pointer by taking
1192 * the base address, and adding per-thread-scratch-space * thread ID.
1193 * Extra padding can be necessary depending how the thread IDs are
1194 * calculated for a particular shader stage.
1197 switch(devinfo
->gen
) {
1200 devinfo
->max_wm_threads
= 64 /* threads-per-PSD */
1201 * devinfo
->num_slices
1202 * 4; /* effective subslices per slice */
1205 devinfo
->max_wm_threads
= 128 /* threads-per-PSD */
1206 * devinfo
->num_slices
1207 * 8; /* subslices per slice */
1213 assert(devinfo
->num_slices
<= ARRAY_SIZE(devinfo
->num_subslices
));
1219 gen_get_device_name(int devid
)
1223 #define CHIPSET(id, family, name) case id: return name;
1224 #include "pci_ids/i965_pci_ids.h"