2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "gen_device_info.h"
31 #include "compiler/shader_enums.h"
32 #include "intel/common/gen_gem.h"
33 #include "util/bitscan.h"
34 #include "util/macros.h"
36 #include "drm-uapi/i915_drm.h"
68 * Get the PCI ID for the device name.
70 * Returns -1 if the device is not known.
73 gen_device_name_to_pci_device_id(const char *name
)
75 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
76 if (!strcmp(name_map
[i
].name
, name
))
77 return name_map
[i
].pci_id
;
83 static const struct gen_device_info gen_device_info_i965
= {
85 .has_negative_rhw_bug
= true,
87 .num_subslices
= { 1, },
88 .num_eu_per_subslice
= 8,
89 .num_thread_per_eu
= 4,
92 .max_wm_threads
= 8 * 4,
96 .timestamp_frequency
= 12500000,
100 static const struct gen_device_info gen_device_info_g4x
= {
104 .has_surface_tile_offset
= true,
107 .num_subslices
= { 1, },
108 .num_eu_per_subslice
= 10,
109 .num_thread_per_eu
= 5,
110 .max_vs_threads
= 32,
112 .max_wm_threads
= 10 * 5,
116 .timestamp_frequency
= 12500000,
120 static const struct gen_device_info gen_device_info_ilk
= {
124 .has_surface_tile_offset
= true,
126 .num_subslices
= { 1, },
127 .num_eu_per_subslice
= 12,
128 .num_thread_per_eu
= 6,
129 .max_vs_threads
= 72,
130 .max_gs_threads
= 32,
131 .max_wm_threads
= 12 * 6,
135 .timestamp_frequency
= 12500000,
139 static const struct gen_device_info gen_device_info_snb_gt1
= {
142 .has_hiz_and_separate_stencil
= true,
145 .has_surface_tile_offset
= true,
146 .needs_unlit_centroid_workaround
= true,
148 .num_subslices
= { 1, },
149 .num_eu_per_subslice
= 6,
150 .num_thread_per_eu
= 6, /* Not confirmed */
151 .max_vs_threads
= 24,
152 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
153 .max_wm_threads
= 40,
157 [MESA_SHADER_VERTEX
] = 24,
160 [MESA_SHADER_VERTEX
] = 256,
161 [MESA_SHADER_GEOMETRY
] = 256,
164 .timestamp_frequency
= 12500000,
168 static const struct gen_device_info gen_device_info_snb_gt2
= {
171 .has_hiz_and_separate_stencil
= true,
174 .has_surface_tile_offset
= true,
175 .needs_unlit_centroid_workaround
= true,
177 .num_subslices
= { 1, },
178 .num_eu_per_subslice
= 12,
179 .num_thread_per_eu
= 6, /* Not confirmed */
180 .max_vs_threads
= 60,
181 .max_gs_threads
= 60,
182 .max_wm_threads
= 80,
186 [MESA_SHADER_VERTEX
] = 24,
189 [MESA_SHADER_VERTEX
] = 256,
190 [MESA_SHADER_GEOMETRY
] = 256,
193 .timestamp_frequency
= 12500000,
197 #define GEN7_FEATURES \
199 .has_hiz_and_separate_stencil = true, \
200 .must_use_separate_stencil = true, \
203 .has_64bit_float = true, \
204 .has_surface_tile_offset = true, \
205 .timestamp_frequency = 12500000
207 static const struct gen_device_info gen_device_info_ivb_gt1
= {
208 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
210 .num_subslices
= { 1, },
211 .num_eu_per_subslice
= 6,
212 .num_thread_per_eu
= 6,
214 .max_vs_threads
= 36,
215 .max_tcs_threads
= 36,
216 .max_tes_threads
= 36,
217 .max_gs_threads
= 36,
218 .max_wm_threads
= 48,
219 .max_cs_threads
= 36,
222 [MESA_SHADER_VERTEX
] = 32,
223 [MESA_SHADER_TESS_EVAL
] = 10,
226 [MESA_SHADER_VERTEX
] = 512,
227 [MESA_SHADER_TESS_CTRL
] = 32,
228 [MESA_SHADER_TESS_EVAL
] = 288,
229 [MESA_SHADER_GEOMETRY
] = 192,
235 static const struct gen_device_info gen_device_info_ivb_gt2
= {
236 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
238 .num_subslices
= { 1, },
239 .num_eu_per_subslice
= 12,
240 .num_thread_per_eu
= 8, /* Not sure why this isn't a multiple of
241 * @max_wm_threads ... */
243 .max_vs_threads
= 128,
244 .max_tcs_threads
= 128,
245 .max_tes_threads
= 128,
246 .max_gs_threads
= 128,
247 .max_wm_threads
= 172,
248 .max_cs_threads
= 64,
251 [MESA_SHADER_VERTEX
] = 32,
252 [MESA_SHADER_TESS_EVAL
] = 10,
255 [MESA_SHADER_VERTEX
] = 704,
256 [MESA_SHADER_TESS_CTRL
] = 64,
257 [MESA_SHADER_TESS_EVAL
] = 448,
258 [MESA_SHADER_GEOMETRY
] = 320,
264 static const struct gen_device_info gen_device_info_byt
= {
265 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
267 .num_subslices
= { 1, },
268 .num_eu_per_subslice
= 4,
269 .num_thread_per_eu
= 8,
272 .max_vs_threads
= 36,
273 .max_tcs_threads
= 36,
274 .max_tes_threads
= 36,
275 .max_gs_threads
= 36,
276 .max_wm_threads
= 48,
277 .max_cs_threads
= 32,
280 [MESA_SHADER_VERTEX
] = 32,
281 [MESA_SHADER_TESS_EVAL
] = 10,
284 [MESA_SHADER_VERTEX
] = 512,
285 [MESA_SHADER_TESS_CTRL
] = 32,
286 [MESA_SHADER_TESS_EVAL
] = 288,
287 [MESA_SHADER_GEOMETRY
] = 192,
293 #define HSW_FEATURES \
295 .is_haswell = true, \
296 .supports_simd16_3src = true, \
297 .has_resource_streamer = true
299 static const struct gen_device_info gen_device_info_hsw_gt1
= {
300 HSW_FEATURES
, .gt
= 1,
302 .num_subslices
= { 1, },
303 .num_eu_per_subslice
= 10,
304 .num_thread_per_eu
= 7,
306 .max_vs_threads
= 70,
307 .max_tcs_threads
= 70,
308 .max_tes_threads
= 70,
309 .max_gs_threads
= 70,
310 .max_wm_threads
= 102,
311 .max_cs_threads
= 70,
314 [MESA_SHADER_VERTEX
] = 32,
315 [MESA_SHADER_TESS_EVAL
] = 10,
318 [MESA_SHADER_VERTEX
] = 640,
319 [MESA_SHADER_TESS_CTRL
] = 64,
320 [MESA_SHADER_TESS_EVAL
] = 384,
321 [MESA_SHADER_GEOMETRY
] = 256,
327 static const struct gen_device_info gen_device_info_hsw_gt2
= {
328 HSW_FEATURES
, .gt
= 2,
330 .num_subslices
= { 2, },
331 .num_eu_per_subslice
= 10,
332 .num_thread_per_eu
= 7,
334 .max_vs_threads
= 280,
335 .max_tcs_threads
= 256,
336 .max_tes_threads
= 280,
337 .max_gs_threads
= 256,
338 .max_wm_threads
= 204,
339 .max_cs_threads
= 70,
342 [MESA_SHADER_VERTEX
] = 64,
343 [MESA_SHADER_TESS_EVAL
] = 10,
346 [MESA_SHADER_VERTEX
] = 1664,
347 [MESA_SHADER_TESS_CTRL
] = 128,
348 [MESA_SHADER_TESS_EVAL
] = 960,
349 [MESA_SHADER_GEOMETRY
] = 640,
355 static const struct gen_device_info gen_device_info_hsw_gt3
= {
356 HSW_FEATURES
, .gt
= 3,
358 .num_subslices
= { 2, },
359 .num_eu_per_subslice
= 10,
360 .num_thread_per_eu
= 7,
362 .max_vs_threads
= 280,
363 .max_tcs_threads
= 256,
364 .max_tes_threads
= 280,
365 .max_gs_threads
= 256,
366 .max_wm_threads
= 408,
367 .max_cs_threads
= 70,
370 [MESA_SHADER_VERTEX
] = 64,
371 [MESA_SHADER_TESS_EVAL
] = 10,
374 [MESA_SHADER_VERTEX
] = 1664,
375 [MESA_SHADER_TESS_CTRL
] = 128,
376 [MESA_SHADER_TESS_EVAL
] = 960,
377 [MESA_SHADER_GEOMETRY
] = 640,
383 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
384 * so keep things conservative for now and set has_sample_with_hiz = false.
386 #define GEN8_FEATURES \
388 .has_hiz_and_separate_stencil = true, \
389 .has_resource_streamer = true, \
390 .must_use_separate_stencil = true, \
392 .has_sample_with_hiz = false, \
394 .has_integer_dword_mul = true, \
395 .has_64bit_float = true, \
396 .has_64bit_int = true, \
397 .supports_simd16_3src = true, \
398 .has_surface_tile_offset = true, \
399 .num_thread_per_eu = 7, \
400 .max_vs_threads = 504, \
401 .max_tcs_threads = 504, \
402 .max_tes_threads = 504, \
403 .max_gs_threads = 504, \
404 .max_wm_threads = 384, \
405 .timestamp_frequency = 12500000
407 static const struct gen_device_info gen_device_info_bdw_gt1
= {
408 GEN8_FEATURES
, .gt
= 1,
409 .is_broadwell
= true,
411 .num_subslices
= { 2, },
412 .num_eu_per_subslice
= 6,
414 .max_cs_threads
= 42,
417 [MESA_SHADER_VERTEX
] = 64,
418 [MESA_SHADER_TESS_EVAL
] = 34,
421 [MESA_SHADER_VERTEX
] = 2560,
422 [MESA_SHADER_TESS_CTRL
] = 504,
423 [MESA_SHADER_TESS_EVAL
] = 1536,
424 /* Reduced from 960, seems to be similar to the bug on Gen9 GT1. */
425 [MESA_SHADER_GEOMETRY
] = 690,
431 static const struct gen_device_info gen_device_info_bdw_gt2
= {
432 GEN8_FEATURES
, .gt
= 2,
433 .is_broadwell
= true,
435 .num_subslices
= { 3, },
436 .num_eu_per_subslice
= 8,
438 .max_cs_threads
= 56,
441 [MESA_SHADER_VERTEX
] = 64,
442 [MESA_SHADER_TESS_EVAL
] = 34,
445 [MESA_SHADER_VERTEX
] = 2560,
446 [MESA_SHADER_TESS_CTRL
] = 504,
447 [MESA_SHADER_TESS_EVAL
] = 1536,
448 [MESA_SHADER_GEOMETRY
] = 960,
454 static const struct gen_device_info gen_device_info_bdw_gt3
= {
455 GEN8_FEATURES
, .gt
= 3,
456 .is_broadwell
= true,
458 .num_subslices
= { 3, 3, },
459 .num_eu_per_subslice
= 8,
461 .max_cs_threads
= 56,
464 [MESA_SHADER_VERTEX
] = 64,
465 [MESA_SHADER_TESS_EVAL
] = 34,
468 [MESA_SHADER_VERTEX
] = 2560,
469 [MESA_SHADER_TESS_CTRL
] = 504,
470 [MESA_SHADER_TESS_EVAL
] = 1536,
471 [MESA_SHADER_GEOMETRY
] = 960,
477 static const struct gen_device_info gen_device_info_chv
= {
478 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
480 .has_integer_dword_mul
= false,
482 .num_subslices
= { 2, },
483 .num_eu_per_subslice
= 8,
485 .max_vs_threads
= 80,
486 .max_tcs_threads
= 80,
487 .max_tes_threads
= 80,
488 .max_gs_threads
= 80,
489 .max_wm_threads
= 128,
490 .max_cs_threads
= 6 * 7,
493 [MESA_SHADER_VERTEX
] = 34,
494 [MESA_SHADER_TESS_EVAL
] = 34,
497 [MESA_SHADER_VERTEX
] = 640,
498 [MESA_SHADER_TESS_CTRL
] = 80,
499 [MESA_SHADER_TESS_EVAL
] = 384,
500 [MESA_SHADER_GEOMETRY
] = 256,
506 #define GEN9_HW_INFO \
508 .max_vs_threads = 336, \
509 .max_gs_threads = 336, \
510 .max_tcs_threads = 336, \
511 .max_tes_threads = 336, \
512 .max_cs_threads = 56, \
513 .timestamp_frequency = 12000000, \
516 [MESA_SHADER_VERTEX] = 64, \
517 [MESA_SHADER_TESS_EVAL] = 34, \
520 [MESA_SHADER_VERTEX] = 1856, \
521 [MESA_SHADER_TESS_CTRL] = 672, \
522 [MESA_SHADER_TESS_EVAL] = 1120, \
523 [MESA_SHADER_GEOMETRY] = 640, \
527 #define GEN9_LP_FEATURES \
530 .has_integer_dword_mul = false, \
533 .has_sample_with_hiz = true, \
535 .num_thread_per_eu = 6, \
536 .max_vs_threads = 112, \
537 .max_tcs_threads = 112, \
538 .max_tes_threads = 112, \
539 .max_gs_threads = 112, \
540 .max_cs_threads = 6 * 6, \
541 .timestamp_frequency = 19200000, \
544 [MESA_SHADER_VERTEX] = 34, \
545 [MESA_SHADER_TESS_EVAL] = 34, \
548 [MESA_SHADER_VERTEX] = 704, \
549 [MESA_SHADER_TESS_CTRL] = 256, \
550 [MESA_SHADER_TESS_EVAL] = 416, \
551 [MESA_SHADER_GEOMETRY] = 256, \
555 #define GEN9_LP_FEATURES_3X6 \
557 .num_subslices = { 3, }, \
558 .num_eu_per_subslice = 6
560 #define GEN9_LP_FEATURES_2X6 \
562 .num_subslices = { 2, }, \
563 .num_eu_per_subslice = 6, \
564 .max_vs_threads = 56, \
565 .max_tcs_threads = 56, \
566 .max_tes_threads = 56, \
567 .max_gs_threads = 56, \
568 .max_cs_threads = 6 * 6, \
571 [MESA_SHADER_VERTEX] = 34, \
572 [MESA_SHADER_TESS_EVAL] = 34, \
575 [MESA_SHADER_VERTEX] = 352, \
576 [MESA_SHADER_TESS_CTRL] = 128, \
577 [MESA_SHADER_TESS_EVAL] = 208, \
578 [MESA_SHADER_GEOMETRY] = 128, \
582 #define GEN9_FEATURES \
585 .has_sample_with_hiz = true
587 static const struct gen_device_info gen_device_info_skl_gt1
= {
588 GEN9_FEATURES
, .gt
= 1,
591 .num_subslices
= { 2, },
592 .num_eu_per_subslice
= 6,
594 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
595 * leading to some vertices to go missing if we use too much URB.
597 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
601 static const struct gen_device_info gen_device_info_skl_gt2
= {
602 GEN9_FEATURES
, .gt
= 2,
605 .num_subslices
= { 3, },
606 .num_eu_per_subslice
= 8,
611 static const struct gen_device_info gen_device_info_skl_gt3
= {
612 GEN9_FEATURES
, .gt
= 3,
615 .num_subslices
= { 3, 3, },
616 .num_eu_per_subslice
= 8,
621 static const struct gen_device_info gen_device_info_skl_gt4
= {
622 GEN9_FEATURES
, .gt
= 4,
625 .num_subslices
= { 3, 3, 3, },
626 .num_eu_per_subslice
= 8,
628 /* From the "L3 Allocation and Programming" documentation:
630 * "URB is limited to 1008KB due to programming restrictions. This is not a
631 * restriction of the L3 implementation, but of the FF and other clients.
632 * Therefore, in a GT4 implementation it is possible for the programmed
633 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
634 * only 1008KB of this will be used."
639 static const struct gen_device_info gen_device_info_bxt
= {
640 GEN9_LP_FEATURES_3X6
,
646 static const struct gen_device_info gen_device_info_bxt_2x6
= {
647 GEN9_LP_FEATURES_2X6
,
653 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
654 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
657 static const struct gen_device_info gen_device_info_kbl_gt1
= {
662 .max_cs_threads
= 7 * 6,
664 .num_subslices
= { 2, },
665 .num_eu_per_subslice
= 6,
667 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
668 * leading to some vertices to go missing if we use too much URB.
670 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
674 static const struct gen_device_info gen_device_info_kbl_gt1_5
= {
679 .max_cs_threads
= 7 * 6,
681 .num_subslices
= { 3, },
682 .num_eu_per_subslice
= 6,
687 static const struct gen_device_info gen_device_info_kbl_gt2
= {
693 .num_subslices
= { 3, },
694 .num_eu_per_subslice
= 8,
699 static const struct gen_device_info gen_device_info_kbl_gt3
= {
705 .num_subslices
= { 3, 3, },
706 .num_eu_per_subslice
= 8,
711 static const struct gen_device_info gen_device_info_kbl_gt4
= {
717 * From the "L3 Allocation and Programming" documentation:
719 * "URB is limited to 1008KB due to programming restrictions. This
720 * is not a restriction of the L3 implementation, but of the FF and
721 * other clients. Therefore, in a GT4 implementation it is
722 * possible for the programmed allocation of the L3 data array to
723 * provide 3*384KB=1152KB for URB, but only 1008KB of this
727 .num_subslices
= { 3, 3, 3, },
728 .num_eu_per_subslice
= 8,
733 static const struct gen_device_info gen_device_info_glk
= {
734 GEN9_LP_FEATURES_3X6
,
735 .is_geminilake
= true,
740 static const struct gen_device_info gen_device_info_glk_2x6
= {
741 GEN9_LP_FEATURES_2X6
,
742 .is_geminilake
= true,
747 static const struct gen_device_info gen_device_info_cfl_gt1
= {
749 .is_coffeelake
= true,
753 .num_subslices
= { 2, },
754 .num_eu_per_subslice
= 6,
756 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
757 * leading to some vertices to go missing if we use too much URB.
759 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
762 static const struct gen_device_info gen_device_info_cfl_gt2
= {
764 .is_coffeelake
= true,
768 .num_subslices
= { 3, },
769 .num_eu_per_subslice
= 8,
774 static const struct gen_device_info gen_device_info_cfl_gt3
= {
776 .is_coffeelake
= true,
780 .num_subslices
= { 3, 3, },
781 .num_eu_per_subslice
= 8,
786 #define GEN10_HW_INFO \
788 .num_thread_per_eu = 7, \
789 .max_vs_threads = 728, \
790 .max_gs_threads = 432, \
791 .max_tcs_threads = 432, \
792 .max_tes_threads = 624, \
793 .max_cs_threads = 56, \
794 .timestamp_frequency = 19200000, \
797 [MESA_SHADER_VERTEX] = 64, \
798 [MESA_SHADER_TESS_EVAL] = 34, \
801 [MESA_SHADER_VERTEX] = 3936, \
802 [MESA_SHADER_TESS_CTRL] = 896, \
803 [MESA_SHADER_TESS_EVAL] = 2064, \
804 [MESA_SHADER_GEOMETRY] = 832, \
808 #define subslices(args...) { args, }
810 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
813 .has_sample_with_hiz = true, \
815 .num_slices = _slices, \
816 .num_subslices = _subslices, \
817 .num_eu_per_subslice = 8, \
820 static const struct gen_device_info gen_device_info_cnl_gt0_5
= {
822 GEN10_FEATURES(1, 1, subslices(2), 2),
823 .is_cannonlake
= true,
827 static const struct gen_device_info gen_device_info_cnl_gt1
= {
829 GEN10_FEATURES(1, 1, subslices(3), 3),
830 .is_cannonlake
= true,
834 static const struct gen_device_info gen_device_info_cnl_gt1_5
= {
836 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
837 .is_cannonlake
= true,
841 static const struct gen_device_info gen_device_info_cnl_gt2
= {
843 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
844 .is_cannonlake
= true,
848 #define GEN11_HW_INFO \
851 .max_vs_threads = 364, \
852 .max_gs_threads = 224, \
853 .max_tcs_threads = 224, \
854 .max_tes_threads = 364, \
857 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
860 .has_64bit_float = false, \
861 .has_64bit_int = false, \
862 .has_integer_dword_mul = false, \
863 .has_sample_with_hiz = false, \
864 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
865 .num_subslices = _subslices, \
866 .num_eu_per_subslice = 8
868 #define GEN11_URB_MIN_MAX_ENTRIES \
870 [MESA_SHADER_VERTEX] = 64, \
871 [MESA_SHADER_TESS_EVAL] = 34, \
874 [MESA_SHADER_VERTEX] = 2384, \
875 [MESA_SHADER_TESS_CTRL] = 1032, \
876 [MESA_SHADER_TESS_EVAL] = 2384, \
877 [MESA_SHADER_GEOMETRY] = 1032, \
880 static const struct gen_device_info gen_device_info_icl_gt2
= {
881 GEN11_FEATURES(2, 1, subslices(8), 8),
883 GEN11_URB_MIN_MAX_ENTRIES
,
888 static const struct gen_device_info gen_device_info_icl_gt1_5
= {
889 GEN11_FEATURES(1, 1, subslices(6), 6),
891 GEN11_URB_MIN_MAX_ENTRIES
,
896 static const struct gen_device_info gen_device_info_icl_gt1
= {
897 GEN11_FEATURES(1, 1, subslices(4), 6),
899 GEN11_URB_MIN_MAX_ENTRIES
,
904 static const struct gen_device_info gen_device_info_icl_gt0_5
= {
905 GEN11_FEATURES(1, 1, subslices(1), 6),
907 GEN11_URB_MIN_MAX_ENTRIES
,
912 static const struct gen_device_info gen_device_info_ehl_7
= {
913 GEN11_FEATURES(1, 1, subslices(4), 4),
914 .is_elkhartlake
= true,
917 [MESA_SHADER_VERTEX
] = 64,
918 [MESA_SHADER_TESS_EVAL
] = 34,
921 [MESA_SHADER_VERTEX
] = 2384,
922 [MESA_SHADER_TESS_CTRL
] = 1032,
923 [MESA_SHADER_TESS_EVAL
] = 2384,
924 [MESA_SHADER_GEOMETRY
] = 1032,
927 .disable_ccs_repack
= true,
931 static const struct gen_device_info gen_device_info_ehl_6
= {
932 GEN11_FEATURES(1, 1, subslices(4), 4),
933 .is_elkhartlake
= true,
936 [MESA_SHADER_VERTEX
] = 64,
937 [MESA_SHADER_TESS_EVAL
] = 34,
940 [MESA_SHADER_VERTEX
] = 2384,
941 [MESA_SHADER_TESS_CTRL
] = 1032,
942 [MESA_SHADER_TESS_EVAL
] = 2384,
943 [MESA_SHADER_GEOMETRY
] = 1032,
946 .disable_ccs_repack
= true,
947 .num_eu_per_subslice
= 6,
951 static const struct gen_device_info gen_device_info_ehl_5
= {
952 GEN11_FEATURES(1, 1, subslices(4), 4),
953 .is_elkhartlake
= true,
956 [MESA_SHADER_VERTEX
] = 64,
957 [MESA_SHADER_TESS_EVAL
] = 34,
960 [MESA_SHADER_VERTEX
] = 2384,
961 [MESA_SHADER_TESS_CTRL
] = 1032,
962 [MESA_SHADER_TESS_EVAL
] = 2384,
963 [MESA_SHADER_GEOMETRY
] = 1032,
966 .disable_ccs_repack
= true,
967 .num_eu_per_subslice
= 4,
971 static const struct gen_device_info gen_device_info_ehl_4
= {
972 GEN11_FEATURES(1, 1, subslices(2), 4),
973 .is_elkhartlake
= true,
976 [MESA_SHADER_VERTEX
] = 64,
977 [MESA_SHADER_TESS_EVAL
] = 34,
980 [MESA_SHADER_VERTEX
] = 2384,
981 [MESA_SHADER_TESS_CTRL
] = 1032,
982 [MESA_SHADER_TESS_EVAL
] = 2384,
983 [MESA_SHADER_GEOMETRY
] = 1032,
986 .disable_ccs_repack
= true,
987 .num_eu_per_subslice
=4,
991 #define GEN12_URB_MIN_MAX_ENTRIES \
993 [MESA_SHADER_VERTEX] = 64, \
994 [MESA_SHADER_TESS_EVAL] = 34, \
997 [MESA_SHADER_VERTEX] = 3576, \
998 [MESA_SHADER_TESS_CTRL] = 1548, \
999 [MESA_SHADER_TESS_EVAL] = 3576, \
1000 [MESA_SHADER_GEOMETRY] = 1548, \
1003 #define GEN12_HW_INFO \
1006 .has_sample_with_hiz = false, \
1007 .has_aux_map = true, \
1008 .max_vs_threads = 546, \
1009 .max_gs_threads = 336, \
1010 .max_tcs_threads = 336, \
1011 .max_tes_threads = 546, \
1012 .max_cs_threads = 112, /* threads per DSS */ \
1014 GEN12_URB_MIN_MAX_ENTRIES, \
1017 #define GEN12_FEATURES(_gt, _slices, _l3) \
1020 .has_64bit_float = false, \
1021 .has_64bit_int = false, \
1022 .has_integer_dword_mul = false, \
1023 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
1024 .simulator_id = 22, \
1025 .num_eu_per_subslice = 16
1027 #define dual_subslices(args...) { args, }
1029 #define GEN12_GT05_FEATURES \
1030 GEN12_FEATURES(1, 1, 4), \
1031 .num_subslices = dual_subslices(1)
1033 #define GEN12_GT_FEATURES(_gt) \
1034 GEN12_FEATURES(1, 1, _gt == 1 ? 4 : 8), \
1035 .num_subslices = dual_subslices(_gt == 1 ? 2 : 6)
1037 static const struct gen_device_info gen_device_info_tgl_gt1
= {
1038 GEN12_GT_FEATURES(1),
1041 static const struct gen_device_info gen_device_info_tgl_gt2
= {
1042 GEN12_GT_FEATURES(2),
1045 static const struct gen_device_info gen_device_info_rkl_gt05
= {
1046 GEN12_GT05_FEATURES
,
1049 static const struct gen_device_info gen_device_info_rkl_gt1
= {
1050 GEN12_GT_FEATURES(1),
1054 gen_device_info_set_eu_mask(struct gen_device_info
*devinfo
,
1059 unsigned subslice_offset
= slice
* devinfo
->eu_slice_stride
+
1060 subslice
* devinfo
->eu_subslice_stride
;
1062 for (unsigned b_eu
= 0; b_eu
< devinfo
->eu_subslice_stride
; b_eu
++) {
1063 devinfo
->eu_masks
[subslice_offset
+ b_eu
] =
1064 (((1U << devinfo
->num_eu_per_subslice
) - 1) >> (b_eu
* 8)) & 0xff;
1068 /* Generate slice/subslice/eu masks from number of
1069 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1072 * These can be overridden with values reported by the kernel either from
1073 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1074 * through the i915 query uapi.
1077 fill_masks(struct gen_device_info
*devinfo
)
1079 devinfo
->slice_masks
= (1U << devinfo
->num_slices
) - 1;
1081 /* Subslice masks */
1082 unsigned max_subslices
= 0;
1083 for (int s
= 0; s
< devinfo
->num_slices
; s
++)
1084 max_subslices
= MAX2(devinfo
->num_subslices
[s
], max_subslices
);
1085 devinfo
->subslice_slice_stride
= DIV_ROUND_UP(max_subslices
, 8);
1087 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1088 devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
] =
1089 (1U << devinfo
->num_subslices
[s
]) - 1;
1093 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(devinfo
->num_eu_per_subslice
, 8);
1094 devinfo
->eu_slice_stride
= max_subslices
* devinfo
->eu_subslice_stride
;
1096 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1097 for (int ss
= 0; ss
< devinfo
->num_subslices
[s
]; ss
++) {
1098 gen_device_info_set_eu_mask(devinfo
, s
, ss
,
1099 (1U << devinfo
->num_eu_per_subslice
) - 1);
1105 reset_masks(struct gen_device_info
*devinfo
)
1107 devinfo
->subslice_slice_stride
= 0;
1108 devinfo
->eu_subslice_stride
= 0;
1109 devinfo
->eu_slice_stride
= 0;
1111 devinfo
->num_slices
= 0;
1112 devinfo
->num_eu_per_subslice
= 0;
1113 memset(devinfo
->num_subslices
, 0, sizeof(devinfo
->num_subslices
));
1115 memset(&devinfo
->slice_masks
, 0, sizeof(devinfo
->slice_masks
));
1116 memset(devinfo
->subslice_masks
, 0, sizeof(devinfo
->subslice_masks
));
1117 memset(devinfo
->eu_masks
, 0, sizeof(devinfo
->eu_masks
));
1118 memset(devinfo
->ppipe_subslices
, 0, sizeof(devinfo
->ppipe_subslices
));
1122 update_from_topology(struct gen_device_info
*devinfo
,
1123 const struct drm_i915_query_topology_info
*topology
)
1125 reset_masks(devinfo
);
1127 devinfo
->subslice_slice_stride
= topology
->subslice_stride
;
1129 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(topology
->max_eus_per_subslice
, 8);
1130 devinfo
->eu_slice_stride
= topology
->max_subslices
* devinfo
->eu_subslice_stride
;
1132 assert(sizeof(devinfo
->slice_masks
) >= DIV_ROUND_UP(topology
->max_slices
, 8));
1133 memcpy(&devinfo
->slice_masks
, topology
->data
, DIV_ROUND_UP(topology
->max_slices
, 8));
1134 devinfo
->num_slices
= __builtin_popcount(devinfo
->slice_masks
);
1136 uint32_t subslice_mask_len
=
1137 topology
->max_slices
* topology
->subslice_stride
;
1138 assert(sizeof(devinfo
->subslice_masks
) >= subslice_mask_len
);
1139 memcpy(devinfo
->subslice_masks
, &topology
->data
[topology
->subslice_offset
],
1142 uint32_t n_subslices
= 0;
1143 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1144 if ((devinfo
->slice_masks
& (1 << s
)) == 0)
1147 for (int b
= 0; b
< devinfo
->subslice_slice_stride
; b
++) {
1148 devinfo
->num_subslices
[s
] +=
1149 __builtin_popcount(devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
+ b
]);
1151 n_subslices
+= devinfo
->num_subslices
[s
];
1153 assert(n_subslices
> 0);
1155 if (devinfo
->gen
== 11) {
1156 /* On ICL we only have one slice */
1157 assert(devinfo
->slice_masks
== 1);
1159 /* Count the number of subslices on each pixel pipe. Assume that
1160 * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
1162 unsigned subslices
= devinfo
->subslice_masks
[0];
1164 while (subslices
> 0) {
1166 devinfo
->ppipe_subslices
[ss
>= 4 ? 1 : 0] += 1;
1172 if (devinfo
->gen
== 12 && devinfo
->num_slices
== 1) {
1173 if (n_subslices
>= 6) {
1174 assert(n_subslices
== 6);
1175 devinfo
->l3_banks
= 8;
1176 } else if (n_subslices
> 2) {
1177 devinfo
->l3_banks
= 6;
1179 devinfo
->l3_banks
= 4;
1183 uint32_t eu_mask_len
=
1184 topology
->eu_stride
* topology
->max_subslices
* topology
->max_slices
;
1185 assert(sizeof(devinfo
->eu_masks
) >= eu_mask_len
);
1186 memcpy(devinfo
->eu_masks
, &topology
->data
[topology
->eu_offset
], eu_mask_len
);
1189 for (int b
= 0; b
< eu_mask_len
; b
++)
1190 n_eus
+= __builtin_popcount(devinfo
->eu_masks
[b
]);
1192 devinfo
->num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1196 update_from_masks(struct gen_device_info
*devinfo
, uint32_t slice_mask
,
1197 uint32_t subslice_mask
, uint32_t n_eus
)
1199 struct drm_i915_query_topology_info
*topology
;
1201 assert((slice_mask
& 0xff) == slice_mask
);
1203 size_t data_length
= 100;
1205 topology
= calloc(1, sizeof(*topology
) + data_length
);
1209 topology
->max_slices
= util_last_bit(slice_mask
);
1210 topology
->max_subslices
= util_last_bit(subslice_mask
);
1212 topology
->subslice_offset
= DIV_ROUND_UP(topology
->max_slices
, 8);
1213 topology
->subslice_stride
= DIV_ROUND_UP(topology
->max_subslices
, 8);
1215 uint32_t n_subslices
= __builtin_popcount(slice_mask
) *
1216 __builtin_popcount(subslice_mask
);
1217 uint32_t num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1218 uint32_t eu_mask
= (1U << num_eu_per_subslice
) - 1;
1220 topology
->eu_offset
= topology
->subslice_offset
+
1221 DIV_ROUND_UP(topology
->max_subslices
, 8);
1222 topology
->eu_stride
= DIV_ROUND_UP(num_eu_per_subslice
, 8);
1224 /* Set slice mask in topology */
1225 for (int b
= 0; b
< topology
->subslice_offset
; b
++)
1226 topology
->data
[b
] = (slice_mask
>> (b
* 8)) & 0xff;
1228 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1230 /* Set subslice mask in topology */
1231 for (int b
= 0; b
< topology
->subslice_stride
; b
++) {
1232 int subslice_offset
= topology
->subslice_offset
+
1233 s
* topology
->subslice_stride
+ b
;
1235 topology
->data
[subslice_offset
] = (subslice_mask
>> (b
* 8)) & 0xff;
1238 /* Set eu mask in topology */
1239 for (int ss
= 0; ss
< topology
->max_subslices
; ss
++) {
1240 for (int b
= 0; b
< topology
->eu_stride
; b
++) {
1241 int eu_offset
= topology
->eu_offset
+
1242 (s
* topology
->max_subslices
+ ss
) * topology
->eu_stride
+ b
;
1244 topology
->data
[eu_offset
] = (eu_mask
>> (b
* 8)) & 0xff;
1249 update_from_topology(devinfo
, topology
);
1256 getparam(int fd
, uint32_t param
, int *value
)
1260 struct drm_i915_getparam gp
= {
1265 int ret
= gen_ioctl(fd
, DRM_IOCTL_I915_GETPARAM
, &gp
);
1274 gen_get_device_info_from_pci_id(int pci_id
,
1275 struct gen_device_info
*devinfo
)
1279 #define CHIPSET(id, family, fam_str, name) \
1280 case id: *devinfo = gen_device_info_##family; break;
1281 #include "pci_ids/i965_pci_ids.h"
1282 #include "pci_ids/iris_pci_ids.h"
1284 fprintf(stderr
, "Driver does not support the 0x%x PCI ID.\n", pci_id
);
1288 fill_masks(devinfo
);
1290 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1292 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1293 * allocate scratch space enough so that each slice has 4 slices allowed."
1295 * The equivalent internal documentation says that this programming note
1296 * applies to all Gen9+ platforms.
1298 * The hardware typically calculates the scratch space pointer by taking
1299 * the base address, and adding per-thread-scratch-space * thread ID.
1300 * Extra padding can be necessary depending how the thread IDs are
1301 * calculated for a particular shader stage.
1304 switch(devinfo
->gen
) {
1307 devinfo
->max_wm_threads
= 64 /* threads-per-PSD */
1308 * devinfo
->num_slices
1309 * 4; /* effective subslices per slice */
1313 devinfo
->max_wm_threads
= 128 /* threads-per-PSD */
1314 * devinfo
->num_slices
1315 * 8; /* subslices per slice */
1318 assert(devinfo
->gen
< 9);
1322 assert(devinfo
->num_slices
<= ARRAY_SIZE(devinfo
->num_subslices
));
1324 devinfo
->chipset_id
= pci_id
;
1329 gen_get_device_name(int devid
)
1333 #define CHIPSET(id, family, fam_str, name) case id: return name " (" fam_str ")"; break;
1334 #include "pci_ids/i965_pci_ids.h"
1335 #include "pci_ids/iris_pci_ids.h"
1342 * for gen8/gen9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology
1346 getparam_topology(struct gen_device_info
*devinfo
, int fd
)
1349 if (!getparam(fd
, I915_PARAM_SLICE_MASK
, &slice_mask
))
1353 if (!getparam(fd
, I915_PARAM_EU_TOTAL
, &n_eus
))
1356 int subslice_mask
= 0;
1357 if (!getparam(fd
, I915_PARAM_SUBSLICE_MASK
, &subslice_mask
))
1360 return update_from_masks(devinfo
, slice_mask
, subslice_mask
, n_eus
);
1364 * preferred API for updating the topology in devinfo (kernel 4.17+)
1367 query_topology(struct gen_device_info
*devinfo
, int fd
)
1369 struct drm_i915_query_item item
= {
1370 .query_id
= DRM_I915_QUERY_TOPOLOGY_INFO
,
1372 struct drm_i915_query query
= {
1374 .items_ptr
= (uintptr_t) &item
,
1377 if (gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &query
))
1380 if (item
.length
< 0)
1383 struct drm_i915_query_topology_info
*topo_info
=
1384 (struct drm_i915_query_topology_info
*) calloc(1, item
.length
);
1385 item
.data_ptr
= (uintptr_t) topo_info
;
1387 if (gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &query
) ||
1391 update_from_topology(devinfo
, topo_info
);
1400 gen_get_device_info_from_fd(int fd
, struct gen_device_info
*devinfo
)
1404 const char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
1405 if (devid_override
&& strlen(devid_override
) > 0) {
1406 if (geteuid() == getuid()) {
1407 devid
= gen_device_name_to_pci_device_id(devid_override
);
1408 /* Fallback to PCI ID. */
1410 devid
= strtol(devid_override
, NULL
, 0);
1412 fprintf(stderr
, "Invalid INTEL_DEVID_OVERRIDE=\"%s\". "
1413 "Use a valid numeric PCI ID or one of the supported "
1414 "platform names: %s", devid_override
, name_map
[0].name
);
1415 for (unsigned i
= 1; i
< ARRAY_SIZE(name_map
); i
++)
1416 fprintf(stderr
, ", %s", name_map
[i
].name
);
1417 fprintf(stderr
, "\n");
1421 fprintf(stderr
, "Ignoring INTEL_DEVID_OVERRIDE=\"%s\" because "
1422 "real and effective user ID don't match.\n", devid_override
);
1427 if (!gen_get_device_info_from_pci_id(devid
, devinfo
))
1429 devinfo
->no_hw
= true;
1431 /* query the device id */
1432 if (!getparam(fd
, I915_PARAM_CHIPSET_ID
, &devid
))
1434 if (!gen_get_device_info_from_pci_id(devid
, devinfo
))
1436 devinfo
->no_hw
= false;
1439 /* remaining initializion queries the kernel for device info */
1443 int timestamp_frequency
;
1444 if (getparam(fd
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1445 ×tamp_frequency
))
1446 devinfo
->timestamp_frequency
= timestamp_frequency
;
1447 else if (devinfo
->gen
>= 10)
1448 /* gen10 and later requires the timestamp_frequency to be updated */
1451 if (!getparam(fd
, I915_PARAM_REVISION
, &devinfo
->revision
))
1452 devinfo
->revision
= 0;
1454 if (!query_topology(devinfo
, fd
)) {
1455 if (devinfo
->gen
>= 10) {
1456 /* topology uAPI required for CNL+ (kernel 4.17+) */
1460 /* else use the kernel 4.13+ api for gen8+. For older kernels, topology
1461 * will be wrong, affecting GPU metrics. In this case, fail silently.
1463 getparam_topology(devinfo
, fd
);