projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
intel: replace large stack buffer with heap allocation
[mesa.git] / src / intel / dev / gen_device_info.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <stdio.h>
27 #include <stdlib.h>
28 #include <string.h>
29 #include <unistd.h>
30 #include "gen_device_info.h"
31 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
33 #include "util/macros.h"
34
35 #include "drm-uapi/i915_drm.h"
36
37 /**
38 * Get the PCI ID for the device name.
39 *
40 * Returns -1 if the device is not known.
41 */
42 int
43 gen_device_name_to_pci_device_id(const char *name)
44 {
45 static const struct {
46 const char *name;
47 int pci_id;
48 } name_map[] = {
49 { "brw", 0x2a02 },
50 { "g4x", 0x2a42 },
51 { "ilk", 0x0042 },
52 { "snb", 0x0126 },
53 { "ivb", 0x016a },
54 { "hsw", 0x0d2e },
55 { "byt", 0x0f33 },
56 { "bdw", 0x162e },
57 { "chv", 0x22B3 },
58 { "skl", 0x1912 },
59 { "bxt", 0x5A85 },
60 { "kbl", 0x5912 },
61 { "aml", 0x591C },
62 { "glk", 0x3185 },
63 { "cfl", 0x3E9B },
64 { "whl", 0x3EA1 },
65 { "cml", 0x9b41 },
66 { "cnl", 0x5a52 },
67 { "icl", 0x8a52 },
68 };
69
70 for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
71 if (!strcmp(name_map[i].name, name))
72 return name_map[i].pci_id;
73 }
74
75 return -1;
76 }
77
78 /**
79 * Get the overridden PCI ID for the device. This is set with the
80 * INTEL_DEVID_OVERRIDE environment variable.
81 *
82 * Returns -1 if the override is not set.
83 */
84 int
85 gen_get_pci_device_id_override(void)
86 {
87 if (geteuid() == getuid()) {
88 const char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
89 if (devid_override) {
90 const int id = gen_device_name_to_pci_device_id(devid_override);
91 return id >= 0 ? id : strtol(devid_override, NULL, 0);
92 }
93 }
94
95 return -1;
96 }
97
98 static const struct gen_device_info gen_device_info_i965 = {
99 .gen = 4,
100 .has_negative_rhw_bug = true,
101 .num_slices = 1,
102 .num_subslices = { 1, },
103 .num_eu_per_subslice = 8,
104 .num_thread_per_eu = 4,
105 .max_vs_threads = 16,
106 .max_gs_threads = 2,
107 .max_wm_threads = 8 * 4,
108 .urb = {
109 .size = 256,
110 },
111 .timestamp_frequency = 12500000,
112 .simulator_id = -1,
113 };
114
115 static const struct gen_device_info gen_device_info_g4x = {
116 .gen = 4,
117 .has_pln = true,
118 .has_compr4 = true,
119 .has_surface_tile_offset = true,
120 .is_g4x = true,
121 .num_slices = 1,
122 .num_subslices = { 1, },
123 .num_eu_per_subslice = 10,
124 .num_thread_per_eu = 5,
125 .max_vs_threads = 32,
126 .max_gs_threads = 2,
127 .max_wm_threads = 10 * 5,
128 .urb = {
129 .size = 384,
130 },
131 .timestamp_frequency = 12500000,
132 .simulator_id = -1,
133 };
134
135 static const struct gen_device_info gen_device_info_ilk = {
136 .gen = 5,
137 .has_pln = true,
138 .has_compr4 = true,
139 .has_surface_tile_offset = true,
140 .num_slices = 1,
141 .num_subslices = { 1, },
142 .num_eu_per_subslice = 12,
143 .num_thread_per_eu = 6,
144 .max_vs_threads = 72,
145 .max_gs_threads = 32,
146 .max_wm_threads = 12 * 6,
147 .urb = {
148 .size = 1024,
149 },
150 .timestamp_frequency = 12500000,
151 .simulator_id = -1,
152 };
153
154 static const struct gen_device_info gen_device_info_snb_gt1 = {
155 .gen = 6,
156 .gt = 1,
157 .has_hiz_and_separate_stencil = true,
158 .has_llc = true,
159 .has_pln = true,
160 .has_surface_tile_offset = true,
161 .needs_unlit_centroid_workaround = true,
162 .num_slices = 1,
163 .num_subslices = { 1, },
164 .num_eu_per_subslice = 6,
165 .num_thread_per_eu = 6, /* Not confirmed */
166 .max_vs_threads = 24,
167 .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
168 .max_wm_threads = 40,
169 .urb = {
170 .size = 32,
171 .min_entries = {
172 [MESA_SHADER_VERTEX] = 24,
173 },
174 .max_entries = {
175 [MESA_SHADER_VERTEX] = 256,
176 [MESA_SHADER_GEOMETRY] = 256,
177 },
178 },
179 .timestamp_frequency = 12500000,
180 .simulator_id = -1,
181 };
182
183 static const struct gen_device_info gen_device_info_snb_gt2 = {
184 .gen = 6,
185 .gt = 2,
186 .has_hiz_and_separate_stencil = true,
187 .has_llc = true,
188 .has_pln = true,
189 .has_surface_tile_offset = true,
190 .needs_unlit_centroid_workaround = true,
191 .num_slices = 1,
192 .num_subslices = { 1, },
193 .num_eu_per_subslice = 12,
194 .num_thread_per_eu = 6, /* Not confirmed */
195 .max_vs_threads = 60,
196 .max_gs_threads = 60,
197 .max_wm_threads = 80,
198 .urb = {
199 .size = 64,
200 .min_entries = {
201 [MESA_SHADER_VERTEX] = 24,
202 },
203 .max_entries = {
204 [MESA_SHADER_VERTEX] = 256,
205 [MESA_SHADER_GEOMETRY] = 256,
206 },
207 },
208 .timestamp_frequency = 12500000,
209 .simulator_id = -1,
210 };
211
212 #define GEN7_FEATURES \
213 .gen = 7, \
214 .has_hiz_and_separate_stencil = true, \
215 .must_use_separate_stencil = true, \
216 .has_llc = true, \
217 .has_pln = true, \
218 .has_64bit_types = true, \
219 .has_surface_tile_offset = true, \
220 .timestamp_frequency = 12500000
221
222 static const struct gen_device_info gen_device_info_ivb_gt1 = {
223 GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
224 .num_slices = 1,
225 .num_subslices = { 1, },
226 .num_eu_per_subslice = 6,
227 .num_thread_per_eu = 6,
228 .l3_banks = 2,
229 .max_vs_threads = 36,
230 .max_tcs_threads = 36,
231 .max_tes_threads = 36,
232 .max_gs_threads = 36,
233 .max_wm_threads = 48,
234 .max_cs_threads = 36,
235 .urb = {
236 .size = 128,
237 .min_entries = {
238 [MESA_SHADER_VERTEX] = 32,
239 [MESA_SHADER_TESS_EVAL] = 10,
240 },
241 .max_entries = {
242 [MESA_SHADER_VERTEX] = 512,
243 [MESA_SHADER_TESS_CTRL] = 32,
244 [MESA_SHADER_TESS_EVAL] = 288,
245 [MESA_SHADER_GEOMETRY] = 192,
246 },
247 },
248 .simulator_id = 7,
249 };
250
251 static const struct gen_device_info gen_device_info_ivb_gt2 = {
252 GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
253 .num_slices = 1,
254 .num_subslices = { 1, },
255 .num_eu_per_subslice = 12,
256 .num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
257 * @max_wm_threads ... */
258 .l3_banks = 4,
259 .max_vs_threads = 128,
260 .max_tcs_threads = 128,
261 .max_tes_threads = 128,
262 .max_gs_threads = 128,
263 .max_wm_threads = 172,
264 .max_cs_threads = 64,
265 .urb = {
266 .size = 256,
267 .min_entries = {
268 [MESA_SHADER_VERTEX] = 32,
269 [MESA_SHADER_TESS_EVAL] = 10,
270 },
271 .max_entries = {
272 [MESA_SHADER_VERTEX] = 704,
273 [MESA_SHADER_TESS_CTRL] = 64,
274 [MESA_SHADER_TESS_EVAL] = 448,
275 [MESA_SHADER_GEOMETRY] = 320,
276 },
277 },
278 .simulator_id = 7,
279 };
280
281 static const struct gen_device_info gen_device_info_byt = {
282 GEN7_FEATURES, .is_baytrail = true, .gt = 1,
283 .num_slices = 1,
284 .num_subslices = { 1, },
285 .num_eu_per_subslice = 4,
286 .num_thread_per_eu = 8,
287 .l3_banks = 1,
288 .has_llc = false,
289 .max_vs_threads = 36,
290 .max_tcs_threads = 36,
291 .max_tes_threads = 36,
292 .max_gs_threads = 36,
293 .max_wm_threads = 48,
294 .max_cs_threads = 32,
295 .urb = {
296 .size = 128,
297 .min_entries = {
298 [MESA_SHADER_VERTEX] = 32,
299 [MESA_SHADER_TESS_EVAL] = 10,
300 },
301 .max_entries = {
302 [MESA_SHADER_VERTEX] = 512,
303 [MESA_SHADER_TESS_CTRL] = 32,
304 [MESA_SHADER_TESS_EVAL] = 288,
305 [MESA_SHADER_GEOMETRY] = 192,
306 },
307 },
308 .simulator_id = 10,
309 };
310
311 #define HSW_FEATURES \
312 GEN7_FEATURES, \
313 .is_haswell = true, \
314 .supports_simd16_3src = true, \
315 .has_resource_streamer = true
316
317 static const struct gen_device_info gen_device_info_hsw_gt1 = {
318 HSW_FEATURES, .gt = 1,
319 .num_slices = 1,
320 .num_subslices = { 1, },
321 .num_eu_per_subslice = 10,
322 .num_thread_per_eu = 7,
323 .l3_banks = 2,
324 .max_vs_threads = 70,
325 .max_tcs_threads = 70,
326 .max_tes_threads = 70,
327 .max_gs_threads = 70,
328 .max_wm_threads = 102,
329 .max_cs_threads = 70,
330 .urb = {
331 .size = 128,
332 .min_entries = {
333 [MESA_SHADER_VERTEX] = 32,
334 [MESA_SHADER_TESS_EVAL] = 10,
335 },
336 .max_entries = {
337 [MESA_SHADER_VERTEX] = 640,
338 [MESA_SHADER_TESS_CTRL] = 64,
339 [MESA_SHADER_TESS_EVAL] = 384,
340 [MESA_SHADER_GEOMETRY] = 256,
341 },
342 },
343 .simulator_id = 9,
344 };
345
346 static const struct gen_device_info gen_device_info_hsw_gt2 = {
347 HSW_FEATURES, .gt = 2,
348 .num_slices = 1,
349 .num_subslices = { 2, },
350 .num_eu_per_subslice = 10,
351 .num_thread_per_eu = 7,
352 .l3_banks = 4,
353 .max_vs_threads = 280,
354 .max_tcs_threads = 256,
355 .max_tes_threads = 280,
356 .max_gs_threads = 256,
357 .max_wm_threads = 204,
358 .max_cs_threads = 70,
359 .urb = {
360 .size = 256,
361 .min_entries = {
362 [MESA_SHADER_VERTEX] = 64,
363 [MESA_SHADER_TESS_EVAL] = 10,
364 },
365 .max_entries = {
366 [MESA_SHADER_VERTEX] = 1664,
367 [MESA_SHADER_TESS_CTRL] = 128,
368 [MESA_SHADER_TESS_EVAL] = 960,
369 [MESA_SHADER_GEOMETRY] = 640,
370 },
371 },
372 .simulator_id = 9,
373 };
374
375 static const struct gen_device_info gen_device_info_hsw_gt3 = {
376 HSW_FEATURES, .gt = 3,
377 .num_slices = 2,
378 .num_subslices = { 2, },
379 .num_eu_per_subslice = 10,
380 .num_thread_per_eu = 7,
381 .l3_banks = 8,
382 .max_vs_threads = 280,
383 .max_tcs_threads = 256,
384 .max_tes_threads = 280,
385 .max_gs_threads = 256,
386 .max_wm_threads = 408,
387 .max_cs_threads = 70,
388 .urb = {
389 .size = 512,
390 .min_entries = {
391 [MESA_SHADER_VERTEX] = 64,
392 [MESA_SHADER_TESS_EVAL] = 10,
393 },
394 .max_entries = {
395 [MESA_SHADER_VERTEX] = 1664,
396 [MESA_SHADER_TESS_CTRL] = 128,
397 [MESA_SHADER_TESS_EVAL] = 960,
398 [MESA_SHADER_GEOMETRY] = 640,
399 },
400 },
401 .simulator_id = 9,
402 };
403
404 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
405 * so keep things conservative for now and set has_sample_with_hiz = false.
406 */
407 #define GEN8_FEATURES \
408 .gen = 8, \
409 .has_hiz_and_separate_stencil = true, \
410 .has_resource_streamer = true, \
411 .must_use_separate_stencil = true, \
412 .has_llc = true, \
413 .has_sample_with_hiz = false, \
414 .has_pln = true, \
415 .has_integer_dword_mul = true, \
416 .has_64bit_types = true, \
417 .supports_simd16_3src = true, \
418 .has_surface_tile_offset = true, \
419 .num_thread_per_eu = 7, \
420 .max_vs_threads = 504, \
421 .max_tcs_threads = 504, \
422 .max_tes_threads = 504, \
423 .max_gs_threads = 504, \
424 .max_wm_threads = 384, \
425 .timestamp_frequency = 12500000
426
427 static const struct gen_device_info gen_device_info_bdw_gt1 = {
428 GEN8_FEATURES, .gt = 1,
429 .is_broadwell = true,
430 .num_slices = 1,
431 .num_subslices = { 2, },
432 .num_eu_per_subslice = 8,
433 .l3_banks = 2,
434 .max_cs_threads = 42,
435 .urb = {
436 .size = 192,
437 .min_entries = {
438 [MESA_SHADER_VERTEX] = 64,
439 [MESA_SHADER_TESS_EVAL] = 34,
440 },
441 .max_entries = {
442 [MESA_SHADER_VERTEX] = 2560,
443 [MESA_SHADER_TESS_CTRL] = 504,
444 [MESA_SHADER_TESS_EVAL] = 1536,
445 [MESA_SHADER_GEOMETRY] = 960,
446 },
447 },
448 .simulator_id = 11,
449 };
450
451 static const struct gen_device_info gen_device_info_bdw_gt2 = {
452 GEN8_FEATURES, .gt = 2,
453 .is_broadwell = true,
454 .num_slices = 1,
455 .num_subslices = { 3, },
456 .num_eu_per_subslice = 8,
457 .l3_banks = 4,
458 .max_cs_threads = 56,
459 .urb = {
460 .size = 384,
461 .min_entries = {
462 [MESA_SHADER_VERTEX] = 64,
463 [MESA_SHADER_TESS_EVAL] = 34,
464 },
465 .max_entries = {
466 [MESA_SHADER_VERTEX] = 2560,
467 [MESA_SHADER_TESS_CTRL] = 504,
468 [MESA_SHADER_TESS_EVAL] = 1536,
469 [MESA_SHADER_GEOMETRY] = 960,
470 },
471 },
472 .simulator_id = 11,
473 };
474
475 static const struct gen_device_info gen_device_info_bdw_gt3 = {
476 GEN8_FEATURES, .gt = 3,
477 .is_broadwell = true,
478 .num_slices = 2,
479 .num_subslices = { 3, 3, },
480 .num_eu_per_subslice = 8,
481 .l3_banks = 8,
482 .max_cs_threads = 56,
483 .urb = {
484 .size = 384,
485 .min_entries = {
486 [MESA_SHADER_VERTEX] = 64,
487 [MESA_SHADER_TESS_EVAL] = 34,
488 },
489 .max_entries = {
490 [MESA_SHADER_VERTEX] = 2560,
491 [MESA_SHADER_TESS_CTRL] = 504,
492 [MESA_SHADER_TESS_EVAL] = 1536,
493 [MESA_SHADER_GEOMETRY] = 960,
494 },
495 },
496 .simulator_id = 11,
497 };
498
499 static const struct gen_device_info gen_device_info_chv = {
500 GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
501 .has_llc = false,
502 .has_integer_dword_mul = false,
503 .num_slices = 1,
504 .num_subslices = { 2, },
505 .num_eu_per_subslice = 8,
506 .l3_banks = 2,
507 .max_vs_threads = 80,
508 .max_tcs_threads = 80,
509 .max_tes_threads = 80,
510 .max_gs_threads = 80,
511 .max_wm_threads = 128,
512 .max_cs_threads = 6 * 7,
513 .urb = {
514 .size = 192,
515 .min_entries = {
516 [MESA_SHADER_VERTEX] = 34,
517 [MESA_SHADER_TESS_EVAL] = 34,
518 },
519 .max_entries = {
520 [MESA_SHADER_VERTEX] = 640,
521 [MESA_SHADER_TESS_CTRL] = 80,
522 [MESA_SHADER_TESS_EVAL] = 384,
523 [MESA_SHADER_GEOMETRY] = 256,
524 },
525 },
526 .simulator_id = 13,
527 };
528
529 #define GEN9_HW_INFO \
530 .gen = 9, \
531 .max_vs_threads = 336, \
532 .max_gs_threads = 336, \
533 .max_tcs_threads = 336, \
534 .max_tes_threads = 336, \
535 .max_cs_threads = 56, \
536 .timestamp_frequency = 12000000, \
537 .urb = { \
538 .size = 384, \
539 .min_entries = { \
540 [MESA_SHADER_VERTEX] = 64, \
541 [MESA_SHADER_TESS_EVAL] = 34, \
542 }, \
543 .max_entries = { \
544 [MESA_SHADER_VERTEX] = 1856, \
545 [MESA_SHADER_TESS_CTRL] = 672, \
546 [MESA_SHADER_TESS_EVAL] = 1120, \
547 [MESA_SHADER_GEOMETRY] = 640, \
548 }, \
549 }
550
551 #define GEN9_LP_FEATURES \
552 GEN8_FEATURES, \
553 GEN9_HW_INFO, \
554 .has_integer_dword_mul = false, \
555 .gt = 1, \
556 .has_llc = false, \
557 .has_sample_with_hiz = true, \
558 .num_slices = 1, \
559 .num_thread_per_eu = 6, \
560 .max_vs_threads = 112, \
561 .max_tcs_threads = 112, \
562 .max_tes_threads = 112, \
563 .max_gs_threads = 112, \
564 .max_cs_threads = 6 * 6, \
565 .timestamp_frequency = 19200000, \
566 .urb = { \
567 .size = 192, \
568 .min_entries = { \
569 [MESA_SHADER_VERTEX] = 34, \
570 [MESA_SHADER_TESS_EVAL] = 34, \
571 }, \
572 .max_entries = { \
573 [MESA_SHADER_VERTEX] = 704, \
574 [MESA_SHADER_TESS_CTRL] = 256, \
575 [MESA_SHADER_TESS_EVAL] = 416, \
576 [MESA_SHADER_GEOMETRY] = 256, \
577 }, \
578 }
579
580 #define GEN9_LP_FEATURES_3X6 \
581 GEN9_LP_FEATURES, \
582 .num_subslices = { 3, }, \
583 .num_eu_per_subslice = 6
584
585 #define GEN9_LP_FEATURES_2X6 \
586 GEN9_LP_FEATURES, \
587 .num_subslices = { 2, }, \
588 .num_eu_per_subslice = 6, \
589 .max_vs_threads = 56, \
590 .max_tcs_threads = 56, \
591 .max_tes_threads = 56, \
592 .max_gs_threads = 56, \
593 .max_cs_threads = 6 * 6, \
594 .urb = { \
595 .size = 128, \
596 .min_entries = { \
597 [MESA_SHADER_VERTEX] = 34, \
598 [MESA_SHADER_TESS_EVAL] = 34, \
599 }, \
600 .max_entries = { \
601 [MESA_SHADER_VERTEX] = 352, \
602 [MESA_SHADER_TESS_CTRL] = 128, \
603 [MESA_SHADER_TESS_EVAL] = 208, \
604 [MESA_SHADER_GEOMETRY] = 128, \
605 }, \
606 }
607
608 #define GEN9_FEATURES \
609 GEN8_FEATURES, \
610 GEN9_HW_INFO, \
611 .has_sample_with_hiz = true
612
613 static const struct gen_device_info gen_device_info_skl_gt1 = {
614 GEN9_FEATURES, .gt = 1,
615 .is_skylake = true,
616 .num_slices = 1,
617 .num_subslices = { 2, },
618 .num_eu_per_subslice = 6,
619 .l3_banks = 2,
620 .urb.size = 192,
621 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
622 * leading to some vertices to go missing if we use too much URB.
623 */
624 .urb.max_entries[MESA_SHADER_VERTEX] = 928,
625 .simulator_id = 12,
626 };
627
628 static const struct gen_device_info gen_device_info_skl_gt2 = {
629 GEN9_FEATURES, .gt = 2,
630 .is_skylake = true,
631 .num_slices = 1,
632 .num_subslices = { 3, },
633 .num_eu_per_subslice = 8,
634 .l3_banks = 4,
635 .simulator_id = 12,
636 };
637
638 static const struct gen_device_info gen_device_info_skl_gt3 = {
639 GEN9_FEATURES, .gt = 3,
640 .is_skylake = true,
641 .num_slices = 2,
642 .num_subslices = { 3, 3, },
643 .num_eu_per_subslice = 8,
644 .l3_banks = 8,
645 .simulator_id = 12,
646 };
647
648 static const struct gen_device_info gen_device_info_skl_gt4 = {
649 GEN9_FEATURES, .gt = 4,
650 .is_skylake = true,
651 .num_slices = 3,
652 .num_subslices = { 3, 3, 3, },
653 .num_eu_per_subslice = 8,
654 .l3_banks = 12,
655 /* From the "L3 Allocation and Programming" documentation:
656 *
657 * "URB is limited to 1008KB due to programming restrictions. This is not a
658 * restriction of the L3 implementation, but of the FF and other clients.
659 * Therefore, in a GT4 implementation it is possible for the programmed
660 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
661 * only 1008KB of this will be used."
662 */
663 .urb.size = 1008 / 3,
664 .simulator_id = 12,
665 };
666
667 static const struct gen_device_info gen_device_info_bxt = {
668 GEN9_LP_FEATURES_3X6,
669 .is_broxton = true,
670 .l3_banks = 2,
671 .simulator_id = 14,
672 };
673
674 static const struct gen_device_info gen_device_info_bxt_2x6 = {
675 GEN9_LP_FEATURES_2X6,
676 .is_broxton = true,
677 .l3_banks = 1,
678 .simulator_id = 14,
679 };
680 /*
681 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
682 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
683 */
684
685 static const struct gen_device_info gen_device_info_kbl_gt1 = {
686 GEN9_FEATURES,
687 .is_kabylake = true,
688 .gt = 1,
689
690 .max_cs_threads = 7 * 6,
691 .urb.size = 192,
692 .num_slices = 1,
693 .num_subslices = { 2, },
694 .num_eu_per_subslice = 6,
695 .l3_banks = 2,
696 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
697 * leading to some vertices to go missing if we use too much URB.
698 */
699 .urb.max_entries[MESA_SHADER_VERTEX] = 928,
700 .simulator_id = 16,
701 };
702
703 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
704 GEN9_FEATURES,
705 .is_kabylake = true,
706 .gt = 1,
707
708 .max_cs_threads = 7 * 6,
709 .num_slices = 1,
710 .num_subslices = { 3, },
711 .num_eu_per_subslice = 6,
712 .l3_banks = 4,
713 .simulator_id = 16,
714 };
715
716 static const struct gen_device_info gen_device_info_kbl_gt2 = {
717 GEN9_FEATURES,
718 .is_kabylake = true,
719 .gt = 2,
720
721 .num_slices = 1,
722 .num_subslices = { 3, },
723 .num_eu_per_subslice = 8,
724 .l3_banks = 4,
725 .simulator_id = 16,
726 };
727
728 static const struct gen_device_info gen_device_info_kbl_gt3 = {
729 GEN9_FEATURES,
730 .is_kabylake = true,
731 .gt = 3,
732
733 .num_slices = 2,
734 .num_subslices = { 3, 3, },
735 .num_eu_per_subslice = 8,
736 .l3_banks = 8,
737 .simulator_id = 16,
738 };
739
740 static const struct gen_device_info gen_device_info_kbl_gt4 = {
741 GEN9_FEATURES,
742 .is_kabylake = true,
743 .gt = 4,
744
745 /*
746 * From the "L3 Allocation and Programming" documentation:
747 *
748 * "URB is limited to 1008KB due to programming restrictions. This
749 * is not a restriction of the L3 implementation, but of the FF and
750 * other clients. Therefore, in a GT4 implementation it is
751 * possible for the programmed allocation of the L3 data array to
752 * provide 3*384KB=1152KB for URB, but only 1008KB of this
753 * will be used."
754 */
755 .urb.size = 1008 / 3,
756 .num_slices = 3,
757 .num_subslices = { 3, 3, 3, },
758 .num_eu_per_subslice = 8,
759 .l3_banks = 12,
760 .simulator_id = 16,
761 };
762
763 static const struct gen_device_info gen_device_info_glk = {
764 GEN9_LP_FEATURES_3X6,
765 .is_geminilake = true,
766 .l3_banks = 2,
767 .simulator_id = 17,
768 };
769
770 static const struct gen_device_info gen_device_info_glk_2x6 = {
771 GEN9_LP_FEATURES_2X6,
772 .is_geminilake = true,
773 .l3_banks = 2,
774 .simulator_id = 17,
775 };
776
777 static const struct gen_device_info gen_device_info_cfl_gt1 = {
778 GEN9_FEATURES,
779 .is_coffeelake = true,
780 .gt = 1,
781
782 .num_slices = 1,
783 .num_subslices = { 2, },
784 .num_eu_per_subslice = 6,
785 .l3_banks = 2,
786 .urb.size = 192,
787 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
788 * leading to some vertices to go missing if we use too much URB.
789 */
790 .urb.max_entries[MESA_SHADER_VERTEX] = 928,
791 .simulator_id = 24,
792 };
793 static const struct gen_device_info gen_device_info_cfl_gt2 = {
794 GEN9_FEATURES,
795 .is_coffeelake = true,
796 .gt = 2,
797
798 .num_slices = 1,
799 .num_subslices = { 3, },
800 .num_eu_per_subslice = 8,
801 .l3_banks = 4,
802 .simulator_id = 24,
803 };
804
805 static const struct gen_device_info gen_device_info_cfl_gt3 = {
806 GEN9_FEATURES,
807 .is_coffeelake = true,
808 .gt = 3,
809
810 .num_slices = 2,
811 .num_subslices = { 3, 3, },
812 .num_eu_per_subslice = 8,
813 .l3_banks = 8,
814 .simulator_id = 24,
815 };
816
817 #define GEN10_HW_INFO \
818 .gen = 10, \
819 .num_thread_per_eu = 7, \
820 .max_vs_threads = 728, \
821 .max_gs_threads = 432, \
822 .max_tcs_threads = 432, \
823 .max_tes_threads = 624, \
824 .max_cs_threads = 56, \
825 .timestamp_frequency = 19200000, \
826 .urb = { \
827 .size = 256, \
828 .min_entries = { \
829 [MESA_SHADER_VERTEX] = 64, \
830 [MESA_SHADER_TESS_EVAL] = 34, \
831 }, \
832 .max_entries = { \
833 [MESA_SHADER_VERTEX] = 3936, \
834 [MESA_SHADER_TESS_CTRL] = 896, \
835 [MESA_SHADER_TESS_EVAL] = 2064, \
836 [MESA_SHADER_GEOMETRY] = 832, \
837 }, \
838 }
839
840 #define subslices(args...) { args, }
841
842 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
843 GEN8_FEATURES, \
844 GEN10_HW_INFO, \
845 .has_sample_with_hiz = true, \
846 .gt = _gt, \
847 .num_slices = _slices, \
848 .num_subslices = _subslices, \
849 .num_eu_per_subslice = 8, \
850 .l3_banks = _l3
851
852 static const struct gen_device_info gen_device_info_cnl_2x8 = {
853 /* GT0.5 */
854 GEN10_FEATURES(1, 1, subslices(2), 2),
855 .is_cannonlake = true,
856 .simulator_id = 15,
857 };
858
859 static const struct gen_device_info gen_device_info_cnl_3x8 = {
860 /* GT1 */
861 GEN10_FEATURES(1, 1, subslices(3), 3),
862 .is_cannonlake = true,
863 .simulator_id = 15,
864 };
865
866 static const struct gen_device_info gen_device_info_cnl_4x8 = {
867 /* GT 1.5 */
868 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
869 .is_cannonlake = true,
870 .simulator_id = 15,
871 };
872
873 static const struct gen_device_info gen_device_info_cnl_5x8 = {
874 /* GT2 */
875 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
876 .is_cannonlake = true,
877 .simulator_id = 15,
878 };
879
880 #define GEN11_HW_INFO \
881 .gen = 11, \
882 .has_pln = false, \
883 .max_vs_threads = 364, \
884 .max_gs_threads = 224, \
885 .max_tcs_threads = 224, \
886 .max_tes_threads = 364, \
887 .max_cs_threads = 56
888
889 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
890 GEN8_FEATURES, \
891 GEN11_HW_INFO, \
892 .has_64bit_types = false, \
893 .has_integer_dword_mul = false, \
894 .has_sample_with_hiz = false, \
895 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
896 .num_subslices = _subslices, \
897 .num_eu_per_subslice = 8
898
899 #define GEN11_URB_MIN_MAX_ENTRIES \
900 .min_entries = { \
901 [MESA_SHADER_VERTEX] = 64, \
902 [MESA_SHADER_TESS_EVAL] = 34, \
903 }, \
904 .max_entries = { \
905 [MESA_SHADER_VERTEX] = 2384, \
906 [MESA_SHADER_TESS_CTRL] = 1032, \
907 [MESA_SHADER_TESS_EVAL] = 2384, \
908 [MESA_SHADER_GEOMETRY] = 1032, \
909 }
910
911 static const struct gen_device_info gen_device_info_icl_8x8 = {
912 GEN11_FEATURES(2, 1, subslices(8), 8),
913 .urb = {
914 .size = 1024,
915 GEN11_URB_MIN_MAX_ENTRIES,
916 },
917 .simulator_id = 19,
918 };
919
920 static const struct gen_device_info gen_device_info_icl_6x8 = {
921 GEN11_FEATURES(1, 1, subslices(6), 6),
922 .urb = {
923 .size = 768,
924 GEN11_URB_MIN_MAX_ENTRIES,
925 },
926 .simulator_id = 19,
927 };
928
929 static const struct gen_device_info gen_device_info_icl_4x8 = {
930 GEN11_FEATURES(1, 1, subslices(4), 6),
931 .urb = {
932 .size = 768,
933 GEN11_URB_MIN_MAX_ENTRIES,
934 },
935 .simulator_id = 19,
936 };
937
938 static const struct gen_device_info gen_device_info_icl_1x8 = {
939 GEN11_FEATURES(1, 1, subslices(1), 6),
940 .urb = {
941 .size = 768,
942 GEN11_URB_MIN_MAX_ENTRIES,
943 },
944 .simulator_id = 19,
945 };
946
947 static const struct gen_device_info gen_device_info_ehl_4x8 = {
948 GEN11_FEATURES(1, 1, subslices(4), 4),
949 .urb = {
950 .size = 512,
951 .min_entries = {
952 [MESA_SHADER_VERTEX] = 64,
953 [MESA_SHADER_TESS_EVAL] = 34,
954 },
955 .max_entries = {
956 [MESA_SHADER_VERTEX] = 2384,
957 [MESA_SHADER_TESS_CTRL] = 1032,
958 [MESA_SHADER_TESS_EVAL] = 2384,
959 [MESA_SHADER_GEOMETRY] = 1032,
960 },
961 },
962 .disable_ccs_repack = true,
963 .simulator_id = 28,
964 };
965
966 /* FIXME: Verfiy below entries when more information is available for this SKU.
967 */
968 static const struct gen_device_info gen_device_info_ehl_4x4 = {
969 GEN11_FEATURES(1, 1, subslices(4), 4),
970 .urb = {
971 .size = 512,
972 .min_entries = {
973 [MESA_SHADER_VERTEX] = 64,
974 [MESA_SHADER_TESS_EVAL] = 34,
975 },
976 .max_entries = {
977 [MESA_SHADER_VERTEX] = 2384,
978 [MESA_SHADER_TESS_CTRL] = 1032,
979 [MESA_SHADER_TESS_EVAL] = 2384,
980 [MESA_SHADER_GEOMETRY] = 1032,
981 },
982 },
983 .disable_ccs_repack = true,
984 .num_eu_per_subslice = 4,
985 .simulator_id = 28,
986 };
987
988 /* FIXME: Verfiy below entries when more information is available for this SKU.
989 */
990 static const struct gen_device_info gen_device_info_ehl_2x4 = {
991 GEN11_FEATURES(1, 1, subslices(2), 4),
992 .urb = {
993 .size = 512,
994 .min_entries = {
995 [MESA_SHADER_VERTEX] = 64,
996 [MESA_SHADER_TESS_EVAL] = 34,
997 },
998 .max_entries = {
999 [MESA_SHADER_VERTEX] = 2384,
1000 [MESA_SHADER_TESS_CTRL] = 1032,
1001 [MESA_SHADER_TESS_EVAL] = 2384,
1002 [MESA_SHADER_GEOMETRY] = 1032,
1003 },
1004 },
1005 .disable_ccs_repack = true,
1006 .num_eu_per_subslice =4,
1007 .simulator_id = 28,
1008 };
1009
1010 static void
1011 gen_device_info_set_eu_mask(struct gen_device_info *devinfo,
1012 unsigned slice,
1013 unsigned subslice,
1014 unsigned eu_mask)
1015 {
1016 unsigned subslice_offset = slice * devinfo->eu_slice_stride +
1017 subslice * devinfo->eu_subslice_stride;
1018
1019 for (unsigned b_eu = 0; b_eu < devinfo->eu_subslice_stride; b_eu++) {
1020 devinfo->eu_masks[subslice_offset + b_eu] =
1021 (((1U << devinfo->num_eu_per_subslice) - 1) >> (b_eu * 8)) & 0xff;
1022 }
1023 }
1024
1025 /* Generate slice/subslice/eu masks from number of
1026 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1027 * structure.
1028 *
1029 * These can be overridden with values reported by the kernel either from
1030 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1031 * through the i915 query uapi.
1032 */
1033 static void
1034 fill_masks(struct gen_device_info *devinfo)
1035 {
1036 devinfo->slice_masks = (1U << devinfo->num_slices) - 1;
1037
1038 /* Subslice masks */
1039 unsigned max_subslices = 0;
1040 for (int s = 0; s < devinfo->num_slices; s++)
1041 max_subslices = MAX2(devinfo->num_subslices[s], max_subslices);
1042 devinfo->subslice_slice_stride = DIV_ROUND_UP(max_subslices, 8);
1043
1044 for (int s = 0; s < devinfo->num_slices; s++) {
1045 devinfo->subslice_masks[s * devinfo->subslice_slice_stride] =
1046 (1U << devinfo->num_subslices[s]) - 1;
1047 }
1048
1049 /* EU masks */
1050 devinfo->eu_subslice_stride = DIV_ROUND_UP(devinfo->num_eu_per_subslice, 8);
1051 devinfo->eu_slice_stride = max_subslices * devinfo->eu_subslice_stride;
1052
1053 for (int s = 0; s < devinfo->num_slices; s++) {
1054 for (int ss = 0; ss < devinfo->num_subslices[s]; ss++) {
1055 gen_device_info_set_eu_mask(devinfo, s, ss,
1056 (1U << devinfo->num_eu_per_subslice) - 1);
1057 }
1058 }
1059 }
1060
1061 bool
1062 gen_device_info_update_from_masks(struct gen_device_info *devinfo,
1063 uint32_t slice_mask,
1064 uint32_t subslice_mask,
1065 uint32_t n_eus)
1066 {
1067 struct drm_i915_query_topology_info *topology;
1068
1069 assert((slice_mask & 0xff) == slice_mask);
1070
1071 size_t data_length = 100;
1072
1073 topology = calloc(1, sizeof(*topology) + data_length);
1074 if (!topology)
1075 return false;
1076
1077 topology->max_slices = util_last_bit(slice_mask);
1078 topology->max_subslices = util_last_bit(subslice_mask);
1079
1080 topology->subslice_offset = DIV_ROUND_UP(topology->max_slices, 8);
1081 topology->subslice_stride = DIV_ROUND_UP(topology->max_subslices, 8);
1082
1083 uint32_t n_subslices = __builtin_popcount(slice_mask) *
1084 __builtin_popcount(subslice_mask);
1085 uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1086 uint32_t eu_mask = (1U << num_eu_per_subslice) - 1;
1087
1088 topology->eu_offset = topology->subslice_offset +
1089 DIV_ROUND_UP(topology->max_subslices, 8);
1090 topology->eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8);
1091
1092 /* Set slice mask in topology */
1093 for (int b = 0; b < topology->subslice_offset; b++)
1094 topology->data[b] = (slice_mask >> (b * 8)) & 0xff;
1095
1096 for (int s = 0; s < topology->max_slices; s++) {
1097
1098 /* Set subslice mask in topology */
1099 for (int b = 0; b < topology->subslice_stride; b++) {
1100 int subslice_offset = topology->subslice_offset +
1101 s * topology->subslice_stride + b;
1102
1103 topology->data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff;
1104 }
1105
1106 /* Set eu mask in topology */
1107 for (int ss = 0; ss < topology->max_subslices; ss++) {
1108 for (int b = 0; b < topology->eu_stride; b++) {
1109 int eu_offset = topology->eu_offset +
1110 (s * topology->max_subslices + ss) * topology->eu_stride + b;
1111
1112 topology->data[eu_offset] = (eu_mask >> (b * 8)) & 0xff;
1113 }
1114 }
1115 }
1116
1117 gen_device_info_update_from_topology(devinfo, topology);
1118 free(topology);
1119
1120 return true;
1121 }
1122
1123 static void
1124 reset_masks(struct gen_device_info *devinfo)
1125 {
1126 devinfo->subslice_slice_stride = 0;
1127 devinfo->eu_subslice_stride = 0;
1128 devinfo->eu_slice_stride = 0;
1129
1130 devinfo->num_slices = 0;
1131 devinfo->num_eu_per_subslice = 0;
1132 memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices));
1133
1134 memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
1135 memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
1136 memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
1137 }
1138
1139 void
1140 gen_device_info_update_from_topology(struct gen_device_info *devinfo,
1141 const struct drm_i915_query_topology_info *topology)
1142 {
1143 reset_masks(devinfo);
1144
1145 devinfo->subslice_slice_stride = topology->subslice_stride;
1146
1147 devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8);
1148 devinfo->eu_slice_stride = topology->max_subslices * devinfo->eu_subslice_stride;
1149
1150 assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8));
1151 memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8));
1152 devinfo->num_slices = __builtin_popcount(devinfo->slice_masks);
1153
1154 uint32_t subslice_mask_len =
1155 topology->max_slices * topology->subslice_stride;
1156 assert(sizeof(devinfo->subslice_masks) >= subslice_mask_len);
1157 memcpy(devinfo->subslice_masks, &topology->data[topology->subslice_offset],
1158 subslice_mask_len);
1159
1160 uint32_t n_subslices = 0;
1161 for (int s = 0; s < topology->max_slices; s++) {
1162 if ((devinfo->slice_masks & (1UL << s)) == 0)
1163 continue;
1164
1165 for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
1166 devinfo->num_subslices[s] +=
1167 __builtin_popcount(devinfo->subslice_masks[b]);
1168 }
1169 n_subslices += devinfo->num_subslices[s];
1170 }
1171 assert(n_subslices > 0);
1172
1173 uint32_t eu_mask_len =
1174 topology->eu_stride * topology->max_subslices * topology->max_slices;
1175 assert(sizeof(devinfo->eu_masks) >= eu_mask_len);
1176 memcpy(devinfo->eu_masks, &topology->data[topology->eu_offset], eu_mask_len);
1177
1178 uint32_t n_eus = 0;
1179 for (int b = 0; b < eu_mask_len; b++)
1180 n_eus += __builtin_popcount(devinfo->eu_masks[b]);
1181
1182 devinfo->num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1183 }
1184
1185 bool
1186 gen_get_device_info(int devid, struct gen_device_info *devinfo)
1187 {
1188 switch (devid) {
1189 #undef CHIPSET
1190 #define CHIPSET(id, family, name) \
1191 case id: *devinfo = gen_device_info_##family; break;
1192 #include "pci_ids/i965_pci_ids.h"
1193 default:
1194 fprintf(stderr, "Driver does not support the 0x%x PCI ID.\n", devid);
1195 return false;
1196 }
1197
1198 fill_masks(devinfo);
1199
1200 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1201 *
1202 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1203 * allocate scratch space enough so that each slice has 4 slices allowed."
1204 *
1205 * The equivalent internal documentation says that this programming note
1206 * applies to all Gen9+ platforms.
1207 *
1208 * The hardware typically calculates the scratch space pointer by taking
1209 * the base address, and adding per-thread-scratch-space * thread ID.
1210 * Extra padding can be necessary depending how the thread IDs are
1211 * calculated for a particular shader stage.
1212 */
1213
1214 switch(devinfo->gen) {
1215 case 9:
1216 case 10:
1217 devinfo->max_wm_threads = 64 /* threads-per-PSD */
1218 * devinfo->num_slices
1219 * 4; /* effective subslices per slice */
1220 break;
1221 case 11:
1222 devinfo->max_wm_threads = 128 /* threads-per-PSD */
1223 * devinfo->num_slices
1224 * 8; /* subslices per slice */
1225 break;
1226 default:
1227 break;
1228 }
1229
1230 assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
1231
1232 return true;
1233 }
1234
1235 const char *
1236 gen_get_device_name(int devid)
1237 {
1238 switch (devid) {
1239 #undef CHIPSET
1240 #define CHIPSET(id, family, name) case id: return name;
1241 #include "pci_ids/i965_pci_ids.h"
1242 default:
1243 return NULL;
1244 }
1245 }