src/intel/dev/gen_device_info.h

   1  /*
   2   * Copyright © 2013 Intel Corporation
   3   *
   4   * Permission is hereby granted, free of charge, to any person obtaining a
   5   * copy of this software and associated documentation files (the "Software"),
   6   * to deal in the Software without restriction, including without limitation
   7   * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8   * and/or sell copies of the Software, and to permit persons to whom the
   9   * Software is furnished to do so, subject to the following conditions:
  10   *
  11   * The above copyright notice and this permission notice (including the next
  12   * paragraph) shall be included in all copies or substantial portions of the
  13   * Software.
  14   *
  15   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19   * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20   * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21   * IN THE SOFTWARE.
  22   *
  23   */
  24
  25 #ifndef GEN_DEVICE_INFO_H
  26 #define GEN_DEVICE_INFO_H
  27
  28 #include <stdbool.h>
  29 #include <stdint.h>
  30
  31 #include "util/macros.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 struct drm_i915_query_topology_info;
  38
  39 #define GEN_DEVICE_MAX_SLICES           (6)  /* Maximum on gen10 */
  40 #define GEN_DEVICE_MAX_SUBSLICES        (8)  /* Maximum on gen11 */
  41 #define GEN_DEVICE_MAX_EUS_PER_SUBSLICE (10) /* Maximum on Haswell */
  42 #define GEN_DEVICE_MAX_PIXEL_PIPES      (2)  /* Maximum on gen11 */
  43
  44 /**
  45  * Intel hardware information and quirks
  46  */
  47 struct gen_device_info
  48 {
  49    int gen; /**< Generation number: 4, 5, 6, 7, ... */
  50    int revision;
  51    int gt;
  52
  53    bool is_g4x;
  54    bool is_ivybridge;
  55    bool is_baytrail;
  56    bool is_haswell;
  57    bool is_broadwell;
  58    bool is_cherryview;
  59    bool is_skylake;
  60    bool is_broxton;
  61    bool is_kabylake;
  62    bool is_geminilake;
  63    bool is_coffeelake;
  64    bool is_cannonlake;
  65    bool is_elkhartlake;
  66
  67    bool has_hiz_and_separate_stencil;
  68    bool must_use_separate_stencil;
  69    bool has_sample_with_hiz;
  70    bool has_llc;
  71
  72    bool has_pln;
  73    bool has_64bit_types;
  74    bool has_integer_dword_mul;
  75    bool has_compr4;
  76    bool has_surface_tile_offset;
  77    bool supports_simd16_3src;
  78    bool has_resource_streamer;
  79    bool disable_ccs_repack;
  80    bool has_aux_map;
  81
  82    /**
  83     * \name Intel hardware quirks
  84     *  @{
  85     */
  86    bool has_negative_rhw_bug;
  87
  88    /**
  89     * Some versions of Gen hardware don't do centroid interpolation correctly
  90     * on unlit pixels, causing incorrect values for derivatives near triangle
  91     * edges.  Enabling this flag causes the fragment shader to use
  92     * non-centroid interpolation for unlit pixels, at the expense of two extra
  93     * fragment shader instructions.
  94     */
  95    bool needs_unlit_centroid_workaround;
  96    /** @} */
  97
  98    /**
  99     * \name GPU hardware limits
 100     *
 101     * In general, you can find shader thread maximums by looking at the "Maximum
 102     * Number of Threads" field in the Intel PRM description of the 3DSTATE_VS,
 103     * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
 104     * limits come from the "Number of URB Entries" field in the
 105     * 3DSTATE_URB_VS command and friends.
 106     *
 107     * These fields are used to calculate the scratch space to allocate.  The
 108     * amount of scratch space can be larger without being harmful on modern
 109     * GPUs, however, prior to Haswell, programming the maximum number of threads
 110     * to greater than the hardware maximum would cause GPU performance to tank.
 111     *
 112     *  @{
 113     */
 114    /**
 115     * Total number of slices present on the device whether or not they've been
 116     * fused off.
 117     *
 118     * XXX: CS thread counts are limited by the inability to do cross subslice
 119     * communication. It is the effectively the number of logical threads which
 120     * can be executed in a subslice. Fuse configurations may cause this number
 121     * to change, so we program @max_cs_threads as the lower maximum.
 122     */
 123    unsigned num_slices;
 124
 125    /**
 126     * Number of subslices for each slice (used to be uniform until CNL).
 127     */
 128    unsigned num_subslices[GEN_DEVICE_MAX_SUBSLICES];
 129
 130    /**
 131     * Number of subslices on each pixel pipe (ICL).
 132     */
 133    unsigned ppipe_subslices[GEN_DEVICE_MAX_PIXEL_PIPES];
 134
 135    /**
 136     * Upper bound of number of EU per subslice (some SKUs might have just 1 EU
 137     * fused across all subslices, like 47 EUs, in which case this number won't
 138     * be acurate for one subslice).
 139     */
 140    unsigned num_eu_per_subslice;
 141
 142    /**
 143     * Number of threads per eu, varies between 4 and 8 between generations.
 144     */
 145    unsigned num_thread_per_eu;
 146
 147    /**
 148     * A bit mask of the slices available.
 149     */
 150    uint8_t slice_masks;
 151
 152    /**
 153     * An array of bit mask of the subslices available, use subslice_slice_stride
 154     * to access this array.
 155     */
 156    uint8_t subslice_masks[GEN_DEVICE_MAX_SLICES *
 157                           DIV_ROUND_UP(GEN_DEVICE_MAX_SUBSLICES, 8)];
 158
 159    /**
 160     * An array of bit mask of EUs available, use eu_slice_stride &
 161     * eu_subslice_stride to access this array.
 162     */
 163    uint8_t eu_masks[GEN_DEVICE_MAX_SLICES *
 164                     GEN_DEVICE_MAX_SUBSLICES *
 165                     DIV_ROUND_UP(GEN_DEVICE_MAX_EUS_PER_SUBSLICE, 8)];
 166
 167    /**
 168     * Stride to access subslice_masks[].
 169     */
 170    uint16_t subslice_slice_stride;
 171
 172    /**
 173     * Strides to access eu_masks[].
 174     */
 175    uint16_t eu_slice_stride;
 176    uint16_t eu_subslice_stride;
 177
 178    unsigned l3_banks;
 179    unsigned max_vs_threads;   /**< Maximum Vertex Shader threads */
 180    unsigned max_tcs_threads;  /**< Maximum Hull Shader threads */
 181    unsigned max_tes_threads;  /**< Maximum Domain Shader threads */
 182    unsigned max_gs_threads;   /**< Maximum Geometry Shader threads. */
 183    /**
 184     * Theoretical maximum number of Pixel Shader threads.
 185     *
 186     * PSD means Pixel Shader Dispatcher. On modern Intel GPUs, hardware will
 187     * automatically scale pixel shader thread count, based on a single value
 188     * programmed into 3DSTATE_PS.
 189     *
 190     * To calculate the maximum number of threads for Gen8 beyond (which have
 191     * multiple Pixel Shader Dispatchers):
 192     *
 193     * - Look up 3DSTATE_PS and find "Maximum Number of Threads Per PSD"
 194     * - Usually there's only one PSD per subslice, so use the number of
 195     *   subslices for number of PSDs.
 196     * - For max_wm_threads, the total should be PSD threads * #PSDs.
 197     */
 198    unsigned max_wm_threads;
 199
 200    /**
 201     * Maximum Compute Shader threads.
 202     *
 203     * Thread count * number of EUs per subslice
 204     */
 205    unsigned max_cs_threads;
 206
 207    struct {
 208       /**
 209        * Hardware default URB size.
 210        *
 211        * The units this is expressed in are somewhat inconsistent: 512b units
 212        * on Gen4-5, KB on Gen6-7, and KB times the slice count on Gen8+.
 213        *
 214        * Look up "URB Size" in the "Device Attributes" page, and take the
 215        * maximum.  Look up the slice count for each GT SKU on the same page.
 216        * urb.size = URB Size (kbytes) / slice count
 217        */
 218       unsigned size;
 219
 220       /**
 221        * The minimum number of URB entries.  See the 3DSTATE_URB_<XS> docs.
 222        */
 223       unsigned min_entries[4];
 224
 225       /**
 226        * The maximum number of URB entries.  See the 3DSTATE_URB_<XS> docs.
 227        */
 228       unsigned max_entries[4];
 229    } urb;
 230
 231    /**
 232     * For the longest time the timestamp frequency for Gen's timestamp counter
 233     * could be assumed to be 12.5MHz, where the least significant bit neatly
 234     * corresponded to 80 nanoseconds.
 235     *
 236     * Since Gen9 the numbers aren't so round, with a a frequency of 12MHz for
 237     * SKL (or scale factor of 83.33333333) and a frequency of 19200000Hz for
 238     * BXT.
 239     *
 240     * For simplicty to fit with the current code scaling by a single constant
 241     * to map from raw timestamps to nanoseconds we now do the conversion in
 242     * floating point instead of integer arithmetic.
 243     *
 244     * In general it's probably worth noting that the documented constants we
 245     * have for the per-platform timestamp frequencies aren't perfect and
 246     * shouldn't be trusted for scaling and comparing timestamps with a large
 247     * delta.
 248     *
 249     * E.g. with crude testing on my system using the 'correct' scale factor I'm
 250     * seeing a drift of ~2 milliseconds per second.
 251     */
 252    uint64_t timestamp_frequency;
 253
 254    /**
 255     * ID to put into the .aub files.
 256     */
 257    int simulator_id;
 258
 259    /**
 260     * holds the pci device id
 261     */
 262    uint32_t chipset_id;
 263
 264    /**
 265     * no_hw is true when the chipset_id pci device id has been overridden
 266     */
 267    bool no_hw;
 268    /** @} */
 269 };
 270
 271 #define gen_device_info_is_9lp(devinfo) \
 272    ((devinfo)->is_broxton || (devinfo)->is_geminilake)
 273
 274 static inline bool
 275 gen_device_info_subslice_available(const struct gen_device_info *devinfo,
 276                                    int slice, int subslice)
 277 {
 278    return (devinfo->subslice_masks[slice * devinfo->subslice_slice_stride +
 279                                    subslice / 8] & (1U << (subslice % 8))) != 0;
 280 }
 281
 282 int gen_device_name_to_pci_device_id(const char *name);
 283 const char *gen_get_device_name(int devid);
 284
 285 static inline uint64_t
 286 gen_device_info_timebase_scale(const struct gen_device_info *devinfo,
 287                                uint64_t gpu_timestamp)
 288 {
 289    return (1000000000ull * gpu_timestamp) / devinfo->timestamp_frequency;
 290 }
 291
 292 bool gen_get_device_info_from_fd(int fh, struct gen_device_info *devinfo);
 293 bool gen_get_device_info_from_pci_id(int pci_id,
 294                                      struct gen_device_info *devinfo);
 295
 296 #ifdef __cplusplus
 297 }
 298 #endif
 299
 300 #endif /* GEN_DEVICE_INFO_H */