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25 #ifndef GEN_DEVICE_INFO_H
26 #define GEN_DEVICE_INFO_H
31 #include "util/macros.h"
37 struct drm_i915_query_topology_info
;
39 #define GEN_DEVICE_MAX_SLICES (6) /* Maximum on gen10 */
40 #define GEN_DEVICE_MAX_SUBSLICES (8) /* Maximum on gen11 */
41 #define GEN_DEVICE_MAX_EUS_PER_SUBSLICE (10) /* Maximum on Haswell */
44 * Intel hardware information and quirks
46 struct gen_device_info
48 int gen
; /**< Generation number: 4, 5, 6, 7, ... */
65 bool has_hiz_and_separate_stencil
;
66 bool must_use_separate_stencil
;
67 bool has_sample_with_hiz
;
72 bool has_integer_dword_mul
;
74 bool has_surface_tile_offset
;
75 bool supports_simd16_3src
;
76 bool has_resource_streamer
;
79 * \name Intel hardware quirks
82 bool has_negative_rhw_bug
;
85 * Some versions of Gen hardware don't do centroid interpolation correctly
86 * on unlit pixels, causing incorrect values for derivatives near triangle
87 * edges. Enabling this flag causes the fragment shader to use
88 * non-centroid interpolation for unlit pixels, at the expense of two extra
89 * fragment shader instructions.
91 bool needs_unlit_centroid_workaround
;
95 * \name GPU hardware limits
97 * In general, you can find shader thread maximums by looking at the "Maximum
98 * Number of Threads" field in the Intel PRM description of the 3DSTATE_VS,
99 * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
100 * limits come from the "Number of URB Entries" field in the
101 * 3DSTATE_URB_VS command and friends.
103 * These fields are used to calculate the scratch space to allocate. The
104 * amount of scratch space can be larger without being harmful on modern
105 * GPUs, however, prior to Haswell, programming the maximum number of threads
106 * to greater than the hardware maximum would cause GPU performance to tank.
111 * Total number of slices present on the device whether or not they've been
114 * XXX: CS thread counts are limited by the inability to do cross subslice
115 * communication. It is the effectively the number of logical threads which
116 * can be executed in a subslice. Fuse configurations may cause this number
117 * to change, so we program @max_cs_threads as the lower maximum.
122 * Number of subslices for each slice (used to be uniform until CNL).
124 unsigned num_subslices
[GEN_DEVICE_MAX_SUBSLICES
];
127 * Upper bound of number of EU per subslice (some SKUs might have just 1 EU
128 * fused across all subslices, like 47 EUs, in which case this number won't
129 * be acurate for one subslice).
131 unsigned num_eu_per_subslice
;
134 * Number of threads per eu, varies between 4 and 8 between generations.
136 unsigned num_thread_per_eu
;
139 * A bit mask of the slices available.
144 * An array of bit mask of the subslices available, use subslice_slice_stride
145 * to access this array.
147 uint8_t subslice_masks
[GEN_DEVICE_MAX_SLICES
*
148 DIV_ROUND_UP(GEN_DEVICE_MAX_SUBSLICES
, 8)];
151 * An array of bit mask of EUs available, use eu_slice_stride &
152 * eu_subslice_stride to access this array.
154 uint8_t eu_masks
[GEN_DEVICE_MAX_SLICES
*
155 GEN_DEVICE_MAX_SUBSLICES
*
156 DIV_ROUND_UP(GEN_DEVICE_MAX_EUS_PER_SUBSLICE
, 8)];
159 * Stride to access subslice_masks[].
161 uint16_t subslice_slice_stride
;
164 * Strides to access eu_masks[].
166 uint16_t eu_slice_stride
;
167 uint16_t eu_subslice_stride
;
170 unsigned max_vs_threads
; /**< Maximum Vertex Shader threads */
171 unsigned max_tcs_threads
; /**< Maximum Hull Shader threads */
172 unsigned max_tes_threads
; /**< Maximum Domain Shader threads */
173 unsigned max_gs_threads
; /**< Maximum Geometry Shader threads. */
175 * Theoretical maximum number of Pixel Shader threads.
177 * PSD means Pixel Shader Dispatcher. On modern Intel GPUs, hardware will
178 * automatically scale pixel shader thread count, based on a single value
179 * programmed into 3DSTATE_PS.
181 * To calculate the maximum number of threads for Gen8 beyond (which have
182 * multiple Pixel Shader Dispatchers):
184 * - Look up 3DSTATE_PS and find "Maximum Number of Threads Per PSD"
185 * - Usually there's only one PSD per subslice, so use the number of
186 * subslices for number of PSDs.
187 * - For max_wm_threads, the total should be PSD threads * #PSDs.
189 unsigned max_wm_threads
;
192 * Maximum Compute Shader threads.
194 * Thread count * number of EUs per subslice
196 unsigned max_cs_threads
;
200 * Hardware default URB size.
202 * The units this is expressed in are somewhat inconsistent: 512b units
203 * on Gen4-5, KB on Gen6-7, and KB times the slice count on Gen8+.
205 * Look up "URB Size" in the "Device Attributes" page, and take the
206 * maximum. Look up the slice count for each GT SKU on the same page.
207 * urb.size = URB Size (kbytes) / slice count
212 * The minimum number of URB entries. See the 3DSTATE_URB_<XS> docs.
214 unsigned min_entries
[4];
217 * The maximum number of URB entries. See the 3DSTATE_URB_<XS> docs.
219 unsigned max_entries
[4];
223 * For the longest time the timestamp frequency for Gen's timestamp counter
224 * could be assumed to be 12.5MHz, where the least significant bit neatly
225 * corresponded to 80 nanoseconds.
227 * Since Gen9 the numbers aren't so round, with a a frequency of 12MHz for
228 * SKL (or scale factor of 83.33333333) and a frequency of 19200000Hz for
231 * For simplicty to fit with the current code scaling by a single constant
232 * to map from raw timestamps to nanoseconds we now do the conversion in
233 * floating point instead of integer arithmetic.
235 * In general it's probably worth noting that the documented constants we
236 * have for the per-platform timestamp frequencies aren't perfect and
237 * shouldn't be trusted for scaling and comparing timestamps with a large
240 * E.g. with crude testing on my system using the 'correct' scale factor I'm
241 * seeing a drift of ~2 milliseconds per second.
243 uint64_t timestamp_frequency
;
246 * ID to put into the .aub files.
253 #define gen_device_info_is_9lp(devinfo) \
254 ((devinfo)->is_broxton || (devinfo)->is_geminilake)
257 gen_device_info_subslice_available(const struct gen_device_info
*devinfo
,
258 int slice
, int subslice
)
260 return (devinfo
->subslice_masks
[slice
* devinfo
->subslice_slice_stride
+
261 subslice
/ 8] & (1U << (subslice
% 8))) != 0;
264 int gen_get_pci_device_id_override(void);
265 int gen_device_name_to_pci_device_id(const char *name
);
266 bool gen_get_device_info(int devid
, struct gen_device_info
*devinfo
);
267 const char *gen_get_device_name(int devid
);
269 /* Used with SLICE_MASK/SUBSLICE_MASK values from DRM_I915_GETPARAM. */
270 void gen_device_info_update_from_masks(struct gen_device_info
*devinfo
,
272 uint32_t subslice_mask
,
274 /* Used with DRM_IOCTL_I915_QUERY & DRM_I915_QUERY_TOPOLOGY_INFO. */
275 void gen_device_info_update_from_topology(struct gen_device_info
*devinfo
,
276 const struct drm_i915_query_topology_info
*topology
);
278 static inline uint64_t
279 gen_device_info_timebase_scale(const struct gen_device_info
*devinfo
,
280 uint64_t gpu_timestamp
)
282 return (1000000000ull * gpu_timestamp
) / devinfo
->timestamp_frequency
;
289 #endif /* GEN_DEVICE_INFO_H */