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25 #ifndef GEN_DEVICE_INFO_H
26 #define GEN_DEVICE_INFO_H
31 #include "util/macros.h"
37 struct drm_i915_query_topology_info
;
39 #define GEN_DEVICE_MAX_SLICES (6) /* Maximum on gen10 */
40 #define GEN_DEVICE_MAX_SUBSLICES (8) /* Maximum on gen11 */
41 #define GEN_DEVICE_MAX_EUS_PER_SUBSLICE (10) /* Maximum on Haswell */
42 #define GEN_DEVICE_MAX_PIXEL_PIPES (2) /* Maximum on gen11 */
45 * Intel hardware information and quirks
47 struct gen_device_info
49 int gen
; /**< Generation number: 4, 5, 6, 7, ... */
66 bool has_hiz_and_separate_stencil
;
67 bool must_use_separate_stencil
;
68 bool has_sample_with_hiz
;
73 bool has_integer_dword_mul
;
75 bool has_surface_tile_offset
;
76 bool supports_simd16_3src
;
77 bool has_resource_streamer
;
78 bool disable_ccs_repack
;
82 * \name Intel hardware quirks
85 bool has_negative_rhw_bug
;
88 * Some versions of Gen hardware don't do centroid interpolation correctly
89 * on unlit pixels, causing incorrect values for derivatives near triangle
90 * edges. Enabling this flag causes the fragment shader to use
91 * non-centroid interpolation for unlit pixels, at the expense of two extra
92 * fragment shader instructions.
94 bool needs_unlit_centroid_workaround
;
98 * \name GPU hardware limits
100 * In general, you can find shader thread maximums by looking at the "Maximum
101 * Number of Threads" field in the Intel PRM description of the 3DSTATE_VS,
102 * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
103 * limits come from the "Number of URB Entries" field in the
104 * 3DSTATE_URB_VS command and friends.
106 * These fields are used to calculate the scratch space to allocate. The
107 * amount of scratch space can be larger without being harmful on modern
108 * GPUs, however, prior to Haswell, programming the maximum number of threads
109 * to greater than the hardware maximum would cause GPU performance to tank.
114 * Total number of slices present on the device whether or not they've been
117 * XXX: CS thread counts are limited by the inability to do cross subslice
118 * communication. It is the effectively the number of logical threads which
119 * can be executed in a subslice. Fuse configurations may cause this number
120 * to change, so we program @max_cs_threads as the lower maximum.
125 * Number of subslices for each slice (used to be uniform until CNL).
127 unsigned num_subslices
[GEN_DEVICE_MAX_SUBSLICES
];
130 * Number of subslices on each pixel pipe (ICL).
132 unsigned ppipe_subslices
[GEN_DEVICE_MAX_PIXEL_PIPES
];
135 * Upper bound of number of EU per subslice (some SKUs might have just 1 EU
136 * fused across all subslices, like 47 EUs, in which case this number won't
137 * be acurate for one subslice).
139 unsigned num_eu_per_subslice
;
142 * Number of threads per eu, varies between 4 and 8 between generations.
144 unsigned num_thread_per_eu
;
147 * A bit mask of the slices available.
152 * An array of bit mask of the subslices available, use subslice_slice_stride
153 * to access this array.
155 uint8_t subslice_masks
[GEN_DEVICE_MAX_SLICES
*
156 DIV_ROUND_UP(GEN_DEVICE_MAX_SUBSLICES
, 8)];
159 * An array of bit mask of EUs available, use eu_slice_stride &
160 * eu_subslice_stride to access this array.
162 uint8_t eu_masks
[GEN_DEVICE_MAX_SLICES
*
163 GEN_DEVICE_MAX_SUBSLICES
*
164 DIV_ROUND_UP(GEN_DEVICE_MAX_EUS_PER_SUBSLICE
, 8)];
167 * Stride to access subslice_masks[].
169 uint16_t subslice_slice_stride
;
172 * Strides to access eu_masks[].
174 uint16_t eu_slice_stride
;
175 uint16_t eu_subslice_stride
;
178 unsigned max_vs_threads
; /**< Maximum Vertex Shader threads */
179 unsigned max_tcs_threads
; /**< Maximum Hull Shader threads */
180 unsigned max_tes_threads
; /**< Maximum Domain Shader threads */
181 unsigned max_gs_threads
; /**< Maximum Geometry Shader threads. */
183 * Theoretical maximum number of Pixel Shader threads.
185 * PSD means Pixel Shader Dispatcher. On modern Intel GPUs, hardware will
186 * automatically scale pixel shader thread count, based on a single value
187 * programmed into 3DSTATE_PS.
189 * To calculate the maximum number of threads for Gen8 beyond (which have
190 * multiple Pixel Shader Dispatchers):
192 * - Look up 3DSTATE_PS and find "Maximum Number of Threads Per PSD"
193 * - Usually there's only one PSD per subslice, so use the number of
194 * subslices for number of PSDs.
195 * - For max_wm_threads, the total should be PSD threads * #PSDs.
197 unsigned max_wm_threads
;
200 * Maximum Compute Shader threads.
202 * Thread count * number of EUs per subslice
204 unsigned max_cs_threads
;
208 * Hardware default URB size.
210 * The units this is expressed in are somewhat inconsistent: 512b units
211 * on Gen4-5, KB on Gen6-7, and KB times the slice count on Gen8+.
213 * Look up "URB Size" in the "Device Attributes" page, and take the
214 * maximum. Look up the slice count for each GT SKU on the same page.
215 * urb.size = URB Size (kbytes) / slice count
220 * The minimum number of URB entries. See the 3DSTATE_URB_<XS> docs.
222 unsigned min_entries
[4];
225 * The maximum number of URB entries. See the 3DSTATE_URB_<XS> docs.
227 unsigned max_entries
[4];
231 * For the longest time the timestamp frequency for Gen's timestamp counter
232 * could be assumed to be 12.5MHz, where the least significant bit neatly
233 * corresponded to 80 nanoseconds.
235 * Since Gen9 the numbers aren't so round, with a a frequency of 12MHz for
236 * SKL (or scale factor of 83.33333333) and a frequency of 19200000Hz for
239 * For simplicty to fit with the current code scaling by a single constant
240 * to map from raw timestamps to nanoseconds we now do the conversion in
241 * floating point instead of integer arithmetic.
243 * In general it's probably worth noting that the documented constants we
244 * have for the per-platform timestamp frequencies aren't perfect and
245 * shouldn't be trusted for scaling and comparing timestamps with a large
248 * E.g. with crude testing on my system using the 'correct' scale factor I'm
249 * seeing a drift of ~2 milliseconds per second.
251 uint64_t timestamp_frequency
;
254 * ID to put into the .aub files.
259 * holds the pci device id
264 * no_hw is true when the chipset_id pci device id has been overridden
270 #define gen_device_info_is_9lp(devinfo) \
271 ((devinfo)->is_broxton || (devinfo)->is_geminilake)
274 gen_device_info_subslice_available(const struct gen_device_info
*devinfo
,
275 int slice
, int subslice
)
277 return (devinfo
->subslice_masks
[slice
* devinfo
->subslice_slice_stride
+
278 subslice
/ 8] & (1U << (subslice
% 8))) != 0;
281 int gen_device_name_to_pci_device_id(const char *name
);
282 const char *gen_get_device_name(int devid
);
284 static inline uint64_t
285 gen_device_info_timebase_scale(const struct gen_device_info
*devinfo
,
286 uint64_t gpu_timestamp
)
288 return (1000000000ull * gpu_timestamp
) / devinfo
->timestamp_frequency
;
291 bool gen_get_device_info_from_fd(int fh
, struct gen_device_info
*devinfo
);
292 bool gen_get_device_info_from_pci_id(int pci_id
,
293 struct gen_device_info
*devinfo
);
299 #endif /* GEN_DEVICE_INFO_H */