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25 #ifndef GEN_DEVICE_INFO_H
26 #define GEN_DEVICE_INFO_H
31 #include "util/macros.h"
37 struct drm_i915_query_topology_info
;
39 #define GEN_DEVICE_MAX_SLICES (6) /* Maximum on gen10 */
40 #define GEN_DEVICE_MAX_SUBSLICES (8) /* Maximum on gen11 */
41 #define GEN_DEVICE_MAX_EUS_PER_SUBSLICE (10) /* Maximum on Haswell */
42 #define GEN_DEVICE_MAX_PIXEL_PIPES (2) /* Maximum on gen11 */
45 * Intel hardware information and quirks
47 struct gen_device_info
49 int gen
; /**< Generation number: 4, 5, 6, 7, ... */
67 bool has_hiz_and_separate_stencil
;
68 bool must_use_separate_stencil
;
69 bool has_sample_with_hiz
;
75 bool has_integer_dword_mul
;
77 bool has_surface_tile_offset
;
78 bool supports_simd16_3src
;
79 bool has_resource_streamer
;
80 bool disable_ccs_repack
;
84 * \name Intel hardware quirks
87 bool has_negative_rhw_bug
;
90 * Some versions of Gen hardware don't do centroid interpolation correctly
91 * on unlit pixels, causing incorrect values for derivatives near triangle
92 * edges. Enabling this flag causes the fragment shader to use
93 * non-centroid interpolation for unlit pixels, at the expense of two extra
94 * fragment shader instructions.
96 bool needs_unlit_centroid_workaround
;
100 * \name GPU hardware limits
102 * In general, you can find shader thread maximums by looking at the "Maximum
103 * Number of Threads" field in the Intel PRM description of the 3DSTATE_VS,
104 * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
105 * limits come from the "Number of URB Entries" field in the
106 * 3DSTATE_URB_VS command and friends.
108 * These fields are used to calculate the scratch space to allocate. The
109 * amount of scratch space can be larger without being harmful on modern
110 * GPUs, however, prior to Haswell, programming the maximum number of threads
111 * to greater than the hardware maximum would cause GPU performance to tank.
116 * Total number of slices present on the device whether or not they've been
119 * XXX: CS thread counts are limited by the inability to do cross subslice
120 * communication. It is the effectively the number of logical threads which
121 * can be executed in a subslice. Fuse configurations may cause this number
122 * to change, so we program @max_cs_threads as the lower maximum.
127 * Number of subslices for each slice (used to be uniform until CNL).
129 unsigned num_subslices
[GEN_DEVICE_MAX_SUBSLICES
];
132 * Number of subslices on each pixel pipe (ICL).
134 unsigned ppipe_subslices
[GEN_DEVICE_MAX_PIXEL_PIPES
];
137 * Upper bound of number of EU per subslice (some SKUs might have just 1 EU
138 * fused across all subslices, like 47 EUs, in which case this number won't
139 * be acurate for one subslice).
141 unsigned num_eu_per_subslice
;
144 * Number of threads per eu, varies between 4 and 8 between generations.
146 unsigned num_thread_per_eu
;
149 * A bit mask of the slices available.
154 * An array of bit mask of the subslices available, use subslice_slice_stride
155 * to access this array.
157 uint8_t subslice_masks
[GEN_DEVICE_MAX_SLICES
*
158 DIV_ROUND_UP(GEN_DEVICE_MAX_SUBSLICES
, 8)];
161 * An array of bit mask of EUs available, use eu_slice_stride &
162 * eu_subslice_stride to access this array.
164 uint8_t eu_masks
[GEN_DEVICE_MAX_SLICES
*
165 GEN_DEVICE_MAX_SUBSLICES
*
166 DIV_ROUND_UP(GEN_DEVICE_MAX_EUS_PER_SUBSLICE
, 8)];
169 * Stride to access subslice_masks[].
171 uint16_t subslice_slice_stride
;
174 * Strides to access eu_masks[].
176 uint16_t eu_slice_stride
;
177 uint16_t eu_subslice_stride
;
180 unsigned max_vs_threads
; /**< Maximum Vertex Shader threads */
181 unsigned max_tcs_threads
; /**< Maximum Hull Shader threads */
182 unsigned max_tes_threads
; /**< Maximum Domain Shader threads */
183 unsigned max_gs_threads
; /**< Maximum Geometry Shader threads. */
185 * Theoretical maximum number of Pixel Shader threads.
187 * PSD means Pixel Shader Dispatcher. On modern Intel GPUs, hardware will
188 * automatically scale pixel shader thread count, based on a single value
189 * programmed into 3DSTATE_PS.
191 * To calculate the maximum number of threads for Gen8 beyond (which have
192 * multiple Pixel Shader Dispatchers):
194 * - Look up 3DSTATE_PS and find "Maximum Number of Threads Per PSD"
195 * - Usually there's only one PSD per subslice, so use the number of
196 * subslices for number of PSDs.
197 * - For max_wm_threads, the total should be PSD threads * #PSDs.
199 unsigned max_wm_threads
;
202 * Maximum Compute Shader threads.
204 * Thread count * number of EUs per subslice
206 unsigned max_cs_threads
;
210 * Fixed size of the URB.
212 * On Gen6 and DG1, this is measured in KB. Gen4-5 instead measure
213 * this in 512b blocks, as that's more convenient there.
215 * On most Gen7+ platforms, the URB is a section of the L3 cache,
216 * and can be resized based on the L3 programming. For those platforms,
217 * simply leave this field blank (zero) - it isn't used.
222 * The minimum number of URB entries. See the 3DSTATE_URB_<XS> docs.
224 unsigned min_entries
[4];
227 * The maximum number of URB entries. See the 3DSTATE_URB_<XS> docs.
229 unsigned max_entries
[4];
233 * For the longest time the timestamp frequency for Gen's timestamp counter
234 * could be assumed to be 12.5MHz, where the least significant bit neatly
235 * corresponded to 80 nanoseconds.
237 * Since Gen9 the numbers aren't so round, with a a frequency of 12MHz for
238 * SKL (or scale factor of 83.33333333) and a frequency of 19200000Hz for
241 * For simplicty to fit with the current code scaling by a single constant
242 * to map from raw timestamps to nanoseconds we now do the conversion in
243 * floating point instead of integer arithmetic.
245 * In general it's probably worth noting that the documented constants we
246 * have for the per-platform timestamp frequencies aren't perfect and
247 * shouldn't be trusted for scaling and comparing timestamps with a large
250 * E.g. with crude testing on my system using the 'correct' scale factor I'm
251 * seeing a drift of ~2 milliseconds per second.
253 uint64_t timestamp_frequency
;
256 * ID to put into the .aub files.
261 * holds the pci device id
266 * no_hw is true when the chipset_id pci device id has been overridden
272 #define gen_device_info_is_9lp(devinfo) \
273 ((devinfo)->is_broxton || (devinfo)->is_geminilake)
276 gen_device_info_subslice_available(const struct gen_device_info
*devinfo
,
277 int slice
, int subslice
)
279 return (devinfo
->subslice_masks
[slice
* devinfo
->subslice_slice_stride
+
280 subslice
/ 8] & (1U << (subslice
% 8))) != 0;
283 int gen_device_name_to_pci_device_id(const char *name
);
284 const char *gen_get_device_name(int devid
);
286 static inline uint64_t
287 gen_device_info_timebase_scale(const struct gen_device_info
*devinfo
,
288 uint64_t gpu_timestamp
)
290 return (1000000000ull * gpu_timestamp
) / devinfo
->timestamp_frequency
;
293 bool gen_get_device_info_from_fd(int fh
, struct gen_device_info
*devinfo
);
294 bool gen_get_device_info_from_pci_id(int pci_id
,
295 struct gen_device_info
*devinfo
);
301 #endif /* GEN_DEVICE_INFO_H */