src/intel/dev/gen_device_info.h

   1  /*
   2   * Copyright © 2013 Intel Corporation
   3   *
   4   * Permission is hereby granted, free of charge, to any person obtaining a
   5   * copy of this software and associated documentation files (the "Software"),
   6   * to deal in the Software without restriction, including without limitation
   7   * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8   * and/or sell copies of the Software, and to permit persons to whom the
   9   * Software is furnished to do so, subject to the following conditions:
  10   *
  11   * The above copyright notice and this permission notice (including the next
  12   * paragraph) shall be included in all copies or substantial portions of the
  13   * Software.
  14   *
  15   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19   * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20   * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21   * IN THE SOFTWARE.
  22   *
  23   */
  24
  25 #ifndef GEN_DEVICE_INFO_H
  26 #define GEN_DEVICE_INFO_H
  27
  28 #include <stdbool.h>
  29 #include <stdint.h>
  30
  31 #include "util/macros.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 struct drm_i915_query_topology_info;
  38
  39 #define GEN_DEVICE_MAX_SLICES           (6)  /* Maximum on gen10 */
  40 #define GEN_DEVICE_MAX_SUBSLICES        (8)  /* Maximum on gen11 */
  41 #define GEN_DEVICE_MAX_EUS_PER_SUBSLICE (10) /* Maximum on Haswell */
  42
  43 /**
  44  * Intel hardware information and quirks
  45  */
  46 struct gen_device_info
  47 {
  48    int gen; /**< Generation number: 4, 5, 6, 7, ... */
  49    int gt;
  50
  51    bool is_g4x;
  52    bool is_ivybridge;
  53    bool is_baytrail;
  54    bool is_haswell;
  55    bool is_broadwell;
  56    bool is_cherryview;
  57    bool is_skylake;
  58    bool is_broxton;
  59    bool is_kabylake;
  60    bool is_geminilake;
  61    bool is_coffeelake;
  62    bool is_cannonlake;
  63
  64    bool has_hiz_and_separate_stencil;
  65    bool must_use_separate_stencil;
  66    bool has_sample_with_hiz;
  67    bool has_llc;
  68
  69    bool has_pln;
  70    bool has_64bit_types;
  71    bool has_integer_dword_mul;
  72    bool has_compr4;
  73    bool has_surface_tile_offset;
  74    bool supports_simd16_3src;
  75    bool has_resource_streamer;
  76
  77    /**
  78     * \name Intel hardware quirks
  79     *  @{
  80     */
  81    bool has_negative_rhw_bug;
  82
  83    /**
  84     * Some versions of Gen hardware don't do centroid interpolation correctly
  85     * on unlit pixels, causing incorrect values for derivatives near triangle
  86     * edges.  Enabling this flag causes the fragment shader to use
  87     * non-centroid interpolation for unlit pixels, at the expense of two extra
  88     * fragment shader instructions.
  89     */
  90    bool needs_unlit_centroid_workaround;
  91    /** @} */
  92
  93    /**
  94     * \name GPU hardware limits
  95     *
  96     * In general, you can find shader thread maximums by looking at the "Maximum
  97     * Number of Threads" field in the Intel PRM description of the 3DSTATE_VS,
  98     * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
  99     * limits come from the "Number of URB Entries" field in the
 100     * 3DSTATE_URB_VS command and friends.
 101     *
 102     * These fields are used to calculate the scratch space to allocate.  The
 103     * amount of scratch space can be larger without being harmful on modern
 104     * GPUs, however, prior to Haswell, programming the maximum number of threads
 105     * to greater than the hardware maximum would cause GPU performance to tank.
 106     *
 107     *  @{
 108     */
 109    /**
 110     * Total number of slices present on the device whether or not they've been
 111     * fused off.
 112     *
 113     * XXX: CS thread counts are limited by the inability to do cross subslice
 114     * communication. It is the effectively the number of logical threads which
 115     * can be executed in a subslice. Fuse configurations may cause this number
 116     * to change, so we program @max_cs_threads as the lower maximum.
 117     */
 118    unsigned num_slices;
 119
 120    /**
 121     * Number of subslices for each slice (used to be uniform until CNL).
 122     */
 123    unsigned num_subslices[GEN_DEVICE_MAX_SUBSLICES];
 124
 125    /**
 126     * Upper bound of number of EU per subslice (some SKUs might have just 1 EU
 127     * fused across all subslices, like 47 EUs, in which case this number won't
 128     * be acurate for one subslice).
 129     */
 130    unsigned num_eu_per_subslice;
 131
 132    /**
 133     * Number of threads per eu, varies between 4 and 8 between generations.
 134     */
 135    unsigned num_thread_per_eu;
 136
 137    /**
 138     * A bit mask of the slices available.
 139     */
 140    uint8_t slice_masks;
 141
 142    /**
 143     * An array of bit mask of the subslices available, use subslice_slice_stride
 144     * to access this array.
 145     */
 146    uint8_t subslice_masks[GEN_DEVICE_MAX_SLICES *
 147                           DIV_ROUND_UP(GEN_DEVICE_MAX_SUBSLICES, 8)];
 148
 149    /**
 150     * An array of bit mask of EUs available, use eu_slice_stride &
 151     * eu_subslice_stride to access this array.
 152     */
 153    uint8_t eu_masks[GEN_DEVICE_MAX_SLICES *
 154                     GEN_DEVICE_MAX_SUBSLICES *
 155                     DIV_ROUND_UP(GEN_DEVICE_MAX_EUS_PER_SUBSLICE, 8)];
 156
 157    /**
 158     * Stride to access subslice_masks[].
 159     */
 160    uint16_t subslice_slice_stride;
 161
 162    /**
 163     * Strides to access eu_masks[].
 164     */
 165    uint16_t eu_slice_stride;
 166    uint16_t eu_subslice_stride;
 167
 168    unsigned l3_banks;
 169    unsigned max_vs_threads;   /**< Maximum Vertex Shader threads */
 170    unsigned max_tcs_threads;  /**< Maximum Hull Shader threads */
 171    unsigned max_tes_threads;  /**< Maximum Domain Shader threads */
 172    unsigned max_gs_threads;   /**< Maximum Geometry Shader threads. */
 173    /**
 174     * Theoretical maximum number of Pixel Shader threads.
 175     *
 176     * PSD means Pixel Shader Dispatcher. On modern Intel GPUs, hardware will
 177     * automatically scale pixel shader thread count, based on a single value
 178     * programmed into 3DSTATE_PS.
 179     *
 180     * To calculate the maximum number of threads for Gen8 beyond (which have
 181     * multiple Pixel Shader Dispatchers):
 182     *
 183     * - Look up 3DSTATE_PS and find "Maximum Number of Threads Per PSD"
 184     * - Usually there's only one PSD per subslice, so use the number of
 185     *   subslices for number of PSDs.
 186     * - For max_wm_threads, the total should be PSD threads * #PSDs.
 187     */
 188    unsigned max_wm_threads;
 189
 190    /**
 191     * Maximum Compute Shader threads.
 192     *
 193     * Thread count * number of EUs per subslice
 194     */
 195    unsigned max_cs_threads;
 196
 197    struct {
 198       /**
 199        * Hardware default URB size.
 200        *
 201        * The units this is expressed in are somewhat inconsistent: 512b units
 202        * on Gen4-5, KB on Gen6-7, and KB times the slice count on Gen8+.
 203        *
 204        * Look up "URB Size" in the "Device Attributes" page, and take the
 205        * maximum.  Look up the slice count for each GT SKU on the same page.
 206        * urb.size = URB Size (kbytes) / slice count
 207        */
 208       unsigned size;
 209
 210       /**
 211        * The minimum number of URB entries.  See the 3DSTATE_URB_<XS> docs.
 212        */
 213       unsigned min_entries[4];
 214
 215       /**
 216        * The maximum number of URB entries.  See the 3DSTATE_URB_<XS> docs.
 217        */
 218       unsigned max_entries[4];
 219    } urb;
 220
 221    /**
 222     * For the longest time the timestamp frequency for Gen's timestamp counter
 223     * could be assumed to be 12.5MHz, where the least significant bit neatly
 224     * corresponded to 80 nanoseconds.
 225     *
 226     * Since Gen9 the numbers aren't so round, with a a frequency of 12MHz for
 227     * SKL (or scale factor of 83.33333333) and a frequency of 19200000Hz for
 228     * BXT.
 229     *
 230     * For simplicty to fit with the current code scaling by a single constant
 231     * to map from raw timestamps to nanoseconds we now do the conversion in
 232     * floating point instead of integer arithmetic.
 233     *
 234     * In general it's probably worth noting that the documented constants we
 235     * have for the per-platform timestamp frequencies aren't perfect and
 236     * shouldn't be trusted for scaling and comparing timestamps with a large
 237     * delta.
 238     *
 239     * E.g. with crude testing on my system using the 'correct' scale factor I'm
 240     * seeing a drift of ~2 milliseconds per second.
 241     */
 242    uint64_t timestamp_frequency;
 243
 244    /** @} */
 245 };
 246
 247 #define gen_device_info_is_9lp(devinfo) \
 248    ((devinfo)->is_broxton || (devinfo)->is_geminilake)
 249
 250 int gen_get_pci_device_id_override(void);
 251 int gen_device_name_to_pci_device_id(const char *name);
 252 bool gen_get_device_info(int devid, struct gen_device_info *devinfo);
 253 const char *gen_get_device_name(int devid);
 254
 255 /* Used with SLICE_MASK/SUBSLICE_MASK values from DRM_I915_GETPARAM. */
 256 void gen_device_info_update_from_masks(struct gen_device_info *devinfo,
 257                                        uint32_t slice_mask,
 258                                        uint32_t subslice_mask,
 259                                        uint32_t n_eus);
 260 /* Used with DRM_IOCTL_I915_QUERY & DRM_I915_QUERY_TOPOLOGY_INFO. */
 261 void gen_device_info_update_from_topology(struct gen_device_info *devinfo,
 262                                           const struct drm_i915_query_topology_info *topology);
 263
 264 #ifdef __cplusplus
 265 }
 266 #endif
 267
 268 #endif /* GEN_DEVICE_INFO_H */