2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
36 void PRINTFLIKE(3, 4) UNUSED
37 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
43 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
46 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
50 isl_device_init(struct isl_device
*dev
,
51 const struct gen_device_info
*info
,
52 bool has_bit6_swizzling
)
55 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
56 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
58 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
59 * device properties at buildtime. Verify that the macros with the device
60 * properties chosen during runtime.
62 ISL_DEV_GEN_SANITIZE(dev
);
63 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
65 /* Did we break hiz or stencil? */
66 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
67 assert(info
->has_hiz_and_separate_stencil
);
68 if (info
->must_use_separate_stencil
)
69 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
73 * @brief Query the set of multisamples supported by the device.
75 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
78 isl_sample_count_mask_t ATTRIBUTE_CONST
79 isl_device_get_sample_counts(struct isl_device
*dev
)
81 if (ISL_DEV_GEN(dev
) >= 9) {
82 return ISL_SAMPLE_COUNT_1_BIT
|
83 ISL_SAMPLE_COUNT_2_BIT
|
84 ISL_SAMPLE_COUNT_4_BIT
|
85 ISL_SAMPLE_COUNT_8_BIT
|
86 ISL_SAMPLE_COUNT_16_BIT
;
87 } else if (ISL_DEV_GEN(dev
) >= 8) {
88 return ISL_SAMPLE_COUNT_1_BIT
|
89 ISL_SAMPLE_COUNT_2_BIT
|
90 ISL_SAMPLE_COUNT_4_BIT
|
91 ISL_SAMPLE_COUNT_8_BIT
;
92 } else if (ISL_DEV_GEN(dev
) >= 7) {
93 return ISL_SAMPLE_COUNT_1_BIT
|
94 ISL_SAMPLE_COUNT_4_BIT
|
95 ISL_SAMPLE_COUNT_8_BIT
;
96 } else if (ISL_DEV_GEN(dev
) >= 6) {
97 return ISL_SAMPLE_COUNT_1_BIT
|
98 ISL_SAMPLE_COUNT_4_BIT
;
100 return ISL_SAMPLE_COUNT_1_BIT
;
105 * @param[out] info is written only on success
108 isl_tiling_get_info(const struct isl_device
*dev
,
109 enum isl_tiling tiling
,
111 struct isl_tile_info
*tile_info
)
113 const uint32_t bs
= format_bpb
/ 8;
114 struct isl_extent2d logical_el
, phys_B
;
116 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
117 /* It is possible to have non-power-of-two formats in a tiled buffer.
118 * The easiest way to handle this is to treat the tile as if it is three
119 * times as wide. This way no pixel will ever cross a tile boundary.
120 * This really only works on legacy X and Y tiling formats.
122 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
123 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
124 return isl_tiling_get_info(dev
, tiling
, format_bpb
/ 3, tile_info
);
128 case ISL_TILING_LINEAR
:
130 logical_el
= isl_extent2d(1, 1);
131 phys_B
= isl_extent2d(bs
, 1);
136 logical_el
= isl_extent2d(512 / bs
, 8);
137 phys_B
= isl_extent2d(512, 8);
142 logical_el
= isl_extent2d(128 / bs
, 32);
143 phys_B
= isl_extent2d(128, 32);
148 logical_el
= isl_extent2d(64, 64);
149 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
151 * "If the surface is a stencil buffer (and thus has Tile Mode set
152 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
153 * computed based on width, as the stencil buffer is stored with two
156 * This, together with the fact that stencil buffers are referred to as
157 * being Y-tiled in the PRMs for older hardware implies that the
158 * physical size of a W-tile is actually the same as for a Y-tile.
160 phys_B
= isl_extent2d(128, 32);
164 case ISL_TILING_Ys
: {
165 if (ISL_DEV_GEN(dev
) < 9)
168 if (!isl_is_pow2(bs
))
171 bool is_Ys
= tiling
== ISL_TILING_Ys
;
174 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
175 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
177 logical_el
= isl_extent2d(width
/ bs
, height
);
178 phys_B
= isl_extent2d(width
, height
);
183 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
184 * 128bpb format. The tiling has the same physical dimensions as
185 * Y-tiling but actually has two HiZ columns per Y-tiled column.
188 logical_el
= isl_extent2d(16, 16);
189 phys_B
= isl_extent2d(128, 32);
193 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
194 * have a block size of 1 or 2 bits per block and each CCS element
195 * corresponds to one cache-line pair in the main surface. From the Sky
196 * Lake PRM Vol. 12 in the section on planes:
198 * "The Color Control Surface (CCS) contains the compression status
199 * of the cache-line pairs. The compression state of the cache-line
200 * pair is specified by 2 bits in the CCS. Each CCS cache-line
201 * represents an area on the main surface of 16x16 sets of 128 byte
202 * Y-tiled cache-line-pairs. CCS is always Y tiled."
204 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
205 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
206 * that yields total tile area of 128x128 cache-line pairs or CCS
207 * elements. On older hardware, each CCS element is 1 bit and the tile
208 * is 128x256 elements.
210 assert(format_bpb
== 1 || format_bpb
== 2);
211 logical_el
= isl_extent2d(128, 256 / format_bpb
);
212 phys_B
= isl_extent2d(128, 32);
216 unreachable("not reached");
219 *tile_info
= (struct isl_tile_info
) {
221 .format_bpb
= format_bpb
,
222 .logical_extent_el
= logical_el
,
223 .phys_extent_B
= phys_B
,
230 * @param[out] tiling is set only on success
233 isl_surf_choose_tiling(const struct isl_device
*dev
,
234 const struct isl_surf_init_info
*restrict info
,
235 enum isl_tiling
*tiling
)
237 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
239 if (ISL_DEV_GEN(dev
) >= 6) {
240 gen6_filter_tiling(dev
, info
, &tiling_flags
);
242 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
243 gen6_filter_tiling(dev
, info
, &tiling_flags
);
246 #define CHOOSE(__tiling) \
248 if (tiling_flags & (1u << (__tiling))) { \
249 *tiling = (__tiling); \
254 /* Of the tiling modes remaining, choose the one that offers the best
258 if (info
->dim
== ISL_SURF_DIM_1D
) {
259 /* Prefer linear for 1D surfaces because they do not benefit from
260 * tiling. To the contrary, tiling leads to wasted memory and poor
261 * memory locality due to the swizzling and alignment restrictions
262 * required in tiled surfaces.
264 CHOOSE(ISL_TILING_LINEAR
);
267 CHOOSE(ISL_TILING_CCS
);
268 CHOOSE(ISL_TILING_HIZ
);
269 CHOOSE(ISL_TILING_Ys
);
270 CHOOSE(ISL_TILING_Yf
);
271 CHOOSE(ISL_TILING_Y0
);
272 CHOOSE(ISL_TILING_X
);
273 CHOOSE(ISL_TILING_W
);
274 CHOOSE(ISL_TILING_LINEAR
);
278 /* No tiling mode accomodates the inputs. */
283 isl_choose_msaa_layout(const struct isl_device
*dev
,
284 const struct isl_surf_init_info
*info
,
285 enum isl_tiling tiling
,
286 enum isl_msaa_layout
*msaa_layout
)
288 if (ISL_DEV_GEN(dev
) >= 8) {
289 return gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
290 } else if (ISL_DEV_GEN(dev
) >= 7) {
291 return gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
292 } else if (ISL_DEV_GEN(dev
) >= 6) {
293 return gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
295 return gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
300 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
302 assert(isl_is_pow2(samples
));
304 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
307 * If the surface is multisampled and it is a depth or stencil surface
308 * or Multisampled Surface StorageFormat in SURFACE_STATE is
309 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
312 return (struct isl_extent2d
) {
313 .width
= 1 << ((ffs(samples
) - 0) / 2),
314 .height
= 1 << ((ffs(samples
) - 1) / 2),
319 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
320 uint32_t *width
, uint32_t *height
)
322 const struct isl_extent2d px_size_sa
=
323 isl_get_interleaved_msaa_px_size_sa(samples
);
326 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
328 *height
= isl_align(*height
, 2) * px_size_sa
.width
;
331 static enum isl_array_pitch_span
332 isl_choose_array_pitch_span(const struct isl_device
*dev
,
333 const struct isl_surf_init_info
*restrict info
,
334 enum isl_dim_layout dim_layout
,
335 const struct isl_extent4d
*phys_level0_sa
)
337 switch (dim_layout
) {
338 case ISL_DIM_LAYOUT_GEN9_1D
:
339 case ISL_DIM_LAYOUT_GEN4_2D
:
340 if (ISL_DEV_GEN(dev
) >= 8) {
341 /* QPitch becomes programmable in Broadwell. So choose the
342 * most compact QPitch possible in order to conserve memory.
344 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
345 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
347 * - Software must ensure that this field is set to a value
348 * sufficiently large such that the array slices in the surface
349 * do not overlap. Refer to the Memory Data Formats section for
350 * information on how surfaces are stored in memory.
352 * - This field specifies the distance in rows between array
353 * slices. It is used only in the following cases:
355 * - Surface Array is enabled OR
356 * - Number of Mulitsamples is not NUMSAMPLES_1 and
357 * Multisampled Surface Storage Format set to MSFMT_MSS OR
358 * - Surface Type is SURFTYPE_CUBE
360 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
361 } else if (ISL_DEV_GEN(dev
) >= 7) {
362 /* Note that Ivybridge introduces
363 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
364 * driver more control over the QPitch.
367 if (phys_level0_sa
->array_len
== 1) {
368 /* The hardware will never use the QPitch. So choose the most
369 * compact QPitch possible in order to conserve memory.
371 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
374 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
375 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
376 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
377 * Section 6.18.4.7: Surface Arrays (p112):
379 * If Surface Array Spacing is set to ARYSPC_FULL (note that
380 * the depth buffer and stencil buffer have an implied value of
383 return ISL_ARRAY_PITCH_SPAN_FULL
;
386 if (info
->levels
== 1) {
387 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
390 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
393 return ISL_ARRAY_PITCH_SPAN_FULL
;
394 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
395 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
396 isl_surf_usage_is_stencil(info
->usage
)) {
397 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
398 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
400 * The separate stencil buffer does not support mip mapping, thus
401 * the storage for LODs other than LOD 0 is not needed.
403 assert(info
->levels
== 1);
404 assert(phys_level0_sa
->array_len
== 1);
405 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
407 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
408 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
409 isl_surf_usage_is_stencil(info
->usage
)) {
410 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
411 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
413 * The separate stencil buffer does not support mip mapping,
414 * thus the storage for LODs other than LOD 0 is not needed.
416 assert(info
->levels
== 1);
417 assert(phys_level0_sa
->array_len
== 1);
418 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
421 if (phys_level0_sa
->array_len
== 1) {
422 /* The hardware will never use the QPitch. So choose the most
423 * compact QPitch possible in order to conserve memory.
425 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
428 return ISL_ARRAY_PITCH_SPAN_FULL
;
431 case ISL_DIM_LAYOUT_GEN4_3D
:
432 /* The hardware will never use the QPitch. So choose the most
433 * compact QPitch possible in order to conserve memory.
435 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
438 unreachable("bad isl_dim_layout");
439 return ISL_ARRAY_PITCH_SPAN_FULL
;
443 isl_choose_image_alignment_el(const struct isl_device
*dev
,
444 const struct isl_surf_init_info
*restrict info
,
445 enum isl_tiling tiling
,
446 enum isl_dim_layout dim_layout
,
447 enum isl_msaa_layout msaa_layout
,
448 struct isl_extent3d
*image_align_el
)
450 if (info
->format
== ISL_FORMAT_HIZ
) {
451 assert(ISL_DEV_GEN(dev
) >= 6);
452 /* HiZ surfaces are always aligned to 16x8 pixels in the primary surface
453 * which works out to 2x2 HiZ elments.
455 *image_align_el
= isl_extent3d(2, 2, 1);
459 if (ISL_DEV_GEN(dev
) >= 9) {
460 gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
461 msaa_layout
, image_align_el
);
462 } else if (ISL_DEV_GEN(dev
) >= 8) {
463 gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
464 msaa_layout
, image_align_el
);
465 } else if (ISL_DEV_GEN(dev
) >= 7) {
466 gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
467 msaa_layout
, image_align_el
);
468 } else if (ISL_DEV_GEN(dev
) >= 6) {
469 gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
470 msaa_layout
, image_align_el
);
472 gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
473 msaa_layout
, image_align_el
);
477 static enum isl_dim_layout
478 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
479 enum isl_surf_dim logical_dim
,
480 enum isl_tiling tiling
)
482 if (ISL_DEV_GEN(dev
) >= 9) {
483 switch (logical_dim
) {
484 case ISL_SURF_DIM_1D
:
485 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
487 * One-dimensional surfaces use a tiling mode of linear.
488 * Technically, they are not tiled resources, but the Tiled
489 * Resource Mode field in RENDER_SURFACE_STATE is still used to
490 * indicate the alignment requirements for this linear surface
491 * (See 1D Alignment requirements for how 4K and 64KB Tiled
492 * Resource Modes impact alignment). Alternatively, a 1D surface
493 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
496 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
497 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
499 if (tiling
== ISL_TILING_LINEAR
)
500 return ISL_DIM_LAYOUT_GEN9_1D
;
502 return ISL_DIM_LAYOUT_GEN4_2D
;
503 case ISL_SURF_DIM_2D
:
504 case ISL_SURF_DIM_3D
:
505 return ISL_DIM_LAYOUT_GEN4_2D
;
508 switch (logical_dim
) {
509 case ISL_SURF_DIM_1D
:
510 case ISL_SURF_DIM_2D
:
511 return ISL_DIM_LAYOUT_GEN4_2D
;
512 case ISL_SURF_DIM_3D
:
513 return ISL_DIM_LAYOUT_GEN4_3D
;
517 unreachable("bad isl_surf_dim");
518 return ISL_DIM_LAYOUT_GEN4_2D
;
522 * Calculate the physical extent of the surface's first level, in units of
523 * surface samples. The result is aligned to the format's compression block.
526 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
527 const struct isl_surf_init_info
*restrict info
,
528 enum isl_dim_layout dim_layout
,
529 enum isl_tiling tiling
,
530 enum isl_msaa_layout msaa_layout
,
531 struct isl_extent4d
*phys_level0_sa
)
533 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
535 if (isl_format_is_yuv(info
->format
))
536 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
539 case ISL_SURF_DIM_1D
:
540 assert(info
->height
== 1);
541 assert(info
->depth
== 1);
542 assert(info
->samples
== 1);
543 assert(!isl_format_is_compressed(info
->format
));
545 switch (dim_layout
) {
546 case ISL_DIM_LAYOUT_GEN4_3D
:
547 unreachable("bad isl_dim_layout");
549 case ISL_DIM_LAYOUT_GEN9_1D
:
550 case ISL_DIM_LAYOUT_GEN4_2D
:
551 *phys_level0_sa
= (struct isl_extent4d
) {
555 .a
= info
->array_len
,
561 case ISL_SURF_DIM_2D
:
562 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
564 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
565 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
567 switch (msaa_layout
) {
568 case ISL_MSAA_LAYOUT_NONE
:
569 assert(info
->depth
== 1);
570 assert(info
->samples
== 1);
572 *phys_level0_sa
= (struct isl_extent4d
) {
573 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
574 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
576 .a
= info
->array_len
,
580 case ISL_MSAA_LAYOUT_ARRAY
:
581 assert(info
->depth
== 1);
582 assert(info
->levels
== 1);
583 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
584 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
586 *phys_level0_sa
= (struct isl_extent4d
) {
590 .a
= info
->array_len
* info
->samples
,
594 case ISL_MSAA_LAYOUT_INTERLEAVED
:
595 assert(info
->depth
== 1);
596 assert(info
->levels
== 1);
597 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
598 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
600 *phys_level0_sa
= (struct isl_extent4d
) {
604 .a
= info
->array_len
,
607 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
614 case ISL_SURF_DIM_3D
:
615 assert(info
->array_len
== 1);
616 assert(info
->samples
== 1);
619 isl_finishme("%s:%s: compression block with depth > 1",
623 switch (dim_layout
) {
624 case ISL_DIM_LAYOUT_GEN9_1D
:
625 unreachable("bad isl_dim_layout");
627 case ISL_DIM_LAYOUT_GEN4_2D
:
628 assert(ISL_DEV_GEN(dev
) >= 9);
630 *phys_level0_sa
= (struct isl_extent4d
) {
631 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
632 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
638 case ISL_DIM_LAYOUT_GEN4_3D
:
639 assert(ISL_DEV_GEN(dev
) < 9);
640 *phys_level0_sa
= (struct isl_extent4d
) {
641 .w
= isl_align(info
->width
, fmtl
->bw
),
642 .h
= isl_align(info
->height
, fmtl
->bh
),
653 * A variant of isl_calc_phys_slice0_extent_sa() specific to
654 * ISL_DIM_LAYOUT_GEN4_2D.
657 isl_calc_phys_slice0_extent_sa_gen4_2d(
658 const struct isl_device
*dev
,
659 const struct isl_surf_init_info
*restrict info
,
660 enum isl_msaa_layout msaa_layout
,
661 const struct isl_extent3d
*image_align_sa
,
662 const struct isl_extent4d
*phys_level0_sa
,
663 struct isl_extent2d
*phys_slice0_sa
)
665 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
667 assert(phys_level0_sa
->depth
== 1);
669 if (info
->levels
== 1) {
670 /* Do not pad the surface to the image alignment. Instead, pad it only
671 * to the pixel format's block alignment.
673 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
674 * cycles on the below mipmap layout caluclations. Reducing the
675 * alignment here is safe because we later align the row pitch and array
676 * pitch to the tile boundary. It is safe even for
677 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
678 * to accomodate the interleaved samples.
680 * For linear surfaces, reducing the alignment here permits us to later
681 * choose an arbitrary, non-aligned row pitch. If the surface backs
682 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
683 * VkBufferImageCopy::bufferRowLength.
685 *phys_slice0_sa
= (struct isl_extent2d
) {
686 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
687 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
692 uint32_t slice_top_w
= 0;
693 uint32_t slice_bottom_w
= 0;
694 uint32_t slice_left_h
= 0;
695 uint32_t slice_right_h
= 0;
697 uint32_t W0
= phys_level0_sa
->w
;
698 uint32_t H0
= phys_level0_sa
->h
;
700 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
701 uint32_t W
= isl_minify(W0
, l
);
702 uint32_t H
= isl_minify(H0
, l
);
704 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
705 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
722 *phys_slice0_sa
= (struct isl_extent2d
) {
723 .w
= MAX(slice_top_w
, slice_bottom_w
),
724 .h
= MAX(slice_left_h
, slice_right_h
),
729 * A variant of isl_calc_phys_slice0_extent_sa() specific to
730 * ISL_DIM_LAYOUT_GEN4_3D.
733 isl_calc_phys_slice0_extent_sa_gen4_3d(
734 const struct isl_device
*dev
,
735 const struct isl_surf_init_info
*restrict info
,
736 const struct isl_extent3d
*image_align_sa
,
737 const struct isl_extent4d
*phys_level0_sa
,
738 struct isl_extent2d
*phys_slice0_sa
)
740 assert(info
->samples
== 1);
741 assert(phys_level0_sa
->array_len
== 1);
743 uint32_t slice_w
= 0;
744 uint32_t slice_h
= 0;
746 uint32_t W0
= phys_level0_sa
->w
;
747 uint32_t H0
= phys_level0_sa
->h
;
748 uint32_t D0
= phys_level0_sa
->d
;
750 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
751 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
752 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
753 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
755 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
756 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
758 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
759 slice_h
+= level_h
* max_layers_vert
;
762 *phys_slice0_sa
= (struct isl_extent2d
) {
769 * A variant of isl_calc_phys_slice0_extent_sa() specific to
770 * ISL_DIM_LAYOUT_GEN9_1D.
773 isl_calc_phys_slice0_extent_sa_gen9_1d(
774 const struct isl_device
*dev
,
775 const struct isl_surf_init_info
*restrict info
,
776 const struct isl_extent3d
*image_align_sa
,
777 const struct isl_extent4d
*phys_level0_sa
,
778 struct isl_extent2d
*phys_slice0_sa
)
780 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
782 assert(phys_level0_sa
->height
== 1);
783 assert(phys_level0_sa
->depth
== 1);
784 assert(info
->samples
== 1);
785 assert(image_align_sa
->w
>= fmtl
->bw
);
787 uint32_t slice_w
= 0;
788 const uint32_t W0
= phys_level0_sa
->w
;
790 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
791 uint32_t W
= isl_minify(W0
, l
);
792 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
797 *phys_slice0_sa
= isl_extent2d(slice_w
, 1);
801 * Calculate the physical extent of the surface's first array slice, in units
802 * of surface samples. If the surface is multi-leveled, then the result will
803 * be aligned to \a image_align_sa.
806 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
807 const struct isl_surf_init_info
*restrict info
,
808 enum isl_dim_layout dim_layout
,
809 enum isl_msaa_layout msaa_layout
,
810 const struct isl_extent3d
*image_align_sa
,
811 const struct isl_extent4d
*phys_level0_sa
,
812 struct isl_extent2d
*phys_slice0_sa
)
814 switch (dim_layout
) {
815 case ISL_DIM_LAYOUT_GEN9_1D
:
816 isl_calc_phys_slice0_extent_sa_gen9_1d(dev
, info
,
817 image_align_sa
, phys_level0_sa
,
820 case ISL_DIM_LAYOUT_GEN4_2D
:
821 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
822 image_align_sa
, phys_level0_sa
,
825 case ISL_DIM_LAYOUT_GEN4_3D
:
826 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
827 phys_level0_sa
, phys_slice0_sa
);
833 * Calculate the pitch between physical array slices, in units of rows of
837 isl_calc_array_pitch_el_rows(const struct isl_device
*dev
,
838 const struct isl_surf_init_info
*restrict info
,
839 const struct isl_tile_info
*tile_info
,
840 enum isl_dim_layout dim_layout
,
841 enum isl_array_pitch_span array_pitch_span
,
842 const struct isl_extent3d
*image_align_sa
,
843 const struct isl_extent4d
*phys_level0_sa
,
844 const struct isl_extent2d
*phys_slice0_sa
)
846 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
847 uint32_t pitch_sa_rows
= 0;
849 switch (dim_layout
) {
850 case ISL_DIM_LAYOUT_GEN9_1D
:
851 /* Each row is an array slice */
854 case ISL_DIM_LAYOUT_GEN4_2D
:
855 switch (array_pitch_span
) {
856 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
857 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
859 case ISL_ARRAY_PITCH_SPAN_FULL
: {
860 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
861 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
862 * Surfaces >> Surface Arrays.
864 uint32_t H0_sa
= phys_level0_sa
->h
;
865 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
867 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
868 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
871 if (ISL_DEV_GEN(dev
) >= 7) {
872 /* The QPitch equation changed slightly in Ivybridge. */
878 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
880 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
881 (info
->height
% 4 == 1)) {
882 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
883 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
885 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
886 * the value calculated in the equation above , for every
887 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
889 * XXX(chadv): Is the errata natural corollary of the physical
890 * layout of interleaved samples?
895 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
900 case ISL_DIM_LAYOUT_GEN4_3D
:
901 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
902 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
905 unreachable("bad isl_dim_layout");
909 assert(pitch_sa_rows
% fmtl
->bh
== 0);
910 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
912 if (ISL_DEV_GEN(dev
) >= 9 && fmtl
->txc
== ISL_TXC_CCS
) {
914 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
916 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
917 * layout with these alignments in the RT space: Horizontal
918 * Alignment = 128 and Vertical Alignment = 64."
920 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
922 * "For non-multisampled render target's CCS auxiliary surface,
923 * QPitch must be computed with Horizontal Alignment = 128 and
924 * Surface Vertical Alignment = 256. These alignments are only for
925 * CCS buffer and not for associated render target."
927 * The first restriction is already handled by isl_choose_image_alignment_el
928 * but the second restriction, which is an extension of the first, only
929 * applies to qpitch and must be applied here.
931 assert(fmtl
->bh
== 4);
932 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
935 if (ISL_DEV_GEN(dev
) >= 9 &&
936 info
->dim
== ISL_SURF_DIM_3D
&&
937 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
938 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
940 * Tile Mode != Linear: This field must be set to an integer multiple
943 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
946 return pitch_el_rows
;
950 * Calculate the pitch of each surface row, in bytes.
953 isl_calc_linear_row_pitch(const struct isl_device
*dev
,
954 const struct isl_surf_init_info
*restrict info
,
955 const struct isl_extent2d
*phys_slice0_sa
)
957 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
959 uint32_t row_pitch
= info
->min_pitch
;
961 /* First, align the surface to a cache line boundary, as the PRM explains
964 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
965 * Formats >> Surface Padding Requirements >> Render Target and Media
968 * The data port accesses data (pixels) outside of the surface if they
969 * are contained in the same cache request as pixels that are within the
970 * surface. These pixels will not be returned by the requesting message,
971 * however if these pixels lie outside of defined pages in the GTT,
972 * a GTT error will result when the cache request is processed. In order
973 * to avoid these GTT errors, “padding” at the bottom of the surface is
974 * sometimes necessary.
976 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
977 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
979 * The sampling engine accesses texels outside of the surface if they
980 * are contained in the same cache line as texels that are within the
981 * surface. These texels will not participate in any calculation
982 * performed by the sampling engine and will not affect the result of
983 * any sampling engine operation, however if these texels lie outside of
984 * defined pages in the GTT, a GTT error will result when the cache line
985 * is accessed. In order to avoid these GTT errors, “padding” at the
986 * bottom and right side of a sampling engine surface is sometimes
989 * It is possible that a cache line will straddle a page boundary if the
990 * base address or pitch is not aligned. All pages included in the cache
991 * lines that are part of the surface must map to valid GTT entries to
992 * avoid errors. To determine the necessary padding on the bottom and
993 * right side of the surface, refer to the table in Alignment Unit Size
994 * section for the i and j parameters for the surface format in use. The
995 * surface must then be extended to the next multiple of the alignment
996 * unit size in each dimension, and all texels contained in this
997 * extended surface must have valid GTT entries.
999 * For example, suppose the surface size is 15 texels by 10 texels and
1000 * the alignment parameters are i=4 and j=2. In this case, the extended
1001 * surface would be 16 by 10. Note that these calculations are done in
1002 * texels, and must be converted to bytes based on the surface format
1003 * being used to determine whether additional pages need to be defined.
1005 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
1006 const uint32_t bs
= fmtl
->bpb
/ 8;
1007 row_pitch
= MAX(row_pitch
, bs
* (phys_slice0_sa
->w
/ fmtl
->bw
));
1009 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1010 * RENDER_SURFACE_STATE Surface Pitch (p349):
1012 * - For linear render target surfaces and surfaces accessed with the
1013 * typed data port messages, the pitch must be a multiple of the
1014 * element size for non-YUV surface formats. Pitch must be
1015 * a multiple of 2 * element size for YUV surface formats.
1017 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1018 * ignore because isl doesn't do buffers.]
1020 * - For other linear surfaces, the pitch can be any multiple of
1023 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1024 if (isl_format_is_yuv(info
->format
)) {
1025 row_pitch
= isl_align_npot(row_pitch
, 2 * bs
);
1027 row_pitch
= isl_align_npot(row_pitch
, bs
);
1035 * Calculate and apply any padding required for the surface.
1037 * @param[inout] total_h_el is updated with the new height
1038 * @param[out] pad_bytes is overwritten with additional padding requirements.
1041 isl_apply_surface_padding(const struct isl_device
*dev
,
1042 const struct isl_surf_init_info
*restrict info
,
1043 const struct isl_tile_info
*tile_info
,
1044 uint32_t *total_h_el
,
1045 uint32_t *pad_bytes
)
1047 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1051 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1052 * Formats >> Surface Padding Requirements >> Render Target and Media
1055 * The data port accesses data (pixels) outside of the surface if they
1056 * are contained in the same cache request as pixels that are within the
1057 * surface. These pixels will not be returned by the requesting message,
1058 * however if these pixels lie outside of defined pages in the GTT,
1059 * a GTT error will result when the cache request is processed. In
1060 * order to avoid these GTT errors, “padding” at the bottom of the
1061 * surface is sometimes necessary.
1063 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1064 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
1066 * ... Lots of padding requirements, all listed separately below.
1069 /* We can safely ignore the first padding requirement, quoted below,
1070 * because isl doesn't do buffers.
1072 * - [pre-BDW] For buffers, which have no inherent “height,” padding
1073 * requirements are different. A buffer must be padded to the next
1074 * multiple of 256 array elements, with an additional 16 bytes added
1075 * beyond that to account for the L1 cache line.
1079 * - For compressed textures [...], padding at the bottom of the surface
1080 * is to an even compressed row.
1082 if (isl_format_is_compressed(info
->format
))
1083 *total_h_el
= isl_align(*total_h_el
, 2);
1086 * - For cube surfaces, an additional two rows of padding are required
1087 * at the bottom of the surface.
1089 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
1093 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
1094 * additional padding is required. These surfaces require an extra row
1095 * plus 16 bytes of padding at the bottom in addition to the general
1096 * padding requirements.
1098 if (isl_format_is_yuv(info
->format
) &&
1099 (fmtl
->bpb
== 96 || fmtl
->bpb
== 48|| fmtl
->bpb
== 24)) {
1105 * - For linear surfaces, additional padding of 64 bytes is required at
1106 * the bottom of the surface. This is in addition to the padding
1109 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
1112 /* The below text weakens, not strengthens, the padding requirements for
1113 * linear surfaces. Therefore we can safely ignore it.
1115 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
1116 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
1117 * padding requirement is to the next aligned 64-byte boundary beyond
1118 * the end of the surface. The rest of the padding requirements
1119 * documented above do not apply to these surfaces.
1123 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
1124 * height % 4 != 0, the surface must be padded with
1125 * 4-(height % 4)*Surface Pitch # of bytes.
1127 if (ISL_DEV_GEN(dev
) >= 9 &&
1128 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1129 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1130 *total_h_el
= isl_align(*total_h_el
, 4);
1134 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1135 * to 4 times the Surface Pitch # of bytes
1137 if (ISL_DEV_GEN(dev
) >= 9 &&
1138 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1139 info
->dim
== ISL_SURF_DIM_1D
) {
1145 isl_surf_init_s(const struct isl_device
*dev
,
1146 struct isl_surf
*surf
,
1147 const struct isl_surf_init_info
*restrict info
)
1149 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1151 const struct isl_extent4d logical_level0_px
= {
1155 .a
= info
->array_len
,
1158 enum isl_tiling tiling
;
1159 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1162 struct isl_tile_info tile_info
;
1163 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bpb
, &tile_info
))
1166 const enum isl_dim_layout dim_layout
=
1167 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
);
1169 enum isl_msaa_layout msaa_layout
;
1170 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1173 struct isl_extent3d image_align_el
;
1174 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1177 struct isl_extent3d image_align_sa
=
1178 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1180 struct isl_extent4d phys_level0_sa
;
1181 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1183 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1184 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1186 enum isl_array_pitch_span array_pitch_span
=
1187 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1189 struct isl_extent2d phys_slice0_sa
;
1190 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1191 &image_align_sa
, &phys_level0_sa
,
1193 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1194 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1196 const uint32_t array_pitch_el_rows
=
1197 isl_calc_array_pitch_el_rows(dev
, info
, &tile_info
, dim_layout
,
1198 array_pitch_span
, &image_align_sa
,
1199 &phys_level0_sa
, &phys_slice0_sa
);
1201 uint32_t total_h_el
= phys_level0_sa
.array_len
* array_pitch_el_rows
;
1204 isl_apply_surface_padding(dev
, info
, &tile_info
, &total_h_el
, &pad_bytes
);
1206 uint32_t row_pitch
, size
, base_alignment
;
1207 if (tiling
== ISL_TILING_LINEAR
) {
1208 row_pitch
= isl_calc_linear_row_pitch(dev
, info
, &phys_slice0_sa
);
1209 size
= row_pitch
* total_h_el
+ pad_bytes
;
1211 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1213 * "The Base Address for linear render target surfaces and surfaces
1214 * accessed with the typed surface read/write data port messages must
1215 * be element-size aligned, for non-YUV surface formats, or a
1216 * multiple of 2 element-sizes for YUV surface formats. Other linear
1217 * surfaces have no alignment requirements (byte alignment is
1220 base_alignment
= MAX(1, info
->min_alignment
);
1221 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1222 if (isl_format_is_yuv(info
->format
)) {
1223 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 4);
1225 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 8);
1228 base_alignment
= isl_round_up_to_power_of_two(base_alignment
);
1230 assert(fmtl
->bpb
% tile_info
.format_bpb
== 0);
1231 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
.format_bpb
;
1233 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1234 const uint32_t total_w_el
= phys_slice0_sa
.width
/ fmtl
->bw
;
1235 const uint32_t total_w_tl
=
1236 isl_align_div(total_w_el
* tile_el_scale
,
1237 tile_info
.logical_extent_el
.width
);
1239 row_pitch
= total_w_tl
* tile_info
.phys_extent_B
.width
;
1240 if (row_pitch
< info
->min_pitch
) {
1241 row_pitch
= isl_align_npot(info
->min_pitch
,
1242 tile_info
.phys_extent_B
.width
);
1245 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1246 const uint32_t total_h_tl
=
1247 isl_align_div(total_h_el
, tile_info
.logical_extent_el
.height
);
1249 size
= total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch
;
1251 const uint32_t tile_size
= tile_info
.phys_extent_B
.width
*
1252 tile_info
.phys_extent_B
.height
;
1253 assert(isl_is_pow2(info
->min_alignment
) && isl_is_pow2(tile_size
));
1254 base_alignment
= MAX(info
->min_alignment
, tile_size
);
1257 *surf
= (struct isl_surf
) {
1259 .dim_layout
= dim_layout
,
1260 .msaa_layout
= msaa_layout
,
1262 .format
= info
->format
,
1264 .levels
= info
->levels
,
1265 .samples
= info
->samples
,
1267 .image_alignment_el
= image_align_el
,
1268 .logical_level0_px
= logical_level0_px
,
1269 .phys_level0_sa
= phys_level0_sa
,
1272 .alignment
= base_alignment
,
1273 .row_pitch
= row_pitch
,
1274 .array_pitch_el_rows
= array_pitch_el_rows
,
1275 .array_pitch_span
= array_pitch_span
,
1277 .usage
= info
->usage
,
1284 isl_surf_get_tile_info(const struct isl_device
*dev
,
1285 const struct isl_surf
*surf
,
1286 struct isl_tile_info
*tile_info
)
1288 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1289 isl_tiling_get_info(dev
, surf
->tiling
, fmtl
->bpb
, tile_info
);
1293 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1294 const struct isl_surf
*surf
,
1295 struct isl_surf
*hiz_surf
)
1297 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1299 /* Multisampled depth is always interleaved */
1300 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1301 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1303 isl_surf_init(dev
, hiz_surf
,
1304 .dim
= ISL_SURF_DIM_2D
,
1305 .format
= ISL_FORMAT_HIZ
,
1306 .width
= surf
->logical_level0_px
.width
,
1307 .height
= surf
->logical_level0_px
.height
,
1309 .levels
= surf
->levels
,
1310 .array_len
= surf
->logical_level0_px
.array_len
,
1311 /* On SKL+, HiZ is always single-sampled */
1312 .samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
,
1313 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1314 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1318 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1319 const struct isl_surf
*surf
,
1320 struct isl_surf
*mcs_surf
)
1322 /* It must be multisampled with an array layout */
1323 assert(surf
->samples
> 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1325 /* The following are true of all multisampled surfaces */
1326 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1327 assert(surf
->levels
== 1);
1328 assert(surf
->logical_level0_px
.depth
== 1);
1330 enum isl_format mcs_format
;
1331 switch (surf
->samples
) {
1332 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1333 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1334 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1335 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1337 unreachable("Invalid sample count");
1340 isl_surf_init(dev
, mcs_surf
,
1341 .dim
= ISL_SURF_DIM_2D
,
1342 .format
= mcs_format
,
1343 .width
= surf
->logical_level0_px
.width
,
1344 .height
= surf
->logical_level0_px
.height
,
1347 .array_len
= surf
->logical_level0_px
.array_len
,
1348 .samples
= 1, /* MCS surfaces are really single-sampled */
1349 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1350 .tiling_flags
= ISL_TILING_Y0_BIT
);
1354 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1355 const struct isl_surf
*surf
,
1356 struct isl_surf
*ccs_surf
)
1358 assert(surf
->samples
== 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
);
1359 assert(ISL_DEV_GEN(dev
) >= 7);
1361 assert(ISL_DEV_GEN(dev
) >= 8 || surf
->dim
== ISL_SURF_DIM_2D
);
1363 assert(surf
->logical_level0_px
.depth
== 1);
1365 /* TODO: More conditions where it can fail. */
1367 enum isl_format ccs_format
;
1368 if (ISL_DEV_GEN(dev
) >= 9) {
1369 if (!isl_tiling_is_any_y(surf
->tiling
))
1372 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1373 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
1374 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
1375 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
1379 } else if (surf
->tiling
== ISL_TILING_Y0
) {
1380 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1381 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
1382 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
1383 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
1387 } else if (surf
->tiling
== ISL_TILING_X
) {
1388 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1389 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
1390 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
1391 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
1399 isl_surf_init(dev
, ccs_surf
,
1400 .dim
= ISL_SURF_DIM_2D
,
1401 .format
= ccs_format
,
1402 .width
= surf
->logical_level0_px
.width
,
1403 .height
= surf
->logical_level0_px
.height
,
1405 .levels
= surf
->levels
,
1406 .array_len
= surf
->logical_level0_px
.array_len
,
1408 .usage
= ISL_SURF_USAGE_CCS_BIT
,
1409 .tiling_flags
= ISL_TILING_CCS_BIT
);
1415 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1416 const struct isl_surf_fill_state_info
*restrict info
)
1419 isl_surf_usage_flags_t _base_usage
=
1420 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1421 ISL_SURF_USAGE_TEXTURE_BIT
|
1422 ISL_SURF_USAGE_STORAGE_BIT
);
1423 /* They may only specify one of the above bits at a time */
1424 assert(__builtin_popcount(_base_usage
) == 1);
1425 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1426 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1429 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1430 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1431 info
->surf
->logical_level0_px
.depth
);
1433 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1434 info
->surf
->logical_level0_px
.array_len
);
1437 switch (ISL_DEV_GEN(dev
)) {
1439 if (ISL_DEV_IS_G4X(dev
)) {
1440 /* G45 surface state is the same as gen5 */
1441 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1443 isl_gen4_surf_fill_state_s(dev
, state
, info
);
1447 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1450 isl_gen6_surf_fill_state_s(dev
, state
, info
);
1453 if (ISL_DEV_IS_HASWELL(dev
)) {
1454 isl_gen75_surf_fill_state_s(dev
, state
, info
);
1456 isl_gen7_surf_fill_state_s(dev
, state
, info
);
1460 isl_gen8_surf_fill_state_s(dev
, state
, info
);
1463 isl_gen9_surf_fill_state_s(dev
, state
, info
);
1466 assert(!"Cannot fill surface state for this gen");
1471 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1472 const struct isl_buffer_fill_state_info
*restrict info
)
1474 switch (ISL_DEV_GEN(dev
)) {
1477 /* Gen 4-5 are all the same when it comes to buffer surfaces */
1478 isl_gen5_buffer_fill_state_s(state
, info
);
1481 isl_gen6_buffer_fill_state_s(state
, info
);
1484 if (ISL_DEV_IS_HASWELL(dev
)) {
1485 isl_gen75_buffer_fill_state_s(state
, info
);
1487 isl_gen7_buffer_fill_state_s(state
, info
);
1491 isl_gen8_buffer_fill_state_s(state
, info
);
1494 isl_gen9_buffer_fill_state_s(state
, info
);
1497 assert(!"Cannot fill surface state for this gen");
1502 * A variant of isl_surf_get_image_offset_sa() specific to
1503 * ISL_DIM_LAYOUT_GEN4_2D.
1506 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1507 uint32_t level
, uint32_t logical_array_layer
,
1508 uint32_t *x_offset_sa
,
1509 uint32_t *y_offset_sa
)
1511 assert(level
< surf
->levels
);
1512 if (surf
->dim
== ISL_SURF_DIM_3D
)
1513 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
1515 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1517 const struct isl_extent3d image_align_sa
=
1518 isl_surf_get_image_alignment_sa(surf
);
1520 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1521 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1523 const uint32_t phys_layer
= logical_array_layer
*
1524 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
1527 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1529 for (uint32_t l
= 0; l
< level
; ++l
) {
1531 uint32_t W
= isl_minify(W0
, l
);
1532 x
+= isl_align_npot(W
, image_align_sa
.w
);
1534 uint32_t H
= isl_minify(H0
, l
);
1535 y
+= isl_align_npot(H
, image_align_sa
.h
);
1544 * A variant of isl_surf_get_image_offset_sa() specific to
1545 * ISL_DIM_LAYOUT_GEN4_3D.
1548 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1549 uint32_t level
, uint32_t logical_z_offset_px
,
1550 uint32_t *x_offset_sa
,
1551 uint32_t *y_offset_sa
)
1553 assert(level
< surf
->levels
);
1554 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1555 assert(surf
->phys_level0_sa
.array_len
== 1);
1557 const struct isl_extent3d image_align_sa
=
1558 isl_surf_get_image_alignment_sa(surf
);
1560 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1561 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1562 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1567 for (uint32_t l
= 0; l
< level
; ++l
) {
1568 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1569 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
.d
);
1570 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1572 y
+= level_h
* max_layers_vert
;
1575 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1576 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1577 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, level
), image_align_sa
.d
);
1579 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1581 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1582 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
1589 * A variant of isl_surf_get_image_offset_sa() specific to
1590 * ISL_DIM_LAYOUT_GEN9_1D.
1593 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
1594 uint32_t level
, uint32_t layer
,
1595 uint32_t *x_offset_sa
,
1596 uint32_t *y_offset_sa
)
1598 assert(level
< surf
->levels
);
1599 assert(layer
< surf
->phys_level0_sa
.array_len
);
1600 assert(surf
->phys_level0_sa
.height
== 1);
1601 assert(surf
->phys_level0_sa
.depth
== 1);
1602 assert(surf
->samples
== 1);
1604 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1605 const struct isl_extent3d image_align_sa
=
1606 isl_surf_get_image_alignment_sa(surf
);
1610 for (uint32_t l
= 0; l
< level
; ++l
) {
1611 uint32_t W
= isl_minify(W0
, l
);
1612 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
1618 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1622 * Calculate the offset, in units of surface samples, to a subimage in the
1625 * @invariant level < surface levels
1626 * @invariant logical_array_layer < logical array length of surface
1627 * @invariant logical_z_offset_px < logical depth of surface at level
1630 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1632 uint32_t logical_array_layer
,
1633 uint32_t logical_z_offset_px
,
1634 uint32_t *x_offset_sa
,
1635 uint32_t *y_offset_sa
)
1637 assert(level
< surf
->levels
);
1638 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1639 assert(logical_z_offset_px
1640 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1642 switch (surf
->dim_layout
) {
1643 case ISL_DIM_LAYOUT_GEN9_1D
:
1644 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
1645 x_offset_sa
, y_offset_sa
);
1647 case ISL_DIM_LAYOUT_GEN4_2D
:
1648 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
1649 + logical_z_offset_px
,
1650 x_offset_sa
, y_offset_sa
);
1652 case ISL_DIM_LAYOUT_GEN4_3D
:
1653 get_image_offset_sa_gen4_3d(surf
, level
, logical_z_offset_px
,
1654 x_offset_sa
, y_offset_sa
);
1658 unreachable("not reached");
1663 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1665 uint32_t logical_array_layer
,
1666 uint32_t logical_z_offset_px
,
1667 uint32_t *x_offset_el
,
1668 uint32_t *y_offset_el
)
1670 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1672 assert(level
< surf
->levels
);
1673 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1674 assert(logical_z_offset_px
1675 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1677 uint32_t x_offset_sa
, y_offset_sa
;
1678 isl_surf_get_image_offset_sa(surf
, level
,
1679 logical_array_layer
,
1680 logical_z_offset_px
,
1684 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
1685 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
1689 isl_tiling_get_intratile_offset_el(const struct isl_device
*dev
,
1690 enum isl_tiling tiling
,
1693 uint32_t total_x_offset_el
,
1694 uint32_t total_y_offset_el
,
1695 uint32_t *base_address_offset
,
1696 uint32_t *x_offset_el
,
1697 uint32_t *y_offset_el
)
1699 if (tiling
== ISL_TILING_LINEAR
) {
1700 *base_address_offset
= total_y_offset_el
* row_pitch
+
1701 total_x_offset_el
* bs
;
1707 const uint32_t bpb
= bs
* 8;
1709 struct isl_tile_info tile_info
;
1710 isl_tiling_get_info(dev
, tiling
, bpb
, &tile_info
);
1712 assert(row_pitch
% tile_info
.phys_extent_B
.width
== 0);
1714 /* For non-power-of-two formats, we need the address to be both tile and
1715 * element-aligned. The easiest way to achieve this is to work with a tile
1716 * that is three times as wide as the regular tile.
1718 * The tile info returned by get_tile_info has a logical size that is an
1719 * integer number of tile_info.format_bpb size elements. To scale the
1720 * tile, we scale up the physical width and then treat the logical tile
1721 * size as if it has bpb size elements.
1723 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
1724 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
1726 /* Compute the offset into the tile */
1727 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
1728 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
1730 /* Compute the offset of the tile in units of whole tiles */
1731 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
1732 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
1734 *base_address_offset
=
1735 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch
+
1736 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
1740 isl_surf_get_depth_format(const struct isl_device
*dev
,
1741 const struct isl_surf
*surf
)
1743 /* Support for separate stencil buffers began in gen5. Support for
1744 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
1745 * those that supported separate and interleaved stencil, were gen5 and
1748 * For a list of all available formats, see the Sandybridge PRM >> Volume
1749 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
1753 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1755 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
1758 assert(ISL_DEV_GEN(dev
) < 7);
1760 switch (surf
->format
) {
1762 unreachable("bad isl depth format");
1763 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1764 assert(ISL_DEV_GEN(dev
) < 7);
1765 return 0; /* D32_FLOAT_S8X24_UINT */
1766 case ISL_FORMAT_R32_FLOAT
:
1767 assert(!has_stencil
);
1768 return 1; /* D32_FLOAT */
1769 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1771 assert(ISL_DEV_GEN(dev
) < 7);
1772 return 2; /* D24_UNORM_S8_UINT */
1774 assert(ISL_DEV_GEN(dev
) >= 5);
1775 return 3; /* D24_UNORM_X8_UINT */
1777 case ISL_FORMAT_R16_UNORM
:
1778 assert(!has_stencil
);
1779 return 5; /* D16_UNORM */