2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "genxml/genX_bits.h"
38 void PRINTFLIKE(3, 4) UNUSED
39 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
45 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
48 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
52 isl_device_init(struct isl_device
*dev
,
53 const struct gen_device_info
*info
,
54 bool has_bit6_swizzling
)
57 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
58 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
60 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
61 * device properties at buildtime. Verify that the macros with the device
62 * properties chosen during runtime.
64 ISL_DEV_GEN_SANITIZE(dev
);
65 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
67 /* Did we break hiz or stencil? */
68 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
69 assert(info
->has_hiz_and_separate_stencil
);
70 if (info
->must_use_separate_stencil
)
71 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
73 dev
->ss
.size
= RENDER_SURFACE_STATE_length(info
) * 4;
74 dev
->ss
.align
= isl_align(dev
->ss
.size
, 32);
76 dev
->ss
.clear_value_size
=
77 isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info
) +
78 RENDER_SURFACE_STATE_GreenClearColor_bits(info
) +
79 RENDER_SURFACE_STATE_BlueClearColor_bits(info
) +
80 RENDER_SURFACE_STATE_AlphaClearColor_bits(info
), 32) / 8;
82 dev
->ss
.clear_value_offset
=
83 RENDER_SURFACE_STATE_RedClearColor_start(info
) / 32 * 4;
85 assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) % 8 == 0);
87 RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) / 8;
89 /* The "Auxiliary Surface Base Address" field starts a bit higher up
90 * because the bottom 12 bits are used for other things. Round down to
91 * the nearest dword before.
93 dev
->ss
.aux_addr_offset
=
94 (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info
) & ~31) / 8;
96 dev
->ds
.size
= _3DSTATE_DEPTH_BUFFER_length(info
) * 4;
97 assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
98 dev
->ds
.depth_offset
=
99 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
101 if (dev
->use_separate_stencil
) {
102 dev
->ds
.size
+= _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
103 _3DSTATE_HIER_DEPTH_BUFFER_length(info
) * 4 +
104 _3DSTATE_CLEAR_PARAMS_length(info
) * 4;
106 assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
107 dev
->ds
.stencil_offset
=
108 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
109 _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) / 8;
111 assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
113 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
114 _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
115 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
117 dev
->ds
.stencil_offset
= 0;
118 dev
->ds
.hiz_offset
= 0;
123 * @brief Query the set of multisamples supported by the device.
125 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
128 isl_sample_count_mask_t ATTRIBUTE_CONST
129 isl_device_get_sample_counts(struct isl_device
*dev
)
131 if (ISL_DEV_GEN(dev
) >= 9) {
132 return ISL_SAMPLE_COUNT_1_BIT
|
133 ISL_SAMPLE_COUNT_2_BIT
|
134 ISL_SAMPLE_COUNT_4_BIT
|
135 ISL_SAMPLE_COUNT_8_BIT
|
136 ISL_SAMPLE_COUNT_16_BIT
;
137 } else if (ISL_DEV_GEN(dev
) >= 8) {
138 return ISL_SAMPLE_COUNT_1_BIT
|
139 ISL_SAMPLE_COUNT_2_BIT
|
140 ISL_SAMPLE_COUNT_4_BIT
|
141 ISL_SAMPLE_COUNT_8_BIT
;
142 } else if (ISL_DEV_GEN(dev
) >= 7) {
143 return ISL_SAMPLE_COUNT_1_BIT
|
144 ISL_SAMPLE_COUNT_4_BIT
|
145 ISL_SAMPLE_COUNT_8_BIT
;
146 } else if (ISL_DEV_GEN(dev
) >= 6) {
147 return ISL_SAMPLE_COUNT_1_BIT
|
148 ISL_SAMPLE_COUNT_4_BIT
;
150 return ISL_SAMPLE_COUNT_1_BIT
;
155 * @param[out] info is written only on success
158 isl_tiling_get_info(enum isl_tiling tiling
,
160 struct isl_tile_info
*tile_info
)
162 const uint32_t bs
= format_bpb
/ 8;
163 struct isl_extent2d logical_el
, phys_B
;
165 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
166 /* It is possible to have non-power-of-two formats in a tiled buffer.
167 * The easiest way to handle this is to treat the tile as if it is three
168 * times as wide. This way no pixel will ever cross a tile boundary.
169 * This really only works on legacy X and Y tiling formats.
171 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
172 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
173 isl_tiling_get_info(tiling
, format_bpb
/ 3, tile_info
);
178 case ISL_TILING_LINEAR
:
180 logical_el
= isl_extent2d(1, 1);
181 phys_B
= isl_extent2d(bs
, 1);
186 logical_el
= isl_extent2d(512 / bs
, 8);
187 phys_B
= isl_extent2d(512, 8);
192 logical_el
= isl_extent2d(128 / bs
, 32);
193 phys_B
= isl_extent2d(128, 32);
198 logical_el
= isl_extent2d(64, 64);
199 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
201 * "If the surface is a stencil buffer (and thus has Tile Mode set
202 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
203 * computed based on width, as the stencil buffer is stored with two
206 * This, together with the fact that stencil buffers are referred to as
207 * being Y-tiled in the PRMs for older hardware implies that the
208 * physical size of a W-tile is actually the same as for a Y-tile.
210 phys_B
= isl_extent2d(128, 32);
214 case ISL_TILING_Ys
: {
215 bool is_Ys
= tiling
== ISL_TILING_Ys
;
218 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
219 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
221 logical_el
= isl_extent2d(width
/ bs
, height
);
222 phys_B
= isl_extent2d(width
, height
);
227 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
228 * 128bpb format. The tiling has the same physical dimensions as
229 * Y-tiling but actually has two HiZ columns per Y-tiled column.
232 logical_el
= isl_extent2d(16, 16);
233 phys_B
= isl_extent2d(128, 32);
237 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
238 * have a block size of 1 or 2 bits per block and each CCS element
239 * corresponds to one cache-line pair in the main surface. From the Sky
240 * Lake PRM Vol. 12 in the section on planes:
242 * "The Color Control Surface (CCS) contains the compression status
243 * of the cache-line pairs. The compression state of the cache-line
244 * pair is specified by 2 bits in the CCS. Each CCS cache-line
245 * represents an area on the main surface of 16x16 sets of 128 byte
246 * Y-tiled cache-line-pairs. CCS is always Y tiled."
248 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
249 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
250 * that yields total tile area of 128x128 cache-line pairs or CCS
251 * elements. On older hardware, each CCS element is 1 bit and the tile
252 * is 128x256 elements.
254 assert(format_bpb
== 1 || format_bpb
== 2);
255 logical_el
= isl_extent2d(128, 256 / format_bpb
);
256 phys_B
= isl_extent2d(128, 32);
260 unreachable("not reached");
263 *tile_info
= (struct isl_tile_info
) {
265 .format_bpb
= format_bpb
,
266 .logical_extent_el
= logical_el
,
267 .phys_extent_B
= phys_B
,
272 isl_color_value_is_zero(union isl_color_value value
,
273 enum isl_format format
)
275 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
277 #define RETURN_FALSE_IF_NOT_0(c, i) \
278 if (fmtl->channels.c.bits && value.u32[i] != 0) \
281 RETURN_FALSE_IF_NOT_0(r
, 0);
282 RETURN_FALSE_IF_NOT_0(g
, 1);
283 RETURN_FALSE_IF_NOT_0(b
, 2);
284 RETURN_FALSE_IF_NOT_0(a
, 3);
286 #undef RETURN_FALSE_IF_NOT_0
292 isl_color_value_is_zero_one(union isl_color_value value
,
293 enum isl_format format
)
295 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
297 #define RETURN_FALSE_IF_NOT_0_1(c, i, field) \
298 if (fmtl->channels.c.bits && value.field[i] != 0 && value.field[i] != 1) \
301 if (isl_format_has_int_channel(format
)) {
302 RETURN_FALSE_IF_NOT_0_1(r
, 0, u32
);
303 RETURN_FALSE_IF_NOT_0_1(g
, 1, u32
);
304 RETURN_FALSE_IF_NOT_0_1(b
, 2, u32
);
305 RETURN_FALSE_IF_NOT_0_1(a
, 3, u32
);
307 RETURN_FALSE_IF_NOT_0_1(r
, 0, f32
);
308 RETURN_FALSE_IF_NOT_0_1(g
, 1, f32
);
309 RETURN_FALSE_IF_NOT_0_1(b
, 2, f32
);
310 RETURN_FALSE_IF_NOT_0_1(a
, 3, f32
);
313 #undef RETURN_FALSE_IF_NOT_0_1
319 * @param[out] tiling is set only on success
322 isl_surf_choose_tiling(const struct isl_device
*dev
,
323 const struct isl_surf_init_info
*restrict info
,
324 enum isl_tiling
*tiling
)
326 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
328 /* HiZ surfaces always use the HiZ tiling */
329 if (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) {
330 assert(info
->format
== ISL_FORMAT_HIZ
);
331 assert(tiling_flags
== ISL_TILING_HIZ_BIT
);
332 *tiling
= ISL_TILING_HIZ
;
336 /* CCS surfaces always use the CCS tiling */
337 if (info
->usage
& ISL_SURF_USAGE_CCS_BIT
) {
338 assert(isl_format_get_layout(info
->format
)->txc
== ISL_TXC_CCS
);
339 assert(tiling_flags
== ISL_TILING_CCS_BIT
);
340 *tiling
= ISL_TILING_CCS
;
344 if (ISL_DEV_GEN(dev
) >= 6) {
345 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
347 isl_gen4_filter_tiling(dev
, info
, &tiling_flags
);
350 #define CHOOSE(__tiling) \
352 if (tiling_flags & (1u << (__tiling))) { \
353 *tiling = (__tiling); \
358 /* Of the tiling modes remaining, choose the one that offers the best
362 if (info
->dim
== ISL_SURF_DIM_1D
) {
363 /* Prefer linear for 1D surfaces because they do not benefit from
364 * tiling. To the contrary, tiling leads to wasted memory and poor
365 * memory locality due to the swizzling and alignment restrictions
366 * required in tiled surfaces.
368 CHOOSE(ISL_TILING_LINEAR
);
371 CHOOSE(ISL_TILING_Ys
);
372 CHOOSE(ISL_TILING_Yf
);
373 CHOOSE(ISL_TILING_Y0
);
374 CHOOSE(ISL_TILING_X
);
375 CHOOSE(ISL_TILING_W
);
376 CHOOSE(ISL_TILING_LINEAR
);
380 /* No tiling mode accomodates the inputs. */
385 isl_choose_msaa_layout(const struct isl_device
*dev
,
386 const struct isl_surf_init_info
*info
,
387 enum isl_tiling tiling
,
388 enum isl_msaa_layout
*msaa_layout
)
390 if (ISL_DEV_GEN(dev
) >= 8) {
391 return isl_gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
392 } else if (ISL_DEV_GEN(dev
) >= 7) {
393 return isl_gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
394 } else if (ISL_DEV_GEN(dev
) >= 6) {
395 return isl_gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
397 return isl_gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
402 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
404 assert(isl_is_pow2(samples
));
406 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
409 * If the surface is multisampled and it is a depth or stencil surface
410 * or Multisampled Surface StorageFormat in SURFACE_STATE is
411 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
414 return (struct isl_extent2d
) {
415 .width
= 1 << ((ffs(samples
) - 0) / 2),
416 .height
= 1 << ((ffs(samples
) - 1) / 2),
421 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
422 uint32_t *width
, uint32_t *height
)
424 const struct isl_extent2d px_size_sa
=
425 isl_get_interleaved_msaa_px_size_sa(samples
);
428 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
430 *height
= isl_align(*height
, 2) * px_size_sa
.height
;
433 static enum isl_array_pitch_span
434 isl_choose_array_pitch_span(const struct isl_device
*dev
,
435 const struct isl_surf_init_info
*restrict info
,
436 enum isl_dim_layout dim_layout
,
437 const struct isl_extent4d
*phys_level0_sa
)
439 switch (dim_layout
) {
440 case ISL_DIM_LAYOUT_GEN9_1D
:
441 case ISL_DIM_LAYOUT_GEN4_2D
:
442 if (ISL_DEV_GEN(dev
) >= 8) {
443 /* QPitch becomes programmable in Broadwell. So choose the
444 * most compact QPitch possible in order to conserve memory.
446 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
447 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
449 * - Software must ensure that this field is set to a value
450 * sufficiently large such that the array slices in the surface
451 * do not overlap. Refer to the Memory Data Formats section for
452 * information on how surfaces are stored in memory.
454 * - This field specifies the distance in rows between array
455 * slices. It is used only in the following cases:
457 * - Surface Array is enabled OR
458 * - Number of Mulitsamples is not NUMSAMPLES_1 and
459 * Multisampled Surface Storage Format set to MSFMT_MSS OR
460 * - Surface Type is SURFTYPE_CUBE
462 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
463 } else if (ISL_DEV_GEN(dev
) >= 7) {
464 /* Note that Ivybridge introduces
465 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
466 * driver more control over the QPitch.
469 if (phys_level0_sa
->array_len
== 1) {
470 /* The hardware will never use the QPitch. So choose the most
471 * compact QPitch possible in order to conserve memory.
473 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
476 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
477 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
478 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
479 * Section 6.18.4.7: Surface Arrays (p112):
481 * If Surface Array Spacing is set to ARYSPC_FULL (note that
482 * the depth buffer and stencil buffer have an implied value of
485 return ISL_ARRAY_PITCH_SPAN_FULL
;
488 if (info
->levels
== 1) {
489 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
492 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
495 return ISL_ARRAY_PITCH_SPAN_FULL
;
496 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
497 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
498 isl_surf_usage_is_stencil(info
->usage
)) {
499 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
500 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
502 * The separate stencil buffer does not support mip mapping, thus
503 * the storage for LODs other than LOD 0 is not needed.
505 assert(info
->levels
== 1);
506 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
508 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
509 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
510 isl_surf_usage_is_stencil(info
->usage
)) {
511 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
512 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
514 * The separate stencil buffer does not support mip mapping,
515 * thus the storage for LODs other than LOD 0 is not needed.
517 assert(info
->levels
== 1);
518 assert(phys_level0_sa
->array_len
== 1);
519 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
522 if (phys_level0_sa
->array_len
== 1) {
523 /* The hardware will never use the QPitch. So choose the most
524 * compact QPitch possible in order to conserve memory.
526 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
529 return ISL_ARRAY_PITCH_SPAN_FULL
;
532 case ISL_DIM_LAYOUT_GEN4_3D
:
533 /* The hardware will never use the QPitch. So choose the most
534 * compact QPitch possible in order to conserve memory.
536 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
538 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
539 /* Each array image in the gen6 stencil of HiZ surface is compact in the
540 * sense that every LOD is a compact array of the same size as LOD0.
542 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
545 unreachable("bad isl_dim_layout");
546 return ISL_ARRAY_PITCH_SPAN_FULL
;
550 isl_choose_image_alignment_el(const struct isl_device
*dev
,
551 const struct isl_surf_init_info
*restrict info
,
552 enum isl_tiling tiling
,
553 enum isl_dim_layout dim_layout
,
554 enum isl_msaa_layout msaa_layout
,
555 struct isl_extent3d
*image_align_el
)
557 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
558 if (fmtl
->txc
== ISL_TXC_MCS
) {
559 assert(tiling
== ISL_TILING_Y0
);
562 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
564 * Height, width, and layout of MCS buffer in this case must match with
565 * Render Target height, width, and layout. MCS buffer is tiledY.
567 * To avoid wasting memory, choose the smallest alignment possible:
568 * HALIGN_4 and VALIGN_4.
570 *image_align_el
= isl_extent3d(4, 4, 1);
572 } else if (info
->format
== ISL_FORMAT_HIZ
) {
573 assert(ISL_DEV_GEN(dev
) >= 6);
574 if (ISL_DEV_GEN(dev
) == 6) {
575 /* HiZ surfaces on Sandy Bridge are packed tightly. */
576 *image_align_el
= isl_extent3d(1, 1, 1);
578 /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the
579 * primary surface which works out to 2x2 HiZ elments.
581 *image_align_el
= isl_extent3d(2, 2, 1);
586 if (ISL_DEV_GEN(dev
) >= 9) {
587 isl_gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
588 msaa_layout
, image_align_el
);
589 } else if (ISL_DEV_GEN(dev
) >= 8) {
590 isl_gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
591 msaa_layout
, image_align_el
);
592 } else if (ISL_DEV_GEN(dev
) >= 7) {
593 isl_gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
594 msaa_layout
, image_align_el
);
595 } else if (ISL_DEV_GEN(dev
) >= 6) {
596 isl_gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
597 msaa_layout
, image_align_el
);
599 isl_gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
600 msaa_layout
, image_align_el
);
604 static enum isl_dim_layout
605 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
606 enum isl_surf_dim logical_dim
,
607 enum isl_tiling tiling
,
608 isl_surf_usage_flags_t usage
)
610 /* Sandy bridge needs a special layout for HiZ and stencil. */
611 if (ISL_DEV_GEN(dev
) == 6 &&
612 (tiling
== ISL_TILING_W
|| tiling
== ISL_TILING_HIZ
))
613 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
615 if (ISL_DEV_GEN(dev
) >= 9) {
616 switch (logical_dim
) {
617 case ISL_SURF_DIM_1D
:
618 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
620 * One-dimensional surfaces use a tiling mode of linear.
621 * Technically, they are not tiled resources, but the Tiled
622 * Resource Mode field in RENDER_SURFACE_STATE is still used to
623 * indicate the alignment requirements for this linear surface
624 * (See 1D Alignment requirements for how 4K and 64KB Tiled
625 * Resource Modes impact alignment). Alternatively, a 1D surface
626 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
629 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
630 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
632 if (tiling
== ISL_TILING_LINEAR
)
633 return ISL_DIM_LAYOUT_GEN9_1D
;
635 return ISL_DIM_LAYOUT_GEN4_2D
;
636 case ISL_SURF_DIM_2D
:
637 case ISL_SURF_DIM_3D
:
638 return ISL_DIM_LAYOUT_GEN4_2D
;
641 switch (logical_dim
) {
642 case ISL_SURF_DIM_1D
:
643 case ISL_SURF_DIM_2D
:
644 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
646 * The cube face textures are stored in the same way as 3D surfaces
647 * are stored (see section 6.17.5 for details). For cube surfaces,
648 * however, the depth is equal to the number of faces (always 6) and
649 * is not reduced for each MIP.
651 if (ISL_DEV_GEN(dev
) == 4 && (usage
& ISL_SURF_USAGE_CUBE_BIT
))
652 return ISL_DIM_LAYOUT_GEN4_3D
;
654 return ISL_DIM_LAYOUT_GEN4_2D
;
655 case ISL_SURF_DIM_3D
:
656 return ISL_DIM_LAYOUT_GEN4_3D
;
660 unreachable("bad isl_surf_dim");
661 return ISL_DIM_LAYOUT_GEN4_2D
;
665 * Calculate the physical extent of the surface's first level, in units of
666 * surface samples. The result is aligned to the format's compression block.
669 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
670 const struct isl_surf_init_info
*restrict info
,
671 enum isl_dim_layout dim_layout
,
672 enum isl_tiling tiling
,
673 enum isl_msaa_layout msaa_layout
,
674 struct isl_extent4d
*phys_level0_sa
)
676 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
678 if (isl_format_is_yuv(info
->format
))
679 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
682 case ISL_SURF_DIM_1D
:
683 assert(info
->height
== 1);
684 assert(info
->depth
== 1);
685 assert(info
->samples
== 1);
687 switch (dim_layout
) {
688 case ISL_DIM_LAYOUT_GEN4_3D
:
689 unreachable("bad isl_dim_layout");
691 case ISL_DIM_LAYOUT_GEN9_1D
:
692 case ISL_DIM_LAYOUT_GEN4_2D
:
693 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
694 *phys_level0_sa
= (struct isl_extent4d
) {
695 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
698 .a
= info
->array_len
,
704 case ISL_SURF_DIM_2D
:
705 if (ISL_DEV_GEN(dev
) == 4 && (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
))
706 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_3D
);
708 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
||
709 dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
711 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
712 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
714 switch (msaa_layout
) {
715 case ISL_MSAA_LAYOUT_NONE
:
716 assert(info
->depth
== 1);
717 assert(info
->samples
== 1);
719 *phys_level0_sa
= (struct isl_extent4d
) {
720 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
721 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
723 .a
= info
->array_len
,
727 case ISL_MSAA_LAYOUT_ARRAY
:
728 assert(info
->depth
== 1);
729 assert(info
->levels
== 1);
730 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
731 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
733 *phys_level0_sa
= (struct isl_extent4d
) {
737 .a
= info
->array_len
* info
->samples
,
741 case ISL_MSAA_LAYOUT_INTERLEAVED
:
742 assert(info
->depth
== 1);
743 assert(info
->levels
== 1);
744 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
746 *phys_level0_sa
= (struct isl_extent4d
) {
750 .a
= info
->array_len
,
753 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
757 phys_level0_sa
->w
= isl_align(phys_level0_sa
->w
, fmtl
->bw
);
758 phys_level0_sa
->h
= isl_align(phys_level0_sa
->h
, fmtl
->bh
);
763 case ISL_SURF_DIM_3D
:
764 assert(info
->array_len
== 1);
765 assert(info
->samples
== 1);
768 isl_finishme("%s:%s: compression block with depth > 1",
772 switch (dim_layout
) {
773 case ISL_DIM_LAYOUT_GEN9_1D
:
774 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
775 unreachable("bad isl_dim_layout");
777 case ISL_DIM_LAYOUT_GEN4_2D
:
778 assert(ISL_DEV_GEN(dev
) >= 9);
780 *phys_level0_sa
= (struct isl_extent4d
) {
781 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
782 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
788 case ISL_DIM_LAYOUT_GEN4_3D
:
789 assert(ISL_DEV_GEN(dev
) < 9);
790 *phys_level0_sa
= (struct isl_extent4d
) {
791 .w
= isl_align(info
->width
, fmtl
->bw
),
792 .h
= isl_align(info
->height
, fmtl
->bh
),
803 * Calculate the pitch between physical array slices, in units of rows of
807 isl_calc_array_pitch_el_rows_gen4_2d(
808 const struct isl_device
*dev
,
809 const struct isl_surf_init_info
*restrict info
,
810 const struct isl_tile_info
*tile_info
,
811 const struct isl_extent3d
*image_align_sa
,
812 const struct isl_extent4d
*phys_level0_sa
,
813 enum isl_array_pitch_span array_pitch_span
,
814 const struct isl_extent2d
*phys_slice0_sa
)
816 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
817 uint32_t pitch_sa_rows
= 0;
819 switch (array_pitch_span
) {
820 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
821 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
823 case ISL_ARRAY_PITCH_SPAN_FULL
: {
824 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
825 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
826 * Surfaces >> Surface Arrays.
828 uint32_t H0_sa
= phys_level0_sa
->h
;
829 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
831 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
832 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
835 if (ISL_DEV_GEN(dev
) >= 7) {
836 /* The QPitch equation changed slightly in Ivybridge. */
842 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
844 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
845 (info
->height
% 4 == 1)) {
846 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
847 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
849 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
850 * the value calculated in the equation above , for every
851 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
853 * XXX(chadv): Is the errata natural corollary of the physical
854 * layout of interleaved samples?
859 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
864 assert(pitch_sa_rows
% fmtl
->bh
== 0);
865 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
867 if (ISL_DEV_GEN(dev
) >= 9 && fmtl
->txc
== ISL_TXC_CCS
) {
869 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
871 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
872 * layout with these alignments in the RT space: Horizontal
873 * Alignment = 128 and Vertical Alignment = 64."
875 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
877 * "For non-multisampled render target's CCS auxiliary surface,
878 * QPitch must be computed with Horizontal Alignment = 128 and
879 * Surface Vertical Alignment = 256. These alignments are only for
880 * CCS buffer and not for associated render target."
882 * The first restriction is already handled by isl_choose_image_alignment_el
883 * but the second restriction, which is an extension of the first, only
884 * applies to qpitch and must be applied here.
886 assert(fmtl
->bh
== 4);
887 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
890 if (ISL_DEV_GEN(dev
) >= 9 &&
891 info
->dim
== ISL_SURF_DIM_3D
&&
892 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
893 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
895 * Tile Mode != Linear: This field must be set to an integer multiple
898 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
901 return pitch_el_rows
;
905 * A variant of isl_calc_phys_slice0_extent_sa() specific to
906 * ISL_DIM_LAYOUT_GEN4_2D.
909 isl_calc_phys_slice0_extent_sa_gen4_2d(
910 const struct isl_device
*dev
,
911 const struct isl_surf_init_info
*restrict info
,
912 enum isl_msaa_layout msaa_layout
,
913 const struct isl_extent3d
*image_align_sa
,
914 const struct isl_extent4d
*phys_level0_sa
,
915 struct isl_extent2d
*phys_slice0_sa
)
917 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
919 assert(phys_level0_sa
->depth
== 1);
921 if (info
->levels
== 1) {
922 /* Do not pad the surface to the image alignment. Instead, pad it only
923 * to the pixel format's block alignment.
925 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
926 * cycles on the below mipmap layout caluclations. Reducing the
927 * alignment here is safe because we later align the row pitch and array
928 * pitch to the tile boundary. It is safe even for
929 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
930 * to accomodate the interleaved samples.
932 * For linear surfaces, reducing the alignment here permits us to later
933 * choose an arbitrary, non-aligned row pitch. If the surface backs
934 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
935 * VkBufferImageCopy::bufferRowLength.
937 *phys_slice0_sa
= (struct isl_extent2d
) {
938 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
939 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
944 uint32_t slice_top_w
= 0;
945 uint32_t slice_bottom_w
= 0;
946 uint32_t slice_left_h
= 0;
947 uint32_t slice_right_h
= 0;
949 uint32_t W0
= phys_level0_sa
->w
;
950 uint32_t H0
= phys_level0_sa
->h
;
952 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
953 uint32_t W
= isl_minify(W0
, l
);
954 uint32_t H
= isl_minify(H0
, l
);
956 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
957 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
974 *phys_slice0_sa
= (struct isl_extent2d
) {
975 .w
= MAX(slice_top_w
, slice_bottom_w
),
976 .h
= MAX(slice_left_h
, slice_right_h
),
981 isl_calc_phys_total_extent_el_gen4_2d(
982 const struct isl_device
*dev
,
983 const struct isl_surf_init_info
*restrict info
,
984 const struct isl_tile_info
*tile_info
,
985 enum isl_msaa_layout msaa_layout
,
986 const struct isl_extent3d
*image_align_sa
,
987 const struct isl_extent4d
*phys_level0_sa
,
988 enum isl_array_pitch_span array_pitch_span
,
989 uint32_t *array_pitch_el_rows
,
990 struct isl_extent2d
*total_extent_el
)
992 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
994 struct isl_extent2d phys_slice0_sa
;
995 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
996 image_align_sa
, phys_level0_sa
,
998 *array_pitch_el_rows
=
999 isl_calc_array_pitch_el_rows_gen4_2d(dev
, info
, tile_info
,
1000 image_align_sa
, phys_level0_sa
,
1003 *total_extent_el
= (struct isl_extent2d
) {
1004 .w
= isl_assert_div(phys_slice0_sa
.w
, fmtl
->bw
),
1005 .h
= *array_pitch_el_rows
* (phys_level0_sa
->array_len
- 1) +
1006 isl_assert_div(phys_slice0_sa
.h
, fmtl
->bh
),
1011 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1012 * ISL_DIM_LAYOUT_GEN4_3D.
1015 isl_calc_phys_total_extent_el_gen4_3d(
1016 const struct isl_device
*dev
,
1017 const struct isl_surf_init_info
*restrict info
,
1018 const struct isl_extent3d
*image_align_sa
,
1019 const struct isl_extent4d
*phys_level0_sa
,
1020 uint32_t *array_pitch_el_rows
,
1021 struct isl_extent2d
*phys_total_el
)
1023 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1025 assert(info
->samples
== 1);
1027 if (info
->dim
!= ISL_SURF_DIM_3D
) {
1028 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
1030 * The cube face textures are stored in the same way as 3D surfaces
1031 * are stored (see section 6.17.5 for details). For cube surfaces,
1032 * however, the depth is equal to the number of faces (always 6) and
1033 * is not reduced for each MIP.
1035 assert(ISL_DEV_GEN(dev
) == 4);
1036 assert(info
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
1037 assert(phys_level0_sa
->array_len
== 6);
1039 assert(phys_level0_sa
->array_len
== 1);
1042 uint32_t total_w
= 0;
1043 uint32_t total_h
= 0;
1045 uint32_t W0
= phys_level0_sa
->w
;
1046 uint32_t H0
= phys_level0_sa
->h
;
1047 uint32_t D0
= phys_level0_sa
->d
;
1048 uint32_t A0
= phys_level0_sa
->a
;
1050 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1051 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
1052 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
1053 uint32_t level_d
= info
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : A0
;
1055 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
1056 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1058 total_w
= MAX(total_w
, level_w
* max_layers_horiz
);
1059 total_h
+= level_h
* max_layers_vert
;
1062 /* GEN4_3D layouts don't really have an array pitch since each LOD has a
1063 * different number of horizontal and vertical layers. We have to set it
1064 * to something, so at least make it true for LOD0.
1066 *array_pitch_el_rows
=
1067 isl_align_npot(phys_level0_sa
->h
, image_align_sa
->h
) / fmtl
->bw
;
1068 *phys_total_el
= (struct isl_extent2d
) {
1069 .w
= isl_assert_div(total_w
, fmtl
->bw
),
1070 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1075 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1076 * ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ.
1079 isl_calc_phys_total_extent_el_gen6_stencil_hiz(
1080 const struct isl_device
*dev
,
1081 const struct isl_surf_init_info
*restrict info
,
1082 const struct isl_tile_info
*tile_info
,
1083 const struct isl_extent3d
*image_align_sa
,
1084 const struct isl_extent4d
*phys_level0_sa
,
1085 uint32_t *array_pitch_el_rows
,
1086 struct isl_extent2d
*phys_total_el
)
1088 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1090 const struct isl_extent2d tile_extent_sa
= {
1091 .w
= tile_info
->logical_extent_el
.w
* fmtl
->bw
,
1092 .h
= tile_info
->logical_extent_el
.h
* fmtl
->bh
,
1094 /* Tile size is a multiple of image alignment */
1095 assert(tile_extent_sa
.w
% image_align_sa
->w
== 0);
1096 assert(tile_extent_sa
.h
% image_align_sa
->h
== 0);
1098 const uint32_t W0
= phys_level0_sa
->w
;
1099 const uint32_t H0
= phys_level0_sa
->h
;
1101 /* Each image has the same height as LOD0 because the hardware thinks
1102 * everything is LOD0
1104 const uint32_t H
= isl_align(H0
, image_align_sa
->h
) * phys_level0_sa
->a
;
1106 uint32_t total_top_w
= 0;
1107 uint32_t total_bottom_w
= 0;
1108 uint32_t total_h
= 0;
1110 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1111 const uint32_t W
= isl_minify(W0
, l
);
1113 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
1114 const uint32_t h
= isl_align(H
, tile_extent_sa
.h
);
1119 } else if (l
== 1) {
1123 total_bottom_w
+= w
;
1127 *array_pitch_el_rows
=
1128 isl_assert_div(isl_align(H0
, image_align_sa
->h
), fmtl
->bh
);
1129 *phys_total_el
= (struct isl_extent2d
) {
1130 .w
= isl_assert_div(MAX(total_top_w
, total_bottom_w
), fmtl
->bw
),
1131 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1136 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1137 * ISL_DIM_LAYOUT_GEN9_1D.
1140 isl_calc_phys_total_extent_el_gen9_1d(
1141 const struct isl_device
*dev
,
1142 const struct isl_surf_init_info
*restrict info
,
1143 const struct isl_extent3d
*image_align_sa
,
1144 const struct isl_extent4d
*phys_level0_sa
,
1145 uint32_t *array_pitch_el_rows
,
1146 struct isl_extent2d
*phys_total_el
)
1148 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1150 assert(phys_level0_sa
->height
/ fmtl
->bh
== 1);
1151 assert(phys_level0_sa
->depth
== 1);
1152 assert(info
->samples
== 1);
1153 assert(image_align_sa
->w
>= fmtl
->bw
);
1155 uint32_t slice_w
= 0;
1156 const uint32_t W0
= phys_level0_sa
->w
;
1158 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1159 uint32_t W
= isl_minify(W0
, l
);
1160 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1165 *array_pitch_el_rows
= 1;
1166 *phys_total_el
= (struct isl_extent2d
) {
1167 .w
= isl_assert_div(slice_w
, fmtl
->bw
),
1168 .h
= phys_level0_sa
->array_len
,
1173 * Calculate the two-dimensional total physical extent of the surface, in
1174 * units of surface elements.
1177 isl_calc_phys_total_extent_el(const struct isl_device
*dev
,
1178 const struct isl_surf_init_info
*restrict info
,
1179 const struct isl_tile_info
*tile_info
,
1180 enum isl_dim_layout dim_layout
,
1181 enum isl_msaa_layout msaa_layout
,
1182 const struct isl_extent3d
*image_align_sa
,
1183 const struct isl_extent4d
*phys_level0_sa
,
1184 enum isl_array_pitch_span array_pitch_span
,
1185 uint32_t *array_pitch_el_rows
,
1186 struct isl_extent2d
*total_extent_el
)
1188 switch (dim_layout
) {
1189 case ISL_DIM_LAYOUT_GEN9_1D
:
1190 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1191 isl_calc_phys_total_extent_el_gen9_1d(dev
, info
,
1192 image_align_sa
, phys_level0_sa
,
1193 array_pitch_el_rows
,
1196 case ISL_DIM_LAYOUT_GEN4_2D
:
1197 isl_calc_phys_total_extent_el_gen4_2d(dev
, info
, tile_info
, msaa_layout
,
1198 image_align_sa
, phys_level0_sa
,
1200 array_pitch_el_rows
,
1203 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
1204 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1205 isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev
, info
, tile_info
,
1208 array_pitch_el_rows
,
1211 case ISL_DIM_LAYOUT_GEN4_3D
:
1212 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1213 isl_calc_phys_total_extent_el_gen4_3d(dev
, info
,
1214 image_align_sa
, phys_level0_sa
,
1215 array_pitch_el_rows
,
1222 isl_calc_row_pitch_alignment(const struct isl_surf_init_info
*surf_info
,
1223 const struct isl_tile_info
*tile_info
)
1225 if (tile_info
->tiling
!= ISL_TILING_LINEAR
)
1226 return tile_info
->phys_extent_B
.width
;
1228 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1229 * RENDER_SURFACE_STATE Surface Pitch (p349):
1231 * - For linear render target surfaces and surfaces accessed with the
1232 * typed data port messages, the pitch must be a multiple of the
1233 * element size for non-YUV surface formats. Pitch must be
1234 * a multiple of 2 * element size for YUV surface formats.
1236 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1237 * ignore because isl doesn't do buffers.]
1239 * - For other linear surfaces, the pitch can be any multiple of
1242 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1243 const uint32_t bs
= fmtl
->bpb
/ 8;
1245 if (surf_info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1246 if (isl_format_is_yuv(surf_info
->format
)) {
1257 isl_calc_linear_min_row_pitch(const struct isl_device
*dev
,
1258 const struct isl_surf_init_info
*info
,
1259 const struct isl_extent2d
*phys_total_el
,
1262 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1263 const uint32_t bs
= fmtl
->bpb
/ 8;
1265 return isl_align_npot(bs
* phys_total_el
->w
, alignment
);
1269 isl_calc_tiled_min_row_pitch(const struct isl_device
*dev
,
1270 const struct isl_surf_init_info
*surf_info
,
1271 const struct isl_tile_info
*tile_info
,
1272 const struct isl_extent2d
*phys_total_el
,
1275 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1277 assert(fmtl
->bpb
% tile_info
->format_bpb
== 0);
1279 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
->format_bpb
;
1280 const uint32_t total_w_tl
=
1281 isl_align_div(phys_total_el
->w
* tile_el_scale
,
1282 tile_info
->logical_extent_el
.width
);
1284 assert(alignment
== tile_info
->phys_extent_B
.width
);
1285 return total_w_tl
* tile_info
->phys_extent_B
.width
;
1289 isl_calc_min_row_pitch(const struct isl_device
*dev
,
1290 const struct isl_surf_init_info
*surf_info
,
1291 const struct isl_tile_info
*tile_info
,
1292 const struct isl_extent2d
*phys_total_el
,
1295 if (tile_info
->tiling
== ISL_TILING_LINEAR
) {
1296 return isl_calc_linear_min_row_pitch(dev
, surf_info
, phys_total_el
,
1299 return isl_calc_tiled_min_row_pitch(dev
, surf_info
, tile_info
,
1300 phys_total_el
, alignment
);
1305 * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
1306 * size is `bits` bits?
1308 * Hardware pitch fields are offset by 1. For example, if the size of
1309 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
1310 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
1311 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
1314 pitch_in_range(uint32_t n
, uint32_t bits
)
1317 return likely(bits
!= 0 && 1 <= n
&& n
<= (1 << bits
));
1321 isl_calc_row_pitch(const struct isl_device
*dev
,
1322 const struct isl_surf_init_info
*surf_info
,
1323 const struct isl_tile_info
*tile_info
,
1324 enum isl_dim_layout dim_layout
,
1325 const struct isl_extent2d
*phys_total_el
,
1326 uint32_t *out_row_pitch
)
1328 uint32_t alignment
=
1329 isl_calc_row_pitch_alignment(surf_info
, tile_info
);
1331 /* If pitch isn't given and it can be chosen freely, align it by cache line
1332 * allowing one to use blit engine on the surface.
1334 if (surf_info
->row_pitch
== 0 && tile_info
->tiling
== ISL_TILING_LINEAR
) {
1335 /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
1337 * "Base address of the destination surface: X=0, Y=0. Lower 32bits
1338 * of the 48bit addressing. When Src Tiling is enabled (Bit_15
1339 * enabled), this address must be 4KB-aligned. When Tiling is not
1340 * enabled, this address should be CL (64byte) aligned."
1342 alignment
= MAX2(alignment
, 64);
1345 const uint32_t min_row_pitch
=
1346 isl_calc_min_row_pitch(dev
, surf_info
, tile_info
, phys_total_el
,
1349 uint32_t row_pitch
= min_row_pitch
;
1351 if (surf_info
->row_pitch
!= 0) {
1352 row_pitch
= surf_info
->row_pitch
;
1354 if (row_pitch
< min_row_pitch
)
1357 if (row_pitch
% alignment
!= 0)
1361 const uint32_t row_pitch_tiles
= row_pitch
/ tile_info
->phys_extent_B
.width
;
1366 if (dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
1367 /* SurfacePitch is ignored for this layout. */
1371 if ((surf_info
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1372 ISL_SURF_USAGE_TEXTURE_BIT
|
1373 ISL_SURF_USAGE_STORAGE_BIT
)) &&
1374 !pitch_in_range(row_pitch
, RENDER_SURFACE_STATE_SurfacePitch_bits(dev
->info
)))
1377 if ((surf_info
->usage
& (ISL_SURF_USAGE_CCS_BIT
|
1378 ISL_SURF_USAGE_MCS_BIT
)) &&
1379 !pitch_in_range(row_pitch_tiles
, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev
->info
)))
1382 if ((surf_info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1383 !pitch_in_range(row_pitch
, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1386 if ((surf_info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) &&
1387 !pitch_in_range(row_pitch
, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1390 const uint32_t stencil_pitch_bits
= dev
->use_separate_stencil
?
1391 _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev
->info
) :
1392 _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
);
1394 if ((surf_info
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) &&
1395 !pitch_in_range(row_pitch
, stencil_pitch_bits
))
1399 *out_row_pitch
= row_pitch
;
1404 isl_surf_init_s(const struct isl_device
*dev
,
1405 struct isl_surf
*surf
,
1406 const struct isl_surf_init_info
*restrict info
)
1408 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1410 const struct isl_extent4d logical_level0_px
= {
1414 .a
= info
->array_len
,
1417 enum isl_tiling tiling
;
1418 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1421 struct isl_tile_info tile_info
;
1422 isl_tiling_get_info(tiling
, fmtl
->bpb
, &tile_info
);
1424 const enum isl_dim_layout dim_layout
=
1425 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
, info
->usage
);
1427 enum isl_msaa_layout msaa_layout
;
1428 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1431 struct isl_extent3d image_align_el
;
1432 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1435 struct isl_extent3d image_align_sa
=
1436 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1438 struct isl_extent4d phys_level0_sa
;
1439 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1441 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1442 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1444 enum isl_array_pitch_span array_pitch_span
=
1445 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1447 uint32_t array_pitch_el_rows
;
1448 struct isl_extent2d phys_total_el
;
1449 isl_calc_phys_total_extent_el(dev
, info
, &tile_info
,
1450 dim_layout
, msaa_layout
,
1451 &image_align_sa
, &phys_level0_sa
,
1452 array_pitch_span
, &array_pitch_el_rows
,
1456 if (!isl_calc_row_pitch(dev
, info
, &tile_info
, dim_layout
,
1457 &phys_total_el
, &row_pitch
))
1460 uint32_t base_alignment
;
1462 if (tiling
== ISL_TILING_LINEAR
) {
1463 size
= (uint64_t) row_pitch
* phys_total_el
.h
;
1465 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1467 * "The Base Address for linear render target surfaces and surfaces
1468 * accessed with the typed surface read/write data port messages must
1469 * be element-size aligned, for non-YUV surface formats, or a
1470 * multiple of 2 element-sizes for YUV surface formats. Other linear
1471 * surfaces have no alignment requirements (byte alignment is
1474 base_alignment
= MAX(1, info
->min_alignment
);
1475 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1476 if (isl_format_is_yuv(info
->format
)) {
1477 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 4);
1479 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 8);
1482 base_alignment
= isl_round_up_to_power_of_two(base_alignment
);
1484 const uint32_t total_h_tl
=
1485 isl_align_div(phys_total_el
.h
, tile_info
.logical_extent_el
.height
);
1487 size
= (uint64_t) total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch
;
1489 const uint32_t tile_size
= tile_info
.phys_extent_B
.width
*
1490 tile_info
.phys_extent_B
.height
;
1491 assert(isl_is_pow2(info
->min_alignment
) && isl_is_pow2(tile_size
));
1492 base_alignment
= MAX(info
->min_alignment
, tile_size
);
1495 if (ISL_DEV_GEN(dev
) < 9) {
1496 /* From the Broadwell PRM Vol 5, Surface Layout:
1498 * "In addition to restrictions on maximum height, width, and depth,
1499 * surfaces are also restricted to a maximum size in bytes. This
1500 * maximum is 2 GB for all products and all surface types."
1502 * This comment is applicable to all Pre-gen9 platforms.
1504 if (size
> (uint64_t) 1 << 31)
1506 } else if (ISL_DEV_GEN(dev
) < 11) {
1507 /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
1508 * "In addition to restrictions on maximum height, width, and depth,
1509 * surfaces are also restricted to a maximum size of 2^38 bytes.
1510 * All pixels within the surface must be contained within 2^38 bytes
1511 * of the base address."
1513 if (size
> (uint64_t) 1 << 38)
1516 /* gen11+ platforms raised this limit to 2^44 bytes. */
1517 if (size
> (uint64_t) 1 << 44)
1521 *surf
= (struct isl_surf
) {
1523 .dim_layout
= dim_layout
,
1524 .msaa_layout
= msaa_layout
,
1526 .format
= info
->format
,
1528 .levels
= info
->levels
,
1529 .samples
= info
->samples
,
1531 .image_alignment_el
= image_align_el
,
1532 .logical_level0_px
= logical_level0_px
,
1533 .phys_level0_sa
= phys_level0_sa
,
1536 .alignment
= base_alignment
,
1537 .row_pitch
= row_pitch
,
1538 .array_pitch_el_rows
= array_pitch_el_rows
,
1539 .array_pitch_span
= array_pitch_span
,
1541 .usage
= info
->usage
,
1548 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1549 struct isl_tile_info
*tile_info
)
1551 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1552 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, tile_info
);
1556 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1557 const struct isl_surf
*surf
,
1558 struct isl_surf
*hiz_surf
)
1560 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1562 /* Multisampled depth is always interleaved */
1563 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1564 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1566 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
1568 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
1569 * Target View Extent, and Depth Coordinate Offset X/Y of the
1570 * hierarchical depth buffer are inherited from the depth buffer. The
1571 * height and width of the hierarchical depth buffer that must be
1572 * allocated are computed by the following formulas, where HZ is the
1573 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
1574 * Z_Width, and Z_Depth values given in these formulas are those present
1575 * in 3DSTATE_DEPTH_BUFFER incremented by one.
1577 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
1578 * being applied to the table below if Number of Multisamples is set to
1579 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
1580 * Z_Width must be multiplied by 4 before being applied to the table
1581 * below if Number of Multisamples is set to NUMSAMPLES_8."
1583 * In the Sky Lake PRM, the second paragraph is replaced with this:
1585 * "The Z_Height and Z_Width values must equal those present in
1586 * 3DSTATE_DEPTH_BUFFER incremented by one."
1588 * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
1589 * block corresponds to a region of 8x4 samples in the primary depth
1590 * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
1591 * a region of 8x4 pixels in the primary depth surface regardless of the
1592 * number of samples. The dimensions of a HiZ block in both pixels and
1593 * samples are given in the table below:
1595 * | SNB - BDW | SKL+
1596 * ------+-----------+-------------
1597 * 1x | 8 x 4 sa | 8 x 4 sa
1598 * MSAA | 8 x 4 px | 8 x 4 px
1599 * ------+-----------+-------------
1600 * 2x | 8 x 4 sa | 16 x 4 sa
1601 * MSAA | 4 x 4 px | 8 x 4 px
1602 * ------+-----------+-------------
1603 * 4x | 8 x 4 sa | 16 x 8 sa
1604 * MSAA | 4 x 2 px | 8 x 4 px
1605 * ------+-----------+-------------
1606 * 8x | 8 x 4 sa | 32 x 8 sa
1607 * MSAA | 2 x 2 px | 8 x 4 px
1608 * ------+-----------+-------------
1609 * 16x | N/A | 32 x 16 sa
1610 * MSAA | N/A | 8 x 4 px
1611 * ------+-----------+-------------
1613 * There are a number of different ways that this discrepency could be
1614 * handled. The way we have chosen is to simply make MSAA HiZ have the
1615 * same number of samples as the parent surface pre-Sky Lake and always be
1616 * single-sampled on Sky Lake and above. Since the block sizes of
1617 * compressed formats are given in samples, this neatly handles everything
1618 * without the need for additional HiZ formats with different block sizes
1621 const unsigned samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
;
1623 return isl_surf_init(dev
, hiz_surf
,
1625 .format
= ISL_FORMAT_HIZ
,
1626 .width
= surf
->logical_level0_px
.width
,
1627 .height
= surf
->logical_level0_px
.height
,
1628 .depth
= surf
->logical_level0_px
.depth
,
1629 .levels
= surf
->levels
,
1630 .array_len
= surf
->logical_level0_px
.array_len
,
1632 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1633 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1637 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1638 const struct isl_surf
*surf
,
1639 struct isl_surf
*mcs_surf
)
1641 /* It must be multisampled with an array layout */
1642 assert(surf
->samples
> 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1644 /* The following are true of all multisampled surfaces */
1645 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1646 assert(surf
->levels
== 1);
1647 assert(surf
->logical_level0_px
.depth
== 1);
1649 /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
1650 * bits which means the maximum pitch of a compression surface is 512
1651 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
1652 * 64bpp, this gives us a maximum width of 8192 pixels. We can create
1653 * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
1654 * and 8x, we have enough room for the full 16k supported by the hardware.
1656 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
1659 enum isl_format mcs_format
;
1660 switch (surf
->samples
) {
1661 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1662 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1663 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1664 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1666 unreachable("Invalid sample count");
1669 return isl_surf_init(dev
, mcs_surf
,
1670 .dim
= ISL_SURF_DIM_2D
,
1671 .format
= mcs_format
,
1672 .width
= surf
->logical_level0_px
.width
,
1673 .height
= surf
->logical_level0_px
.height
,
1676 .array_len
= surf
->logical_level0_px
.array_len
,
1677 .samples
= 1, /* MCS surfaces are really single-sampled */
1678 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1679 .tiling_flags
= ISL_TILING_Y0_BIT
);
1683 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1684 const struct isl_surf
*surf
,
1685 struct isl_surf
*ccs_surf
,
1688 assert(surf
->samples
== 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
);
1689 assert(ISL_DEV_GEN(dev
) >= 7);
1691 if (surf
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)
1694 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
1695 * work for 3D textures until gen9 where the layout of 3D textures changes
1696 * to match 2D array textures.
1698 if (ISL_DEV_GEN(dev
) <= 8 && surf
->dim
!= ISL_SURF_DIM_2D
)
1701 /* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
1702 * Non-MultiSampler Render Target Restrictions):
1704 * "Support is for non-mip-mapped and non-array surface types only."
1706 * This restriction is lifted on gen8+. Technically, it may be possible to
1707 * create a CCS for an arrayed or mipmapped image and only enable CCS_D
1708 * when rendering to the base slice. However, there is no documentation
1709 * tell us what the hardware would do in that case or what it does if you
1710 * walk off the bases slice. (Does it ignore CCS or does it start
1711 * scribbling over random memory?) We play it safe and just follow the
1712 * docs and don't allow CCS_D for arrayed or mip-mapped surfaces.
1714 if (ISL_DEV_GEN(dev
) <= 7 &&
1715 (surf
->levels
> 1 || surf
->logical_level0_px
.array_len
> 1))
1718 if (isl_format_is_compressed(surf
->format
))
1721 /* TODO: More conditions where it can fail. */
1723 enum isl_format ccs_format
;
1724 if (ISL_DEV_GEN(dev
) >= 9) {
1725 if (!isl_tiling_is_any_y(surf
->tiling
))
1728 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1729 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
1730 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
1731 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
1735 } else if (surf
->tiling
== ISL_TILING_Y0
) {
1736 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1737 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
1738 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
1739 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
1743 } else if (surf
->tiling
== ISL_TILING_X
) {
1744 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1745 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
1746 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
1747 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
1755 return isl_surf_init(dev
, ccs_surf
,
1757 .format
= ccs_format
,
1758 .width
= surf
->logical_level0_px
.width
,
1759 .height
= surf
->logical_level0_px
.height
,
1760 .depth
= surf
->logical_level0_px
.depth
,
1761 .levels
= surf
->levels
,
1762 .array_len
= surf
->logical_level0_px
.array_len
,
1764 .row_pitch
= row_pitch
,
1765 .usage
= ISL_SURF_USAGE_CCS_BIT
,
1766 .tiling_flags
= ISL_TILING_CCS_BIT
);
1769 #define isl_genX_call(dev, func, ...) \
1770 switch (ISL_DEV_GEN(dev)) { \
1772 /* G45 surface state is the same as gen5 */ \
1773 if (ISL_DEV_IS_G4X(dev)) { \
1774 isl_gen5_##func(__VA_ARGS__); \
1776 isl_gen4_##func(__VA_ARGS__); \
1780 isl_gen5_##func(__VA_ARGS__); \
1783 isl_gen6_##func(__VA_ARGS__); \
1786 if (ISL_DEV_IS_HASWELL(dev)) { \
1787 isl_gen75_##func(__VA_ARGS__); \
1789 isl_gen7_##func(__VA_ARGS__); \
1793 isl_gen8_##func(__VA_ARGS__); \
1796 isl_gen9_##func(__VA_ARGS__); \
1799 isl_gen10_##func(__VA_ARGS__); \
1802 isl_gen11_##func(__VA_ARGS__); \
1805 assert(!"Unknown hardware generation"); \
1809 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1810 const struct isl_surf_fill_state_info
*restrict info
)
1813 isl_surf_usage_flags_t _base_usage
=
1814 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1815 ISL_SURF_USAGE_TEXTURE_BIT
|
1816 ISL_SURF_USAGE_STORAGE_BIT
);
1817 /* They may only specify one of the above bits at a time */
1818 assert(__builtin_popcount(_base_usage
) == 1);
1819 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1820 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1823 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1824 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1825 info
->surf
->logical_level0_px
.depth
);
1827 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1828 info
->surf
->logical_level0_px
.array_len
);
1831 isl_genX_call(dev
, surf_fill_state_s
, dev
, state
, info
);
1835 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1836 const struct isl_buffer_fill_state_info
*restrict info
)
1838 isl_genX_call(dev
, buffer_fill_state_s
, state
, info
);
1842 isl_null_fill_state(const struct isl_device
*dev
, void *state
,
1843 struct isl_extent3d size
)
1845 isl_genX_call(dev
, null_fill_state
, state
, size
);
1849 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
1850 const struct isl_depth_stencil_hiz_emit_info
*restrict info
)
1852 if (info
->depth_surf
&& info
->stencil_surf
) {
1853 if (!dev
->info
->has_hiz_and_separate_stencil
) {
1854 assert(info
->depth_surf
== info
->stencil_surf
);
1855 assert(info
->depth_address
== info
->stencil_address
);
1857 assert(info
->depth_surf
->dim
== info
->stencil_surf
->dim
);
1860 if (info
->depth_surf
) {
1861 assert((info
->depth_surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
));
1862 if (info
->depth_surf
->dim
== ISL_SURF_DIM_3D
) {
1863 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1864 info
->depth_surf
->logical_level0_px
.depth
);
1866 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1867 info
->depth_surf
->logical_level0_px
.array_len
);
1871 if (info
->stencil_surf
) {
1872 assert((info
->stencil_surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
));
1873 if (info
->stencil_surf
->dim
== ISL_SURF_DIM_3D
) {
1874 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1875 info
->stencil_surf
->logical_level0_px
.depth
);
1877 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1878 info
->stencil_surf
->logical_level0_px
.array_len
);
1882 isl_genX_call(dev
, emit_depth_stencil_hiz_s
, dev
, batch
, info
);
1886 * A variant of isl_surf_get_image_offset_sa() specific to
1887 * ISL_DIM_LAYOUT_GEN4_2D.
1890 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1891 uint32_t level
, uint32_t logical_array_layer
,
1892 uint32_t *x_offset_sa
,
1893 uint32_t *y_offset_sa
)
1895 assert(level
< surf
->levels
);
1896 if (surf
->dim
== ISL_SURF_DIM_3D
)
1897 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
1899 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1901 const struct isl_extent3d image_align_sa
=
1902 isl_surf_get_image_alignment_sa(surf
);
1904 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1905 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1907 const uint32_t phys_layer
= logical_array_layer
*
1908 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
1911 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1913 for (uint32_t l
= 0; l
< level
; ++l
) {
1915 uint32_t W
= isl_minify(W0
, l
);
1916 x
+= isl_align_npot(W
, image_align_sa
.w
);
1918 uint32_t H
= isl_minify(H0
, l
);
1919 y
+= isl_align_npot(H
, image_align_sa
.h
);
1928 * A variant of isl_surf_get_image_offset_sa() specific to
1929 * ISL_DIM_LAYOUT_GEN4_3D.
1932 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1933 uint32_t level
, uint32_t logical_z_offset_px
,
1934 uint32_t *x_offset_sa
,
1935 uint32_t *y_offset_sa
)
1937 assert(level
< surf
->levels
);
1938 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1939 assert(surf
->phys_level0_sa
.array_len
== 1);
1940 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1942 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1943 assert(surf
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
1944 assert(surf
->phys_level0_sa
.array_len
== 6);
1945 assert(logical_z_offset_px
< surf
->phys_level0_sa
.array_len
);
1948 const struct isl_extent3d image_align_sa
=
1949 isl_surf_get_image_alignment_sa(surf
);
1951 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1952 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1953 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1954 const uint32_t AL
= surf
->phys_level0_sa
.array_len
;
1959 for (uint32_t l
= 0; l
< level
; ++l
) {
1960 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1961 const uint32_t level_d
=
1962 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : AL
,
1964 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1966 y
+= level_h
* max_layers_vert
;
1969 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1970 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1971 const uint32_t level_d
=
1972 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, level
) : AL
,
1975 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1977 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1978 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
1985 get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf
*surf
,
1987 uint32_t logical_array_layer
,
1988 uint32_t *x_offset_sa
,
1989 uint32_t *y_offset_sa
)
1991 assert(level
< surf
->levels
);
1992 assert(surf
->logical_level0_px
.depth
== 1);
1993 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1995 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1997 const struct isl_extent3d image_align_sa
=
1998 isl_surf_get_image_alignment_sa(surf
);
2000 struct isl_tile_info tile_info
;
2001 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, &tile_info
);
2002 const struct isl_extent2d tile_extent_sa
= {
2003 .w
= tile_info
.logical_extent_el
.w
* fmtl
->bw
,
2004 .h
= tile_info
.logical_extent_el
.h
* fmtl
->bh
,
2006 /* Tile size is a multiple of image alignment */
2007 assert(tile_extent_sa
.w
% image_align_sa
.w
== 0);
2008 assert(tile_extent_sa
.h
% image_align_sa
.h
== 0);
2010 const uint32_t W0
= surf
->phys_level0_sa
.w
;
2011 const uint32_t H0
= surf
->phys_level0_sa
.h
;
2013 /* Each image has the same height as LOD0 because the hardware thinks
2014 * everything is LOD0
2016 const uint32_t H
= isl_align(H0
, image_align_sa
.h
);
2018 /* Quick sanity check for consistency */
2019 if (surf
->phys_level0_sa
.array_len
> 1)
2020 assert(surf
->array_pitch_el_rows
== isl_assert_div(H
, fmtl
->bh
));
2022 uint32_t x
= 0, y
= 0;
2023 for (uint32_t l
= 0; l
< level
; ++l
) {
2024 const uint32_t W
= isl_minify(W0
, l
);
2026 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
2027 const uint32_t h
= isl_align(H
* surf
->phys_level0_sa
.a
,
2037 y
+= H
* logical_array_layer
;
2044 * A variant of isl_surf_get_image_offset_sa() specific to
2045 * ISL_DIM_LAYOUT_GEN9_1D.
2048 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
2049 uint32_t level
, uint32_t layer
,
2050 uint32_t *x_offset_sa
,
2051 uint32_t *y_offset_sa
)
2053 assert(level
< surf
->levels
);
2054 assert(layer
< surf
->phys_level0_sa
.array_len
);
2055 assert(surf
->phys_level0_sa
.height
== 1);
2056 assert(surf
->phys_level0_sa
.depth
== 1);
2057 assert(surf
->samples
== 1);
2059 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2060 const struct isl_extent3d image_align_sa
=
2061 isl_surf_get_image_alignment_sa(surf
);
2065 for (uint32_t l
= 0; l
< level
; ++l
) {
2066 uint32_t W
= isl_minify(W0
, l
);
2067 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
2073 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2077 * Calculate the offset, in units of surface samples, to a subimage in the
2080 * @invariant level < surface levels
2081 * @invariant logical_array_layer < logical array length of surface
2082 * @invariant logical_z_offset_px < logical depth of surface at level
2085 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
2087 uint32_t logical_array_layer
,
2088 uint32_t logical_z_offset_px
,
2089 uint32_t *x_offset_sa
,
2090 uint32_t *y_offset_sa
)
2092 assert(level
< surf
->levels
);
2093 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2094 assert(logical_z_offset_px
2095 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2097 switch (surf
->dim_layout
) {
2098 case ISL_DIM_LAYOUT_GEN9_1D
:
2099 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
2100 x_offset_sa
, y_offset_sa
);
2102 case ISL_DIM_LAYOUT_GEN4_2D
:
2103 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
2104 + logical_z_offset_px
,
2105 x_offset_sa
, y_offset_sa
);
2107 case ISL_DIM_LAYOUT_GEN4_3D
:
2108 get_image_offset_sa_gen4_3d(surf
, level
, logical_array_layer
+
2109 logical_z_offset_px
,
2110 x_offset_sa
, y_offset_sa
);
2112 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
2113 get_image_offset_sa_gen6_stencil_hiz(surf
, level
, logical_array_layer
+
2114 logical_z_offset_px
,
2115 x_offset_sa
, y_offset_sa
);
2119 unreachable("not reached");
2124 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
2126 uint32_t logical_array_layer
,
2127 uint32_t logical_z_offset_px
,
2128 uint32_t *x_offset_el
,
2129 uint32_t *y_offset_el
)
2131 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2133 assert(level
< surf
->levels
);
2134 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2135 assert(logical_z_offset_px
2136 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2138 uint32_t x_offset_sa
, y_offset_sa
;
2139 isl_surf_get_image_offset_sa(surf
, level
,
2140 logical_array_layer
,
2141 logical_z_offset_px
,
2145 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
2146 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
2150 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
2152 uint32_t logical_array_layer
,
2153 uint32_t logical_z_offset_px
,
2155 uint32_t *x_offset_sa
,
2156 uint32_t *y_offset_sa
)
2158 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2160 uint32_t total_x_offset_el
, total_y_offset_el
;
2161 isl_surf_get_image_offset_el(surf
, level
, logical_array_layer
,
2162 logical_z_offset_px
,
2164 &total_y_offset_el
);
2166 uint32_t x_offset_el
, y_offset_el
;
2167 isl_tiling_get_intratile_offset_el(surf
->tiling
, fmtl
->bpb
,
2176 *x_offset_sa
= x_offset_el
* fmtl
->bw
;
2178 assert(x_offset_el
== 0);
2182 *y_offset_sa
= y_offset_el
* fmtl
->bh
;
2184 assert(y_offset_el
== 0);
2189 isl_surf_get_image_surf(const struct isl_device
*dev
,
2190 const struct isl_surf
*surf
,
2192 uint32_t logical_array_layer
,
2193 uint32_t logical_z_offset_px
,
2194 struct isl_surf
*image_surf
,
2196 uint32_t *x_offset_sa
,
2197 uint32_t *y_offset_sa
)
2199 isl_surf_get_image_offset_B_tile_sa(surf
,
2201 logical_array_layer
,
2202 logical_z_offset_px
,
2207 /* Even for cube maps there will be only single face, therefore drop the
2208 * corresponding flag if present.
2210 const isl_surf_usage_flags_t usage
=
2211 surf
->usage
& (~ISL_SURF_USAGE_CUBE_BIT
);
2214 ok
= isl_surf_init(dev
, image_surf
,
2215 .dim
= ISL_SURF_DIM_2D
,
2216 .format
= surf
->format
,
2217 .width
= isl_minify(surf
->logical_level0_px
.w
, level
),
2218 .height
= isl_minify(surf
->logical_level0_px
.h
, level
),
2222 .samples
= surf
->samples
,
2223 .row_pitch
= surf
->row_pitch
,
2225 .tiling_flags
= (1 << surf
->tiling
));
2230 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
2233 uint32_t total_x_offset_el
,
2234 uint32_t total_y_offset_el
,
2235 uint32_t *base_address_offset
,
2236 uint32_t *x_offset_el
,
2237 uint32_t *y_offset_el
)
2239 if (tiling
== ISL_TILING_LINEAR
) {
2240 assert(bpb
% 8 == 0);
2241 *base_address_offset
= total_y_offset_el
* row_pitch
+
2242 total_x_offset_el
* (bpb
/ 8);
2248 struct isl_tile_info tile_info
;
2249 isl_tiling_get_info(tiling
, bpb
, &tile_info
);
2251 assert(row_pitch
% tile_info
.phys_extent_B
.width
== 0);
2253 /* For non-power-of-two formats, we need the address to be both tile and
2254 * element-aligned. The easiest way to achieve this is to work with a tile
2255 * that is three times as wide as the regular tile.
2257 * The tile info returned by get_tile_info has a logical size that is an
2258 * integer number of tile_info.format_bpb size elements. To scale the
2259 * tile, we scale up the physical width and then treat the logical tile
2260 * size as if it has bpb size elements.
2262 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
2263 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
2265 /* Compute the offset into the tile */
2266 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
2267 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
2269 /* Compute the offset of the tile in units of whole tiles */
2270 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
2271 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
2273 *base_address_offset
=
2274 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch
+
2275 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
2279 isl_surf_get_depth_format(const struct isl_device
*dev
,
2280 const struct isl_surf
*surf
)
2282 /* Support for separate stencil buffers began in gen5. Support for
2283 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
2284 * those that supported separate and interleaved stencil, were gen5 and
2287 * For a list of all available formats, see the Sandybridge PRM >> Volume
2288 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
2292 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
2294 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
2297 assert(ISL_DEV_GEN(dev
) < 7);
2299 switch (surf
->format
) {
2301 unreachable("bad isl depth format");
2302 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
2303 assert(ISL_DEV_GEN(dev
) < 7);
2304 return 0; /* D32_FLOAT_S8X24_UINT */
2305 case ISL_FORMAT_R32_FLOAT
:
2306 assert(!has_stencil
);
2307 return 1; /* D32_FLOAT */
2308 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
2310 assert(ISL_DEV_GEN(dev
) < 7);
2311 return 2; /* D24_UNORM_S8_UINT */
2313 assert(ISL_DEV_GEN(dev
) >= 5);
2314 return 3; /* D24_UNORM_X8_UINT */
2316 case ISL_FORMAT_R16_UNORM
:
2317 assert(!has_stencil
);
2318 return 5; /* D16_UNORM */