2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "genxml/genX_bits.h"
39 isl_memcpy_linear_to_tiled(uint32_t xt1
, uint32_t xt2
,
40 uint32_t yt1
, uint32_t yt2
,
41 char *dst
, const char *src
,
42 uint32_t dst_pitch
, int32_t src_pitch
,
44 enum isl_tiling tiling
,
45 isl_memcpy_type copy_type
)
48 if (copy_type
== ISL_MEMCPY_STREAMING_LOAD
) {
49 _isl_memcpy_linear_to_tiled_sse41(
50 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
56 _isl_memcpy_linear_to_tiled(
57 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
62 isl_memcpy_tiled_to_linear(uint32_t xt1
, uint32_t xt2
,
63 uint32_t yt1
, uint32_t yt2
,
64 char *dst
, const char *src
,
65 int32_t dst_pitch
, uint32_t src_pitch
,
67 enum isl_tiling tiling
,
68 isl_memcpy_type copy_type
)
71 if (copy_type
== ISL_MEMCPY_STREAMING_LOAD
) {
72 _isl_memcpy_tiled_to_linear_sse41(
73 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
79 _isl_memcpy_tiled_to_linear(
80 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
84 void PRINTFLIKE(3, 4) UNUSED
85 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
91 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
94 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
98 isl_device_init(struct isl_device
*dev
,
99 const struct gen_device_info
*info
,
100 bool has_bit6_swizzling
)
102 /* Gen8+ don't have bit6 swizzling, ensure callsite is not confused. */
103 assert(!(has_bit6_swizzling
&& info
->gen
>= 8));
106 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
107 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
109 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
110 * device properties at buildtime. Verify that the macros with the device
111 * properties chosen during runtime.
113 ISL_DEV_GEN_SANITIZE(dev
);
114 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
116 /* Did we break hiz or stencil? */
117 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
118 assert(info
->has_hiz_and_separate_stencil
);
119 if (info
->must_use_separate_stencil
)
120 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
122 dev
->ss
.size
= RENDER_SURFACE_STATE_length(info
) * 4;
123 dev
->ss
.align
= isl_align(dev
->ss
.size
, 32);
125 dev
->ss
.clear_color_state_size
=
126 isl_align(CLEAR_COLOR_length(info
) * 4, 64);
127 dev
->ss
.clear_color_state_offset
=
128 RENDER_SURFACE_STATE_ClearValueAddress_start(info
) / 32 * 4;
130 dev
->ss
.clear_value_size
=
131 isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info
) +
132 RENDER_SURFACE_STATE_GreenClearColor_bits(info
) +
133 RENDER_SURFACE_STATE_BlueClearColor_bits(info
) +
134 RENDER_SURFACE_STATE_AlphaClearColor_bits(info
), 32) / 8;
136 dev
->ss
.clear_value_offset
=
137 RENDER_SURFACE_STATE_RedClearColor_start(info
) / 32 * 4;
139 assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) % 8 == 0);
140 dev
->ss
.addr_offset
=
141 RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) / 8;
143 /* The "Auxiliary Surface Base Address" field starts a bit higher up
144 * because the bottom 12 bits are used for other things. Round down to
145 * the nearest dword before.
147 dev
->ss
.aux_addr_offset
=
148 (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info
) & ~31) / 8;
150 dev
->ds
.size
= _3DSTATE_DEPTH_BUFFER_length(info
) * 4;
151 assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
152 dev
->ds
.depth_offset
=
153 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
155 if (dev
->use_separate_stencil
) {
156 dev
->ds
.size
+= _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
157 _3DSTATE_HIER_DEPTH_BUFFER_length(info
) * 4 +
158 _3DSTATE_CLEAR_PARAMS_length(info
) * 4;
160 assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
161 dev
->ds
.stencil_offset
=
162 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
163 _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) / 8;
165 assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
167 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
168 _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
169 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
171 dev
->ds
.stencil_offset
= 0;
172 dev
->ds
.hiz_offset
= 0;
177 * @brief Query the set of multisamples supported by the device.
179 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
182 isl_sample_count_mask_t ATTRIBUTE_CONST
183 isl_device_get_sample_counts(struct isl_device
*dev
)
185 if (ISL_DEV_GEN(dev
) >= 9) {
186 return ISL_SAMPLE_COUNT_1_BIT
|
187 ISL_SAMPLE_COUNT_2_BIT
|
188 ISL_SAMPLE_COUNT_4_BIT
|
189 ISL_SAMPLE_COUNT_8_BIT
|
190 ISL_SAMPLE_COUNT_16_BIT
;
191 } else if (ISL_DEV_GEN(dev
) >= 8) {
192 return ISL_SAMPLE_COUNT_1_BIT
|
193 ISL_SAMPLE_COUNT_2_BIT
|
194 ISL_SAMPLE_COUNT_4_BIT
|
195 ISL_SAMPLE_COUNT_8_BIT
;
196 } else if (ISL_DEV_GEN(dev
) >= 7) {
197 return ISL_SAMPLE_COUNT_1_BIT
|
198 ISL_SAMPLE_COUNT_4_BIT
|
199 ISL_SAMPLE_COUNT_8_BIT
;
200 } else if (ISL_DEV_GEN(dev
) >= 6) {
201 return ISL_SAMPLE_COUNT_1_BIT
|
202 ISL_SAMPLE_COUNT_4_BIT
;
204 return ISL_SAMPLE_COUNT_1_BIT
;
209 * @param[out] info is written only on success
212 isl_tiling_get_info(enum isl_tiling tiling
,
214 struct isl_tile_info
*tile_info
)
216 const uint32_t bs
= format_bpb
/ 8;
217 struct isl_extent2d logical_el
, phys_B
;
219 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
220 /* It is possible to have non-power-of-two formats in a tiled buffer.
221 * The easiest way to handle this is to treat the tile as if it is three
222 * times as wide. This way no pixel will ever cross a tile boundary.
223 * This really only works on legacy X and Y tiling formats.
225 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
226 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
227 isl_tiling_get_info(tiling
, format_bpb
/ 3, tile_info
);
232 case ISL_TILING_LINEAR
:
234 logical_el
= isl_extent2d(1, 1);
235 phys_B
= isl_extent2d(bs
, 1);
240 logical_el
= isl_extent2d(512 / bs
, 8);
241 phys_B
= isl_extent2d(512, 8);
246 logical_el
= isl_extent2d(128 / bs
, 32);
247 phys_B
= isl_extent2d(128, 32);
252 logical_el
= isl_extent2d(64, 64);
253 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
255 * "If the surface is a stencil buffer (and thus has Tile Mode set
256 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
257 * computed based on width, as the stencil buffer is stored with two
260 * This, together with the fact that stencil buffers are referred to as
261 * being Y-tiled in the PRMs for older hardware implies that the
262 * physical size of a W-tile is actually the same as for a Y-tile.
264 phys_B
= isl_extent2d(128, 32);
268 case ISL_TILING_Ys
: {
269 bool is_Ys
= tiling
== ISL_TILING_Ys
;
272 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
273 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
275 logical_el
= isl_extent2d(width
/ bs
, height
);
276 phys_B
= isl_extent2d(width
, height
);
281 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
282 * 128bpb format. The tiling has the same physical dimensions as
283 * Y-tiling but actually has two HiZ columns per Y-tiled column.
286 logical_el
= isl_extent2d(16, 16);
287 phys_B
= isl_extent2d(128, 32);
291 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
292 * have a block size of 1 or 2 bits per block and each CCS element
293 * corresponds to one cache-line pair in the main surface. From the Sky
294 * Lake PRM Vol. 12 in the section on planes:
296 * "The Color Control Surface (CCS) contains the compression status
297 * of the cache-line pairs. The compression state of the cache-line
298 * pair is specified by 2 bits in the CCS. Each CCS cache-line
299 * represents an area on the main surface of 16x16 sets of 128 byte
300 * Y-tiled cache-line-pairs. CCS is always Y tiled."
302 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
303 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
304 * that yields total tile area of 128x128 cache-line pairs or CCS
305 * elements. On older hardware, each CCS element is 1 bit and the tile
306 * is 128x256 elements.
308 assert(format_bpb
== 1 || format_bpb
== 2);
309 logical_el
= isl_extent2d(128, 256 / format_bpb
);
310 phys_B
= isl_extent2d(128, 32);
314 unreachable("not reached");
317 *tile_info
= (struct isl_tile_info
) {
319 .format_bpb
= format_bpb
,
320 .logical_extent_el
= logical_el
,
321 .phys_extent_B
= phys_B
,
326 isl_color_value_is_zero(union isl_color_value value
,
327 enum isl_format format
)
329 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
331 #define RETURN_FALSE_IF_NOT_0(c, i) \
332 if (fmtl->channels.c.bits && value.u32[i] != 0) \
335 RETURN_FALSE_IF_NOT_0(r
, 0);
336 RETURN_FALSE_IF_NOT_0(g
, 1);
337 RETURN_FALSE_IF_NOT_0(b
, 2);
338 RETURN_FALSE_IF_NOT_0(a
, 3);
340 #undef RETURN_FALSE_IF_NOT_0
346 isl_color_value_is_zero_one(union isl_color_value value
,
347 enum isl_format format
)
349 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
351 #define RETURN_FALSE_IF_NOT_0_1(c, i, field) \
352 if (fmtl->channels.c.bits && value.field[i] != 0 && value.field[i] != 1) \
355 if (isl_format_has_int_channel(format
)) {
356 RETURN_FALSE_IF_NOT_0_1(r
, 0, u32
);
357 RETURN_FALSE_IF_NOT_0_1(g
, 1, u32
);
358 RETURN_FALSE_IF_NOT_0_1(b
, 2, u32
);
359 RETURN_FALSE_IF_NOT_0_1(a
, 3, u32
);
361 RETURN_FALSE_IF_NOT_0_1(r
, 0, f32
);
362 RETURN_FALSE_IF_NOT_0_1(g
, 1, f32
);
363 RETURN_FALSE_IF_NOT_0_1(b
, 2, f32
);
364 RETURN_FALSE_IF_NOT_0_1(a
, 3, f32
);
367 #undef RETURN_FALSE_IF_NOT_0_1
373 * @param[out] tiling is set only on success
376 isl_surf_choose_tiling(const struct isl_device
*dev
,
377 const struct isl_surf_init_info
*restrict info
,
378 enum isl_tiling
*tiling
)
380 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
382 /* HiZ surfaces always use the HiZ tiling */
383 if (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) {
384 assert(info
->format
== ISL_FORMAT_HIZ
);
385 assert(tiling_flags
== ISL_TILING_HIZ_BIT
);
386 *tiling
= ISL_TILING_HIZ
;
390 /* CCS surfaces always use the CCS tiling */
391 if (info
->usage
& ISL_SURF_USAGE_CCS_BIT
) {
392 assert(isl_format_get_layout(info
->format
)->txc
== ISL_TXC_CCS
);
393 assert(tiling_flags
== ISL_TILING_CCS_BIT
);
394 *tiling
= ISL_TILING_CCS
;
398 if (ISL_DEV_GEN(dev
) >= 6) {
399 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
401 isl_gen4_filter_tiling(dev
, info
, &tiling_flags
);
404 #define CHOOSE(__tiling) \
406 if (tiling_flags & (1u << (__tiling))) { \
407 *tiling = (__tiling); \
412 /* Of the tiling modes remaining, choose the one that offers the best
416 if (info
->dim
== ISL_SURF_DIM_1D
) {
417 /* Prefer linear for 1D surfaces because they do not benefit from
418 * tiling. To the contrary, tiling leads to wasted memory and poor
419 * memory locality due to the swizzling and alignment restrictions
420 * required in tiled surfaces.
422 CHOOSE(ISL_TILING_LINEAR
);
425 CHOOSE(ISL_TILING_Ys
);
426 CHOOSE(ISL_TILING_Yf
);
427 CHOOSE(ISL_TILING_Y0
);
428 CHOOSE(ISL_TILING_X
);
429 CHOOSE(ISL_TILING_W
);
430 CHOOSE(ISL_TILING_LINEAR
);
434 /* No tiling mode accomodates the inputs. */
439 isl_choose_msaa_layout(const struct isl_device
*dev
,
440 const struct isl_surf_init_info
*info
,
441 enum isl_tiling tiling
,
442 enum isl_msaa_layout
*msaa_layout
)
444 if (ISL_DEV_GEN(dev
) >= 8) {
445 return isl_gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
446 } else if (ISL_DEV_GEN(dev
) >= 7) {
447 return isl_gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
448 } else if (ISL_DEV_GEN(dev
) >= 6) {
449 return isl_gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
451 return isl_gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
456 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
458 assert(isl_is_pow2(samples
));
460 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
463 * If the surface is multisampled and it is a depth or stencil surface
464 * or Multisampled Surface StorageFormat in SURFACE_STATE is
465 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
468 return (struct isl_extent2d
) {
469 .width
= 1 << ((ffs(samples
) - 0) / 2),
470 .height
= 1 << ((ffs(samples
) - 1) / 2),
475 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
476 uint32_t *width
, uint32_t *height
)
478 const struct isl_extent2d px_size_sa
=
479 isl_get_interleaved_msaa_px_size_sa(samples
);
482 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
484 *height
= isl_align(*height
, 2) * px_size_sa
.height
;
487 static enum isl_array_pitch_span
488 isl_choose_array_pitch_span(const struct isl_device
*dev
,
489 const struct isl_surf_init_info
*restrict info
,
490 enum isl_dim_layout dim_layout
,
491 const struct isl_extent4d
*phys_level0_sa
)
493 switch (dim_layout
) {
494 case ISL_DIM_LAYOUT_GEN9_1D
:
495 case ISL_DIM_LAYOUT_GEN4_2D
:
496 if (ISL_DEV_GEN(dev
) >= 8) {
497 /* QPitch becomes programmable in Broadwell. So choose the
498 * most compact QPitch possible in order to conserve memory.
500 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
501 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
503 * - Software must ensure that this field is set to a value
504 * sufficiently large such that the array slices in the surface
505 * do not overlap. Refer to the Memory Data Formats section for
506 * information on how surfaces are stored in memory.
508 * - This field specifies the distance in rows between array
509 * slices. It is used only in the following cases:
511 * - Surface Array is enabled OR
512 * - Number of Mulitsamples is not NUMSAMPLES_1 and
513 * Multisampled Surface Storage Format set to MSFMT_MSS OR
514 * - Surface Type is SURFTYPE_CUBE
516 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
517 } else if (ISL_DEV_GEN(dev
) >= 7) {
518 /* Note that Ivybridge introduces
519 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
520 * driver more control over the QPitch.
523 if (phys_level0_sa
->array_len
== 1) {
524 /* The hardware will never use the QPitch. So choose the most
525 * compact QPitch possible in order to conserve memory.
527 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
530 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
531 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
532 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
533 * Section 6.18.4.7: Surface Arrays (p112):
535 * If Surface Array Spacing is set to ARYSPC_FULL (note that
536 * the depth buffer and stencil buffer have an implied value of
539 return ISL_ARRAY_PITCH_SPAN_FULL
;
542 if (info
->levels
== 1) {
543 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
546 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
549 return ISL_ARRAY_PITCH_SPAN_FULL
;
550 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
551 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
552 isl_surf_usage_is_stencil(info
->usage
)) {
553 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
554 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
556 * The separate stencil buffer does not support mip mapping, thus
557 * the storage for LODs other than LOD 0 is not needed.
559 assert(info
->levels
== 1);
560 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
562 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
563 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
564 isl_surf_usage_is_stencil(info
->usage
)) {
565 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
566 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
568 * The separate stencil buffer does not support mip mapping,
569 * thus the storage for LODs other than LOD 0 is not needed.
571 assert(info
->levels
== 1);
572 assert(phys_level0_sa
->array_len
== 1);
573 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
576 if (phys_level0_sa
->array_len
== 1) {
577 /* The hardware will never use the QPitch. So choose the most
578 * compact QPitch possible in order to conserve memory.
580 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
583 return ISL_ARRAY_PITCH_SPAN_FULL
;
586 case ISL_DIM_LAYOUT_GEN4_3D
:
587 /* The hardware will never use the QPitch. So choose the most
588 * compact QPitch possible in order to conserve memory.
590 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
592 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
593 /* Each array image in the gen6 stencil of HiZ surface is compact in the
594 * sense that every LOD is a compact array of the same size as LOD0.
596 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
599 unreachable("bad isl_dim_layout");
600 return ISL_ARRAY_PITCH_SPAN_FULL
;
604 isl_choose_image_alignment_el(const struct isl_device
*dev
,
605 const struct isl_surf_init_info
*restrict info
,
606 enum isl_tiling tiling
,
607 enum isl_dim_layout dim_layout
,
608 enum isl_msaa_layout msaa_layout
,
609 struct isl_extent3d
*image_align_el
)
611 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
612 if (fmtl
->txc
== ISL_TXC_MCS
) {
613 assert(tiling
== ISL_TILING_Y0
);
616 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
618 * Height, width, and layout of MCS buffer in this case must match with
619 * Render Target height, width, and layout. MCS buffer is tiledY.
621 * To avoid wasting memory, choose the smallest alignment possible:
622 * HALIGN_4 and VALIGN_4.
624 *image_align_el
= isl_extent3d(4, 4, 1);
626 } else if (info
->format
== ISL_FORMAT_HIZ
) {
627 assert(ISL_DEV_GEN(dev
) >= 6);
628 if (ISL_DEV_GEN(dev
) == 6) {
629 /* HiZ surfaces on Sandy Bridge are packed tightly. */
630 *image_align_el
= isl_extent3d(1, 1, 1);
632 /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the
633 * primary surface which works out to 2x2 HiZ elments.
635 *image_align_el
= isl_extent3d(2, 2, 1);
640 if (ISL_DEV_GEN(dev
) >= 9) {
641 isl_gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
642 msaa_layout
, image_align_el
);
643 } else if (ISL_DEV_GEN(dev
) >= 8) {
644 isl_gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
645 msaa_layout
, image_align_el
);
646 } else if (ISL_DEV_GEN(dev
) >= 7) {
647 isl_gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
648 msaa_layout
, image_align_el
);
649 } else if (ISL_DEV_GEN(dev
) >= 6) {
650 isl_gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
651 msaa_layout
, image_align_el
);
653 isl_gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
654 msaa_layout
, image_align_el
);
658 static enum isl_dim_layout
659 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
660 enum isl_surf_dim logical_dim
,
661 enum isl_tiling tiling
,
662 isl_surf_usage_flags_t usage
)
664 /* Sandy bridge needs a special layout for HiZ and stencil. */
665 if (ISL_DEV_GEN(dev
) == 6 &&
666 (tiling
== ISL_TILING_W
|| tiling
== ISL_TILING_HIZ
))
667 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
669 if (ISL_DEV_GEN(dev
) >= 9) {
670 switch (logical_dim
) {
671 case ISL_SURF_DIM_1D
:
672 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
674 * One-dimensional surfaces use a tiling mode of linear.
675 * Technically, they are not tiled resources, but the Tiled
676 * Resource Mode field in RENDER_SURFACE_STATE is still used to
677 * indicate the alignment requirements for this linear surface
678 * (See 1D Alignment requirements for how 4K and 64KB Tiled
679 * Resource Modes impact alignment). Alternatively, a 1D surface
680 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
683 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
684 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
686 if (tiling
== ISL_TILING_LINEAR
)
687 return ISL_DIM_LAYOUT_GEN9_1D
;
689 return ISL_DIM_LAYOUT_GEN4_2D
;
690 case ISL_SURF_DIM_2D
:
691 case ISL_SURF_DIM_3D
:
692 return ISL_DIM_LAYOUT_GEN4_2D
;
695 switch (logical_dim
) {
696 case ISL_SURF_DIM_1D
:
697 case ISL_SURF_DIM_2D
:
698 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
700 * The cube face textures are stored in the same way as 3D surfaces
701 * are stored (see section 6.17.5 for details). For cube surfaces,
702 * however, the depth is equal to the number of faces (always 6) and
703 * is not reduced for each MIP.
705 if (ISL_DEV_GEN(dev
) == 4 && (usage
& ISL_SURF_USAGE_CUBE_BIT
))
706 return ISL_DIM_LAYOUT_GEN4_3D
;
708 return ISL_DIM_LAYOUT_GEN4_2D
;
709 case ISL_SURF_DIM_3D
:
710 return ISL_DIM_LAYOUT_GEN4_3D
;
714 unreachable("bad isl_surf_dim");
715 return ISL_DIM_LAYOUT_GEN4_2D
;
719 * Calculate the physical extent of the surface's first level, in units of
720 * surface samples. The result is aligned to the format's compression block.
723 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
724 const struct isl_surf_init_info
*restrict info
,
725 enum isl_dim_layout dim_layout
,
726 enum isl_tiling tiling
,
727 enum isl_msaa_layout msaa_layout
,
728 struct isl_extent4d
*phys_level0_sa
)
730 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
732 if (isl_format_is_yuv(info
->format
))
733 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
736 case ISL_SURF_DIM_1D
:
737 assert(info
->height
== 1);
738 assert(info
->depth
== 1);
739 assert(info
->samples
== 1);
741 switch (dim_layout
) {
742 case ISL_DIM_LAYOUT_GEN4_3D
:
743 unreachable("bad isl_dim_layout");
745 case ISL_DIM_LAYOUT_GEN9_1D
:
746 case ISL_DIM_LAYOUT_GEN4_2D
:
747 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
748 *phys_level0_sa
= (struct isl_extent4d
) {
749 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
752 .a
= info
->array_len
,
758 case ISL_SURF_DIM_2D
:
759 if (ISL_DEV_GEN(dev
) == 4 && (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
))
760 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_3D
);
762 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
||
763 dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
765 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
766 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
768 switch (msaa_layout
) {
769 case ISL_MSAA_LAYOUT_NONE
:
770 assert(info
->depth
== 1);
771 assert(info
->samples
== 1);
773 *phys_level0_sa
= (struct isl_extent4d
) {
774 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
775 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
777 .a
= info
->array_len
,
781 case ISL_MSAA_LAYOUT_ARRAY
:
782 assert(info
->depth
== 1);
783 assert(info
->levels
== 1);
784 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
785 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
787 *phys_level0_sa
= (struct isl_extent4d
) {
791 .a
= info
->array_len
* info
->samples
,
795 case ISL_MSAA_LAYOUT_INTERLEAVED
:
796 assert(info
->depth
== 1);
797 assert(info
->levels
== 1);
798 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
800 *phys_level0_sa
= (struct isl_extent4d
) {
804 .a
= info
->array_len
,
807 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
811 phys_level0_sa
->w
= isl_align(phys_level0_sa
->w
, fmtl
->bw
);
812 phys_level0_sa
->h
= isl_align(phys_level0_sa
->h
, fmtl
->bh
);
817 case ISL_SURF_DIM_3D
:
818 assert(info
->array_len
== 1);
819 assert(info
->samples
== 1);
822 isl_finishme("%s:%s: compression block with depth > 1",
826 switch (dim_layout
) {
827 case ISL_DIM_LAYOUT_GEN9_1D
:
828 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
829 unreachable("bad isl_dim_layout");
831 case ISL_DIM_LAYOUT_GEN4_2D
:
832 assert(ISL_DEV_GEN(dev
) >= 9);
834 *phys_level0_sa
= (struct isl_extent4d
) {
835 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
836 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
842 case ISL_DIM_LAYOUT_GEN4_3D
:
843 assert(ISL_DEV_GEN(dev
) < 9);
844 *phys_level0_sa
= (struct isl_extent4d
) {
845 .w
= isl_align(info
->width
, fmtl
->bw
),
846 .h
= isl_align(info
->height
, fmtl
->bh
),
857 * Calculate the pitch between physical array slices, in units of rows of
861 isl_calc_array_pitch_el_rows_gen4_2d(
862 const struct isl_device
*dev
,
863 const struct isl_surf_init_info
*restrict info
,
864 const struct isl_tile_info
*tile_info
,
865 const struct isl_extent3d
*image_align_sa
,
866 const struct isl_extent4d
*phys_level0_sa
,
867 enum isl_array_pitch_span array_pitch_span
,
868 const struct isl_extent2d
*phys_slice0_sa
)
870 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
871 uint32_t pitch_sa_rows
= 0;
873 switch (array_pitch_span
) {
874 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
875 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
877 case ISL_ARRAY_PITCH_SPAN_FULL
: {
878 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
879 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
880 * Surfaces >> Surface Arrays.
882 uint32_t H0_sa
= phys_level0_sa
->h
;
883 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
885 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
886 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
889 if (ISL_DEV_GEN(dev
) >= 7) {
890 /* The QPitch equation changed slightly in Ivybridge. */
896 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
898 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
899 (info
->height
% 4 == 1)) {
900 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
901 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
903 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
904 * the value calculated in the equation above , for every
905 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
907 * XXX(chadv): Is the errata natural corollary of the physical
908 * layout of interleaved samples?
913 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
918 assert(pitch_sa_rows
% fmtl
->bh
== 0);
919 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
921 if (ISL_DEV_GEN(dev
) >= 9 && fmtl
->txc
== ISL_TXC_CCS
) {
923 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
925 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
926 * layout with these alignments in the RT space: Horizontal
927 * Alignment = 128 and Vertical Alignment = 64."
929 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
931 * "For non-multisampled render target's CCS auxiliary surface,
932 * QPitch must be computed with Horizontal Alignment = 128 and
933 * Surface Vertical Alignment = 256. These alignments are only for
934 * CCS buffer and not for associated render target."
936 * The first restriction is already handled by isl_choose_image_alignment_el
937 * but the second restriction, which is an extension of the first, only
938 * applies to qpitch and must be applied here.
940 assert(fmtl
->bh
== 4);
941 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
944 if (ISL_DEV_GEN(dev
) >= 9 &&
945 info
->dim
== ISL_SURF_DIM_3D
&&
946 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
947 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
949 * Tile Mode != Linear: This field must be set to an integer multiple
952 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
955 return pitch_el_rows
;
959 * A variant of isl_calc_phys_slice0_extent_sa() specific to
960 * ISL_DIM_LAYOUT_GEN4_2D.
963 isl_calc_phys_slice0_extent_sa_gen4_2d(
964 const struct isl_device
*dev
,
965 const struct isl_surf_init_info
*restrict info
,
966 enum isl_msaa_layout msaa_layout
,
967 const struct isl_extent3d
*image_align_sa
,
968 const struct isl_extent4d
*phys_level0_sa
,
969 struct isl_extent2d
*phys_slice0_sa
)
971 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
973 assert(phys_level0_sa
->depth
== 1);
975 if (info
->levels
== 1) {
976 /* Do not pad the surface to the image alignment. Instead, pad it only
977 * to the pixel format's block alignment.
979 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
980 * cycles on the below mipmap layout caluclations. Reducing the
981 * alignment here is safe because we later align the row pitch and array
982 * pitch to the tile boundary. It is safe even for
983 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
984 * to accomodate the interleaved samples.
986 * For linear surfaces, reducing the alignment here permits us to later
987 * choose an arbitrary, non-aligned row pitch. If the surface backs
988 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
989 * VkBufferImageCopy::bufferRowLength.
991 *phys_slice0_sa
= (struct isl_extent2d
) {
992 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
993 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
998 uint32_t slice_top_w
= 0;
999 uint32_t slice_bottom_w
= 0;
1000 uint32_t slice_left_h
= 0;
1001 uint32_t slice_right_h
= 0;
1003 uint32_t W0
= phys_level0_sa
->w
;
1004 uint32_t H0
= phys_level0_sa
->h
;
1006 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1007 uint32_t W
= isl_minify(W0
, l
);
1008 uint32_t H
= isl_minify(H0
, l
);
1010 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1011 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
1017 } else if (l
== 1) {
1020 } else if (l
== 2) {
1021 slice_bottom_w
+= w
;
1028 *phys_slice0_sa
= (struct isl_extent2d
) {
1029 .w
= MAX(slice_top_w
, slice_bottom_w
),
1030 .h
= MAX(slice_left_h
, slice_right_h
),
1035 isl_calc_phys_total_extent_el_gen4_2d(
1036 const struct isl_device
*dev
,
1037 const struct isl_surf_init_info
*restrict info
,
1038 const struct isl_tile_info
*tile_info
,
1039 enum isl_msaa_layout msaa_layout
,
1040 const struct isl_extent3d
*image_align_sa
,
1041 const struct isl_extent4d
*phys_level0_sa
,
1042 enum isl_array_pitch_span array_pitch_span
,
1043 uint32_t *array_pitch_el_rows
,
1044 struct isl_extent2d
*total_extent_el
)
1046 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1048 struct isl_extent2d phys_slice0_sa
;
1049 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
1050 image_align_sa
, phys_level0_sa
,
1052 *array_pitch_el_rows
=
1053 isl_calc_array_pitch_el_rows_gen4_2d(dev
, info
, tile_info
,
1054 image_align_sa
, phys_level0_sa
,
1057 *total_extent_el
= (struct isl_extent2d
) {
1058 .w
= isl_assert_div(phys_slice0_sa
.w
, fmtl
->bw
),
1059 .h
= *array_pitch_el_rows
* (phys_level0_sa
->array_len
- 1) +
1060 isl_assert_div(phys_slice0_sa
.h
, fmtl
->bh
),
1065 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1066 * ISL_DIM_LAYOUT_GEN4_3D.
1069 isl_calc_phys_total_extent_el_gen4_3d(
1070 const struct isl_device
*dev
,
1071 const struct isl_surf_init_info
*restrict info
,
1072 const struct isl_extent3d
*image_align_sa
,
1073 const struct isl_extent4d
*phys_level0_sa
,
1074 uint32_t *array_pitch_el_rows
,
1075 struct isl_extent2d
*phys_total_el
)
1077 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1079 assert(info
->samples
== 1);
1081 if (info
->dim
!= ISL_SURF_DIM_3D
) {
1082 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
1084 * The cube face textures are stored in the same way as 3D surfaces
1085 * are stored (see section 6.17.5 for details). For cube surfaces,
1086 * however, the depth is equal to the number of faces (always 6) and
1087 * is not reduced for each MIP.
1089 assert(ISL_DEV_GEN(dev
) == 4);
1090 assert(info
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
1091 assert(phys_level0_sa
->array_len
== 6);
1093 assert(phys_level0_sa
->array_len
== 1);
1096 uint32_t total_w
= 0;
1097 uint32_t total_h
= 0;
1099 uint32_t W0
= phys_level0_sa
->w
;
1100 uint32_t H0
= phys_level0_sa
->h
;
1101 uint32_t D0
= phys_level0_sa
->d
;
1102 uint32_t A0
= phys_level0_sa
->a
;
1104 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1105 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
1106 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
1107 uint32_t level_d
= info
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : A0
;
1109 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
1110 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1112 total_w
= MAX(total_w
, level_w
* max_layers_horiz
);
1113 total_h
+= level_h
* max_layers_vert
;
1116 /* GEN4_3D layouts don't really have an array pitch since each LOD has a
1117 * different number of horizontal and vertical layers. We have to set it
1118 * to something, so at least make it true for LOD0.
1120 *array_pitch_el_rows
=
1121 isl_align_npot(phys_level0_sa
->h
, image_align_sa
->h
) / fmtl
->bw
;
1122 *phys_total_el
= (struct isl_extent2d
) {
1123 .w
= isl_assert_div(total_w
, fmtl
->bw
),
1124 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1129 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1130 * ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ.
1133 isl_calc_phys_total_extent_el_gen6_stencil_hiz(
1134 const struct isl_device
*dev
,
1135 const struct isl_surf_init_info
*restrict info
,
1136 const struct isl_tile_info
*tile_info
,
1137 const struct isl_extent3d
*image_align_sa
,
1138 const struct isl_extent4d
*phys_level0_sa
,
1139 uint32_t *array_pitch_el_rows
,
1140 struct isl_extent2d
*phys_total_el
)
1142 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1144 const struct isl_extent2d tile_extent_sa
= {
1145 .w
= tile_info
->logical_extent_el
.w
* fmtl
->bw
,
1146 .h
= tile_info
->logical_extent_el
.h
* fmtl
->bh
,
1148 /* Tile size is a multiple of image alignment */
1149 assert(tile_extent_sa
.w
% image_align_sa
->w
== 0);
1150 assert(tile_extent_sa
.h
% image_align_sa
->h
== 0);
1152 const uint32_t W0
= phys_level0_sa
->w
;
1153 const uint32_t H0
= phys_level0_sa
->h
;
1155 /* Each image has the same height as LOD0 because the hardware thinks
1156 * everything is LOD0
1158 const uint32_t H
= isl_align(H0
, image_align_sa
->h
) * phys_level0_sa
->a
;
1160 uint32_t total_top_w
= 0;
1161 uint32_t total_bottom_w
= 0;
1162 uint32_t total_h
= 0;
1164 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1165 const uint32_t W
= isl_minify(W0
, l
);
1167 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
1168 const uint32_t h
= isl_align(H
, tile_extent_sa
.h
);
1173 } else if (l
== 1) {
1177 total_bottom_w
+= w
;
1181 *array_pitch_el_rows
=
1182 isl_assert_div(isl_align(H0
, image_align_sa
->h
), fmtl
->bh
);
1183 *phys_total_el
= (struct isl_extent2d
) {
1184 .w
= isl_assert_div(MAX(total_top_w
, total_bottom_w
), fmtl
->bw
),
1185 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1190 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1191 * ISL_DIM_LAYOUT_GEN9_1D.
1194 isl_calc_phys_total_extent_el_gen9_1d(
1195 const struct isl_device
*dev
,
1196 const struct isl_surf_init_info
*restrict info
,
1197 const struct isl_extent3d
*image_align_sa
,
1198 const struct isl_extent4d
*phys_level0_sa
,
1199 uint32_t *array_pitch_el_rows
,
1200 struct isl_extent2d
*phys_total_el
)
1202 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1204 assert(phys_level0_sa
->height
/ fmtl
->bh
== 1);
1205 assert(phys_level0_sa
->depth
== 1);
1206 assert(info
->samples
== 1);
1207 assert(image_align_sa
->w
>= fmtl
->bw
);
1209 uint32_t slice_w
= 0;
1210 const uint32_t W0
= phys_level0_sa
->w
;
1212 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1213 uint32_t W
= isl_minify(W0
, l
);
1214 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1219 *array_pitch_el_rows
= 1;
1220 *phys_total_el
= (struct isl_extent2d
) {
1221 .w
= isl_assert_div(slice_w
, fmtl
->bw
),
1222 .h
= phys_level0_sa
->array_len
,
1227 * Calculate the two-dimensional total physical extent of the surface, in
1228 * units of surface elements.
1231 isl_calc_phys_total_extent_el(const struct isl_device
*dev
,
1232 const struct isl_surf_init_info
*restrict info
,
1233 const struct isl_tile_info
*tile_info
,
1234 enum isl_dim_layout dim_layout
,
1235 enum isl_msaa_layout msaa_layout
,
1236 const struct isl_extent3d
*image_align_sa
,
1237 const struct isl_extent4d
*phys_level0_sa
,
1238 enum isl_array_pitch_span array_pitch_span
,
1239 uint32_t *array_pitch_el_rows
,
1240 struct isl_extent2d
*total_extent_el
)
1242 switch (dim_layout
) {
1243 case ISL_DIM_LAYOUT_GEN9_1D
:
1244 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1245 isl_calc_phys_total_extent_el_gen9_1d(dev
, info
,
1246 image_align_sa
, phys_level0_sa
,
1247 array_pitch_el_rows
,
1250 case ISL_DIM_LAYOUT_GEN4_2D
:
1251 isl_calc_phys_total_extent_el_gen4_2d(dev
, info
, tile_info
, msaa_layout
,
1252 image_align_sa
, phys_level0_sa
,
1254 array_pitch_el_rows
,
1257 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
1258 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1259 isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev
, info
, tile_info
,
1262 array_pitch_el_rows
,
1265 case ISL_DIM_LAYOUT_GEN4_3D
:
1266 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1267 isl_calc_phys_total_extent_el_gen4_3d(dev
, info
,
1268 image_align_sa
, phys_level0_sa
,
1269 array_pitch_el_rows
,
1276 isl_calc_row_pitch_alignment(const struct isl_surf_init_info
*surf_info
,
1277 const struct isl_tile_info
*tile_info
)
1279 if (tile_info
->tiling
!= ISL_TILING_LINEAR
)
1280 return tile_info
->phys_extent_B
.width
;
1282 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1283 * RENDER_SURFACE_STATE Surface Pitch (p349):
1285 * - For linear render target surfaces and surfaces accessed with the
1286 * typed data port messages, the pitch must be a multiple of the
1287 * element size for non-YUV surface formats. Pitch must be
1288 * a multiple of 2 * element size for YUV surface formats.
1290 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1291 * ignore because isl doesn't do buffers.]
1293 * - For other linear surfaces, the pitch can be any multiple of
1296 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1297 const uint32_t bs
= fmtl
->bpb
/ 8;
1299 if (surf_info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1300 if (isl_format_is_yuv(surf_info
->format
)) {
1311 isl_calc_linear_min_row_pitch(const struct isl_device
*dev
,
1312 const struct isl_surf_init_info
*info
,
1313 const struct isl_extent2d
*phys_total_el
,
1314 uint32_t alignment_B
)
1316 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1317 const uint32_t bs
= fmtl
->bpb
/ 8;
1319 return isl_align_npot(bs
* phys_total_el
->w
, alignment_B
);
1323 isl_calc_tiled_min_row_pitch(const struct isl_device
*dev
,
1324 const struct isl_surf_init_info
*surf_info
,
1325 const struct isl_tile_info
*tile_info
,
1326 const struct isl_extent2d
*phys_total_el
,
1327 uint32_t alignment_B
)
1329 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1331 assert(fmtl
->bpb
% tile_info
->format_bpb
== 0);
1333 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
->format_bpb
;
1334 const uint32_t total_w_tl
=
1335 isl_align_div(phys_total_el
->w
* tile_el_scale
,
1336 tile_info
->logical_extent_el
.width
);
1338 assert(alignment_B
== tile_info
->phys_extent_B
.width
);
1339 return total_w_tl
* tile_info
->phys_extent_B
.width
;
1343 isl_calc_min_row_pitch(const struct isl_device
*dev
,
1344 const struct isl_surf_init_info
*surf_info
,
1345 const struct isl_tile_info
*tile_info
,
1346 const struct isl_extent2d
*phys_total_el
,
1347 uint32_t alignment_B
)
1349 if (tile_info
->tiling
== ISL_TILING_LINEAR
) {
1350 return isl_calc_linear_min_row_pitch(dev
, surf_info
, phys_total_el
,
1353 return isl_calc_tiled_min_row_pitch(dev
, surf_info
, tile_info
,
1354 phys_total_el
, alignment_B
);
1359 * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
1360 * size is `bits` bits?
1362 * Hardware pitch fields are offset by 1. For example, if the size of
1363 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
1364 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
1365 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
1368 pitch_in_range(uint32_t n
, uint32_t bits
)
1371 return likely(bits
!= 0 && 1 <= n
&& n
<= (1 << bits
));
1375 isl_calc_row_pitch(const struct isl_device
*dev
,
1376 const struct isl_surf_init_info
*surf_info
,
1377 const struct isl_tile_info
*tile_info
,
1378 enum isl_dim_layout dim_layout
,
1379 const struct isl_extent2d
*phys_total_el
,
1380 uint32_t *out_row_pitch_B
)
1382 uint32_t alignment_B
=
1383 isl_calc_row_pitch_alignment(surf_info
, tile_info
);
1385 const uint32_t min_row_pitch_B
=
1386 isl_calc_min_row_pitch(dev
, surf_info
, tile_info
, phys_total_el
,
1389 uint32_t row_pitch_B
= min_row_pitch_B
;
1391 if (surf_info
->row_pitch_B
!= 0) {
1392 row_pitch_B
= surf_info
->row_pitch_B
;
1394 if (row_pitch_B
< min_row_pitch_B
)
1397 if (row_pitch_B
% alignment_B
!= 0)
1401 const uint32_t row_pitch_tl
= row_pitch_B
/ tile_info
->phys_extent_B
.width
;
1403 if (row_pitch_B
== 0)
1406 if (dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
1407 /* SurfacePitch is ignored for this layout. */
1411 if ((surf_info
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1412 ISL_SURF_USAGE_TEXTURE_BIT
|
1413 ISL_SURF_USAGE_STORAGE_BIT
)) &&
1414 !pitch_in_range(row_pitch_B
, RENDER_SURFACE_STATE_SurfacePitch_bits(dev
->info
)))
1417 if ((surf_info
->usage
& (ISL_SURF_USAGE_CCS_BIT
|
1418 ISL_SURF_USAGE_MCS_BIT
)) &&
1419 !pitch_in_range(row_pitch_tl
, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev
->info
)))
1422 if ((surf_info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1423 !pitch_in_range(row_pitch_B
, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1426 if ((surf_info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) &&
1427 !pitch_in_range(row_pitch_B
, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1430 const uint32_t stencil_pitch_bits
= dev
->use_separate_stencil
?
1431 _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev
->info
) :
1432 _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
);
1434 if ((surf_info
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) &&
1435 !pitch_in_range(row_pitch_B
, stencil_pitch_bits
))
1439 *out_row_pitch_B
= row_pitch_B
;
1444 isl_surf_init_s(const struct isl_device
*dev
,
1445 struct isl_surf
*surf
,
1446 const struct isl_surf_init_info
*restrict info
)
1448 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1450 const struct isl_extent4d logical_level0_px
= {
1454 .a
= info
->array_len
,
1457 enum isl_tiling tiling
;
1458 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1461 struct isl_tile_info tile_info
;
1462 isl_tiling_get_info(tiling
, fmtl
->bpb
, &tile_info
);
1464 const enum isl_dim_layout dim_layout
=
1465 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
, info
->usage
);
1467 enum isl_msaa_layout msaa_layout
;
1468 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1471 struct isl_extent3d image_align_el
;
1472 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1475 struct isl_extent3d image_align_sa
=
1476 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1478 struct isl_extent4d phys_level0_sa
;
1479 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1481 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1482 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1484 enum isl_array_pitch_span array_pitch_span
=
1485 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1487 uint32_t array_pitch_el_rows
;
1488 struct isl_extent2d phys_total_el
;
1489 isl_calc_phys_total_extent_el(dev
, info
, &tile_info
,
1490 dim_layout
, msaa_layout
,
1491 &image_align_sa
, &phys_level0_sa
,
1492 array_pitch_span
, &array_pitch_el_rows
,
1495 uint32_t row_pitch_B
;
1496 if (!isl_calc_row_pitch(dev
, info
, &tile_info
, dim_layout
,
1497 &phys_total_el
, &row_pitch_B
))
1500 uint32_t base_alignment_B
;
1502 if (tiling
== ISL_TILING_LINEAR
) {
1503 size_B
= (uint64_t) row_pitch_B
* phys_total_el
.h
;
1505 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1507 * "The Base Address for linear render target surfaces and surfaces
1508 * accessed with the typed surface read/write data port messages must
1509 * be element-size aligned, for non-YUV surface formats, or a
1510 * multiple of 2 element-sizes for YUV surface formats. Other linear
1511 * surfaces have no alignment requirements (byte alignment is
1514 base_alignment_B
= MAX(1, info
->min_alignment_B
);
1515 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1516 if (isl_format_is_yuv(info
->format
)) {
1517 base_alignment_B
= MAX(base_alignment_B
, fmtl
->bpb
/ 4);
1519 base_alignment_B
= MAX(base_alignment_B
, fmtl
->bpb
/ 8);
1522 base_alignment_B
= isl_round_up_to_power_of_two(base_alignment_B
);
1524 /* From the Skylake PRM Vol 2c, PLANE_STRIDE::Stride:
1526 * "For Linear memory, this field specifies the stride in chunks of
1527 * 64 bytes (1 cache line)."
1529 if (isl_surf_usage_is_display(info
->usage
))
1530 base_alignment_B
= MAX(base_alignment_B
, 64);
1532 const uint32_t total_h_tl
=
1533 isl_align_div(phys_total_el
.h
, tile_info
.logical_extent_el
.height
);
1535 size_B
= (uint64_t) total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch_B
;
1537 const uint32_t tile_size_B
= tile_info
.phys_extent_B
.width
*
1538 tile_info
.phys_extent_B
.height
;
1539 assert(isl_is_pow2(info
->min_alignment_B
) && isl_is_pow2(tile_size_B
));
1540 base_alignment_B
= MAX(info
->min_alignment_B
, tile_size_B
);
1543 if (ISL_DEV_GEN(dev
) < 9) {
1544 /* From the Broadwell PRM Vol 5, Surface Layout:
1546 * "In addition to restrictions on maximum height, width, and depth,
1547 * surfaces are also restricted to a maximum size in bytes. This
1548 * maximum is 2 GB for all products and all surface types."
1550 * This comment is applicable to all Pre-gen9 platforms.
1552 if (size_B
> (uint64_t) 1 << 31)
1554 } else if (ISL_DEV_GEN(dev
) < 11) {
1555 /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
1556 * "In addition to restrictions on maximum height, width, and depth,
1557 * surfaces are also restricted to a maximum size of 2^38 bytes.
1558 * All pixels within the surface must be contained within 2^38 bytes
1559 * of the base address."
1561 if (size_B
> (uint64_t) 1 << 38)
1564 /* gen11+ platforms raised this limit to 2^44 bytes. */
1565 if (size_B
> (uint64_t) 1 << 44)
1569 *surf
= (struct isl_surf
) {
1571 .dim_layout
= dim_layout
,
1572 .msaa_layout
= msaa_layout
,
1574 .format
= info
->format
,
1576 .levels
= info
->levels
,
1577 .samples
= info
->samples
,
1579 .image_alignment_el
= image_align_el
,
1580 .logical_level0_px
= logical_level0_px
,
1581 .phys_level0_sa
= phys_level0_sa
,
1584 .alignment_B
= base_alignment_B
,
1585 .row_pitch_B
= row_pitch_B
,
1586 .array_pitch_el_rows
= array_pitch_el_rows
,
1587 .array_pitch_span
= array_pitch_span
,
1589 .usage
= info
->usage
,
1596 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1597 struct isl_tile_info
*tile_info
)
1599 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1600 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, tile_info
);
1604 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1605 const struct isl_surf
*surf
,
1606 struct isl_surf
*hiz_surf
)
1608 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1610 /* HiZ only works with Y-tiled depth buffers */
1611 if (!isl_tiling_is_any_y(surf
->tiling
))
1614 /* On SNB+, compressed depth buffers cannot be interleaved with stencil. */
1615 switch (surf
->format
) {
1616 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1617 if (isl_surf_usage_is_depth_and_stencil(surf
->usage
)) {
1618 assert(ISL_DEV_GEN(dev
) == 5);
1619 unreachable("This should work, but is untested");
1622 case ISL_FORMAT_R16_UNORM
:
1623 case ISL_FORMAT_R32_FLOAT
:
1625 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1626 if (ISL_DEV_GEN(dev
) == 5) {
1627 assert(isl_surf_usage_is_depth_and_stencil(surf
->usage
));
1628 unreachable("This should work, but is untested");
1635 /* Multisampled depth is always interleaved */
1636 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1637 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1639 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
1641 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
1642 * Target View Extent, and Depth Coordinate Offset X/Y of the
1643 * hierarchical depth buffer are inherited from the depth buffer. The
1644 * height and width of the hierarchical depth buffer that must be
1645 * allocated are computed by the following formulas, where HZ is the
1646 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
1647 * Z_Width, and Z_Depth values given in these formulas are those present
1648 * in 3DSTATE_DEPTH_BUFFER incremented by one.
1650 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
1651 * being applied to the table below if Number of Multisamples is set to
1652 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
1653 * Z_Width must be multiplied by 4 before being applied to the table
1654 * below if Number of Multisamples is set to NUMSAMPLES_8."
1656 * In the Sky Lake PRM, the second paragraph is replaced with this:
1658 * "The Z_Height and Z_Width values must equal those present in
1659 * 3DSTATE_DEPTH_BUFFER incremented by one."
1661 * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
1662 * block corresponds to a region of 8x4 samples in the primary depth
1663 * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
1664 * a region of 8x4 pixels in the primary depth surface regardless of the
1665 * number of samples. The dimensions of a HiZ block in both pixels and
1666 * samples are given in the table below:
1668 * | SNB - BDW | SKL+
1669 * ------+-----------+-------------
1670 * 1x | 8 x 4 sa | 8 x 4 sa
1671 * MSAA | 8 x 4 px | 8 x 4 px
1672 * ------+-----------+-------------
1673 * 2x | 8 x 4 sa | 16 x 4 sa
1674 * MSAA | 4 x 4 px | 8 x 4 px
1675 * ------+-----------+-------------
1676 * 4x | 8 x 4 sa | 16 x 8 sa
1677 * MSAA | 4 x 2 px | 8 x 4 px
1678 * ------+-----------+-------------
1679 * 8x | 8 x 4 sa | 32 x 8 sa
1680 * MSAA | 2 x 2 px | 8 x 4 px
1681 * ------+-----------+-------------
1682 * 16x | N/A | 32 x 16 sa
1683 * MSAA | N/A | 8 x 4 px
1684 * ------+-----------+-------------
1686 * There are a number of different ways that this discrepency could be
1687 * handled. The way we have chosen is to simply make MSAA HiZ have the
1688 * same number of samples as the parent surface pre-Sky Lake and always be
1689 * single-sampled on Sky Lake and above. Since the block sizes of
1690 * compressed formats are given in samples, this neatly handles everything
1691 * without the need for additional HiZ formats with different block sizes
1694 const unsigned samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
;
1696 return isl_surf_init(dev
, hiz_surf
,
1698 .format
= ISL_FORMAT_HIZ
,
1699 .width
= surf
->logical_level0_px
.width
,
1700 .height
= surf
->logical_level0_px
.height
,
1701 .depth
= surf
->logical_level0_px
.depth
,
1702 .levels
= surf
->levels
,
1703 .array_len
= surf
->logical_level0_px
.array_len
,
1705 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1706 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1710 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1711 const struct isl_surf
*surf
,
1712 struct isl_surf
*mcs_surf
)
1714 /* The following are true of all multisampled surfaces */
1715 assert(surf
->samples
> 1);
1716 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1717 assert(surf
->levels
== 1);
1718 assert(surf
->logical_level0_px
.depth
== 1);
1720 /* It must be multisampled with an array layout */
1721 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_ARRAY
)
1724 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
1726 * This field must be set to 0 for all SINT MSRTs when all RT channels
1729 * In practice this means that we have to disable MCS for all signed
1730 * integer MSAA buffers. The alternative, to disable MCS only when one
1731 * of the render target channels is disabled, is impractical because it
1732 * would require converting between CMS and UMS MSAA layouts on the fly,
1733 * which is expensive.
1735 if (ISL_DEV_GEN(dev
) == 7 && isl_format_has_sint_channel(surf
->format
))
1738 /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
1739 * bits which means the maximum pitch of a compression surface is 512
1740 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
1741 * 64bpp, this gives us a maximum width of 8192 pixels. We can create
1742 * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
1743 * and 8x, we have enough room for the full 16k supported by the hardware.
1745 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
1748 enum isl_format mcs_format
;
1749 switch (surf
->samples
) {
1750 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1751 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1752 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1753 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1755 unreachable("Invalid sample count");
1758 return isl_surf_init(dev
, mcs_surf
,
1759 .dim
= ISL_SURF_DIM_2D
,
1760 .format
= mcs_format
,
1761 .width
= surf
->logical_level0_px
.width
,
1762 .height
= surf
->logical_level0_px
.height
,
1765 .array_len
= surf
->logical_level0_px
.array_len
,
1766 .samples
= 1, /* MCS surfaces are really single-sampled */
1767 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1768 .tiling_flags
= ISL_TILING_Y0_BIT
);
1772 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1773 const struct isl_surf
*surf
,
1774 struct isl_surf
*ccs_surf
,
1775 uint32_t row_pitch_B
)
1777 assert(surf
->samples
== 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
);
1779 /* CCS support does not exist prior to Gen7 */
1780 if (ISL_DEV_GEN(dev
) <= 6)
1783 if (surf
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)
1786 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
1787 * work for 3D textures until gen9 where the layout of 3D textures changes
1788 * to match 2D array textures.
1790 if (ISL_DEV_GEN(dev
) <= 8 && surf
->dim
!= ISL_SURF_DIM_2D
)
1793 /* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
1794 * Non-MultiSampler Render Target Restrictions):
1796 * "Support is for non-mip-mapped and non-array surface types only."
1798 * This restriction is lifted on gen8+. Technically, it may be possible to
1799 * create a CCS for an arrayed or mipmapped image and only enable CCS_D
1800 * when rendering to the base slice. However, there is no documentation
1801 * tell us what the hardware would do in that case or what it does if you
1802 * walk off the bases slice. (Does it ignore CCS or does it start
1803 * scribbling over random memory?) We play it safe and just follow the
1804 * docs and don't allow CCS_D for arrayed or mip-mapped surfaces.
1806 if (ISL_DEV_GEN(dev
) <= 7 &&
1807 (surf
->levels
> 1 || surf
->logical_level0_px
.array_len
> 1))
1810 if (isl_format_is_compressed(surf
->format
))
1813 /* TODO: More conditions where it can fail. */
1815 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
1816 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
1818 * - Support is limited to tiled render targets.
1819 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
1820 * 64bpp, and 128bpp.
1822 * From the Skylake documentation, it is made clear that X-tiling is no
1825 * - MCS and Lossless compression is supported for
1826 * TiledY/TileYs/TileYf non-MSRTs only.
1828 enum isl_format ccs_format
;
1829 if (ISL_DEV_GEN(dev
) >= 9) {
1830 if (!isl_tiling_is_any_y(surf
->tiling
))
1833 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1834 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
1835 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
1836 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
1840 } else if (surf
->tiling
== ISL_TILING_Y0
) {
1841 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1842 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
1843 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
1844 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
1848 } else if (surf
->tiling
== ISL_TILING_X
) {
1849 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1850 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
1851 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
1852 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
1860 return isl_surf_init(dev
, ccs_surf
,
1862 .format
= ccs_format
,
1863 .width
= surf
->logical_level0_px
.width
,
1864 .height
= surf
->logical_level0_px
.height
,
1865 .depth
= surf
->logical_level0_px
.depth
,
1866 .levels
= surf
->levels
,
1867 .array_len
= surf
->logical_level0_px
.array_len
,
1869 .row_pitch_B
= row_pitch_B
,
1870 .usage
= ISL_SURF_USAGE_CCS_BIT
,
1871 .tiling_flags
= ISL_TILING_CCS_BIT
);
1874 #define isl_genX_call(dev, func, ...) \
1875 switch (ISL_DEV_GEN(dev)) { \
1877 /* G45 surface state is the same as gen5 */ \
1878 if (ISL_DEV_IS_G4X(dev)) { \
1879 isl_gen5_##func(__VA_ARGS__); \
1881 isl_gen4_##func(__VA_ARGS__); \
1885 isl_gen5_##func(__VA_ARGS__); \
1888 isl_gen6_##func(__VA_ARGS__); \
1891 if (ISL_DEV_IS_HASWELL(dev)) { \
1892 isl_gen75_##func(__VA_ARGS__); \
1894 isl_gen7_##func(__VA_ARGS__); \
1898 isl_gen8_##func(__VA_ARGS__); \
1901 isl_gen9_##func(__VA_ARGS__); \
1904 isl_gen10_##func(__VA_ARGS__); \
1907 isl_gen11_##func(__VA_ARGS__); \
1910 assert(!"Unknown hardware generation"); \
1914 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1915 const struct isl_surf_fill_state_info
*restrict info
)
1918 isl_surf_usage_flags_t _base_usage
=
1919 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1920 ISL_SURF_USAGE_TEXTURE_BIT
|
1921 ISL_SURF_USAGE_STORAGE_BIT
);
1922 /* They may only specify one of the above bits at a time */
1923 assert(__builtin_popcount(_base_usage
) == 1);
1924 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1925 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1928 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1929 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1930 info
->surf
->logical_level0_px
.depth
);
1932 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1933 info
->surf
->logical_level0_px
.array_len
);
1936 isl_genX_call(dev
, surf_fill_state_s
, dev
, state
, info
);
1940 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1941 const struct isl_buffer_fill_state_info
*restrict info
)
1943 isl_genX_call(dev
, buffer_fill_state_s
, state
, info
);
1947 isl_null_fill_state(const struct isl_device
*dev
, void *state
,
1948 struct isl_extent3d size
)
1950 isl_genX_call(dev
, null_fill_state
, state
, size
);
1954 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
1955 const struct isl_depth_stencil_hiz_emit_info
*restrict info
)
1957 if (info
->depth_surf
&& info
->stencil_surf
) {
1958 if (!dev
->info
->has_hiz_and_separate_stencil
) {
1959 assert(info
->depth_surf
== info
->stencil_surf
);
1960 assert(info
->depth_address
== info
->stencil_address
);
1962 assert(info
->depth_surf
->dim
== info
->stencil_surf
->dim
);
1965 if (info
->depth_surf
) {
1966 assert((info
->depth_surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
));
1967 if (info
->depth_surf
->dim
== ISL_SURF_DIM_3D
) {
1968 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1969 info
->depth_surf
->logical_level0_px
.depth
);
1971 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1972 info
->depth_surf
->logical_level0_px
.array_len
);
1976 if (info
->stencil_surf
) {
1977 assert((info
->stencil_surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
));
1978 if (info
->stencil_surf
->dim
== ISL_SURF_DIM_3D
) {
1979 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1980 info
->stencil_surf
->logical_level0_px
.depth
);
1982 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1983 info
->stencil_surf
->logical_level0_px
.array_len
);
1987 isl_genX_call(dev
, emit_depth_stencil_hiz_s
, dev
, batch
, info
);
1991 * A variant of isl_surf_get_image_offset_sa() specific to
1992 * ISL_DIM_LAYOUT_GEN4_2D.
1995 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1996 uint32_t level
, uint32_t logical_array_layer
,
1997 uint32_t *x_offset_sa
,
1998 uint32_t *y_offset_sa
)
2000 assert(level
< surf
->levels
);
2001 if (surf
->dim
== ISL_SURF_DIM_3D
)
2002 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
2004 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2006 const struct isl_extent3d image_align_sa
=
2007 isl_surf_get_image_alignment_sa(surf
);
2009 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2010 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2012 const uint32_t phys_layer
= logical_array_layer
*
2013 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
2016 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2018 for (uint32_t l
= 0; l
< level
; ++l
) {
2020 uint32_t W
= isl_minify(W0
, l
);
2021 x
+= isl_align_npot(W
, image_align_sa
.w
);
2023 uint32_t H
= isl_minify(H0
, l
);
2024 y
+= isl_align_npot(H
, image_align_sa
.h
);
2033 * A variant of isl_surf_get_image_offset_sa() specific to
2034 * ISL_DIM_LAYOUT_GEN4_3D.
2037 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
2038 uint32_t level
, uint32_t logical_z_offset_px
,
2039 uint32_t *x_offset_sa
,
2040 uint32_t *y_offset_sa
)
2042 assert(level
< surf
->levels
);
2043 if (surf
->dim
== ISL_SURF_DIM_3D
) {
2044 assert(surf
->phys_level0_sa
.array_len
== 1);
2045 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
2047 assert(surf
->dim
== ISL_SURF_DIM_2D
);
2048 assert(surf
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
2049 assert(surf
->phys_level0_sa
.array_len
== 6);
2050 assert(logical_z_offset_px
< surf
->phys_level0_sa
.array_len
);
2053 const struct isl_extent3d image_align_sa
=
2054 isl_surf_get_image_alignment_sa(surf
);
2056 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2057 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2058 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
2059 const uint32_t AL
= surf
->phys_level0_sa
.array_len
;
2064 for (uint32_t l
= 0; l
< level
; ++l
) {
2065 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
2066 const uint32_t level_d
=
2067 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : AL
,
2069 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
2071 y
+= level_h
* max_layers_vert
;
2074 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
2075 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
2076 const uint32_t level_d
=
2077 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, level
) : AL
,
2080 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
2082 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
2083 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
2090 get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf
*surf
,
2092 uint32_t logical_array_layer
,
2093 uint32_t *x_offset_sa
,
2094 uint32_t *y_offset_sa
)
2096 assert(level
< surf
->levels
);
2097 assert(surf
->logical_level0_px
.depth
== 1);
2098 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2100 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2102 const struct isl_extent3d image_align_sa
=
2103 isl_surf_get_image_alignment_sa(surf
);
2105 struct isl_tile_info tile_info
;
2106 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, &tile_info
);
2107 const struct isl_extent2d tile_extent_sa
= {
2108 .w
= tile_info
.logical_extent_el
.w
* fmtl
->bw
,
2109 .h
= tile_info
.logical_extent_el
.h
* fmtl
->bh
,
2111 /* Tile size is a multiple of image alignment */
2112 assert(tile_extent_sa
.w
% image_align_sa
.w
== 0);
2113 assert(tile_extent_sa
.h
% image_align_sa
.h
== 0);
2115 const uint32_t W0
= surf
->phys_level0_sa
.w
;
2116 const uint32_t H0
= surf
->phys_level0_sa
.h
;
2118 /* Each image has the same height as LOD0 because the hardware thinks
2119 * everything is LOD0
2121 const uint32_t H
= isl_align(H0
, image_align_sa
.h
);
2123 /* Quick sanity check for consistency */
2124 if (surf
->phys_level0_sa
.array_len
> 1)
2125 assert(surf
->array_pitch_el_rows
== isl_assert_div(H
, fmtl
->bh
));
2127 uint32_t x
= 0, y
= 0;
2128 for (uint32_t l
= 0; l
< level
; ++l
) {
2129 const uint32_t W
= isl_minify(W0
, l
);
2131 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
2132 const uint32_t h
= isl_align(H
* surf
->phys_level0_sa
.a
,
2142 y
+= H
* logical_array_layer
;
2149 * A variant of isl_surf_get_image_offset_sa() specific to
2150 * ISL_DIM_LAYOUT_GEN9_1D.
2153 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
2154 uint32_t level
, uint32_t layer
,
2155 uint32_t *x_offset_sa
,
2156 uint32_t *y_offset_sa
)
2158 assert(level
< surf
->levels
);
2159 assert(layer
< surf
->phys_level0_sa
.array_len
);
2160 assert(surf
->phys_level0_sa
.height
== 1);
2161 assert(surf
->phys_level0_sa
.depth
== 1);
2162 assert(surf
->samples
== 1);
2164 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2165 const struct isl_extent3d image_align_sa
=
2166 isl_surf_get_image_alignment_sa(surf
);
2170 for (uint32_t l
= 0; l
< level
; ++l
) {
2171 uint32_t W
= isl_minify(W0
, l
);
2172 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
2178 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2182 * Calculate the offset, in units of surface samples, to a subimage in the
2185 * @invariant level < surface levels
2186 * @invariant logical_array_layer < logical array length of surface
2187 * @invariant logical_z_offset_px < logical depth of surface at level
2190 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
2192 uint32_t logical_array_layer
,
2193 uint32_t logical_z_offset_px
,
2194 uint32_t *x_offset_sa
,
2195 uint32_t *y_offset_sa
)
2197 assert(level
< surf
->levels
);
2198 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2199 assert(logical_z_offset_px
2200 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2202 switch (surf
->dim_layout
) {
2203 case ISL_DIM_LAYOUT_GEN9_1D
:
2204 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
2205 x_offset_sa
, y_offset_sa
);
2207 case ISL_DIM_LAYOUT_GEN4_2D
:
2208 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
2209 + logical_z_offset_px
,
2210 x_offset_sa
, y_offset_sa
);
2212 case ISL_DIM_LAYOUT_GEN4_3D
:
2213 get_image_offset_sa_gen4_3d(surf
, level
, logical_array_layer
+
2214 logical_z_offset_px
,
2215 x_offset_sa
, y_offset_sa
);
2217 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
2218 get_image_offset_sa_gen6_stencil_hiz(surf
, level
, logical_array_layer
+
2219 logical_z_offset_px
,
2220 x_offset_sa
, y_offset_sa
);
2224 unreachable("not reached");
2229 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
2231 uint32_t logical_array_layer
,
2232 uint32_t logical_z_offset_px
,
2233 uint32_t *x_offset_el
,
2234 uint32_t *y_offset_el
)
2236 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2238 assert(level
< surf
->levels
);
2239 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2240 assert(logical_z_offset_px
2241 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2243 uint32_t x_offset_sa
, y_offset_sa
;
2244 isl_surf_get_image_offset_sa(surf
, level
,
2245 logical_array_layer
,
2246 logical_z_offset_px
,
2250 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
2251 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
2255 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
2257 uint32_t logical_array_layer
,
2258 uint32_t logical_z_offset_px
,
2260 uint32_t *x_offset_sa
,
2261 uint32_t *y_offset_sa
)
2263 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2265 uint32_t total_x_offset_el
, total_y_offset_el
;
2266 isl_surf_get_image_offset_el(surf
, level
, logical_array_layer
,
2267 logical_z_offset_px
,
2269 &total_y_offset_el
);
2271 uint32_t x_offset_el
, y_offset_el
;
2272 isl_tiling_get_intratile_offset_el(surf
->tiling
, fmtl
->bpb
,
2281 *x_offset_sa
= x_offset_el
* fmtl
->bw
;
2283 assert(x_offset_el
== 0);
2287 *y_offset_sa
= y_offset_el
* fmtl
->bh
;
2289 assert(y_offset_el
== 0);
2294 isl_surf_get_image_surf(const struct isl_device
*dev
,
2295 const struct isl_surf
*surf
,
2297 uint32_t logical_array_layer
,
2298 uint32_t logical_z_offset_px
,
2299 struct isl_surf
*image_surf
,
2301 uint32_t *x_offset_sa
,
2302 uint32_t *y_offset_sa
)
2304 isl_surf_get_image_offset_B_tile_sa(surf
,
2306 logical_array_layer
,
2307 logical_z_offset_px
,
2312 /* Even for cube maps there will be only single face, therefore drop the
2313 * corresponding flag if present.
2315 const isl_surf_usage_flags_t usage
=
2316 surf
->usage
& (~ISL_SURF_USAGE_CUBE_BIT
);
2319 ok
= isl_surf_init(dev
, image_surf
,
2320 .dim
= ISL_SURF_DIM_2D
,
2321 .format
= surf
->format
,
2322 .width
= isl_minify(surf
->logical_level0_px
.w
, level
),
2323 .height
= isl_minify(surf
->logical_level0_px
.h
, level
),
2327 .samples
= surf
->samples
,
2328 .row_pitch_B
= surf
->row_pitch_B
,
2330 .tiling_flags
= (1 << surf
->tiling
));
2335 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
2337 uint32_t row_pitch_B
,
2338 uint32_t total_x_offset_el
,
2339 uint32_t total_y_offset_el
,
2340 uint32_t *base_address_offset
,
2341 uint32_t *x_offset_el
,
2342 uint32_t *y_offset_el
)
2344 if (tiling
== ISL_TILING_LINEAR
) {
2345 assert(bpb
% 8 == 0);
2346 *base_address_offset
= total_y_offset_el
* row_pitch_B
+
2347 total_x_offset_el
* (bpb
/ 8);
2353 struct isl_tile_info tile_info
;
2354 isl_tiling_get_info(tiling
, bpb
, &tile_info
);
2356 assert(row_pitch_B
% tile_info
.phys_extent_B
.width
== 0);
2358 /* For non-power-of-two formats, we need the address to be both tile and
2359 * element-aligned. The easiest way to achieve this is to work with a tile
2360 * that is three times as wide as the regular tile.
2362 * The tile info returned by get_tile_info has a logical size that is an
2363 * integer number of tile_info.format_bpb size elements. To scale the
2364 * tile, we scale up the physical width and then treat the logical tile
2365 * size as if it has bpb size elements.
2367 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
2368 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
2370 /* Compute the offset into the tile */
2371 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
2372 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
2374 /* Compute the offset of the tile in units of whole tiles */
2375 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
2376 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
2378 *base_address_offset
=
2379 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch_B
+
2380 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
2384 isl_surf_get_depth_format(const struct isl_device
*dev
,
2385 const struct isl_surf
*surf
)
2387 /* Support for separate stencil buffers began in gen5. Support for
2388 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
2389 * those that supported separate and interleaved stencil, were gen5 and
2392 * For a list of all available formats, see the Sandybridge PRM >> Volume
2393 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
2397 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
2399 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
2402 assert(ISL_DEV_GEN(dev
) < 7);
2404 switch (surf
->format
) {
2406 unreachable("bad isl depth format");
2407 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
2408 assert(ISL_DEV_GEN(dev
) < 7);
2409 return 0; /* D32_FLOAT_S8X24_UINT */
2410 case ISL_FORMAT_R32_FLOAT
:
2411 assert(!has_stencil
);
2412 return 1; /* D32_FLOAT */
2413 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
2415 assert(ISL_DEV_GEN(dev
) < 7);
2416 return 2; /* D24_UNORM_S8_UINT */
2418 assert(ISL_DEV_GEN(dev
) >= 5);
2419 return 3; /* D24_UNORM_X8_UINT */
2421 case ISL_FORMAT_R16_UNORM
:
2422 assert(!has_stencil
);
2423 return 5; /* D16_UNORM */
2428 isl_swizzle_supports_rendering(const struct gen_device_info
*devinfo
,
2429 struct isl_swizzle swizzle
)
2431 if (devinfo
->is_haswell
) {
2432 /* From the Haswell PRM,
2433 * RENDER_SURFACE_STATE::Shader Channel Select Red
2435 * "The Shader channel selects also define which shader channels are
2436 * written to which surface channel. If the Shader channel select is
2437 * SCS_ZERO or SCS_ONE then it is not written to the surface. If the
2438 * shader channel select is SCS_RED it is written to the surface red
2439 * channel and so on. If more than one shader channel select is set
2440 * to the same surface channel only the first shader channel in RGBA
2441 * order will be written."
2444 } else if (devinfo
->gen
<= 7) {
2445 /* Ivy Bridge and early doesn't have any swizzling */
2446 return isl_swizzle_is_identity(swizzle
);
2448 /* From the Sky Lake PRM Vol. 2d,
2449 * RENDER_SURFACE_STATE::Shader Channel Select Red
2451 * "For Render Target, Red, Green and Blue Shader Channel Selects
2452 * MUST be such that only valid components can be swapped i.e. only
2453 * change the order of components in the pixel. Any other values for
2454 * these Shader Channel Select fields are not valid for Render
2455 * Targets. This also means that there MUST not be multiple shader
2456 * channels mapped to the same RT channel."
2458 * From the Sky Lake PRM Vol. 2d,
2459 * RENDER_SURFACE_STATE::Shader Channel Select Alpha
2461 * "For Render Target, this field MUST be programmed to
2462 * value = SCS_ALPHA."
2464 return (swizzle
.r
== ISL_CHANNEL_SELECT_RED
||
2465 swizzle
.r
== ISL_CHANNEL_SELECT_GREEN
||
2466 swizzle
.r
== ISL_CHANNEL_SELECT_BLUE
) &&
2467 (swizzle
.g
== ISL_CHANNEL_SELECT_RED
||
2468 swizzle
.g
== ISL_CHANNEL_SELECT_GREEN
||
2469 swizzle
.g
== ISL_CHANNEL_SELECT_BLUE
) &&
2470 (swizzle
.b
== ISL_CHANNEL_SELECT_RED
||
2471 swizzle
.b
== ISL_CHANNEL_SELECT_GREEN
||
2472 swizzle
.b
== ISL_CHANNEL_SELECT_BLUE
) &&
2473 swizzle
.r
!= swizzle
.g
&&
2474 swizzle
.r
!= swizzle
.b
&&
2475 swizzle
.g
!= swizzle
.b
&&
2476 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
;
2480 static enum isl_channel_select
2481 swizzle_select(enum isl_channel_select chan
, struct isl_swizzle swizzle
)
2484 case ISL_CHANNEL_SELECT_ZERO
:
2485 case ISL_CHANNEL_SELECT_ONE
:
2487 case ISL_CHANNEL_SELECT_RED
:
2489 case ISL_CHANNEL_SELECT_GREEN
:
2491 case ISL_CHANNEL_SELECT_BLUE
:
2493 case ISL_CHANNEL_SELECT_ALPHA
:
2496 unreachable("Invalid swizzle component");
2501 * Returns the single swizzle that is equivalent to applying the two given
2502 * swizzles in sequence.
2505 isl_swizzle_compose(struct isl_swizzle first
, struct isl_swizzle second
)
2507 return (struct isl_swizzle
) {
2508 .r
= swizzle_select(first
.r
, second
),
2509 .g
= swizzle_select(first
.g
, second
),
2510 .b
= swizzle_select(first
.b
, second
),
2511 .a
= swizzle_select(first
.a
, second
),
2516 * Returns a swizzle that is the pseudo-inverse of this swizzle.
2519 isl_swizzle_invert(struct isl_swizzle swizzle
)
2521 /* Default to zero for channels which do not show up in the swizzle */
2522 enum isl_channel_select chans
[4] = {
2523 ISL_CHANNEL_SELECT_ZERO
,
2524 ISL_CHANNEL_SELECT_ZERO
,
2525 ISL_CHANNEL_SELECT_ZERO
,
2526 ISL_CHANNEL_SELECT_ZERO
,
2529 /* We go in ABGR order so that, if there are any duplicates, the first one
2530 * is taken if you look at it in RGBA order. This is what Haswell hardware
2531 * does for render target swizzles.
2533 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
2534 chans
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_ALPHA
;
2535 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
2536 chans
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_BLUE
;
2537 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
2538 chans
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_GREEN
;
2539 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
2540 chans
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_RED
;
2542 return (struct isl_swizzle
) { chans
[0], chans
[1], chans
[2], chans
[3] };