2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
36 void PRINTFLIKE(3, 4) UNUSED
37 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
43 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
46 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
50 isl_device_init(struct isl_device
*dev
,
51 const struct gen_device_info
*info
,
52 bool has_bit6_swizzling
)
55 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
56 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
58 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
59 * device properties at buildtime. Verify that the macros with the device
60 * properties chosen during runtime.
62 ISL_DEV_GEN_SANITIZE(dev
);
63 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
65 /* Did we break hiz or stencil? */
66 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
67 assert(info
->has_hiz_and_separate_stencil
);
68 if (info
->must_use_separate_stencil
)
69 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
73 * @brief Query the set of multisamples supported by the device.
75 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
78 isl_sample_count_mask_t ATTRIBUTE_CONST
79 isl_device_get_sample_counts(struct isl_device
*dev
)
81 if (ISL_DEV_GEN(dev
) >= 9) {
82 return ISL_SAMPLE_COUNT_1_BIT
|
83 ISL_SAMPLE_COUNT_2_BIT
|
84 ISL_SAMPLE_COUNT_4_BIT
|
85 ISL_SAMPLE_COUNT_8_BIT
|
86 ISL_SAMPLE_COUNT_16_BIT
;
87 } else if (ISL_DEV_GEN(dev
) >= 8) {
88 return ISL_SAMPLE_COUNT_1_BIT
|
89 ISL_SAMPLE_COUNT_2_BIT
|
90 ISL_SAMPLE_COUNT_4_BIT
|
91 ISL_SAMPLE_COUNT_8_BIT
;
92 } else if (ISL_DEV_GEN(dev
) >= 7) {
93 return ISL_SAMPLE_COUNT_1_BIT
|
94 ISL_SAMPLE_COUNT_4_BIT
|
95 ISL_SAMPLE_COUNT_8_BIT
;
96 } else if (ISL_DEV_GEN(dev
) >= 6) {
97 return ISL_SAMPLE_COUNT_1_BIT
|
98 ISL_SAMPLE_COUNT_4_BIT
;
100 return ISL_SAMPLE_COUNT_1_BIT
;
105 * @param[out] info is written only on success
108 isl_tiling_get_info(const struct isl_device
*dev
,
109 enum isl_tiling tiling
,
111 struct isl_tile_info
*tile_info
)
113 const uint32_t bs
= format_bpb
/ 8;
114 struct isl_extent2d logical_el
, phys_B
;
116 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
117 /* It is possible to have non-power-of-two formats in a tiled buffer.
118 * The easiest way to handle this is to treat the tile as if it is three
119 * times as wide. This way no pixel will ever cross a tile boundary.
120 * This really only works on legacy X and Y tiling formats.
122 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
123 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
124 return isl_tiling_get_info(dev
, tiling
, format_bpb
/ 3, tile_info
);
128 case ISL_TILING_LINEAR
:
130 logical_el
= isl_extent2d(1, 1);
131 phys_B
= isl_extent2d(bs
, 1);
136 logical_el
= isl_extent2d(512 / bs
, 8);
137 phys_B
= isl_extent2d(512, 8);
142 logical_el
= isl_extent2d(128 / bs
, 32);
143 phys_B
= isl_extent2d(128, 32);
148 logical_el
= isl_extent2d(64, 64);
149 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
151 * "If the surface is a stencil buffer (and thus has Tile Mode set
152 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
153 * computed based on width, as the stencil buffer is stored with two
156 * This, together with the fact that stencil buffers are referred to as
157 * being Y-tiled in the PRMs for older hardware implies that the
158 * physical size of a W-tile is actually the same as for a Y-tile.
160 phys_B
= isl_extent2d(128, 32);
164 case ISL_TILING_Ys
: {
165 if (ISL_DEV_GEN(dev
) < 9)
168 if (!isl_is_pow2(bs
))
171 bool is_Ys
= tiling
== ISL_TILING_Ys
;
174 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
175 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
177 logical_el
= isl_extent2d(width
/ bs
, height
);
178 phys_B
= isl_extent2d(width
, height
);
183 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
184 * 128bpb format. The tiling has the same physical dimensions as
185 * Y-tiling but actually has two HiZ columns per Y-tiled column.
188 logical_el
= isl_extent2d(16, 16);
189 phys_B
= isl_extent2d(128, 32);
193 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
194 * have a block size of 1 or 2 bits per block and each CCS element
195 * corresponds to one cache-line pair in the main surface. From the Sky
196 * Lake PRM Vol. 12 in the section on planes:
198 * "The Color Control Surface (CCS) contains the compression status
199 * of the cache-line pairs. The compression state of the cache-line
200 * pair is specified by 2 bits in the CCS. Each CCS cache-line
201 * represents an area on the main surface of 16x16 sets of 128 byte
202 * Y-tiled cache-line-pairs. CCS is always Y tiled."
204 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
205 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
206 * that yields total tile area of 128x128 cache-line pairs or CCS
207 * elements. On older hardware, each CCS element is 1 bit and the tile
208 * is 128x256 elements.
210 assert(format_bpb
== 1 || format_bpb
== 2);
211 logical_el
= isl_extent2d(128, 256 / format_bpb
);
212 phys_B
= isl_extent2d(128, 32);
216 unreachable("not reached");
219 *tile_info
= (struct isl_tile_info
) {
221 .format_bpb
= format_bpb
,
222 .logical_extent_el
= logical_el
,
223 .phys_extent_B
= phys_B
,
230 * @param[out] tiling is set only on success
233 isl_surf_choose_tiling(const struct isl_device
*dev
,
234 const struct isl_surf_init_info
*restrict info
,
235 enum isl_tiling
*tiling
)
237 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
239 /* HiZ surfaces always use the HiZ tiling */
240 if (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) {
241 assert(info
->format
== ISL_FORMAT_HIZ
);
242 assert(tiling_flags
== ISL_TILING_HIZ_BIT
);
243 *tiling
= ISL_TILING_HIZ
;
247 /* CCS surfaces always use the CCS tiling */
248 if (info
->usage
& ISL_SURF_USAGE_CCS_BIT
) {
249 assert(isl_format_get_layout(info
->format
)->txc
== ISL_TXC_CCS
);
250 assert(tiling_flags
== ISL_TILING_CCS_BIT
);
251 *tiling
= ISL_TILING_CCS
;
255 if (ISL_DEV_GEN(dev
) >= 6) {
256 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
258 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
259 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
262 #define CHOOSE(__tiling) \
264 if (tiling_flags & (1u << (__tiling))) { \
265 *tiling = (__tiling); \
270 /* Of the tiling modes remaining, choose the one that offers the best
274 if (info
->dim
== ISL_SURF_DIM_1D
) {
275 /* Prefer linear for 1D surfaces because they do not benefit from
276 * tiling. To the contrary, tiling leads to wasted memory and poor
277 * memory locality due to the swizzling and alignment restrictions
278 * required in tiled surfaces.
280 CHOOSE(ISL_TILING_LINEAR
);
283 CHOOSE(ISL_TILING_Ys
);
284 CHOOSE(ISL_TILING_Yf
);
285 CHOOSE(ISL_TILING_Y0
);
286 CHOOSE(ISL_TILING_X
);
287 CHOOSE(ISL_TILING_W
);
288 CHOOSE(ISL_TILING_LINEAR
);
292 /* No tiling mode accomodates the inputs. */
297 isl_choose_msaa_layout(const struct isl_device
*dev
,
298 const struct isl_surf_init_info
*info
,
299 enum isl_tiling tiling
,
300 enum isl_msaa_layout
*msaa_layout
)
302 if (ISL_DEV_GEN(dev
) >= 8) {
303 return isl_gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
304 } else if (ISL_DEV_GEN(dev
) >= 7) {
305 return isl_gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
306 } else if (ISL_DEV_GEN(dev
) >= 6) {
307 return isl_gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
309 return isl_gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
314 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
316 assert(isl_is_pow2(samples
));
318 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
321 * If the surface is multisampled and it is a depth or stencil surface
322 * or Multisampled Surface StorageFormat in SURFACE_STATE is
323 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
326 return (struct isl_extent2d
) {
327 .width
= 1 << ((ffs(samples
) - 0) / 2),
328 .height
= 1 << ((ffs(samples
) - 1) / 2),
333 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
334 uint32_t *width
, uint32_t *height
)
336 const struct isl_extent2d px_size_sa
=
337 isl_get_interleaved_msaa_px_size_sa(samples
);
340 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
342 *height
= isl_align(*height
, 2) * px_size_sa
.height
;
345 static enum isl_array_pitch_span
346 isl_choose_array_pitch_span(const struct isl_device
*dev
,
347 const struct isl_surf_init_info
*restrict info
,
348 enum isl_dim_layout dim_layout
,
349 const struct isl_extent4d
*phys_level0_sa
)
351 switch (dim_layout
) {
352 case ISL_DIM_LAYOUT_GEN9_1D
:
353 case ISL_DIM_LAYOUT_GEN4_2D
:
354 if (ISL_DEV_GEN(dev
) >= 8) {
355 /* QPitch becomes programmable in Broadwell. So choose the
356 * most compact QPitch possible in order to conserve memory.
358 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
359 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
361 * - Software must ensure that this field is set to a value
362 * sufficiently large such that the array slices in the surface
363 * do not overlap. Refer to the Memory Data Formats section for
364 * information on how surfaces are stored in memory.
366 * - This field specifies the distance in rows between array
367 * slices. It is used only in the following cases:
369 * - Surface Array is enabled OR
370 * - Number of Mulitsamples is not NUMSAMPLES_1 and
371 * Multisampled Surface Storage Format set to MSFMT_MSS OR
372 * - Surface Type is SURFTYPE_CUBE
374 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
375 } else if (ISL_DEV_GEN(dev
) >= 7) {
376 /* Note that Ivybridge introduces
377 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
378 * driver more control over the QPitch.
381 if (phys_level0_sa
->array_len
== 1) {
382 /* The hardware will never use the QPitch. So choose the most
383 * compact QPitch possible in order to conserve memory.
385 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
388 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
389 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
390 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
391 * Section 6.18.4.7: Surface Arrays (p112):
393 * If Surface Array Spacing is set to ARYSPC_FULL (note that
394 * the depth buffer and stencil buffer have an implied value of
397 return ISL_ARRAY_PITCH_SPAN_FULL
;
400 if (info
->levels
== 1) {
401 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
404 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
407 return ISL_ARRAY_PITCH_SPAN_FULL
;
408 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
409 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
410 isl_surf_usage_is_stencil(info
->usage
)) {
411 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
412 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
414 * The separate stencil buffer does not support mip mapping, thus
415 * the storage for LODs other than LOD 0 is not needed.
417 assert(info
->levels
== 1);
418 assert(phys_level0_sa
->array_len
== 1);
419 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
421 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
422 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
423 isl_surf_usage_is_stencil(info
->usage
)) {
424 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
425 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
427 * The separate stencil buffer does not support mip mapping,
428 * thus the storage for LODs other than LOD 0 is not needed.
430 assert(info
->levels
== 1);
431 assert(phys_level0_sa
->array_len
== 1);
432 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
435 if (phys_level0_sa
->array_len
== 1) {
436 /* The hardware will never use the QPitch. So choose the most
437 * compact QPitch possible in order to conserve memory.
439 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
442 return ISL_ARRAY_PITCH_SPAN_FULL
;
445 case ISL_DIM_LAYOUT_GEN4_3D
:
446 /* The hardware will never use the QPitch. So choose the most
447 * compact QPitch possible in order to conserve memory.
449 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
452 unreachable("bad isl_dim_layout");
453 return ISL_ARRAY_PITCH_SPAN_FULL
;
457 isl_choose_image_alignment_el(const struct isl_device
*dev
,
458 const struct isl_surf_init_info
*restrict info
,
459 enum isl_tiling tiling
,
460 enum isl_dim_layout dim_layout
,
461 enum isl_msaa_layout msaa_layout
,
462 struct isl_extent3d
*image_align_el
)
464 if (info
->format
== ISL_FORMAT_HIZ
) {
465 assert(ISL_DEV_GEN(dev
) >= 6);
466 /* HiZ surfaces are always aligned to 16x8 pixels in the primary surface
467 * which works out to 2x2 HiZ elments.
469 *image_align_el
= isl_extent3d(2, 2, 1);
473 if (ISL_DEV_GEN(dev
) >= 9) {
474 isl_gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
475 msaa_layout
, image_align_el
);
476 } else if (ISL_DEV_GEN(dev
) >= 8) {
477 isl_gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
478 msaa_layout
, image_align_el
);
479 } else if (ISL_DEV_GEN(dev
) >= 7) {
480 isl_gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
481 msaa_layout
, image_align_el
);
482 } else if (ISL_DEV_GEN(dev
) >= 6) {
483 isl_gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
484 msaa_layout
, image_align_el
);
486 isl_gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
487 msaa_layout
, image_align_el
);
491 static enum isl_dim_layout
492 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
493 enum isl_surf_dim logical_dim
,
494 enum isl_tiling tiling
)
496 if (ISL_DEV_GEN(dev
) >= 9) {
497 switch (logical_dim
) {
498 case ISL_SURF_DIM_1D
:
499 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
501 * One-dimensional surfaces use a tiling mode of linear.
502 * Technically, they are not tiled resources, but the Tiled
503 * Resource Mode field in RENDER_SURFACE_STATE is still used to
504 * indicate the alignment requirements for this linear surface
505 * (See 1D Alignment requirements for how 4K and 64KB Tiled
506 * Resource Modes impact alignment). Alternatively, a 1D surface
507 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
510 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
511 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
513 if (tiling
== ISL_TILING_LINEAR
)
514 return ISL_DIM_LAYOUT_GEN9_1D
;
516 return ISL_DIM_LAYOUT_GEN4_2D
;
517 case ISL_SURF_DIM_2D
:
518 case ISL_SURF_DIM_3D
:
519 return ISL_DIM_LAYOUT_GEN4_2D
;
522 switch (logical_dim
) {
523 case ISL_SURF_DIM_1D
:
524 case ISL_SURF_DIM_2D
:
525 return ISL_DIM_LAYOUT_GEN4_2D
;
526 case ISL_SURF_DIM_3D
:
527 return ISL_DIM_LAYOUT_GEN4_3D
;
531 unreachable("bad isl_surf_dim");
532 return ISL_DIM_LAYOUT_GEN4_2D
;
536 * Calculate the physical extent of the surface's first level, in units of
537 * surface samples. The result is aligned to the format's compression block.
540 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
541 const struct isl_surf_init_info
*restrict info
,
542 enum isl_dim_layout dim_layout
,
543 enum isl_tiling tiling
,
544 enum isl_msaa_layout msaa_layout
,
545 struct isl_extent4d
*phys_level0_sa
)
547 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
549 if (isl_format_is_yuv(info
->format
))
550 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
553 case ISL_SURF_DIM_1D
:
554 assert(info
->height
== 1);
555 assert(info
->depth
== 1);
556 assert(info
->samples
== 1);
558 switch (dim_layout
) {
559 case ISL_DIM_LAYOUT_GEN4_3D
:
560 unreachable("bad isl_dim_layout");
562 case ISL_DIM_LAYOUT_GEN9_1D
:
563 case ISL_DIM_LAYOUT_GEN4_2D
:
564 *phys_level0_sa
= (struct isl_extent4d
) {
565 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
568 .a
= info
->array_len
,
574 case ISL_SURF_DIM_2D
:
575 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
577 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
578 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
580 switch (msaa_layout
) {
581 case ISL_MSAA_LAYOUT_NONE
:
582 assert(info
->depth
== 1);
583 assert(info
->samples
== 1);
585 *phys_level0_sa
= (struct isl_extent4d
) {
586 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
587 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
589 .a
= info
->array_len
,
593 case ISL_MSAA_LAYOUT_ARRAY
:
594 assert(info
->depth
== 1);
595 assert(info
->levels
== 1);
596 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
597 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
599 *phys_level0_sa
= (struct isl_extent4d
) {
603 .a
= info
->array_len
* info
->samples
,
607 case ISL_MSAA_LAYOUT_INTERLEAVED
:
608 assert(info
->depth
== 1);
609 assert(info
->levels
== 1);
610 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
612 *phys_level0_sa
= (struct isl_extent4d
) {
616 .a
= info
->array_len
,
619 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
623 phys_level0_sa
->w
= isl_align(phys_level0_sa
->w
, fmtl
->bw
);
624 phys_level0_sa
->h
= isl_align(phys_level0_sa
->h
, fmtl
->bh
);
629 case ISL_SURF_DIM_3D
:
630 assert(info
->array_len
== 1);
631 assert(info
->samples
== 1);
634 isl_finishme("%s:%s: compression block with depth > 1",
638 switch (dim_layout
) {
639 case ISL_DIM_LAYOUT_GEN9_1D
:
640 unreachable("bad isl_dim_layout");
642 case ISL_DIM_LAYOUT_GEN4_2D
:
643 assert(ISL_DEV_GEN(dev
) >= 9);
645 *phys_level0_sa
= (struct isl_extent4d
) {
646 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
647 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
653 case ISL_DIM_LAYOUT_GEN4_3D
:
654 assert(ISL_DEV_GEN(dev
) < 9);
655 *phys_level0_sa
= (struct isl_extent4d
) {
656 .w
= isl_align(info
->width
, fmtl
->bw
),
657 .h
= isl_align(info
->height
, fmtl
->bh
),
668 * A variant of isl_calc_phys_slice0_extent_sa() specific to
669 * ISL_DIM_LAYOUT_GEN4_2D.
672 isl_calc_phys_slice0_extent_sa_gen4_2d(
673 const struct isl_device
*dev
,
674 const struct isl_surf_init_info
*restrict info
,
675 enum isl_msaa_layout msaa_layout
,
676 const struct isl_extent3d
*image_align_sa
,
677 const struct isl_extent4d
*phys_level0_sa
,
678 struct isl_extent2d
*phys_slice0_sa
)
680 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
682 assert(phys_level0_sa
->depth
== 1);
684 if (info
->levels
== 1) {
685 /* Do not pad the surface to the image alignment. Instead, pad it only
686 * to the pixel format's block alignment.
688 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
689 * cycles on the below mipmap layout caluclations. Reducing the
690 * alignment here is safe because we later align the row pitch and array
691 * pitch to the tile boundary. It is safe even for
692 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
693 * to accomodate the interleaved samples.
695 * For linear surfaces, reducing the alignment here permits us to later
696 * choose an arbitrary, non-aligned row pitch. If the surface backs
697 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
698 * VkBufferImageCopy::bufferRowLength.
700 *phys_slice0_sa
= (struct isl_extent2d
) {
701 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
702 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
707 uint32_t slice_top_w
= 0;
708 uint32_t slice_bottom_w
= 0;
709 uint32_t slice_left_h
= 0;
710 uint32_t slice_right_h
= 0;
712 uint32_t W0
= phys_level0_sa
->w
;
713 uint32_t H0
= phys_level0_sa
->h
;
715 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
716 uint32_t W
= isl_minify(W0
, l
);
717 uint32_t H
= isl_minify(H0
, l
);
719 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
720 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
737 *phys_slice0_sa
= (struct isl_extent2d
) {
738 .w
= MAX(slice_top_w
, slice_bottom_w
),
739 .h
= MAX(slice_left_h
, slice_right_h
),
744 * A variant of isl_calc_phys_slice0_extent_sa() specific to
745 * ISL_DIM_LAYOUT_GEN4_3D.
748 isl_calc_phys_slice0_extent_sa_gen4_3d(
749 const struct isl_device
*dev
,
750 const struct isl_surf_init_info
*restrict info
,
751 const struct isl_extent3d
*image_align_sa
,
752 const struct isl_extent4d
*phys_level0_sa
,
753 struct isl_extent2d
*phys_slice0_sa
)
755 assert(info
->samples
== 1);
756 assert(phys_level0_sa
->array_len
== 1);
758 uint32_t slice_w
= 0;
759 uint32_t slice_h
= 0;
761 uint32_t W0
= phys_level0_sa
->w
;
762 uint32_t H0
= phys_level0_sa
->h
;
763 uint32_t D0
= phys_level0_sa
->d
;
765 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
766 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
767 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
768 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
770 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
771 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
773 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
774 slice_h
+= level_h
* max_layers_vert
;
777 *phys_slice0_sa
= (struct isl_extent2d
) {
784 * A variant of isl_calc_phys_slice0_extent_sa() specific to
785 * ISL_DIM_LAYOUT_GEN9_1D.
788 isl_calc_phys_slice0_extent_sa_gen9_1d(
789 const struct isl_device
*dev
,
790 const struct isl_surf_init_info
*restrict info
,
791 const struct isl_extent3d
*image_align_sa
,
792 const struct isl_extent4d
*phys_level0_sa
,
793 struct isl_extent2d
*phys_slice0_sa
)
795 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
797 assert(phys_level0_sa
->height
== 1);
798 assert(phys_level0_sa
->depth
== 1);
799 assert(info
->samples
== 1);
800 assert(image_align_sa
->w
>= fmtl
->bw
);
802 uint32_t slice_w
= 0;
803 const uint32_t W0
= phys_level0_sa
->w
;
805 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
806 uint32_t W
= isl_minify(W0
, l
);
807 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
812 *phys_slice0_sa
= isl_extent2d(slice_w
, 1);
816 * Calculate the physical extent of the surface's first array slice, in units
817 * of surface samples. If the surface is multi-leveled, then the result will
818 * be aligned to \a image_align_sa.
821 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
822 const struct isl_surf_init_info
*restrict info
,
823 enum isl_dim_layout dim_layout
,
824 enum isl_msaa_layout msaa_layout
,
825 const struct isl_extent3d
*image_align_sa
,
826 const struct isl_extent4d
*phys_level0_sa
,
827 struct isl_extent2d
*phys_slice0_sa
)
829 switch (dim_layout
) {
830 case ISL_DIM_LAYOUT_GEN9_1D
:
831 isl_calc_phys_slice0_extent_sa_gen9_1d(dev
, info
,
832 image_align_sa
, phys_level0_sa
,
835 case ISL_DIM_LAYOUT_GEN4_2D
:
836 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
837 image_align_sa
, phys_level0_sa
,
840 case ISL_DIM_LAYOUT_GEN4_3D
:
841 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
842 phys_level0_sa
, phys_slice0_sa
);
848 * Calculate the pitch between physical array slices, in units of rows of
852 isl_calc_array_pitch_el_rows(const struct isl_device
*dev
,
853 const struct isl_surf_init_info
*restrict info
,
854 const struct isl_tile_info
*tile_info
,
855 enum isl_dim_layout dim_layout
,
856 enum isl_array_pitch_span array_pitch_span
,
857 const struct isl_extent3d
*image_align_sa
,
858 const struct isl_extent4d
*phys_level0_sa
,
859 const struct isl_extent2d
*phys_slice0_sa
)
861 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
862 uint32_t pitch_sa_rows
= 0;
864 switch (dim_layout
) {
865 case ISL_DIM_LAYOUT_GEN9_1D
:
866 /* Each row is an array slice */
869 case ISL_DIM_LAYOUT_GEN4_2D
:
870 switch (array_pitch_span
) {
871 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
872 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
874 case ISL_ARRAY_PITCH_SPAN_FULL
: {
875 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
876 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
877 * Surfaces >> Surface Arrays.
879 uint32_t H0_sa
= phys_level0_sa
->h
;
880 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
882 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
883 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
886 if (ISL_DEV_GEN(dev
) >= 7) {
887 /* The QPitch equation changed slightly in Ivybridge. */
893 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
895 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
896 (info
->height
% 4 == 1)) {
897 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
898 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
900 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
901 * the value calculated in the equation above , for every
902 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
904 * XXX(chadv): Is the errata natural corollary of the physical
905 * layout of interleaved samples?
910 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
915 case ISL_DIM_LAYOUT_GEN4_3D
:
916 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
917 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
920 unreachable("bad isl_dim_layout");
924 assert(pitch_sa_rows
% fmtl
->bh
== 0);
925 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
927 if (ISL_DEV_GEN(dev
) >= 9 && fmtl
->txc
== ISL_TXC_CCS
) {
929 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
931 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
932 * layout with these alignments in the RT space: Horizontal
933 * Alignment = 128 and Vertical Alignment = 64."
935 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
937 * "For non-multisampled render target's CCS auxiliary surface,
938 * QPitch must be computed with Horizontal Alignment = 128 and
939 * Surface Vertical Alignment = 256. These alignments are only for
940 * CCS buffer and not for associated render target."
942 * The first restriction is already handled by isl_choose_image_alignment_el
943 * but the second restriction, which is an extension of the first, only
944 * applies to qpitch and must be applied here.
946 assert(fmtl
->bh
== 4);
947 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
950 if (ISL_DEV_GEN(dev
) >= 9 &&
951 info
->dim
== ISL_SURF_DIM_3D
&&
952 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
953 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
955 * Tile Mode != Linear: This field must be set to an integer multiple
958 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
961 return pitch_el_rows
;
965 * Calculate the pitch of each surface row, in bytes.
968 isl_calc_linear_row_pitch(const struct isl_device
*dev
,
969 const struct isl_surf_init_info
*restrict info
,
970 const struct isl_extent2d
*phys_slice0_sa
)
972 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
974 uint32_t row_pitch
= info
->min_pitch
;
976 /* First, align the surface to a cache line boundary, as the PRM explains
979 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
980 * Formats >> Surface Padding Requirements >> Render Target and Media
983 * The data port accesses data (pixels) outside of the surface if they
984 * are contained in the same cache request as pixels that are within the
985 * surface. These pixels will not be returned by the requesting message,
986 * however if these pixels lie outside of defined pages in the GTT,
987 * a GTT error will result when the cache request is processed. In order
988 * to avoid these GTT errors, “padding” at the bottom of the surface is
989 * sometimes necessary.
991 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
992 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
994 * The sampling engine accesses texels outside of the surface if they
995 * are contained in the same cache line as texels that are within the
996 * surface. These texels will not participate in any calculation
997 * performed by the sampling engine and will not affect the result of
998 * any sampling engine operation, however if these texels lie outside of
999 * defined pages in the GTT, a GTT error will result when the cache line
1000 * is accessed. In order to avoid these GTT errors, “padding” at the
1001 * bottom and right side of a sampling engine surface is sometimes
1004 * It is possible that a cache line will straddle a page boundary if the
1005 * base address or pitch is not aligned. All pages included in the cache
1006 * lines that are part of the surface must map to valid GTT entries to
1007 * avoid errors. To determine the necessary padding on the bottom and
1008 * right side of the surface, refer to the table in Alignment Unit Size
1009 * section for the i and j parameters for the surface format in use. The
1010 * surface must then be extended to the next multiple of the alignment
1011 * unit size in each dimension, and all texels contained in this
1012 * extended surface must have valid GTT entries.
1014 * For example, suppose the surface size is 15 texels by 10 texels and
1015 * the alignment parameters are i=4 and j=2. In this case, the extended
1016 * surface would be 16 by 10. Note that these calculations are done in
1017 * texels, and must be converted to bytes based on the surface format
1018 * being used to determine whether additional pages need to be defined.
1020 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
1021 const uint32_t bs
= fmtl
->bpb
/ 8;
1022 row_pitch
= MAX(row_pitch
, bs
* (phys_slice0_sa
->w
/ fmtl
->bw
));
1024 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1025 * RENDER_SURFACE_STATE Surface Pitch (p349):
1027 * - For linear render target surfaces and surfaces accessed with the
1028 * typed data port messages, the pitch must be a multiple of the
1029 * element size for non-YUV surface formats. Pitch must be
1030 * a multiple of 2 * element size for YUV surface formats.
1032 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1033 * ignore because isl doesn't do buffers.]
1035 * - For other linear surfaces, the pitch can be any multiple of
1038 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1039 if (isl_format_is_yuv(info
->format
)) {
1040 row_pitch
= isl_align_npot(row_pitch
, 2 * bs
);
1042 row_pitch
= isl_align_npot(row_pitch
, bs
);
1050 * Calculate and apply any padding required for the surface.
1052 * @param[inout] total_h_el is updated with the new height
1053 * @param[out] pad_bytes is overwritten with additional padding requirements.
1056 isl_apply_surface_padding(const struct isl_device
*dev
,
1057 const struct isl_surf_init_info
*restrict info
,
1058 const struct isl_tile_info
*tile_info
,
1059 uint32_t *total_h_el
,
1060 uint32_t *pad_bytes
)
1062 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1066 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1067 * Formats >> Surface Padding Requirements >> Render Target and Media
1070 * The data port accesses data (pixels) outside of the surface if they
1071 * are contained in the same cache request as pixels that are within the
1072 * surface. These pixels will not be returned by the requesting message,
1073 * however if these pixels lie outside of defined pages in the GTT,
1074 * a GTT error will result when the cache request is processed. In
1075 * order to avoid these GTT errors, “padding” at the bottom of the
1076 * surface is sometimes necessary.
1078 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1079 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
1081 * ... Lots of padding requirements, all listed separately below.
1084 /* We can safely ignore the first padding requirement, quoted below,
1085 * because isl doesn't do buffers.
1087 * - [pre-BDW] For buffers, which have no inherent “height,” padding
1088 * requirements are different. A buffer must be padded to the next
1089 * multiple of 256 array elements, with an additional 16 bytes added
1090 * beyond that to account for the L1 cache line.
1094 * - For compressed textures [...], padding at the bottom of the surface
1095 * is to an even compressed row.
1097 if (isl_format_is_compressed(info
->format
))
1098 *total_h_el
= isl_align(*total_h_el
, 2);
1101 * - For cube surfaces, an additional two rows of padding are required
1102 * at the bottom of the surface.
1104 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
1108 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
1109 * additional padding is required. These surfaces require an extra row
1110 * plus 16 bytes of padding at the bottom in addition to the general
1111 * padding requirements.
1113 if (isl_format_is_yuv(info
->format
) &&
1114 (fmtl
->bpb
== 96 || fmtl
->bpb
== 48|| fmtl
->bpb
== 24)) {
1120 * - For linear surfaces, additional padding of 64 bytes is required at
1121 * the bottom of the surface. This is in addition to the padding
1124 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
1127 /* The below text weakens, not strengthens, the padding requirements for
1128 * linear surfaces. Therefore we can safely ignore it.
1130 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
1131 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
1132 * padding requirement is to the next aligned 64-byte boundary beyond
1133 * the end of the surface. The rest of the padding requirements
1134 * documented above do not apply to these surfaces.
1138 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
1139 * height % 4 != 0, the surface must be padded with
1140 * 4-(height % 4)*Surface Pitch # of bytes.
1142 if (ISL_DEV_GEN(dev
) >= 9 &&
1143 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1144 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1145 *total_h_el
= isl_align(*total_h_el
, 4);
1149 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1150 * to 4 times the Surface Pitch # of bytes
1152 if (ISL_DEV_GEN(dev
) >= 9 &&
1153 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1154 info
->dim
== ISL_SURF_DIM_1D
) {
1160 isl_surf_init_s(const struct isl_device
*dev
,
1161 struct isl_surf
*surf
,
1162 const struct isl_surf_init_info
*restrict info
)
1164 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1166 const struct isl_extent4d logical_level0_px
= {
1170 .a
= info
->array_len
,
1173 enum isl_tiling tiling
;
1174 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1177 struct isl_tile_info tile_info
;
1178 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bpb
, &tile_info
))
1181 const enum isl_dim_layout dim_layout
=
1182 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
);
1184 enum isl_msaa_layout msaa_layout
;
1185 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1188 struct isl_extent3d image_align_el
;
1189 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1192 struct isl_extent3d image_align_sa
=
1193 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1195 struct isl_extent4d phys_level0_sa
;
1196 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1198 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1199 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1201 enum isl_array_pitch_span array_pitch_span
=
1202 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1204 struct isl_extent2d phys_slice0_sa
;
1205 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1206 &image_align_sa
, &phys_level0_sa
,
1208 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1209 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1211 const uint32_t array_pitch_el_rows
=
1212 isl_calc_array_pitch_el_rows(dev
, info
, &tile_info
, dim_layout
,
1213 array_pitch_span
, &image_align_sa
,
1214 &phys_level0_sa
, &phys_slice0_sa
);
1216 uint32_t total_h_el
= phys_level0_sa
.array_len
* array_pitch_el_rows
;
1219 isl_apply_surface_padding(dev
, info
, &tile_info
, &total_h_el
, &pad_bytes
);
1221 uint32_t row_pitch
, size
, base_alignment
;
1222 if (tiling
== ISL_TILING_LINEAR
) {
1223 row_pitch
= isl_calc_linear_row_pitch(dev
, info
, &phys_slice0_sa
);
1224 size
= row_pitch
* total_h_el
+ pad_bytes
;
1226 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1228 * "The Base Address for linear render target surfaces and surfaces
1229 * accessed with the typed surface read/write data port messages must
1230 * be element-size aligned, for non-YUV surface formats, or a
1231 * multiple of 2 element-sizes for YUV surface formats. Other linear
1232 * surfaces have no alignment requirements (byte alignment is
1235 base_alignment
= MAX(1, info
->min_alignment
);
1236 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1237 if (isl_format_is_yuv(info
->format
)) {
1238 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 4);
1240 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 8);
1243 base_alignment
= isl_round_up_to_power_of_two(base_alignment
);
1245 assert(fmtl
->bpb
% tile_info
.format_bpb
== 0);
1246 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
.format_bpb
;
1248 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1249 const uint32_t total_w_el
= phys_slice0_sa
.width
/ fmtl
->bw
;
1250 const uint32_t total_w_tl
=
1251 isl_align_div(total_w_el
* tile_el_scale
,
1252 tile_info
.logical_extent_el
.width
);
1254 row_pitch
= total_w_tl
* tile_info
.phys_extent_B
.width
;
1255 if (row_pitch
< info
->min_pitch
) {
1256 row_pitch
= isl_align_npot(info
->min_pitch
,
1257 tile_info
.phys_extent_B
.width
);
1260 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1261 const uint32_t total_h_tl
=
1262 isl_align_div(total_h_el
, tile_info
.logical_extent_el
.height
);
1264 size
= total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch
;
1266 const uint32_t tile_size
= tile_info
.phys_extent_B
.width
*
1267 tile_info
.phys_extent_B
.height
;
1268 assert(isl_is_pow2(info
->min_alignment
) && isl_is_pow2(tile_size
));
1269 base_alignment
= MAX(info
->min_alignment
, tile_size
);
1272 *surf
= (struct isl_surf
) {
1274 .dim_layout
= dim_layout
,
1275 .msaa_layout
= msaa_layout
,
1277 .format
= info
->format
,
1279 .levels
= info
->levels
,
1280 .samples
= info
->samples
,
1282 .image_alignment_el
= image_align_el
,
1283 .logical_level0_px
= logical_level0_px
,
1284 .phys_level0_sa
= phys_level0_sa
,
1287 .alignment
= base_alignment
,
1288 .row_pitch
= row_pitch
,
1289 .array_pitch_el_rows
= array_pitch_el_rows
,
1290 .array_pitch_span
= array_pitch_span
,
1292 .usage
= info
->usage
,
1299 isl_surf_get_tile_info(const struct isl_device
*dev
,
1300 const struct isl_surf
*surf
,
1301 struct isl_tile_info
*tile_info
)
1303 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1304 isl_tiling_get_info(dev
, surf
->tiling
, fmtl
->bpb
, tile_info
);
1308 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1309 const struct isl_surf
*surf
,
1310 struct isl_surf
*hiz_surf
)
1312 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1314 /* Multisampled depth is always interleaved */
1315 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1316 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1318 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
1320 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
1321 * Target View Extent, and Depth Coordinate Offset X/Y of the
1322 * hierarchical depth buffer are inherited from the depth buffer. The
1323 * height and width of the hierarchical depth buffer that must be
1324 * allocated are computed by the following formulas, where HZ is the
1325 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
1326 * Z_Width, and Z_Depth values given in these formulas are those present
1327 * in 3DSTATE_DEPTH_BUFFER incremented by one.
1329 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
1330 * being applied to the table below if Number of Multisamples is set to
1331 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
1332 * Z_Width must be multiplied by 4 before being applied to the table
1333 * below if Number of Multisamples is set to NUMSAMPLES_8."
1335 * In the Sky Lake PRM, the second paragraph is replaced with this:
1337 * "The Z_Height and Z_Width values must equal those present in
1338 * 3DSTATE_DEPTH_BUFFER incremented by one."
1340 * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
1341 * block corresponds to a region of 8x4 samples in the primary depth
1342 * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
1343 * a region of 8x4 pixels in the primary depth surface regardless of the
1344 * number of samples. The dimensions of a HiZ block in both pixels and
1345 * samples are given in the table below:
1347 * | SNB - BDW | SKL+
1348 * ------+-----------+-------------
1349 * 1x | 8 x 4 sa | 8 x 4 sa
1350 * MSAA | 8 x 4 px | 8 x 4 px
1351 * ------+-----------+-------------
1352 * 2x | 8 x 4 sa | 16 x 4 sa
1353 * MSAA | 4 x 4 px | 8 x 4 px
1354 * ------+-----------+-------------
1355 * 4x | 8 x 4 sa | 16 x 8 sa
1356 * MSAA | 4 x 2 px | 8 x 4 px
1357 * ------+-----------+-------------
1358 * 8x | 8 x 4 sa | 32 x 8 sa
1359 * MSAA | 2 x 2 px | 8 x 4 px
1360 * ------+-----------+-------------
1361 * 16x | N/A | 32 x 16 sa
1362 * MSAA | N/A | 8 x 4 px
1363 * ------+-----------+-------------
1365 * There are a number of different ways that this discrepency could be
1366 * handled. The way we have chosen is to simply make MSAA HiZ have the
1367 * same number of samples as the parent surface pre-Sky Lake and always be
1368 * single-sampled on Sky Lake and above. Since the block sizes of
1369 * compressed formats are given in samples, this neatly handles everything
1370 * without the need for additional HiZ formats with different block sizes
1373 const unsigned samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
;
1375 isl_surf_init(dev
, hiz_surf
,
1377 .format
= ISL_FORMAT_HIZ
,
1378 .width
= surf
->logical_level0_px
.width
,
1379 .height
= surf
->logical_level0_px
.height
,
1380 .depth
= surf
->logical_level0_px
.depth
,
1381 .levels
= surf
->levels
,
1382 .array_len
= surf
->logical_level0_px
.array_len
,
1384 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1385 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1389 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1390 const struct isl_surf
*surf
,
1391 struct isl_surf
*mcs_surf
)
1393 /* It must be multisampled with an array layout */
1394 assert(surf
->samples
> 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1396 /* The following are true of all multisampled surfaces */
1397 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1398 assert(surf
->levels
== 1);
1399 assert(surf
->logical_level0_px
.depth
== 1);
1401 enum isl_format mcs_format
;
1402 switch (surf
->samples
) {
1403 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1404 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1405 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1406 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1408 unreachable("Invalid sample count");
1411 isl_surf_init(dev
, mcs_surf
,
1412 .dim
= ISL_SURF_DIM_2D
,
1413 .format
= mcs_format
,
1414 .width
= surf
->logical_level0_px
.width
,
1415 .height
= surf
->logical_level0_px
.height
,
1418 .array_len
= surf
->logical_level0_px
.array_len
,
1419 .samples
= 1, /* MCS surfaces are really single-sampled */
1420 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1421 .tiling_flags
= ISL_TILING_Y0_BIT
);
1425 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1426 const struct isl_surf
*surf
,
1427 struct isl_surf
*ccs_surf
)
1429 assert(surf
->samples
== 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
);
1430 assert(ISL_DEV_GEN(dev
) >= 7);
1432 assert(ISL_DEV_GEN(dev
) >= 8 || surf
->dim
== ISL_SURF_DIM_2D
);
1434 assert(surf
->logical_level0_px
.depth
== 1);
1436 /* TODO: More conditions where it can fail. */
1438 enum isl_format ccs_format
;
1439 if (ISL_DEV_GEN(dev
) >= 9) {
1440 if (!isl_tiling_is_any_y(surf
->tiling
))
1443 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1444 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
1445 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
1446 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
1450 } else if (surf
->tiling
== ISL_TILING_Y0
) {
1451 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1452 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
1453 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
1454 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
1458 } else if (surf
->tiling
== ISL_TILING_X
) {
1459 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1460 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
1461 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
1462 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
1470 isl_surf_init(dev
, ccs_surf
,
1471 .dim
= ISL_SURF_DIM_2D
,
1472 .format
= ccs_format
,
1473 .width
= surf
->logical_level0_px
.width
,
1474 .height
= surf
->logical_level0_px
.height
,
1476 .levels
= surf
->levels
,
1477 .array_len
= surf
->logical_level0_px
.array_len
,
1479 .usage
= ISL_SURF_USAGE_CCS_BIT
,
1480 .tiling_flags
= ISL_TILING_CCS_BIT
);
1486 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1487 const struct isl_surf_fill_state_info
*restrict info
)
1490 isl_surf_usage_flags_t _base_usage
=
1491 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1492 ISL_SURF_USAGE_TEXTURE_BIT
|
1493 ISL_SURF_USAGE_STORAGE_BIT
);
1494 /* They may only specify one of the above bits at a time */
1495 assert(__builtin_popcount(_base_usage
) == 1);
1496 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1497 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1500 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1501 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1502 info
->surf
->logical_level0_px
.depth
);
1504 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1505 info
->surf
->logical_level0_px
.array_len
);
1508 switch (ISL_DEV_GEN(dev
)) {
1510 if (ISL_DEV_IS_G4X(dev
)) {
1511 /* G45 surface state is the same as gen5 */
1512 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1514 isl_gen4_surf_fill_state_s(dev
, state
, info
);
1518 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1521 isl_gen6_surf_fill_state_s(dev
, state
, info
);
1524 if (ISL_DEV_IS_HASWELL(dev
)) {
1525 isl_gen75_surf_fill_state_s(dev
, state
, info
);
1527 isl_gen7_surf_fill_state_s(dev
, state
, info
);
1531 isl_gen8_surf_fill_state_s(dev
, state
, info
);
1534 isl_gen9_surf_fill_state_s(dev
, state
, info
);
1537 assert(!"Cannot fill surface state for this gen");
1542 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1543 const struct isl_buffer_fill_state_info
*restrict info
)
1545 switch (ISL_DEV_GEN(dev
)) {
1548 /* Gen 4-5 are all the same when it comes to buffer surfaces */
1549 isl_gen5_buffer_fill_state_s(state
, info
);
1552 isl_gen6_buffer_fill_state_s(state
, info
);
1555 if (ISL_DEV_IS_HASWELL(dev
)) {
1556 isl_gen75_buffer_fill_state_s(state
, info
);
1558 isl_gen7_buffer_fill_state_s(state
, info
);
1562 isl_gen8_buffer_fill_state_s(state
, info
);
1565 isl_gen9_buffer_fill_state_s(state
, info
);
1568 assert(!"Cannot fill surface state for this gen");
1573 * A variant of isl_surf_get_image_offset_sa() specific to
1574 * ISL_DIM_LAYOUT_GEN4_2D.
1577 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1578 uint32_t level
, uint32_t logical_array_layer
,
1579 uint32_t *x_offset_sa
,
1580 uint32_t *y_offset_sa
)
1582 assert(level
< surf
->levels
);
1583 if (surf
->dim
== ISL_SURF_DIM_3D
)
1584 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
1586 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1588 const struct isl_extent3d image_align_sa
=
1589 isl_surf_get_image_alignment_sa(surf
);
1591 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1592 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1594 const uint32_t phys_layer
= logical_array_layer
*
1595 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
1598 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1600 for (uint32_t l
= 0; l
< level
; ++l
) {
1602 uint32_t W
= isl_minify(W0
, l
);
1603 x
+= isl_align_npot(W
, image_align_sa
.w
);
1605 uint32_t H
= isl_minify(H0
, l
);
1606 y
+= isl_align_npot(H
, image_align_sa
.h
);
1615 * A variant of isl_surf_get_image_offset_sa() specific to
1616 * ISL_DIM_LAYOUT_GEN4_3D.
1619 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1620 uint32_t level
, uint32_t logical_z_offset_px
,
1621 uint32_t *x_offset_sa
,
1622 uint32_t *y_offset_sa
)
1624 assert(level
< surf
->levels
);
1625 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1626 assert(surf
->phys_level0_sa
.array_len
== 1);
1628 const struct isl_extent3d image_align_sa
=
1629 isl_surf_get_image_alignment_sa(surf
);
1631 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1632 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1633 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1638 for (uint32_t l
= 0; l
< level
; ++l
) {
1639 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1640 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
.d
);
1641 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1643 y
+= level_h
* max_layers_vert
;
1646 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1647 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1648 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, level
), image_align_sa
.d
);
1650 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1652 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1653 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
1660 * A variant of isl_surf_get_image_offset_sa() specific to
1661 * ISL_DIM_LAYOUT_GEN9_1D.
1664 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
1665 uint32_t level
, uint32_t layer
,
1666 uint32_t *x_offset_sa
,
1667 uint32_t *y_offset_sa
)
1669 assert(level
< surf
->levels
);
1670 assert(layer
< surf
->phys_level0_sa
.array_len
);
1671 assert(surf
->phys_level0_sa
.height
== 1);
1672 assert(surf
->phys_level0_sa
.depth
== 1);
1673 assert(surf
->samples
== 1);
1675 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1676 const struct isl_extent3d image_align_sa
=
1677 isl_surf_get_image_alignment_sa(surf
);
1681 for (uint32_t l
= 0; l
< level
; ++l
) {
1682 uint32_t W
= isl_minify(W0
, l
);
1683 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
1689 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1693 * Calculate the offset, in units of surface samples, to a subimage in the
1696 * @invariant level < surface levels
1697 * @invariant logical_array_layer < logical array length of surface
1698 * @invariant logical_z_offset_px < logical depth of surface at level
1701 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1703 uint32_t logical_array_layer
,
1704 uint32_t logical_z_offset_px
,
1705 uint32_t *x_offset_sa
,
1706 uint32_t *y_offset_sa
)
1708 assert(level
< surf
->levels
);
1709 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1710 assert(logical_z_offset_px
1711 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1713 switch (surf
->dim_layout
) {
1714 case ISL_DIM_LAYOUT_GEN9_1D
:
1715 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
1716 x_offset_sa
, y_offset_sa
);
1718 case ISL_DIM_LAYOUT_GEN4_2D
:
1719 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
1720 + logical_z_offset_px
,
1721 x_offset_sa
, y_offset_sa
);
1723 case ISL_DIM_LAYOUT_GEN4_3D
:
1724 get_image_offset_sa_gen4_3d(surf
, level
, logical_z_offset_px
,
1725 x_offset_sa
, y_offset_sa
);
1729 unreachable("not reached");
1734 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1736 uint32_t logical_array_layer
,
1737 uint32_t logical_z_offset_px
,
1738 uint32_t *x_offset_el
,
1739 uint32_t *y_offset_el
)
1741 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1743 assert(level
< surf
->levels
);
1744 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1745 assert(logical_z_offset_px
1746 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1748 uint32_t x_offset_sa
, y_offset_sa
;
1749 isl_surf_get_image_offset_sa(surf
, level
,
1750 logical_array_layer
,
1751 logical_z_offset_px
,
1755 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
1756 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
1760 isl_tiling_get_intratile_offset_el(const struct isl_device
*dev
,
1761 enum isl_tiling tiling
,
1764 uint32_t total_x_offset_el
,
1765 uint32_t total_y_offset_el
,
1766 uint32_t *base_address_offset
,
1767 uint32_t *x_offset_el
,
1768 uint32_t *y_offset_el
)
1770 if (tiling
== ISL_TILING_LINEAR
) {
1771 *base_address_offset
= total_y_offset_el
* row_pitch
+
1772 total_x_offset_el
* bs
;
1778 const uint32_t bpb
= bs
* 8;
1780 struct isl_tile_info tile_info
;
1781 isl_tiling_get_info(dev
, tiling
, bpb
, &tile_info
);
1783 assert(row_pitch
% tile_info
.phys_extent_B
.width
== 0);
1785 /* For non-power-of-two formats, we need the address to be both tile and
1786 * element-aligned. The easiest way to achieve this is to work with a tile
1787 * that is three times as wide as the regular tile.
1789 * The tile info returned by get_tile_info has a logical size that is an
1790 * integer number of tile_info.format_bpb size elements. To scale the
1791 * tile, we scale up the physical width and then treat the logical tile
1792 * size as if it has bpb size elements.
1794 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
1795 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
1797 /* Compute the offset into the tile */
1798 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
1799 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
1801 /* Compute the offset of the tile in units of whole tiles */
1802 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
1803 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
1805 *base_address_offset
=
1806 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch
+
1807 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
1811 isl_surf_get_depth_format(const struct isl_device
*dev
,
1812 const struct isl_surf
*surf
)
1814 /* Support for separate stencil buffers began in gen5. Support for
1815 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
1816 * those that supported separate and interleaved stencil, were gen5 and
1819 * For a list of all available formats, see the Sandybridge PRM >> Volume
1820 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
1824 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1826 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
1829 assert(ISL_DEV_GEN(dev
) < 7);
1831 switch (surf
->format
) {
1833 unreachable("bad isl depth format");
1834 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1835 assert(ISL_DEV_GEN(dev
) < 7);
1836 return 0; /* D32_FLOAT_S8X24_UINT */
1837 case ISL_FORMAT_R32_FLOAT
:
1838 assert(!has_stencil
);
1839 return 1; /* D32_FLOAT */
1840 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1842 assert(ISL_DEV_GEN(dev
) < 7);
1843 return 2; /* D24_UNORM_S8_UINT */
1845 assert(ISL_DEV_GEN(dev
) >= 5);
1846 return 3; /* D24_UNORM_X8_UINT */
1848 case ISL_FORMAT_R16_UNORM
:
1849 assert(!has_stencil
);
1850 return 5; /* D16_UNORM */